./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 03:20:57,114 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 03:20:57,173 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 03:20:57,179 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 03:20:57,179 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 03:20:57,204 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 03:20:57,204 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 03:20:57,205 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 03:20:57,205 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 03:20:57,206 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 03:20:57,207 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 03:20:57,207 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 03:20:57,208 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 03:20:57,208 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 03:20:57,209 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 03:20:57,209 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 03:20:57,210 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 03:20:57,210 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 03:20:57,211 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 03:20:57,211 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 03:20:57,212 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 03:20:57,213 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 03:20:57,213 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 03:20:57,214 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 03:20:57,214 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 03:20:57,215 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 03:20:57,215 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 03:20:57,215 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 03:20:57,216 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 03:20:57,216 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 03:20:57,217 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 03:20:57,217 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 03:20:57,218 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 03:20:57,218 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 03:20:57,218 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 03:20:57,218 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 03:20:57,219 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 03:20:57,219 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 03:20:57,219 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 0dcd4461cca64e9ab41b6ad7ff4c6eaa4177bddcca1c612fa1571b77ac664a95 [2023-11-29 03:20:57,434 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 03:20:57,455 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 03:20:57,458 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 03:20:57,459 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 03:20:57,459 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 03:20:57,461 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2023-11-29 03:21:00,214 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 03:21:00,424 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 03:21:00,425 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/sv-benchmarks/c/systemc/token_ring.13.cil-2.c [2023-11-29 03:21:00,443 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/data/05ba9b778/b80197554a6e4e7697780bffdff5ff48/FLAG5989810d5 [2023-11-29 03:21:00,457 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/data/05ba9b778/b80197554a6e4e7697780bffdff5ff48 [2023-11-29 03:21:00,460 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 03:21:00,461 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 03:21:00,463 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 03:21:00,463 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 03:21:00,469 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 03:21:00,469 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:00,470 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@78af8220 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00, skipping insertion in model container [2023-11-29 03:21:00,471 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:00,529 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 03:21:00,786 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 03:21:00,799 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 03:21:00,871 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 03:21:00,891 INFO L206 MainTranslator]: Completed translation [2023-11-29 03:21:00,891 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00 WrapperNode [2023-11-29 03:21:00,892 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 03:21:00,892 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 03:21:00,893 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 03:21:00,893 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 03:21:00,912 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:00,928 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,032 INFO L138 Inliner]: procedures = 54, calls = 71, calls flagged for inlining = 66, calls inlined = 303, statements flattened = 4682 [2023-11-29 03:21:01,032 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 03:21:01,033 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 03:21:01,033 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 03:21:01,033 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 03:21:01,045 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,045 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,060 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,101 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 03:21:01,101 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,101 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,143 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,176 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,184 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,193 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,203 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 03:21:01,204 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 03:21:01,204 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 03:21:01,204 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 03:21:01,205 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (1/1) ... [2023-11-29 03:21:01,210 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 03:21:01,222 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 03:21:01,234 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 03:21:01,236 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_bf494383-3cd1-4924-8234-3f85a01c1326/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 03:21:01,267 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 03:21:01,268 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 03:21:01,268 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 03:21:01,268 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 03:21:01,399 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 03:21:01,401 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 03:21:03,650 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 03:21:03,687 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 03:21:03,687 INFO L309 CfgBuilder]: Removed 16 assume(true) statements. [2023-11-29 03:21:03,690 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 03:21:03 BoogieIcfgContainer [2023-11-29 03:21:03,690 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 03:21:03,691 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 03:21:03,691 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 03:21:03,694 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 03:21:03,695 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 03:21:03,695 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 03:21:00" (1/3) ... [2023-11-29 03:21:03,696 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3487dadd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 03:21:03, skipping insertion in model container [2023-11-29 03:21:03,696 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 03:21:03,696 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 03:21:00" (2/3) ... [2023-11-29 03:21:03,697 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@3487dadd and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 03:21:03, skipping insertion in model container [2023-11-29 03:21:03,697 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 03:21:03,697 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 03:21:03" (3/3) ... [2023-11-29 03:21:03,698 INFO L332 chiAutomizerObserver]: Analyzing ICFG token_ring.13.cil-2.c [2023-11-29 03:21:03,777 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 03:21:03,777 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 03:21:03,777 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 03:21:03,777 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 03:21:03,777 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 03:21:03,777 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 03:21:03,778 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 03:21:03,778 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 03:21:03,789 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2039 states, 2038 states have (on average 1.4921491658488715) internal successors, (3041), 2038 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:03,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-29 03:21:03,854 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:03,854 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:03,870 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:03,870 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:03,870 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 03:21:03,875 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 2039 states, 2038 states have (on average 1.4921491658488715) internal successors, (3041), 2038 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:03,891 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1860 [2023-11-29 03:21:03,892 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:03,892 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:03,896 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:03,897 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:03,906 INFO L748 eck$LassoCheckResult]: Stem: 154#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1954#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 758#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1947#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1875#L902true assume !(1 == ~m_i~0);~m_st~0 := 2; 471#L902-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1625#L907-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 514#L912-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1555#L917-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 840#L922-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 994#L927-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 494#L932-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 379#L937-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 1485#L942-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 668#L947-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 1544#L952-1true assume !(1 == ~t11_i~0);~t11_st~0 := 2; 586#L957-1true assume !(1 == ~t12_i~0);~t12_st~0 := 2; 915#L962-1true assume !(1 == ~t13_i~0);~t13_st~0 := 2; 364#L967-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1972#L1279true assume 0 == ~M_E~0;~M_E~0 := 1; 1556#L1279-2true assume !(0 == ~T1_E~0); 164#L1284-1true assume !(0 == ~T2_E~0); 1785#L1289-1true assume !(0 == ~T3_E~0); 583#L1294-1true assume !(0 == ~T4_E~0); 591#L1299-1true assume !(0 == ~T5_E~0); 1865#L1304-1true assume !(0 == ~T6_E~0); 1912#L1309-1true assume !(0 == ~T7_E~0); 1881#L1314-1true assume 0 == ~T8_E~0;~T8_E~0 := 1; 126#L1319-1true assume !(0 == ~T9_E~0); 1114#L1324-1true assume !(0 == ~T10_E~0); 214#L1329-1true assume !(0 == ~T11_E~0); 1377#L1334-1true assume !(0 == ~T12_E~0); 1814#L1339-1true assume !(0 == ~T13_E~0); 1534#L1344-1true assume !(0 == ~E_M~0); 1970#L1349-1true assume !(0 == ~E_1~0); 724#L1354-1true assume 0 == ~E_2~0;~E_2~0 := 1; 1119#L1359-1true assume !(0 == ~E_3~0); 1791#L1364-1true assume !(0 == ~E_4~0); 282#L1369-1true assume !(0 == ~E_5~0); 1093#L1374-1true assume !(0 == ~E_6~0); 729#L1379-1true assume !(0 == ~E_7~0); 791#L1384-1true assume !(0 == ~E_8~0); 2016#L1389-1true assume !(0 == ~E_9~0); 1412#L1394-1true assume 0 == ~E_10~0;~E_10~0 := 1; 1880#L1399-1true assume !(0 == ~E_11~0); 1643#L1404-1true assume !(0 == ~E_12~0); 334#L1409-1true assume !(0 == ~E_13~0); 1618#L1414-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1963#L628true assume !(1 == ~m_pc~0); 1420#L628-2true is_master_triggered_~__retres1~0#1 := 0; 944#L639true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 634#is_master_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1660#L1591true assume !(0 != activate_threads_~tmp~1#1); 1897#L1591-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 617#L647true assume 1 == ~t1_pc~0; 242#L648true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 654#L658true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1065#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1640#L1599true assume !(0 != activate_threads_~tmp___0~0#1); 1511#L1599-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1924#L666true assume 1 == ~t2_pc~0; 163#L667true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 249#L677true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 237#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1538#L1607true assume !(0 != activate_threads_~tmp___1~0#1); 883#L1607-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1866#L685true assume !(1 == ~t3_pc~0); 1034#L685-2true is_transmit3_triggered_~__retres1~3#1 := 0; 1686#L696true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1045#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 765#L1615true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1070#L1615-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 409#L704true assume 1 == ~t4_pc~0; 1246#L705true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 776#L715true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 62#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1786#L1623true assume !(0 != activate_threads_~tmp___3~0#1); 653#L1623-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 762#L723true assume !(1 == ~t5_pc~0); 955#L723-2true is_transmit5_triggered_~__retres1~5#1 := 0; 1113#L734true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1654#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 866#L1631true assume !(0 != activate_threads_~tmp___4~0#1); 887#L1631-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 273#L742true assume 1 == ~t6_pc~0; 967#L743true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 358#L753true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 232#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 111#L1639true assume !(0 != activate_threads_~tmp___5~0#1); 1369#L1639-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 315#L761true assume !(1 == ~t7_pc~0); 323#L761-2true is_transmit7_triggered_~__retres1~7#1 := 0; 247#L772true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1967#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 767#L1647true assume !(0 != activate_threads_~tmp___6~0#1); 1565#L1647-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 122#L780true assume 1 == ~t8_pc~0; 592#L781true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 268#L791true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1606#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 736#L1655true assume !(0 != activate_threads_~tmp___7~0#1); 830#L1655-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1403#L799true assume 1 == ~t9_pc~0; 922#L800true assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 123#L810true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 265#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1008#L1663true assume !(0 != activate_threads_~tmp___8~0#1); 1931#L1663-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 853#L818true assume !(1 == ~t10_pc~0); 25#L818-2true is_transmit10_triggered_~__retres1~10#1 := 0; 916#L829true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1385#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 856#L1671true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1099#L1671-2true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 892#L837true assume 1 == ~t11_pc~0; 1808#L838true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 1584#L848true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1516#is_transmit11_triggered_returnLabel#1true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 825#L1679true assume !(0 != activate_threads_~tmp___10~0#1); 1869#L1679-2true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 623#L856true assume !(1 == ~t12_pc~0); 1452#L856-2true is_transmit12_triggered_~__retres1~12#1 := 0; 1253#L867true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34#is_transmit12_triggered_returnLabel#1true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1224#L1687true assume !(0 != activate_threads_~tmp___11~0#1); 1800#L1687-2true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1562#L875true assume 1 == ~t13_pc~0; 589#L876true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 359#L886true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1439#is_transmit13_triggered_returnLabel#1true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 326#L1695true assume !(0 != activate_threads_~tmp___12~0#1); 914#L1695-2true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1908#L1427true assume !(1 == ~M_E~0); 901#L1427-2true assume !(1 == ~T1_E~0); 308#L1432-1true assume !(1 == ~T2_E~0); 1566#L1437-1true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1129#L1442-1true assume !(1 == ~T4_E~0); 1494#L1447-1true assume !(1 == ~T5_E~0); 962#L1452-1true assume !(1 == ~T6_E~0); 87#L1457-1true assume !(1 == ~T7_E~0); 1158#L1462-1true assume !(1 == ~T8_E~0); 1852#L1467-1true assume !(1 == ~T9_E~0); 1185#L1472-1true assume !(1 == ~T10_E~0); 1381#L1477-1true assume 1 == ~T11_E~0;~T11_E~0 := 2; 912#L1482-1true assume !(1 == ~T12_E~0); 1304#L1487-1true assume !(1 == ~T13_E~0); 254#L1492-1true assume !(1 == ~E_M~0); 666#L1497-1true assume !(1 == ~E_1~0); 459#L1502-1true assume !(1 == ~E_2~0); 1303#L1507-1true assume !(1 == ~E_3~0); 190#L1512-1true assume !(1 == ~E_4~0); 1280#L1517-1true assume 1 == ~E_5~0;~E_5~0 := 2; 1398#L1522-1true assume !(1 == ~E_6~0); 615#L1527-1true assume !(1 == ~E_7~0); 1765#L1532-1true assume !(1 == ~E_8~0); 2028#L1537-1true assume !(1 == ~E_9~0); 781#L1542-1true assume !(1 == ~E_10~0); 638#L1547-1true assume !(1 == ~E_11~0); 1796#L1552-1true assume !(1 == ~E_12~0); 44#L1557-1true assume 1 == ~E_13~0;~E_13~0 := 2; 352#L1562-1true assume { :end_inline_reset_delta_events } true; 759#L1928-2true [2023-11-29 03:21:03,910 INFO L750 eck$LassoCheckResult]: Loop: 759#L1928-2true assume !false; 663#L1929true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 533#L1254-1true assume false; 577#eval_returnLabel#1true havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 338#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1610#L1279-3true assume 0 == ~M_E~0;~M_E~0 := 1; 472#L1279-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 461#L1284-3true assume !(0 == ~T2_E~0); 1665#L1289-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 451#L1294-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 1903#L1299-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 721#L1304-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 1146#L1309-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 383#L1314-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 1984#L1319-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1212#L1324-3true assume !(0 == ~T10_E~0); 189#L1329-3true assume 0 == ~T11_E~0;~T11_E~0 := 1; 1834#L1334-3true assume 0 == ~T12_E~0;~T12_E~0 := 1; 644#L1339-3true assume 0 == ~T13_E~0;~T13_E~0 := 1; 938#L1344-3true assume 0 == ~E_M~0;~E_M~0 := 1; 889#L1349-3true assume 0 == ~E_1~0;~E_1~0 := 1; 373#L1354-3true assume 0 == ~E_2~0;~E_2~0 := 1; 898#L1359-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1863#L1364-3true assume !(0 == ~E_4~0); 1750#L1369-3true assume 0 == ~E_5~0;~E_5~0 := 1; 1443#L1374-3true assume 0 == ~E_6~0;~E_6~0 := 1; 256#L1379-3true assume 0 == ~E_7~0;~E_7~0 := 1; 1310#L1384-3true assume 0 == ~E_8~0;~E_8~0 := 1; 372#L1389-3true assume 0 == ~E_9~0;~E_9~0 := 1; 555#L1394-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1957#L1399-3true assume 0 == ~E_11~0;~E_11~0 := 1; 1474#L1404-3true assume !(0 == ~E_12~0); 1397#L1409-3true assume 0 == ~E_13~0;~E_13~0 := 1; 1554#L1414-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 801#L628-45true assume 1 == ~m_pc~0; 553#L629-15true assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 1744#L639-15true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 971#is_master_triggered_returnLabel#16true activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 393#L1591-45true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1667#L1591-47true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 921#L647-45true assume !(1 == ~t1_pc~0); 1404#L647-47true is_transmit1_triggered_~__retres1~1#1 := 0; 735#L658-15true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1867#is_transmit1_triggered_returnLabel#16true activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 218#L1599-45true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1552#L1599-47true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 331#L666-45true assume !(1 == ~t2_pc~0); 630#L666-47true is_transmit2_triggered_~__retres1~2#1 := 0; 1693#L677-15true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 968#is_transmit2_triggered_returnLabel#16true activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1023#L1607-45true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1019#L1607-47true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96#L685-45true assume 1 == ~t3_pc~0; 730#L686-15true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1537#L696-15true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1990#is_transmit3_triggered_returnLabel#16true activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1275#L1615-45true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1558#L1615-47true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1639#L704-45true assume 1 == ~t4_pc~0; 1316#L705-15true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 492#L715-15true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1317#is_transmit4_triggered_returnLabel#16true activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2031#L1623-45true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1993#L1623-47true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 827#L723-45true assume 1 == ~t5_pc~0; 1827#L724-15true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1706#L734-15true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1983#is_transmit5_triggered_returnLabel#16true activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 381#L1631-45true assume !(0 != activate_threads_~tmp___4~0#1); 1937#L1631-47true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1235#L742-45true assume 1 == ~t6_pc~0; 1845#L743-15true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 897#L753-15true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 685#is_transmit6_triggered_returnLabel#16true activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 926#L1639-45true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1279#L1639-47true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 999#L761-45true assume !(1 == ~t7_pc~0); 1167#L761-47true is_transmit7_triggered_~__retres1~7#1 := 0; 535#L772-15true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 755#is_transmit7_triggered_returnLabel#16true activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 192#L1647-45true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1962#L1647-47true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1401#L780-45true assume 1 == ~t8_pc~0; 396#L781-15true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 197#L791-15true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1736#is_transmit8_triggered_returnLabel#16true activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1764#L1655-45true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 180#L1655-47true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 642#L799-45true assume !(1 == ~t9_pc~0); 298#L799-47true is_transmit9_triggered_~__retres1~9#1 := 0; 2022#L810-15true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1091#is_transmit9_triggered_returnLabel#16true activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 963#L1663-45true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1828#L1663-47true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 152#L818-45true assume 1 == ~t10_pc~0; 1064#L819-15true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 943#L829-15true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1203#is_transmit10_triggered_returnLabel#16true activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 491#L1671-45true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1056#L1671-47true assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1530#L837-45true assume 1 == ~t11_pc~0; 1771#L838-15true assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 536#L848-15true is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 188#is_transmit11_triggered_returnLabel#16true activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1856#L1679-45true assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 224#L1679-47true assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2040#L856-45true assume 1 == ~t12_pc~0; 1549#L857-15true assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1274#L867-15true is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1136#is_transmit12_triggered_returnLabel#16true activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1810#L1687-45true assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 734#L1687-47true assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1282#L875-45true assume 1 == ~t13_pc~0; 709#L876-15true assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 757#L886-15true is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1079#is_transmit13_triggered_returnLabel#16true activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1493#L1695-45true assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1775#L1695-47true havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1374#L1427-3true assume !(1 == ~M_E~0); 580#L1427-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1567#L1432-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1006#L1437-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 723#L1442-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1024#L1447-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 51#L1452-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1992#L1457-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1259#L1462-3true assume !(1 == ~T8_E~0); 1681#L1467-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1073#L1472-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1714#L1477-3true assume 1 == ~T11_E~0;~T11_E~0 := 2; 173#L1482-3true assume 1 == ~T12_E~0;~T12_E~0 := 2; 246#L1487-3true assume 1 == ~T13_E~0;~T13_E~0 := 2; 1820#L1492-3true assume 1 == ~E_M~0;~E_M~0 := 2; 337#L1497-3true assume 1 == ~E_1~0;~E_1~0 := 2; 1027#L1502-3true assume !(1 == ~E_2~0); 1210#L1507-3true assume 1 == ~E_3~0;~E_3~0 := 2; 1929#L1512-3true assume 1 == ~E_4~0;~E_4~0 := 2; 361#L1517-3true assume 1 == ~E_5~0;~E_5~0 := 2; 194#L1522-3true assume 1 == ~E_6~0;~E_6~0 := 2; 1682#L1527-3true assume 1 == ~E_7~0;~E_7~0 := 2; 176#L1532-3true assume 1 == ~E_8~0;~E_8~0 := 2; 899#L1537-3true assume 1 == ~E_9~0;~E_9~0 := 2; 1581#L1542-3true assume !(1 == ~E_10~0); 1011#L1547-3true assume 1 == ~E_11~0;~E_11~0 := 2; 710#L1552-3true assume 1 == ~E_12~0;~E_12~0 := 2; 1406#L1557-3true assume 1 == ~E_13~0;~E_13~0 := 2; 285#L1562-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1981#L980-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1421#L1052-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 208#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 817#L1947true assume !(0 == start_simulation_~tmp~3#1); 987#L1947-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1134#L980-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1629#L1052-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1461#L1902true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1173#L1909true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1411#stop_simulation_returnLabel#1true start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1720#L1960true assume !(0 != start_simulation_~tmp___0~1#1); 759#L1928-2true [2023-11-29 03:21:03,919 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:03,920 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 1 times [2023-11-29 03:21:03,928 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:03,928 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2050932279] [2023-11-29 03:21:03,929 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:03,929 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:04,054 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:04,249 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:04,250 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:04,250 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2050932279] [2023-11-29 03:21:04,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2050932279] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:04,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:04,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:04,253 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967355315] [2023-11-29 03:21:04,253 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:04,257 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:04,258 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:04,258 INFO L85 PathProgramCache]: Analyzing trace with hash 1758240959, now seen corresponding path program 1 times [2023-11-29 03:21:04,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:04,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1753962462] [2023-11-29 03:21:04,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:04,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:04,277 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:04,322 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:04,322 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:04,322 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1753962462] [2023-11-29 03:21:04,322 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1753962462] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:04,323 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:04,323 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:21:04,323 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [714963558] [2023-11-29 03:21:04,323 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:04,325 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:04,326 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:04,354 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 2 interpolants. [2023-11-29 03:21:04,354 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=1, Invalid=1, Unknown=0, NotChecked=0, Total=2 [2023-11-29 03:21:04,359 INFO L87 Difference]: Start difference. First operand has 2039 states, 2038 states have (on average 1.4921491658488715) internal successors, (3041), 2038 states have internal predecessors, (3041), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 2 states, 2 states have (on average 79.5) internal successors, (159), 2 states have internal predecessors, (159), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:04,433 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:04,433 INFO L93 Difference]: Finished difference Result 2037 states and 3006 transitions. [2023-11-29 03:21:04,434 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2037 states and 3006 transitions. [2023-11-29 03:21:04,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:04,479 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2037 states to 2032 states and 3001 transitions. [2023-11-29 03:21:04,480 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:04,484 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:04,485 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 3001 transitions. [2023-11-29 03:21:04,494 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:04,495 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3001 transitions. [2023-11-29 03:21:04,516 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 3001 transitions. [2023-11-29 03:21:04,584 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:04,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4768700787401574) internal successors, (3001), 2031 states have internal predecessors, (3001), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:04,600 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 3001 transitions. [2023-11-29 03:21:04,601 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3001 transitions. [2023-11-29 03:21:04,602 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 2 states. [2023-11-29 03:21:04,605 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 3001 transitions. [2023-11-29 03:21:04,605 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 03:21:04,606 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 3001 transitions. [2023-11-29 03:21:04,620 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:04,620 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:04,620 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:04,624 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:04,624 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:04,625 INFO L748 eck$LassoCheckResult]: Stem: 4416#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4417#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5403#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5404#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6103#L902 assume !(1 == ~m_i~0);~m_st~0 := 2; 4997#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4998#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 5068#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5069#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5506#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5507#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5032#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4837#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4838#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5296#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5297#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 5176#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 5177#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 4811#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4812#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 6027#L1279-2 assume !(0 == ~T1_E~0); 4437#L1284-1 assume !(0 == ~T2_E~0); 4438#L1289-1 assume !(0 == ~T3_E~0); 5173#L1294-1 assume !(0 == ~T4_E~0); 5174#L1299-1 assume !(0 == ~T5_E~0); 5185#L1304-1 assume !(0 == ~T6_E~0); 6102#L1309-1 assume !(0 == ~T7_E~0); 6104#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4361#L1319-1 assume !(0 == ~T9_E~0); 4362#L1324-1 assume !(0 == ~T10_E~0); 4535#L1329-1 assume !(0 == ~T11_E~0); 4536#L1334-1 assume !(0 == ~T12_E~0); 5945#L1339-1 assume !(0 == ~T13_E~0); 6017#L1344-1 assume !(0 == ~E_M~0); 6018#L1349-1 assume !(0 == ~E_1~0); 5362#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 5363#L1359-1 assume !(0 == ~E_3~0); 5770#L1364-1 assume !(0 == ~E_4~0); 4661#L1369-1 assume !(0 == ~E_5~0); 4662#L1374-1 assume !(0 == ~E_6~0); 5369#L1379-1 assume !(0 == ~E_7~0); 5370#L1384-1 assume !(0 == ~E_8~0); 5447#L1389-1 assume !(0 == ~E_9~0); 5964#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 5965#L1399-1 assume !(0 == ~E_11~0); 6058#L1404-1 assume !(0 == ~E_12~0); 4759#L1409-1 assume !(0 == ~E_13~0); 4760#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6053#L628 assume !(1 == ~m_pc~0); 4660#L628-2 is_master_triggered_~__retres1~0#1 := 0; 4659#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5244#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5245#L1591 assume !(0 != activate_threads_~tmp~1#1); 6066#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5225#L647 assume 1 == ~t1_pc~0; 4585#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4586#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5276#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5733#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 6005#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6006#L666 assume 1 == ~t2_pc~0; 4434#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4435#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4576#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4577#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 5558#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5559#L685 assume !(1 == ~t3_pc~0); 5653#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5652#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5722#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5411#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5412#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4885#L704 assume 1 == ~t4_pc~0; 4886#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5423#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4225#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4226#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 5274#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5275#L723 assume !(1 == ~t5_pc~0); 5407#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5625#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5763#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5537#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 5538#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4643#L742 assume 1 == ~t6_pc~0; 4644#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4800#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4567#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4330#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 4331#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4721#L761 assume !(1 == ~t7_pc~0); 4722#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4597#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4598#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5414#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 5415#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4353#L780 assume 1 == ~t8_pc~0; 4354#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4633#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4634#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5376#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 5377#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5493#L799 assume 1 == ~t9_pc~0; 5595#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4356#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4357#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4628#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 5696#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5519#L818 assume !(1 == ~t10_pc~0); 4140#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4141#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5588#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5522#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5523#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5565#L837 assume 1 == ~t11_pc~0; 5566#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 5401#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 6009#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5486#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 5487#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5233#L856 assume !(1 == ~t12_pc~0); 5234#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5868#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4158#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4159#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 5846#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 6030#L875 assume 1 == ~t13_pc~0; 5183#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 4801#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4802#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4739#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 4740#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5587#L1427 assume !(1 == ~M_E~0); 5572#L1427-2 assume !(1 == ~T1_E~0); 4708#L1432-1 assume !(1 == ~T2_E~0); 4709#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5775#L1442-1 assume !(1 == ~T4_E~0); 5776#L1447-1 assume !(1 == ~T5_E~0); 5634#L1452-1 assume !(1 == ~T6_E~0); 4277#L1457-1 assume !(1 == ~T7_E~0); 4278#L1462-1 assume !(1 == ~T8_E~0); 5793#L1467-1 assume !(1 == ~T9_E~0); 5814#L1472-1 assume !(1 == ~T10_E~0); 5815#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 5583#L1482-1 assume !(1 == ~T12_E~0); 5584#L1487-1 assume !(1 == ~T13_E~0); 4608#L1492-1 assume !(1 == ~E_M~0); 4609#L1497-1 assume !(1 == ~E_1~0); 4979#L1502-1 assume !(1 == ~E_2~0); 4980#L1507-1 assume !(1 == ~E_3~0); 4485#L1512-1 assume !(1 == ~E_4~0); 4486#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5887#L1522-1 assume !(1 == ~E_6~0); 5222#L1527-1 assume !(1 == ~E_7~0); 5223#L1532-1 assume !(1 == ~E_8~0); 6088#L1537-1 assume !(1 == ~E_9~0); 5430#L1542-1 assume !(1 == ~E_10~0); 5251#L1547-1 assume !(1 == ~E_11~0); 5252#L1552-1 assume !(1 == ~E_12~0); 4181#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 4182#L1562-1 assume { :end_inline_reset_delta_events } true; 4791#L1928-2 [2023-11-29 03:21:04,626 INFO L750 eck$LassoCheckResult]: Loop: 4791#L1928-2 assume !false; 5289#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4866#L1254-1 assume !false; 5098#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4510#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4511#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4710#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5873#L1067 assume !(0 != eval_~tmp~0#1); 5163#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4768#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4769#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4999#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4983#L1284-3 assume !(0 == ~T2_E~0); 4984#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4964#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4965#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5357#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5358#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4845#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4846#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5836#L1324-3 assume !(0 == ~T10_E~0); 4483#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4484#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5257#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5258#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5562#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4829#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4830#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5570#L1364-3 assume !(0 == ~E_4~0); 6087#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5979#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4612#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4613#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4827#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4828#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5134#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5989#L1404-3 assume !(0 == ~E_12~0); 5954#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5955#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5459#L628-45 assume 1 == ~m_pc~0; 5129#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5131#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5642#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4863#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4864#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5594#L647-45 assume !(1 == ~t1_pc~0); 4433#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 4432#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5375#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4541#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4542#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4752#L666-45 assume !(1 == ~t2_pc~0); 4753#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5243#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5640#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5641#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5706#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4293#L685-45 assume 1 == ~t3_pc~0; 4294#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5371#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6019#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5885#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5886#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6028#L704-45 assume !(1 == ~t4_pc~0); 4160#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 4161#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5029#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5910#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6116#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5488#L723-45 assume !(1 == ~t5_pc~0); 5489#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 5966#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6078#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4841#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 4842#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5856#L742-45 assume 1 == ~t6_pc~0; 5857#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5106#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5316#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5317#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5599#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5685#L761-45 assume !(1 == ~t7_pc~0); 5686#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 5100#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5101#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4489#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4490#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5958#L780-45 assume 1 == ~t8_pc~0; 4867#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 4500#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4501#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 6085#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4469#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4470#L799-45 assume !(1 == ~t9_pc~0); 4688#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 4689#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5751#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5635#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5636#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4411#L818-45 assume 1 == ~t10_pc~0; 4412#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 4529#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5612#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5027#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5028#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5731#L837-45 assume !(1 == ~t11_pc~0); 4957#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4958#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4481#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4482#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4550#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4551#L856-45 assume !(1 == ~t12_pc~0); 4552#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 4553#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5782#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5783#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5373#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5374#L875-45 assume 1 == ~t13_pc~0; 5341#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 5342#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5402#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5743#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5999#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5943#L1427-3 assume !(1 == ~M_E~0); 5168#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5169#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5693#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5360#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5361#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4198#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4199#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5871#L1462-3 assume !(1 == ~T8_E~0); 5872#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5739#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5740#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4453#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4454#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4596#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4766#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4767#L1502-3 assume !(1 == ~E_2~0); 5713#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5834#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4805#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4493#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4494#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4460#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4461#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5571#L1542-3 assume !(1 == ~E_10~0); 5699#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5344#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5345#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4664#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4665#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4086#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4523#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4524#L1947 assume !(0 == start_simulation_~tmp~3#1); 5477#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5667#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4725#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 4149#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5802#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5803#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5963#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 4791#L1928-2 [2023-11-29 03:21:04,626 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:04,627 INFO L85 PathProgramCache]: Analyzing trace with hash 1878318605, now seen corresponding path program 2 times [2023-11-29 03:21:04,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:04,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1109128388] [2023-11-29 03:21:04,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:04,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:04,651 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:04,711 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:04,712 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:04,712 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1109128388] [2023-11-29 03:21:04,712 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1109128388] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:04,713 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:04,713 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:04,713 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1425790936] [2023-11-29 03:21:04,713 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:04,714 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:04,714 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:04,715 INFO L85 PathProgramCache]: Analyzing trace with hash 225054192, now seen corresponding path program 1 times [2023-11-29 03:21:04,715 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:04,715 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1893948379] [2023-11-29 03:21:04,715 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:04,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:04,771 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:04,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:04,850 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:04,850 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1893948379] [2023-11-29 03:21:04,850 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1893948379] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:04,851 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:04,851 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:04,851 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [586800689] [2023-11-29 03:21:04,851 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:04,852 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:04,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:04,853 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:04,853 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:04,854 INFO L87 Difference]: Start difference. First operand 2032 states and 3001 transitions. cyclomatic complexity: 970 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:04,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:04,920 INFO L93 Difference]: Finished difference Result 2032 states and 3000 transitions. [2023-11-29 03:21:04,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 3000 transitions. [2023-11-29 03:21:04,938 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:04,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 3000 transitions. [2023-11-29 03:21:04,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:04,957 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:04,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 3000 transitions. [2023-11-29 03:21:04,960 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:04,961 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3000 transitions. [2023-11-29 03:21:04,966 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 3000 transitions. [2023-11-29 03:21:04,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:05,001 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4763779527559056) internal successors, (3000), 2031 states have internal predecessors, (3000), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:05,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 3000 transitions. [2023-11-29 03:21:05,010 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 3000 transitions. [2023-11-29 03:21:05,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:05,011 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 3000 transitions. [2023-11-29 03:21:05,011 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 03:21:05,012 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 3000 transitions. [2023-11-29 03:21:05,025 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:05,025 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:05,026 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:05,029 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:05,029 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:05,030 INFO L748 eck$LassoCheckResult]: Stem: 8487#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8488#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9474#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9475#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10174#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 9068#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9069#L907-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 9139#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 9140#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 9577#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9578#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9103#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8908#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8909#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9367#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 9368#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 9247#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 9248#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 8882#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8883#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 10098#L1279-2 assume !(0 == ~T1_E~0); 8508#L1284-1 assume !(0 == ~T2_E~0); 8509#L1289-1 assume !(0 == ~T3_E~0); 9244#L1294-1 assume !(0 == ~T4_E~0); 9245#L1299-1 assume !(0 == ~T5_E~0); 9256#L1304-1 assume !(0 == ~T6_E~0); 10173#L1309-1 assume !(0 == ~T7_E~0); 10175#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8432#L1319-1 assume !(0 == ~T9_E~0); 8433#L1324-1 assume !(0 == ~T10_E~0); 8606#L1329-1 assume !(0 == ~T11_E~0); 8607#L1334-1 assume !(0 == ~T12_E~0); 10016#L1339-1 assume !(0 == ~T13_E~0); 10088#L1344-1 assume !(0 == ~E_M~0); 10089#L1349-1 assume !(0 == ~E_1~0); 9433#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 9434#L1359-1 assume !(0 == ~E_3~0); 9841#L1364-1 assume !(0 == ~E_4~0); 8732#L1369-1 assume !(0 == ~E_5~0); 8733#L1374-1 assume !(0 == ~E_6~0); 9440#L1379-1 assume !(0 == ~E_7~0); 9441#L1384-1 assume !(0 == ~E_8~0); 9518#L1389-1 assume !(0 == ~E_9~0); 10035#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 10036#L1399-1 assume !(0 == ~E_11~0); 10129#L1404-1 assume !(0 == ~E_12~0); 8830#L1409-1 assume !(0 == ~E_13~0); 8831#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10124#L628 assume !(1 == ~m_pc~0); 8731#L628-2 is_master_triggered_~__retres1~0#1 := 0; 8730#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9315#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9316#L1591 assume !(0 != activate_threads_~tmp~1#1); 10137#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9296#L647 assume 1 == ~t1_pc~0; 8656#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8657#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9347#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9804#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 10076#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10077#L666 assume 1 == ~t2_pc~0; 8505#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8506#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8647#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8648#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 9629#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9630#L685 assume !(1 == ~t3_pc~0); 9724#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9723#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9793#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9482#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9483#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8956#L704 assume 1 == ~t4_pc~0; 8957#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9494#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8296#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8297#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 9345#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9346#L723 assume !(1 == ~t5_pc~0); 9478#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9696#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9834#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9608#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 9609#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8714#L742 assume 1 == ~t6_pc~0; 8715#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8871#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8638#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8401#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 8402#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8792#L761 assume !(1 == ~t7_pc~0); 8793#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8668#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8669#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9485#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 9486#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8424#L780 assume 1 == ~t8_pc~0; 8425#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8704#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8705#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9447#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 9448#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9564#L799 assume 1 == ~t9_pc~0; 9666#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8427#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8428#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8699#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 9767#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9590#L818 assume !(1 == ~t10_pc~0); 8211#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8212#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9659#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9593#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9594#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9636#L837 assume 1 == ~t11_pc~0; 9637#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 9472#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 10080#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9557#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 9558#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9304#L856 assume !(1 == ~t12_pc~0); 9305#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9939#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8229#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8230#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 9917#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 10101#L875 assume 1 == ~t13_pc~0; 9254#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 8872#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8873#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8810#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 8811#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9658#L1427 assume !(1 == ~M_E~0); 9643#L1427-2 assume !(1 == ~T1_E~0); 8779#L1432-1 assume !(1 == ~T2_E~0); 8780#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9846#L1442-1 assume !(1 == ~T4_E~0); 9847#L1447-1 assume !(1 == ~T5_E~0); 9705#L1452-1 assume !(1 == ~T6_E~0); 8348#L1457-1 assume !(1 == ~T7_E~0); 8349#L1462-1 assume !(1 == ~T8_E~0); 9864#L1467-1 assume !(1 == ~T9_E~0); 9885#L1472-1 assume !(1 == ~T10_E~0); 9886#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 9654#L1482-1 assume !(1 == ~T12_E~0); 9655#L1487-1 assume !(1 == ~T13_E~0); 8679#L1492-1 assume !(1 == ~E_M~0); 8680#L1497-1 assume !(1 == ~E_1~0); 9050#L1502-1 assume !(1 == ~E_2~0); 9051#L1507-1 assume !(1 == ~E_3~0); 8556#L1512-1 assume !(1 == ~E_4~0); 8557#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 9958#L1522-1 assume !(1 == ~E_6~0); 9293#L1527-1 assume !(1 == ~E_7~0); 9294#L1532-1 assume !(1 == ~E_8~0); 10159#L1537-1 assume !(1 == ~E_9~0); 9501#L1542-1 assume !(1 == ~E_10~0); 9322#L1547-1 assume !(1 == ~E_11~0); 9323#L1552-1 assume !(1 == ~E_12~0); 8252#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 8253#L1562-1 assume { :end_inline_reset_delta_events } true; 8862#L1928-2 [2023-11-29 03:21:05,030 INFO L750 eck$LassoCheckResult]: Loop: 8862#L1928-2 assume !false; 9360#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8937#L1254-1 assume !false; 9169#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8581#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8582#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8781#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9944#L1067 assume !(0 != eval_~tmp~0#1); 9234#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8839#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8840#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9070#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9054#L1284-3 assume !(0 == ~T2_E~0); 9055#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9035#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9036#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9428#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9429#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8916#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 8917#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9907#L1324-3 assume !(0 == ~T10_E~0); 8554#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 8555#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 9328#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9329#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9633#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8900#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8901#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9641#L1364-3 assume !(0 == ~E_4~0); 10158#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10050#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8683#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8684#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8898#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8899#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9205#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 10060#L1404-3 assume !(0 == ~E_12~0); 10025#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 10026#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9530#L628-45 assume 1 == ~m_pc~0; 9200#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 9202#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9713#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8934#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8935#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9665#L647-45 assume 1 == ~t1_pc~0; 8502#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8503#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9446#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8612#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8613#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8823#L666-45 assume !(1 == ~t2_pc~0); 8824#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 9314#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9711#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9712#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9777#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8364#L685-45 assume 1 == ~t3_pc~0; 8365#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9442#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10090#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9956#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9957#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10099#L704-45 assume !(1 == ~t4_pc~0); 8231#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 8232#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9100#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9981#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10187#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9559#L723-45 assume !(1 == ~t5_pc~0); 9560#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 10037#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10149#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8912#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 8913#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9927#L742-45 assume 1 == ~t6_pc~0; 9928#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9177#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9387#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9388#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9670#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9756#L761-45 assume !(1 == ~t7_pc~0); 9757#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 9171#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9172#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8560#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8561#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10029#L780-45 assume 1 == ~t8_pc~0; 8938#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8571#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8572#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 10156#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8540#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8541#L799-45 assume !(1 == ~t9_pc~0); 8759#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 8760#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9822#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9706#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9707#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8482#L818-45 assume 1 == ~t10_pc~0; 8483#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8600#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9683#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9098#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9099#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9802#L837-45 assume !(1 == ~t11_pc~0); 9028#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 9029#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8552#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8553#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8621#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8622#L856-45 assume 1 == ~t12_pc~0; 10097#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 8624#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9853#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9854#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9444#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9445#L875-45 assume 1 == ~t13_pc~0; 9412#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 9413#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9473#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9814#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 10070#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10014#L1427-3 assume !(1 == ~M_E~0); 9239#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9240#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9764#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9431#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9432#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8269#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8270#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9942#L1462-3 assume !(1 == ~T8_E~0); 9943#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9810#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9811#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 8524#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8525#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8667#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8837#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8838#L1502-3 assume !(1 == ~E_2~0); 9784#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9905#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8876#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8564#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8565#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8531#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8532#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9642#L1542-3 assume !(1 == ~E_10~0); 9770#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9415#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9416#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8735#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8736#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8157#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8594#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8595#L1947 assume !(0 == start_simulation_~tmp~3#1); 9548#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9738#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8796#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8219#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 8220#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9873#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9874#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 10034#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 8862#L1928-2 [2023-11-29 03:21:05,031 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:05,031 INFO L85 PathProgramCache]: Analyzing trace with hash 1533490443, now seen corresponding path program 1 times [2023-11-29 03:21:05,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:05,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [270105336] [2023-11-29 03:21:05,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:05,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:05,051 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:05,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:05,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:05,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [270105336] [2023-11-29 03:21:05,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [270105336] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:05,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:05,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:05,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2020620936] [2023-11-29 03:21:05,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:05,102 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:05,103 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:05,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1923928238, now seen corresponding path program 1 times [2023-11-29 03:21:05,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:05,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1082720825] [2023-11-29 03:21:05,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:05,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:05,124 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:05,220 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:05,221 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:05,221 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1082720825] [2023-11-29 03:21:05,221 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1082720825] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:05,221 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:05,221 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:05,222 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858095823] [2023-11-29 03:21:05,222 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:05,222 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:05,222 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:05,223 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:05,223 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:05,223 INFO L87 Difference]: Start difference. First operand 2032 states and 3000 transitions. cyclomatic complexity: 969 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:05,282 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:05,282 INFO L93 Difference]: Finished difference Result 2032 states and 2999 transitions. [2023-11-29 03:21:05,282 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2999 transitions. [2023-11-29 03:21:05,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:05,315 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2999 transitions. [2023-11-29 03:21:05,315 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:05,317 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:05,317 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2999 transitions. [2023-11-29 03:21:05,321 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:05,321 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2999 transitions. [2023-11-29 03:21:05,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2999 transitions. [2023-11-29 03:21:05,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:05,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4758858267716535) internal successors, (2999), 2031 states have internal predecessors, (2999), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:05,368 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2999 transitions. [2023-11-29 03:21:05,369 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2999 transitions. [2023-11-29 03:21:05,369 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:05,370 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2999 transitions. [2023-11-29 03:21:05,370 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 03:21:05,370 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2999 transitions. [2023-11-29 03:21:05,383 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:05,383 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:05,383 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:05,386 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:05,387 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:05,387 INFO L748 eck$LassoCheckResult]: Stem: 12558#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12559#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 13545#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13546#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14245#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 13139#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13140#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13210#L912-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 13211#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 13648#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 13649#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 13174#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12979#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 12980#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13438#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13439#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 13318#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 13319#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 12953#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12954#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 14169#L1279-2 assume !(0 == ~T1_E~0); 12579#L1284-1 assume !(0 == ~T2_E~0); 12580#L1289-1 assume !(0 == ~T3_E~0); 13315#L1294-1 assume !(0 == ~T4_E~0); 13316#L1299-1 assume !(0 == ~T5_E~0); 13327#L1304-1 assume !(0 == ~T6_E~0); 14244#L1309-1 assume !(0 == ~T7_E~0); 14246#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12503#L1319-1 assume !(0 == ~T9_E~0); 12504#L1324-1 assume !(0 == ~T10_E~0); 12677#L1329-1 assume !(0 == ~T11_E~0); 12678#L1334-1 assume !(0 == ~T12_E~0); 14087#L1339-1 assume !(0 == ~T13_E~0); 14159#L1344-1 assume !(0 == ~E_M~0); 14160#L1349-1 assume !(0 == ~E_1~0); 13504#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 13505#L1359-1 assume !(0 == ~E_3~0); 13912#L1364-1 assume !(0 == ~E_4~0); 12803#L1369-1 assume !(0 == ~E_5~0); 12804#L1374-1 assume !(0 == ~E_6~0); 13511#L1379-1 assume !(0 == ~E_7~0); 13512#L1384-1 assume !(0 == ~E_8~0); 13589#L1389-1 assume !(0 == ~E_9~0); 14106#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 14107#L1399-1 assume !(0 == ~E_11~0); 14200#L1404-1 assume !(0 == ~E_12~0); 12901#L1409-1 assume !(0 == ~E_13~0); 12902#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14195#L628 assume !(1 == ~m_pc~0); 12802#L628-2 is_master_triggered_~__retres1~0#1 := 0; 12801#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13386#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13387#L1591 assume !(0 != activate_threads_~tmp~1#1); 14208#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13367#L647 assume 1 == ~t1_pc~0; 12727#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12728#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13418#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13875#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 14147#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14148#L666 assume 1 == ~t2_pc~0; 12576#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12577#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12718#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12719#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 13700#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13701#L685 assume !(1 == ~t3_pc~0); 13795#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13794#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13864#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13553#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13554#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13027#L704 assume 1 == ~t4_pc~0; 13028#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13565#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12367#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12368#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 13416#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13417#L723 assume !(1 == ~t5_pc~0); 13549#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13767#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13905#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13679#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 13680#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12785#L742 assume 1 == ~t6_pc~0; 12786#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12942#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12709#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12472#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 12473#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12863#L761 assume !(1 == ~t7_pc~0); 12864#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12739#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12740#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13556#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 13557#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12495#L780 assume 1 == ~t8_pc~0; 12496#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12775#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12776#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13518#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 13519#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13635#L799 assume 1 == ~t9_pc~0; 13737#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12498#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12499#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12770#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 13838#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13661#L818 assume !(1 == ~t10_pc~0); 12282#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12283#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13730#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13664#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13665#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13707#L837 assume 1 == ~t11_pc~0; 13708#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 13543#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 14151#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13628#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 13629#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13375#L856 assume !(1 == ~t12_pc~0); 13376#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 14010#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12300#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12301#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 13988#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 14172#L875 assume 1 == ~t13_pc~0; 13325#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 12943#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12944#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12881#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 12882#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13729#L1427 assume !(1 == ~M_E~0); 13714#L1427-2 assume !(1 == ~T1_E~0); 12850#L1432-1 assume !(1 == ~T2_E~0); 12851#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13917#L1442-1 assume !(1 == ~T4_E~0); 13918#L1447-1 assume !(1 == ~T5_E~0); 13776#L1452-1 assume !(1 == ~T6_E~0); 12419#L1457-1 assume !(1 == ~T7_E~0); 12420#L1462-1 assume !(1 == ~T8_E~0); 13935#L1467-1 assume !(1 == ~T9_E~0); 13956#L1472-1 assume !(1 == ~T10_E~0); 13957#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 13725#L1482-1 assume !(1 == ~T12_E~0); 13726#L1487-1 assume !(1 == ~T13_E~0); 12750#L1492-1 assume !(1 == ~E_M~0); 12751#L1497-1 assume !(1 == ~E_1~0); 13121#L1502-1 assume !(1 == ~E_2~0); 13122#L1507-1 assume !(1 == ~E_3~0); 12627#L1512-1 assume !(1 == ~E_4~0); 12628#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 14029#L1522-1 assume !(1 == ~E_6~0); 13364#L1527-1 assume !(1 == ~E_7~0); 13365#L1532-1 assume !(1 == ~E_8~0); 14230#L1537-1 assume !(1 == ~E_9~0); 13572#L1542-1 assume !(1 == ~E_10~0); 13393#L1547-1 assume !(1 == ~E_11~0); 13394#L1552-1 assume !(1 == ~E_12~0); 12323#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 12324#L1562-1 assume { :end_inline_reset_delta_events } true; 12933#L1928-2 [2023-11-29 03:21:05,388 INFO L750 eck$LassoCheckResult]: Loop: 12933#L1928-2 assume !false; 13431#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13008#L1254-1 assume !false; 13240#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12652#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12653#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12852#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 14015#L1067 assume !(0 != eval_~tmp~0#1); 13305#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12910#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12911#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13141#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13125#L1284-3 assume !(0 == ~T2_E~0); 13126#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13106#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13107#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13499#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13500#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12987#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12988#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13978#L1324-3 assume !(0 == ~T10_E~0); 12625#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 12626#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13399#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13400#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13704#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12971#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12972#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13712#L1364-3 assume !(0 == ~E_4~0); 14229#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14121#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12754#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12755#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12969#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 12970#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 13276#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 14131#L1404-3 assume !(0 == ~E_12~0); 14096#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 14097#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13601#L628-45 assume 1 == ~m_pc~0; 13271#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 13273#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13784#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13005#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13006#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13736#L647-45 assume 1 == ~t1_pc~0; 12573#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12574#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13517#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12683#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12684#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12894#L666-45 assume 1 == ~t2_pc~0; 12896#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13385#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13782#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13783#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13848#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12435#L685-45 assume 1 == ~t3_pc~0; 12436#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13513#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14161#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14027#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14028#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14170#L704-45 assume 1 == ~t4_pc~0; 14051#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12303#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13171#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 14052#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14258#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13630#L723-45 assume 1 == ~t5_pc~0; 13632#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14108#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14220#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12983#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 12984#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13998#L742-45 assume 1 == ~t6_pc~0; 13999#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13248#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13458#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13459#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13741#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13827#L761-45 assume !(1 == ~t7_pc~0); 13828#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 13242#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13243#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12631#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12632#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 14100#L780-45 assume 1 == ~t8_pc~0; 13009#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12642#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12643#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 14227#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12611#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12612#L799-45 assume 1 == ~t9_pc~0; 13397#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12831#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13893#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13777#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13778#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12553#L818-45 assume 1 == ~t10_pc~0; 12554#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 12671#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13754#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13169#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13170#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13873#L837-45 assume !(1 == ~t11_pc~0); 13099#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 13100#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12623#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12624#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 12692#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12693#L856-45 assume !(1 == ~t12_pc~0); 12694#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 12695#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13924#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13925#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13515#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13516#L875-45 assume 1 == ~t13_pc~0; 13483#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 13484#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13544#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13885#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 14141#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14085#L1427-3 assume !(1 == ~M_E~0); 13310#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13311#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13835#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13502#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13503#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12340#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12341#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14013#L1462-3 assume !(1 == ~T8_E~0); 14014#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13881#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13882#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 12595#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 12596#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 12738#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 12908#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12909#L1502-3 assume !(1 == ~E_2~0); 13855#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13976#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12947#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12635#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12636#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12602#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12603#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13713#L1542-3 assume !(1 == ~E_10~0); 13841#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 13486#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 13487#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 12806#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12807#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12228#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12665#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12666#L1947 assume !(0 == start_simulation_~tmp~3#1); 13619#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 13809#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12867#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12290#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 12291#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13944#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13945#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 14105#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 12933#L1928-2 [2023-11-29 03:21:05,388 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:05,388 INFO L85 PathProgramCache]: Analyzing trace with hash -992005239, now seen corresponding path program 1 times [2023-11-29 03:21:05,389 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:05,389 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1664654490] [2023-11-29 03:21:05,389 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:05,389 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:05,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:05,451 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:05,451 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:05,451 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1664654490] [2023-11-29 03:21:05,451 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1664654490] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:05,451 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:05,452 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:05,452 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1952071020] [2023-11-29 03:21:05,452 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:05,452 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:05,453 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:05,453 INFO L85 PathProgramCache]: Analyzing trace with hash -549053589, now seen corresponding path program 1 times [2023-11-29 03:21:05,453 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:05,453 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [826734721] [2023-11-29 03:21:05,453 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:05,454 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:05,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:05,534 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:05,534 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:05,534 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [826734721] [2023-11-29 03:21:05,534 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [826734721] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:05,535 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:05,535 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:05,535 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [716915808] [2023-11-29 03:21:05,535 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:05,536 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:05,536 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:05,536 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:05,536 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:05,537 INFO L87 Difference]: Start difference. First operand 2032 states and 2999 transitions. cyclomatic complexity: 968 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:05,592 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:05,592 INFO L93 Difference]: Finished difference Result 2032 states and 2998 transitions. [2023-11-29 03:21:05,592 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2998 transitions. [2023-11-29 03:21:05,609 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:05,643 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2998 transitions. [2023-11-29 03:21:05,643 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:05,645 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:05,646 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2998 transitions. [2023-11-29 03:21:05,650 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:05,650 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2998 transitions. [2023-11-29 03:21:05,655 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2998 transitions. [2023-11-29 03:21:05,690 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:05,695 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4753937007874016) internal successors, (2998), 2031 states have internal predecessors, (2998), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:05,706 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2998 transitions. [2023-11-29 03:21:05,706 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2998 transitions. [2023-11-29 03:21:05,707 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:05,708 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2998 transitions. [2023-11-29 03:21:05,708 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 03:21:05,708 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2998 transitions. [2023-11-29 03:21:05,721 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:05,721 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:05,722 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:05,725 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:05,726 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:05,726 INFO L748 eck$LassoCheckResult]: Stem: 16629#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 16630#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 17616#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17617#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18316#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 17210#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17211#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17281#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17282#L917-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 17719#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 17720#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 17245#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 17050#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 17051#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 17509#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 17510#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 17389#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 17390#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 17024#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17025#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 18240#L1279-2 assume !(0 == ~T1_E~0); 16650#L1284-1 assume !(0 == ~T2_E~0); 16651#L1289-1 assume !(0 == ~T3_E~0); 17386#L1294-1 assume !(0 == ~T4_E~0); 17387#L1299-1 assume !(0 == ~T5_E~0); 17398#L1304-1 assume !(0 == ~T6_E~0); 18315#L1309-1 assume !(0 == ~T7_E~0); 18317#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16574#L1319-1 assume !(0 == ~T9_E~0); 16575#L1324-1 assume !(0 == ~T10_E~0); 16748#L1329-1 assume !(0 == ~T11_E~0); 16749#L1334-1 assume !(0 == ~T12_E~0); 18158#L1339-1 assume !(0 == ~T13_E~0); 18230#L1344-1 assume !(0 == ~E_M~0); 18231#L1349-1 assume !(0 == ~E_1~0); 17575#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 17576#L1359-1 assume !(0 == ~E_3~0); 17983#L1364-1 assume !(0 == ~E_4~0); 16874#L1369-1 assume !(0 == ~E_5~0); 16875#L1374-1 assume !(0 == ~E_6~0); 17582#L1379-1 assume !(0 == ~E_7~0); 17583#L1384-1 assume !(0 == ~E_8~0); 17660#L1389-1 assume !(0 == ~E_9~0); 18177#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 18178#L1399-1 assume !(0 == ~E_11~0); 18271#L1404-1 assume !(0 == ~E_12~0); 16972#L1409-1 assume !(0 == ~E_13~0); 16973#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18266#L628 assume !(1 == ~m_pc~0); 16873#L628-2 is_master_triggered_~__retres1~0#1 := 0; 16872#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17457#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17458#L1591 assume !(0 != activate_threads_~tmp~1#1); 18279#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17438#L647 assume 1 == ~t1_pc~0; 16798#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16799#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17489#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17946#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 18218#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18219#L666 assume 1 == ~t2_pc~0; 16647#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16648#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16789#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16790#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 17771#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17772#L685 assume !(1 == ~t3_pc~0); 17866#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17865#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17935#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 17624#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17625#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17098#L704 assume 1 == ~t4_pc~0; 17099#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17636#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16438#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16439#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 17487#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17488#L723 assume !(1 == ~t5_pc~0); 17620#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17838#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17976#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17750#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 17751#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16856#L742 assume 1 == ~t6_pc~0; 16857#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17013#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16780#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16543#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 16544#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16934#L761 assume !(1 == ~t7_pc~0); 16935#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16810#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16811#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 17627#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 17628#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16566#L780 assume 1 == ~t8_pc~0; 16567#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16846#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16847#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 17589#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 17590#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 17706#L799 assume 1 == ~t9_pc~0; 17808#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 16569#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16570#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 16841#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 17909#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 17732#L818 assume !(1 == ~t10_pc~0); 16353#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 16354#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17801#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17735#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17736#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17778#L837 assume 1 == ~t11_pc~0; 17779#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 17614#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 18222#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 17699#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 17700#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 17446#L856 assume !(1 == ~t12_pc~0); 17447#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 18081#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 16371#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 16372#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 18059#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 18243#L875 assume 1 == ~t13_pc~0; 17396#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17014#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17015#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 16952#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 16953#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17800#L1427 assume !(1 == ~M_E~0); 17785#L1427-2 assume !(1 == ~T1_E~0); 16921#L1432-1 assume !(1 == ~T2_E~0); 16922#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17988#L1442-1 assume !(1 == ~T4_E~0); 17989#L1447-1 assume !(1 == ~T5_E~0); 17847#L1452-1 assume !(1 == ~T6_E~0); 16490#L1457-1 assume !(1 == ~T7_E~0); 16491#L1462-1 assume !(1 == ~T8_E~0); 18006#L1467-1 assume !(1 == ~T9_E~0); 18027#L1472-1 assume !(1 == ~T10_E~0); 18028#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 17796#L1482-1 assume !(1 == ~T12_E~0); 17797#L1487-1 assume !(1 == ~T13_E~0); 16821#L1492-1 assume !(1 == ~E_M~0); 16822#L1497-1 assume !(1 == ~E_1~0); 17192#L1502-1 assume !(1 == ~E_2~0); 17193#L1507-1 assume !(1 == ~E_3~0); 16698#L1512-1 assume !(1 == ~E_4~0); 16699#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 18100#L1522-1 assume !(1 == ~E_6~0); 17435#L1527-1 assume !(1 == ~E_7~0); 17436#L1532-1 assume !(1 == ~E_8~0); 18301#L1537-1 assume !(1 == ~E_9~0); 17643#L1542-1 assume !(1 == ~E_10~0); 17464#L1547-1 assume !(1 == ~E_11~0); 17465#L1552-1 assume !(1 == ~E_12~0); 16394#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 16395#L1562-1 assume { :end_inline_reset_delta_events } true; 17004#L1928-2 [2023-11-29 03:21:05,727 INFO L750 eck$LassoCheckResult]: Loop: 17004#L1928-2 assume !false; 17502#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17079#L1254-1 assume !false; 17311#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16723#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16724#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16923#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 18086#L1067 assume !(0 != eval_~tmp~0#1); 17376#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16981#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16982#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17212#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 17196#L1284-3 assume !(0 == ~T2_E~0); 17197#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17177#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17178#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17570#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17571#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17058#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17059#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18049#L1324-3 assume !(0 == ~T10_E~0); 16696#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 16697#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 17470#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 17471#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 17775#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17042#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17043#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 17783#L1364-3 assume !(0 == ~E_4~0); 18300#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18192#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16825#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 16826#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 17040#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17041#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 17347#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 18202#L1404-3 assume !(0 == ~E_12~0); 18167#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 18168#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17672#L628-45 assume 1 == ~m_pc~0; 17342#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 17344#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17855#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17076#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17077#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17807#L647-45 assume 1 == ~t1_pc~0; 16644#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16645#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17588#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16754#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16755#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16965#L666-45 assume !(1 == ~t2_pc~0); 16966#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 17456#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17853#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17854#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17919#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16506#L685-45 assume 1 == ~t3_pc~0; 16507#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17584#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18232#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18098#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18099#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18241#L704-45 assume !(1 == ~t4_pc~0); 16373#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 16374#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17242#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18123#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18329#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17701#L723-45 assume !(1 == ~t5_pc~0); 17702#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 18179#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18291#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 17054#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 17055#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18069#L742-45 assume 1 == ~t6_pc~0; 18070#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17319#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17529#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 17530#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17812#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17898#L761-45 assume !(1 == ~t7_pc~0); 17899#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 17313#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17314#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 16702#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16703#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18171#L780-45 assume 1 == ~t8_pc~0; 17080#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16713#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16714#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 18298#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16682#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16683#L799-45 assume !(1 == ~t9_pc~0); 16901#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 16902#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17964#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 17848#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17849#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16624#L818-45 assume 1 == ~t10_pc~0; 16625#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16742#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 17825#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 17240#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 17241#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 17944#L837-45 assume !(1 == ~t11_pc~0); 17170#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 17171#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 16694#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 16695#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 16763#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 16764#L856-45 assume !(1 == ~t12_pc~0); 16765#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 16766#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 17995#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 17996#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 17586#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 17587#L875-45 assume 1 == ~t13_pc~0; 17554#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 17555#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 17615#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 17956#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 18212#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18156#L1427-3 assume !(1 == ~M_E~0); 17381#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17382#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17906#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17573#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17574#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16411#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16412#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18084#L1462-3 assume !(1 == ~T8_E~0); 18085#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 17952#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 17953#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 16666#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 16667#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 16809#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 16979#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16980#L1502-3 assume !(1 == ~E_2~0); 17926#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18047#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 17018#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16706#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16707#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16673#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16674#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17784#L1542-3 assume !(1 == ~E_10~0); 17912#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 17557#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 17558#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 16877#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 16878#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16299#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16736#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 16737#L1947 assume !(0 == start_simulation_~tmp~3#1); 17690#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 17880#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 16938#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 16361#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 16362#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18015#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18016#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 18176#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 17004#L1928-2 [2023-11-29 03:21:05,728 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:05,728 INFO L85 PathProgramCache]: Analyzing trace with hash -380736181, now seen corresponding path program 1 times [2023-11-29 03:21:05,728 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:05,728 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123403868] [2023-11-29 03:21:05,729 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:05,729 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:05,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:05,800 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:05,800 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:05,800 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123403868] [2023-11-29 03:21:05,801 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123403868] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:05,801 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:05,801 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:05,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [594382929] [2023-11-29 03:21:05,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:05,802 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:05,802 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:05,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1650149743, now seen corresponding path program 1 times [2023-11-29 03:21:05,803 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:05,803 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [798851279] [2023-11-29 03:21:05,803 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:05,803 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:05,831 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:05,900 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:05,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:05,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [798851279] [2023-11-29 03:21:05,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [798851279] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:05,900 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:05,901 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:05,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1344728249] [2023-11-29 03:21:05,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:05,901 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:05,902 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:05,902 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:05,902 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:05,902 INFO L87 Difference]: Start difference. First operand 2032 states and 2998 transitions. cyclomatic complexity: 967 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:05,958 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:05,958 INFO L93 Difference]: Finished difference Result 2032 states and 2997 transitions. [2023-11-29 03:21:05,958 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2997 transitions. [2023-11-29 03:21:05,971 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:05,987 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2997 transitions. [2023-11-29 03:21:05,987 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:05,990 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:05,990 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2997 transitions. [2023-11-29 03:21:05,994 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:05,994 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2997 transitions. [2023-11-29 03:21:05,998 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2997 transitions. [2023-11-29 03:21:06,027 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:06,032 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4749015748031495) internal successors, (2997), 2031 states have internal predecessors, (2997), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:06,039 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2997 transitions. [2023-11-29 03:21:06,040 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2997 transitions. [2023-11-29 03:21:06,040 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:06,041 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2997 transitions. [2023-11-29 03:21:06,041 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 03:21:06,041 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2997 transitions. [2023-11-29 03:21:06,050 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:06,050 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:06,050 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:06,053 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:06,053 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:06,054 INFO L748 eck$LassoCheckResult]: Stem: 20700#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 20701#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 21687#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21688#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22387#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 21281#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21282#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21352#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21353#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21790#L922-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 21791#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 21316#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 21121#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 21122#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21580#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21581#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 21460#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 21461#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 21095#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21096#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 22311#L1279-2 assume !(0 == ~T1_E~0); 20721#L1284-1 assume !(0 == ~T2_E~0); 20722#L1289-1 assume !(0 == ~T3_E~0); 21457#L1294-1 assume !(0 == ~T4_E~0); 21458#L1299-1 assume !(0 == ~T5_E~0); 21469#L1304-1 assume !(0 == ~T6_E~0); 22386#L1309-1 assume !(0 == ~T7_E~0); 22388#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 20645#L1319-1 assume !(0 == ~T9_E~0); 20646#L1324-1 assume !(0 == ~T10_E~0); 20819#L1329-1 assume !(0 == ~T11_E~0); 20820#L1334-1 assume !(0 == ~T12_E~0); 22229#L1339-1 assume !(0 == ~T13_E~0); 22301#L1344-1 assume !(0 == ~E_M~0); 22302#L1349-1 assume !(0 == ~E_1~0); 21646#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 21647#L1359-1 assume !(0 == ~E_3~0); 22054#L1364-1 assume !(0 == ~E_4~0); 20945#L1369-1 assume !(0 == ~E_5~0); 20946#L1374-1 assume !(0 == ~E_6~0); 21653#L1379-1 assume !(0 == ~E_7~0); 21654#L1384-1 assume !(0 == ~E_8~0); 21731#L1389-1 assume !(0 == ~E_9~0); 22248#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 22249#L1399-1 assume !(0 == ~E_11~0); 22342#L1404-1 assume !(0 == ~E_12~0); 21043#L1409-1 assume !(0 == ~E_13~0); 21044#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22337#L628 assume !(1 == ~m_pc~0); 20944#L628-2 is_master_triggered_~__retres1~0#1 := 0; 20943#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21528#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21529#L1591 assume !(0 != activate_threads_~tmp~1#1); 22350#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21509#L647 assume 1 == ~t1_pc~0; 20869#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20870#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21560#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22017#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 22289#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22290#L666 assume 1 == ~t2_pc~0; 20718#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20719#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20861#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 21842#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21843#L685 assume !(1 == ~t3_pc~0); 21937#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 21936#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22006#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21695#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21696#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21169#L704 assume 1 == ~t4_pc~0; 21170#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21707#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20509#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20510#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 21558#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21559#L723 assume !(1 == ~t5_pc~0); 21691#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21909#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22047#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21821#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 21822#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20927#L742 assume 1 == ~t6_pc~0; 20928#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21084#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20851#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 20614#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 20615#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21005#L761 assume !(1 == ~t7_pc~0); 21006#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20881#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20882#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 21698#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 21699#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20637#L780 assume 1 == ~t8_pc~0; 20638#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 20917#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20918#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 21660#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 21661#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21777#L799 assume 1 == ~t9_pc~0; 21879#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20640#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20641#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 20912#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 21980#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21803#L818 assume !(1 == ~t10_pc~0); 20424#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 20425#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21872#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21806#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21807#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 21849#L837 assume 1 == ~t11_pc~0; 21850#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 21685#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 22293#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 21770#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 21771#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 21517#L856 assume !(1 == ~t12_pc~0); 21518#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 22152#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 20442#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 20443#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 22130#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 22314#L875 assume 1 == ~t13_pc~0; 21467#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21085#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21086#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 21023#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 21024#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21871#L1427 assume !(1 == ~M_E~0); 21856#L1427-2 assume !(1 == ~T1_E~0); 20992#L1432-1 assume !(1 == ~T2_E~0); 20993#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22059#L1442-1 assume !(1 == ~T4_E~0); 22060#L1447-1 assume !(1 == ~T5_E~0); 21918#L1452-1 assume !(1 == ~T6_E~0); 20561#L1457-1 assume !(1 == ~T7_E~0); 20562#L1462-1 assume !(1 == ~T8_E~0); 22077#L1467-1 assume !(1 == ~T9_E~0); 22098#L1472-1 assume !(1 == ~T10_E~0); 22099#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 21867#L1482-1 assume !(1 == ~T12_E~0); 21868#L1487-1 assume !(1 == ~T13_E~0); 20892#L1492-1 assume !(1 == ~E_M~0); 20893#L1497-1 assume !(1 == ~E_1~0); 21263#L1502-1 assume !(1 == ~E_2~0); 21264#L1507-1 assume !(1 == ~E_3~0); 20769#L1512-1 assume !(1 == ~E_4~0); 20770#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 22171#L1522-1 assume !(1 == ~E_6~0); 21506#L1527-1 assume !(1 == ~E_7~0); 21507#L1532-1 assume !(1 == ~E_8~0); 22372#L1537-1 assume !(1 == ~E_9~0); 21714#L1542-1 assume !(1 == ~E_10~0); 21535#L1547-1 assume !(1 == ~E_11~0); 21536#L1552-1 assume !(1 == ~E_12~0); 20465#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 20466#L1562-1 assume { :end_inline_reset_delta_events } true; 21075#L1928-2 [2023-11-29 03:21:06,054 INFO L750 eck$LassoCheckResult]: Loop: 21075#L1928-2 assume !false; 21573#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21150#L1254-1 assume !false; 21382#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20794#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20795#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20994#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 22157#L1067 assume !(0 != eval_~tmp~0#1); 21447#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21052#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21053#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21283#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21267#L1284-3 assume !(0 == ~T2_E~0); 21268#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21248#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21249#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21641#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21642#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21129#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 21130#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 22120#L1324-3 assume !(0 == ~T10_E~0); 20767#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 20768#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 21541#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 21542#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 21846#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21113#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21114#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21854#L1364-3 assume !(0 == ~E_4~0); 22371#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22263#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20896#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20897#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21111#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21112#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21418#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 22273#L1404-3 assume !(0 == ~E_12~0); 22238#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 22239#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21743#L628-45 assume 1 == ~m_pc~0; 21413#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 21415#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21926#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21147#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21148#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21878#L647-45 assume 1 == ~t1_pc~0; 20715#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20716#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21659#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20825#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20826#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21036#L666-45 assume !(1 == ~t2_pc~0); 21037#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 21527#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21924#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21925#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21990#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20577#L685-45 assume 1 == ~t3_pc~0; 20578#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21655#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22303#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22169#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22170#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22312#L704-45 assume 1 == ~t4_pc~0; 22193#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20445#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21313#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 22194#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22400#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21772#L723-45 assume !(1 == ~t5_pc~0); 21773#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 22250#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22362#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21125#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 21126#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22140#L742-45 assume 1 == ~t6_pc~0; 22141#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21390#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21600#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21601#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21883#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21969#L761-45 assume !(1 == ~t7_pc~0); 21970#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 21384#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21385#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 20773#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 20774#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22242#L780-45 assume !(1 == ~t8_pc~0); 21152#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 20784#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20785#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 22369#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 20753#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 20754#L799-45 assume 1 == ~t9_pc~0; 21539#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 20973#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 22035#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 21919#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21920#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 20695#L818-45 assume 1 == ~t10_pc~0; 20696#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20813#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21896#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 21311#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21312#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 22015#L837-45 assume !(1 == ~t11_pc~0); 21241#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 21242#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 20765#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 20766#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 20834#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 20835#L856-45 assume !(1 == ~t12_pc~0); 20836#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 20837#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 22066#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 22067#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 21657#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 21658#L875-45 assume 1 == ~t13_pc~0; 21625#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 21626#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 21686#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 22027#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 22283#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22227#L1427-3 assume !(1 == ~M_E~0); 21452#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21453#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21977#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21644#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21645#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20482#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20483#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 22155#L1462-3 assume !(1 == ~T8_E~0); 22156#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 22023#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 22024#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 20737#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 20738#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 20880#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 21050#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21051#L1502-3 assume !(1 == ~E_2~0); 21997#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22118#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21089#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20777#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20778#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 20744#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 20745#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21855#L1542-3 assume !(1 == ~E_10~0); 21983#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 21628#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 21629#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 20948#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 20949#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 20370#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20807#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 20808#L1947 assume !(0 == start_simulation_~tmp~3#1); 21761#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 21951#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 21009#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 20432#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 20433#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22086#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22087#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 22247#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 21075#L1928-2 [2023-11-29 03:21:06,055 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:06,055 INFO L85 PathProgramCache]: Analyzing trace with hash 1024455497, now seen corresponding path program 1 times [2023-11-29 03:21:06,055 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:06,055 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [815166029] [2023-11-29 03:21:06,055 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:06,056 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:06,071 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:06,108 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:06,109 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:06,109 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [815166029] [2023-11-29 03:21:06,109 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [815166029] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:06,109 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:06,109 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:06,110 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [797798182] [2023-11-29 03:21:06,110 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:06,110 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:06,110 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:06,111 INFO L85 PathProgramCache]: Analyzing trace with hash -1501818386, now seen corresponding path program 1 times [2023-11-29 03:21:06,111 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:06,111 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1058331176] [2023-11-29 03:21:06,111 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:06,111 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:06,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:06,180 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:06,180 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:06,180 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1058331176] [2023-11-29 03:21:06,180 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1058331176] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:06,180 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:06,181 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:06,181 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901312068] [2023-11-29 03:21:06,181 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:06,181 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:06,182 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:06,182 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:06,182 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:06,182 INFO L87 Difference]: Start difference. First operand 2032 states and 2997 transitions. cyclomatic complexity: 966 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:06,253 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:06,253 INFO L93 Difference]: Finished difference Result 2032 states and 2996 transitions. [2023-11-29 03:21:06,254 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2996 transitions. [2023-11-29 03:21:06,265 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:06,280 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2996 transitions. [2023-11-29 03:21:06,280 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:06,282 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:06,282 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2996 transitions. [2023-11-29 03:21:06,286 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:06,286 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2996 transitions. [2023-11-29 03:21:06,290 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2996 transitions. [2023-11-29 03:21:06,318 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:06,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4744094488188977) internal successors, (2996), 2031 states have internal predecessors, (2996), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:06,330 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2996 transitions. [2023-11-29 03:21:06,330 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2996 transitions. [2023-11-29 03:21:06,331 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:06,332 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2996 transitions. [2023-11-29 03:21:06,332 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 03:21:06,332 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2996 transitions. [2023-11-29 03:21:06,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:06,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:06,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:06,344 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:06,344 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:06,344 INFO L748 eck$LassoCheckResult]: Stem: 24771#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 24772#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 25758#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25759#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 26458#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 25352#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25353#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25423#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25424#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25861#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25862#L927-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 25387#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 25192#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 25193#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 25651#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 25652#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 25531#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 25532#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 25166#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25167#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 26382#L1279-2 assume !(0 == ~T1_E~0); 24792#L1284-1 assume !(0 == ~T2_E~0); 24793#L1289-1 assume !(0 == ~T3_E~0); 25528#L1294-1 assume !(0 == ~T4_E~0); 25529#L1299-1 assume !(0 == ~T5_E~0); 25540#L1304-1 assume !(0 == ~T6_E~0); 26457#L1309-1 assume !(0 == ~T7_E~0); 26459#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 24716#L1319-1 assume !(0 == ~T9_E~0); 24717#L1324-1 assume !(0 == ~T10_E~0); 24890#L1329-1 assume !(0 == ~T11_E~0); 24891#L1334-1 assume !(0 == ~T12_E~0); 26300#L1339-1 assume !(0 == ~T13_E~0); 26372#L1344-1 assume !(0 == ~E_M~0); 26373#L1349-1 assume !(0 == ~E_1~0); 25717#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 25718#L1359-1 assume !(0 == ~E_3~0); 26125#L1364-1 assume !(0 == ~E_4~0); 25016#L1369-1 assume !(0 == ~E_5~0); 25017#L1374-1 assume !(0 == ~E_6~0); 25724#L1379-1 assume !(0 == ~E_7~0); 25725#L1384-1 assume !(0 == ~E_8~0); 25802#L1389-1 assume !(0 == ~E_9~0); 26319#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 26320#L1399-1 assume !(0 == ~E_11~0); 26413#L1404-1 assume !(0 == ~E_12~0); 25114#L1409-1 assume !(0 == ~E_13~0); 25115#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 26408#L628 assume !(1 == ~m_pc~0); 25015#L628-2 is_master_triggered_~__retres1~0#1 := 0; 25014#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25599#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25600#L1591 assume !(0 != activate_threads_~tmp~1#1); 26421#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25580#L647 assume 1 == ~t1_pc~0; 24940#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24941#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 26088#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 26360#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 26361#L666 assume 1 == ~t2_pc~0; 24789#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24790#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24931#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24932#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 25913#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25914#L685 assume !(1 == ~t3_pc~0); 26008#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 26007#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26077#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 25766#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25767#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25240#L704 assume 1 == ~t4_pc~0; 25241#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25778#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24580#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24581#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 25629#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25630#L723 assume !(1 == ~t5_pc~0); 25762#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 25980#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26118#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25892#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 25893#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24998#L742 assume 1 == ~t6_pc~0; 24999#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25155#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24922#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24685#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 24686#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25076#L761 assume !(1 == ~t7_pc~0); 25077#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 24952#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24953#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 25769#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 25770#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 24708#L780 assume 1 == ~t8_pc~0; 24709#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24988#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24989#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 25731#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 25732#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 25848#L799 assume 1 == ~t9_pc~0; 25950#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 24711#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 24712#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 24983#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 26051#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 25874#L818 assume !(1 == ~t10_pc~0); 24495#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 24496#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25943#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25877#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25878#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 25920#L837 assume 1 == ~t11_pc~0; 25921#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 25756#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 26364#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 25841#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 25842#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 25588#L856 assume !(1 == ~t12_pc~0); 25589#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 26223#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 24513#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 24514#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 26201#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 26385#L875 assume 1 == ~t13_pc~0; 25538#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25156#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25157#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 25094#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 25095#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25942#L1427 assume !(1 == ~M_E~0); 25927#L1427-2 assume !(1 == ~T1_E~0); 25063#L1432-1 assume !(1 == ~T2_E~0); 25064#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 26130#L1442-1 assume !(1 == ~T4_E~0); 26131#L1447-1 assume !(1 == ~T5_E~0); 25989#L1452-1 assume !(1 == ~T6_E~0); 24632#L1457-1 assume !(1 == ~T7_E~0); 24633#L1462-1 assume !(1 == ~T8_E~0); 26148#L1467-1 assume !(1 == ~T9_E~0); 26169#L1472-1 assume !(1 == ~T10_E~0); 26170#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 25938#L1482-1 assume !(1 == ~T12_E~0); 25939#L1487-1 assume !(1 == ~T13_E~0); 24963#L1492-1 assume !(1 == ~E_M~0); 24964#L1497-1 assume !(1 == ~E_1~0); 25334#L1502-1 assume !(1 == ~E_2~0); 25335#L1507-1 assume !(1 == ~E_3~0); 24840#L1512-1 assume !(1 == ~E_4~0); 24841#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 26242#L1522-1 assume !(1 == ~E_6~0); 25577#L1527-1 assume !(1 == ~E_7~0); 25578#L1532-1 assume !(1 == ~E_8~0); 26443#L1537-1 assume !(1 == ~E_9~0); 25785#L1542-1 assume !(1 == ~E_10~0); 25606#L1547-1 assume !(1 == ~E_11~0); 25607#L1552-1 assume !(1 == ~E_12~0); 24536#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 24537#L1562-1 assume { :end_inline_reset_delta_events } true; 25146#L1928-2 [2023-11-29 03:21:06,345 INFO L750 eck$LassoCheckResult]: Loop: 25146#L1928-2 assume !false; 25644#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25221#L1254-1 assume !false; 25453#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 24865#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24866#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 25065#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 26228#L1067 assume !(0 != eval_~tmp~0#1); 25518#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25123#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25124#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25354#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25338#L1284-3 assume !(0 == ~T2_E~0); 25339#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25319#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25320#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25712#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 25713#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 25200#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 25201#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 26191#L1324-3 assume !(0 == ~T10_E~0); 24838#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 24839#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 25612#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 25613#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 25917#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25184#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25185#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25925#L1364-3 assume !(0 == ~E_4~0); 26442#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 26334#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 24967#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 24968#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 25182#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 25183#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 25489#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 26344#L1404-3 assume !(0 == ~E_12~0); 26309#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 26310#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25814#L628-45 assume 1 == ~m_pc~0; 25484#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 25486#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25997#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 25218#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25219#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25949#L647-45 assume 1 == ~t1_pc~0; 24786#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24787#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25730#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24896#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 24897#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25107#L666-45 assume !(1 == ~t2_pc~0); 25108#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 25598#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25995#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 25996#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 26061#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24648#L685-45 assume 1 == ~t3_pc~0; 24649#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 25726#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 26374#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 26240#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 26241#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 26383#L704-45 assume !(1 == ~t4_pc~0); 24515#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 24516#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25384#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 26265#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 26471#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25843#L723-45 assume !(1 == ~t5_pc~0); 25844#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 26321#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 26433#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 25196#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 25197#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 26211#L742-45 assume 1 == ~t6_pc~0; 26212#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25461#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25671#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 25672#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25954#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 26040#L761-45 assume !(1 == ~t7_pc~0); 26041#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 25455#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25456#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 24844#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24845#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 26313#L780-45 assume 1 == ~t8_pc~0; 25222#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24855#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24856#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 26440#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24824#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24825#L799-45 assume !(1 == ~t9_pc~0); 25043#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 25044#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 26106#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 25990#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 25991#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24766#L818-45 assume !(1 == ~t10_pc~0); 24768#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 24884#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 25967#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 25382#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 25383#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 26086#L837-45 assume !(1 == ~t11_pc~0); 25312#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 25313#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 24836#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 24837#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 24905#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 24906#L856-45 assume !(1 == ~t12_pc~0); 24907#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 24908#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 26137#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 26138#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 25728#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 25729#L875-45 assume 1 == ~t13_pc~0; 25696#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 25697#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 25757#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 26098#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 26354#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 26298#L1427-3 assume !(1 == ~M_E~0); 25523#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25524#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 26048#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25715#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25716#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 24553#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 24554#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 26226#L1462-3 assume !(1 == ~T8_E~0); 26227#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 26094#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 26095#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 24808#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 24809#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 24951#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 25121#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25122#L1502-3 assume !(1 == ~E_2~0); 26068#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 26189#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25160#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 24848#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 24849#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 24815#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24816#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 25926#L1542-3 assume !(1 == ~E_10~0); 26054#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 25699#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 25700#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 25019#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 25020#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 24441#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24878#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 24879#L1947 assume !(0 == start_simulation_~tmp~3#1); 25832#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 26022#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 25080#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 24503#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 24504#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 26157#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 26158#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 26318#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 25146#L1928-2 [2023-11-29 03:21:06,345 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:06,345 INFO L85 PathProgramCache]: Analyzing trace with hash -869878389, now seen corresponding path program 1 times [2023-11-29 03:21:06,346 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:06,346 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1527062269] [2023-11-29 03:21:06,346 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:06,346 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:06,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:06,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:06,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:06,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1527062269] [2023-11-29 03:21:06,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1527062269] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:06,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:06,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:06,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1031043531] [2023-11-29 03:21:06,398 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:06,399 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:06,399 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:06,399 INFO L85 PathProgramCache]: Analyzing trace with hash 2027792560, now seen corresponding path program 1 times [2023-11-29 03:21:06,399 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:06,399 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2077967724] [2023-11-29 03:21:06,399 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:06,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:06,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:06,468 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:06,469 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:06,469 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2077967724] [2023-11-29 03:21:06,469 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2077967724] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:06,469 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:06,469 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:06,469 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1566899690] [2023-11-29 03:21:06,470 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:06,470 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:06,470 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:06,470 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:06,471 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:06,471 INFO L87 Difference]: Start difference. First operand 2032 states and 2996 transitions. cyclomatic complexity: 965 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:06,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:06,520 INFO L93 Difference]: Finished difference Result 2032 states and 2995 transitions. [2023-11-29 03:21:06,521 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2995 transitions. [2023-11-29 03:21:06,532 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:06,547 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2995 transitions. [2023-11-29 03:21:06,547 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:06,549 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:06,550 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2995 transitions. [2023-11-29 03:21:06,553 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:06,553 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2995 transitions. [2023-11-29 03:21:06,558 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2995 transitions. [2023-11-29 03:21:06,586 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:06,590 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4739173228346456) internal successors, (2995), 2031 states have internal predecessors, (2995), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:06,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2995 transitions. [2023-11-29 03:21:06,598 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2995 transitions. [2023-11-29 03:21:06,598 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:06,599 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2995 transitions. [2023-11-29 03:21:06,599 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 03:21:06,599 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2995 transitions. [2023-11-29 03:21:06,608 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:06,608 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:06,608 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:06,611 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:06,611 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:06,612 INFO L748 eck$LassoCheckResult]: Stem: 28842#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 28843#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 29829#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 29830#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30529#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 29423#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 29424#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 29494#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 29495#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 29932#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 29933#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 29458#L932-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 29263#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 29264#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 29722#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 29723#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 29602#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 29603#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 29237#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 29238#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 30453#L1279-2 assume !(0 == ~T1_E~0); 28863#L1284-1 assume !(0 == ~T2_E~0); 28864#L1289-1 assume !(0 == ~T3_E~0); 29599#L1294-1 assume !(0 == ~T4_E~0); 29600#L1299-1 assume !(0 == ~T5_E~0); 29611#L1304-1 assume !(0 == ~T6_E~0); 30528#L1309-1 assume !(0 == ~T7_E~0); 30530#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28787#L1319-1 assume !(0 == ~T9_E~0); 28788#L1324-1 assume !(0 == ~T10_E~0); 28961#L1329-1 assume !(0 == ~T11_E~0); 28962#L1334-1 assume !(0 == ~T12_E~0); 30371#L1339-1 assume !(0 == ~T13_E~0); 30443#L1344-1 assume !(0 == ~E_M~0); 30444#L1349-1 assume !(0 == ~E_1~0); 29788#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 29789#L1359-1 assume !(0 == ~E_3~0); 30196#L1364-1 assume !(0 == ~E_4~0); 29087#L1369-1 assume !(0 == ~E_5~0); 29088#L1374-1 assume !(0 == ~E_6~0); 29795#L1379-1 assume !(0 == ~E_7~0); 29796#L1384-1 assume !(0 == ~E_8~0); 29873#L1389-1 assume !(0 == ~E_9~0); 30390#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 30391#L1399-1 assume !(0 == ~E_11~0); 30484#L1404-1 assume !(0 == ~E_12~0); 29185#L1409-1 assume !(0 == ~E_13~0); 29186#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30479#L628 assume !(1 == ~m_pc~0); 29086#L628-2 is_master_triggered_~__retres1~0#1 := 0; 29085#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29670#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29671#L1591 assume !(0 != activate_threads_~tmp~1#1); 30492#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29651#L647 assume 1 == ~t1_pc~0; 29011#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29012#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29702#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 30159#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 30431#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30432#L666 assume 1 == ~t2_pc~0; 28860#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 28861#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29002#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29003#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 29984#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29985#L685 assume !(1 == ~t3_pc~0); 30079#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 30078#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29837#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29838#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29311#L704 assume 1 == ~t4_pc~0; 29312#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 29849#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 28651#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28652#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 29700#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29701#L723 assume !(1 == ~t5_pc~0); 29833#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 30051#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30189#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29963#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 29964#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29069#L742 assume 1 == ~t6_pc~0; 29070#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29226#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28993#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28756#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 28757#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29147#L761 assume !(1 == ~t7_pc~0); 29148#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 29023#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29024#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 29840#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 29841#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28779#L780 assume 1 == ~t8_pc~0; 28780#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 29059#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29060#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 29802#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 29803#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 29919#L799 assume 1 == ~t9_pc~0; 30021#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28782#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28783#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 29054#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 30122#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 29945#L818 assume !(1 == ~t10_pc~0); 28566#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 28567#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30014#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29948#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29949#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 29991#L837 assume 1 == ~t11_pc~0; 29992#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 29827#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 30435#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 29912#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 29913#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 29659#L856 assume !(1 == ~t12_pc~0); 29660#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 30294#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 28584#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 28585#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 30272#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 30456#L875 assume 1 == ~t13_pc~0; 29609#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29227#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29228#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 29165#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 29166#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30013#L1427 assume !(1 == ~M_E~0); 29998#L1427-2 assume !(1 == ~T1_E~0); 29134#L1432-1 assume !(1 == ~T2_E~0); 29135#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 30201#L1442-1 assume !(1 == ~T4_E~0); 30202#L1447-1 assume !(1 == ~T5_E~0); 30060#L1452-1 assume !(1 == ~T6_E~0); 28703#L1457-1 assume !(1 == ~T7_E~0); 28704#L1462-1 assume !(1 == ~T8_E~0); 30219#L1467-1 assume !(1 == ~T9_E~0); 30240#L1472-1 assume !(1 == ~T10_E~0); 30241#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 30009#L1482-1 assume !(1 == ~T12_E~0); 30010#L1487-1 assume !(1 == ~T13_E~0); 29034#L1492-1 assume !(1 == ~E_M~0); 29035#L1497-1 assume !(1 == ~E_1~0); 29405#L1502-1 assume !(1 == ~E_2~0); 29406#L1507-1 assume !(1 == ~E_3~0); 28911#L1512-1 assume !(1 == ~E_4~0); 28912#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 30313#L1522-1 assume !(1 == ~E_6~0); 29648#L1527-1 assume !(1 == ~E_7~0); 29649#L1532-1 assume !(1 == ~E_8~0); 30514#L1537-1 assume !(1 == ~E_9~0); 29856#L1542-1 assume !(1 == ~E_10~0); 29677#L1547-1 assume !(1 == ~E_11~0); 29678#L1552-1 assume !(1 == ~E_12~0); 28607#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 28608#L1562-1 assume { :end_inline_reset_delta_events } true; 29217#L1928-2 [2023-11-29 03:21:06,612 INFO L750 eck$LassoCheckResult]: Loop: 29217#L1928-2 assume !false; 29715#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 29292#L1254-1 assume !false; 29524#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 28936#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28937#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 29136#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 30299#L1067 assume !(0 != eval_~tmp~0#1); 29589#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 29194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 29195#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29425#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29409#L1284-3 assume !(0 == ~T2_E~0); 29410#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 29390#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 29391#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29783#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 29784#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29271#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 29272#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 30262#L1324-3 assume !(0 == ~T10_E~0); 28909#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 28910#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 29683#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 29684#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 29988#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29255#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29256#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 29996#L1364-3 assume !(0 == ~E_4~0); 30513#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 30405#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29038#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29039#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29253#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29254#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29560#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 30415#L1404-3 assume !(0 == ~E_12~0); 30380#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 30381#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29885#L628-45 assume 1 == ~m_pc~0; 29555#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 29557#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30068#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29289#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 29290#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30020#L647-45 assume 1 == ~t1_pc~0; 28857#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 28858#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29801#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28967#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28968#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29178#L666-45 assume !(1 == ~t2_pc~0); 29179#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 29669#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30066#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 30067#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 30132#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28719#L685-45 assume 1 == ~t3_pc~0; 28720#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 29797#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30445#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 30311#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30312#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30454#L704-45 assume !(1 == ~t4_pc~0); 28586#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 28587#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29455#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 30336#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30542#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29914#L723-45 assume !(1 == ~t5_pc~0); 29915#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 30392#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30504#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 29267#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 29268#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30282#L742-45 assume 1 == ~t6_pc~0; 30283#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29532#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29742#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 29743#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 30025#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30111#L761-45 assume !(1 == ~t7_pc~0); 30112#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 29526#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29527#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 28915#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28916#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 30384#L780-45 assume 1 == ~t8_pc~0; 29293#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28926#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28927#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 30511#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28895#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28896#L799-45 assume 1 == ~t9_pc~0; 29681#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 29115#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 30177#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 30061#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 30062#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28837#L818-45 assume 1 == ~t10_pc~0; 28838#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28955#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 30038#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 29453#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 29454#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 30157#L837-45 assume !(1 == ~t11_pc~0); 29383#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 29384#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 28907#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 28908#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 28976#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 28977#L856-45 assume !(1 == ~t12_pc~0); 28978#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 28979#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 30208#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 30209#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 29799#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 29800#L875-45 assume 1 == ~t13_pc~0; 29767#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 29768#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 29828#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 30169#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 30425#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30369#L1427-3 assume !(1 == ~M_E~0); 29594#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 29595#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30119#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 29786#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 29787#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28624#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28625#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 30297#L1462-3 assume !(1 == ~T8_E~0); 30298#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 30165#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 30166#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 28879#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 28880#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 29022#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 29192#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 29193#L1502-3 assume !(1 == ~E_2~0); 30139#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 30260#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 29231#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28919#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28920#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28886#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 28887#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 29997#L1542-3 assume !(1 == ~E_10~0); 30125#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 29770#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 29771#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 29090#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 29091#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 28512#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28949#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 28950#L1947 assume !(0 == start_simulation_~tmp~3#1); 29903#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 30093#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 29151#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 28574#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 28575#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 30228#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 30229#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 30389#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 29217#L1928-2 [2023-11-29 03:21:06,613 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:06,613 INFO L85 PathProgramCache]: Analyzing trace with hash 1978508041, now seen corresponding path program 1 times [2023-11-29 03:21:06,614 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:06,614 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1789949124] [2023-11-29 03:21:06,614 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:06,614 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:06,629 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:06,663 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:06,663 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:06,663 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1789949124] [2023-11-29 03:21:06,664 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1789949124] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:06,664 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:06,664 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:06,664 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1523675511] [2023-11-29 03:21:06,664 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:06,665 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:06,665 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:06,665 INFO L85 PathProgramCache]: Analyzing trace with hash -689496338, now seen corresponding path program 1 times [2023-11-29 03:21:06,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:06,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2123573821] [2023-11-29 03:21:06,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:06,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:06,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:06,740 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:06,741 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:06,741 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2123573821] [2023-11-29 03:21:06,741 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2123573821] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:06,741 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:06,741 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:06,741 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [460330607] [2023-11-29 03:21:06,742 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:06,742 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:06,742 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:06,742 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:06,743 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:06,743 INFO L87 Difference]: Start difference. First operand 2032 states and 2995 transitions. cyclomatic complexity: 964 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:06,791 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:06,792 INFO L93 Difference]: Finished difference Result 2032 states and 2994 transitions. [2023-11-29 03:21:06,792 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2994 transitions. [2023-11-29 03:21:06,802 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:06,816 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2994 transitions. [2023-11-29 03:21:06,817 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:06,819 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:06,819 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2994 transitions. [2023-11-29 03:21:06,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:06,823 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2994 transitions. [2023-11-29 03:21:06,827 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2994 transitions. [2023-11-29 03:21:06,853 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:06,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4734251968503937) internal successors, (2994), 2031 states have internal predecessors, (2994), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:06,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2994 transitions. [2023-11-29 03:21:06,864 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2994 transitions. [2023-11-29 03:21:06,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:06,865 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2994 transitions. [2023-11-29 03:21:06,865 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 03:21:06,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2994 transitions. [2023-11-29 03:21:06,874 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:06,874 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:06,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:06,877 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:06,877 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:06,878 INFO L748 eck$LassoCheckResult]: Stem: 32913#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 32914#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 33900#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 33901#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34600#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 33494#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33495#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 33565#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 33566#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34003#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 34004#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33529#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 33334#L937-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 33335#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 33793#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 33794#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 33673#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 33674#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 33308#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33309#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 34524#L1279-2 assume !(0 == ~T1_E~0); 32934#L1284-1 assume !(0 == ~T2_E~0); 32935#L1289-1 assume !(0 == ~T3_E~0); 33670#L1294-1 assume !(0 == ~T4_E~0); 33671#L1299-1 assume !(0 == ~T5_E~0); 33682#L1304-1 assume !(0 == ~T6_E~0); 34599#L1309-1 assume !(0 == ~T7_E~0); 34601#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 32858#L1319-1 assume !(0 == ~T9_E~0); 32859#L1324-1 assume !(0 == ~T10_E~0); 33032#L1329-1 assume !(0 == ~T11_E~0); 33033#L1334-1 assume !(0 == ~T12_E~0); 34442#L1339-1 assume !(0 == ~T13_E~0); 34514#L1344-1 assume !(0 == ~E_M~0); 34515#L1349-1 assume !(0 == ~E_1~0); 33859#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 33860#L1359-1 assume !(0 == ~E_3~0); 34267#L1364-1 assume !(0 == ~E_4~0); 33158#L1369-1 assume !(0 == ~E_5~0); 33159#L1374-1 assume !(0 == ~E_6~0); 33866#L1379-1 assume !(0 == ~E_7~0); 33867#L1384-1 assume !(0 == ~E_8~0); 33944#L1389-1 assume !(0 == ~E_9~0); 34461#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 34462#L1399-1 assume !(0 == ~E_11~0); 34555#L1404-1 assume !(0 == ~E_12~0); 33256#L1409-1 assume !(0 == ~E_13~0); 33257#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34550#L628 assume !(1 == ~m_pc~0); 33157#L628-2 is_master_triggered_~__retres1~0#1 := 0; 33156#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33741#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33742#L1591 assume !(0 != activate_threads_~tmp~1#1); 34563#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33722#L647 assume 1 == ~t1_pc~0; 33082#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 33083#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33773#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34230#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 34502#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34503#L666 assume 1 == ~t2_pc~0; 32931#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32932#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33073#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33074#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 34055#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 34056#L685 assume !(1 == ~t3_pc~0); 34150#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34149#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34219#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 33908#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33909#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33382#L704 assume 1 == ~t4_pc~0; 33383#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33920#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32722#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 32723#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 33771#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33772#L723 assume !(1 == ~t5_pc~0); 33904#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 34122#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34260#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34034#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 34035#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33140#L742 assume 1 == ~t6_pc~0; 33141#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33297#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33064#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 32827#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 32828#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33218#L761 assume !(1 == ~t7_pc~0); 33219#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 33094#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33095#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 33911#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 33912#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 32850#L780 assume 1 == ~t8_pc~0; 32851#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33130#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33131#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 33873#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 33874#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 33990#L799 assume 1 == ~t9_pc~0; 34092#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 32853#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 32854#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 33125#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 34193#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 34016#L818 assume !(1 == ~t10_pc~0); 32637#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 32638#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34085#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 34019#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 34020#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34062#L837 assume 1 == ~t11_pc~0; 34063#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33898#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 34506#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 33983#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 33984#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33730#L856 assume !(1 == ~t12_pc~0); 33731#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 34365#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 32655#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 32656#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 34343#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 34527#L875 assume 1 == ~t13_pc~0; 33680#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 33298#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33299#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 33236#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 33237#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34084#L1427 assume !(1 == ~M_E~0); 34069#L1427-2 assume !(1 == ~T1_E~0); 33205#L1432-1 assume !(1 == ~T2_E~0); 33206#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 34272#L1442-1 assume !(1 == ~T4_E~0); 34273#L1447-1 assume !(1 == ~T5_E~0); 34131#L1452-1 assume !(1 == ~T6_E~0); 32774#L1457-1 assume !(1 == ~T7_E~0); 32775#L1462-1 assume !(1 == ~T8_E~0); 34290#L1467-1 assume !(1 == ~T9_E~0); 34311#L1472-1 assume !(1 == ~T10_E~0); 34312#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 34080#L1482-1 assume !(1 == ~T12_E~0); 34081#L1487-1 assume !(1 == ~T13_E~0); 33105#L1492-1 assume !(1 == ~E_M~0); 33106#L1497-1 assume !(1 == ~E_1~0); 33476#L1502-1 assume !(1 == ~E_2~0); 33477#L1507-1 assume !(1 == ~E_3~0); 32982#L1512-1 assume !(1 == ~E_4~0); 32983#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 34384#L1522-1 assume !(1 == ~E_6~0); 33719#L1527-1 assume !(1 == ~E_7~0); 33720#L1532-1 assume !(1 == ~E_8~0); 34585#L1537-1 assume !(1 == ~E_9~0); 33927#L1542-1 assume !(1 == ~E_10~0); 33748#L1547-1 assume !(1 == ~E_11~0); 33749#L1552-1 assume !(1 == ~E_12~0); 32678#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 32679#L1562-1 assume { :end_inline_reset_delta_events } true; 33288#L1928-2 [2023-11-29 03:21:06,878 INFO L750 eck$LassoCheckResult]: Loop: 33288#L1928-2 assume !false; 33786#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 33363#L1254-1 assume !false; 33595#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33007#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33008#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33207#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 34370#L1067 assume !(0 != eval_~tmp~0#1); 33660#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 33265#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 33266#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 33496#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 33480#L1284-3 assume !(0 == ~T2_E~0); 33481#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33461#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33462#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 33854#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 33855#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 33342#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33343#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 34333#L1324-3 assume !(0 == ~T10_E~0); 32980#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 32981#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 33754#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 33755#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 34059#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 33326#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33327#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 34067#L1364-3 assume !(0 == ~E_4~0); 34584#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 34476#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 33109#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33110#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33324#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 33325#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 33631#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 34486#L1404-3 assume !(0 == ~E_12~0); 34451#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 34452#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33956#L628-45 assume 1 == ~m_pc~0; 33626#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 33628#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34139#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33360#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 33361#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34091#L647-45 assume 1 == ~t1_pc~0; 32928#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 32929#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33872#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33038#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 33039#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33249#L666-45 assume !(1 == ~t2_pc~0); 33250#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 33740#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34137#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34138#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 34203#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32790#L685-45 assume 1 == ~t3_pc~0; 32791#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 33868#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34516#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 34382#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 34383#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34525#L704-45 assume !(1 == ~t4_pc~0); 32657#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 32658#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33526#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 34407#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34613#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33985#L723-45 assume !(1 == ~t5_pc~0); 33986#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 34463#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34575#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 33338#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 33339#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34353#L742-45 assume 1 == ~t6_pc~0; 34354#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33603#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33813#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 33814#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34096#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 34182#L761-45 assume !(1 == ~t7_pc~0); 34183#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 33597#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33598#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 32986#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 32987#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34455#L780-45 assume 1 == ~t8_pc~0; 33364#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 32997#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 32998#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 34582#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 32966#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 32967#L799-45 assume !(1 == ~t9_pc~0); 33185#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 33186#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34248#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 34132#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 34133#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 32908#L818-45 assume 1 == ~t10_pc~0; 32909#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 33026#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34109#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 33524#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 33525#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 34228#L837-45 assume 1 == ~t11_pc~0; 34512#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 33455#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 32978#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 32979#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 33047#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 33048#L856-45 assume !(1 == ~t12_pc~0); 33049#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 33050#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 34279#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 34280#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 33870#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 33871#L875-45 assume !(1 == ~t13_pc~0); 33840#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 33839#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 33899#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 34240#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 34496#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34440#L1427-3 assume !(1 == ~M_E~0); 33665#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33666#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34190#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33857#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33858#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 32695#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 32696#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 34368#L1462-3 assume !(1 == ~T8_E~0); 34369#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 34236#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 34237#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 32950#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 32951#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 33093#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 33263#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33264#L1502-3 assume !(1 == ~E_2~0); 34210#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 34331#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33302#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 32990#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 32991#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 32957#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 32958#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 34068#L1542-3 assume !(1 == ~E_10~0); 34196#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 33841#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 33842#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 33161#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 33162#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 32583#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 33020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 33021#L1947 assume !(0 == start_simulation_~tmp~3#1); 33974#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 34164#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 33222#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 32645#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 32646#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 34299#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 34300#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 34460#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 33288#L1928-2 [2023-11-29 03:21:06,879 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:06,879 INFO L85 PathProgramCache]: Analyzing trace with hash -1393291829, now seen corresponding path program 1 times [2023-11-29 03:21:06,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:06,880 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968119941] [2023-11-29 03:21:06,880 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:06,880 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:06,895 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:06,927 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:06,927 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:06,927 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968119941] [2023-11-29 03:21:06,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [968119941] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:06,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:06,928 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:06,928 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2021403013] [2023-11-29 03:21:06,928 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:06,929 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:06,929 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:06,929 INFO L85 PathProgramCache]: Analyzing trace with hash 788038383, now seen corresponding path program 1 times [2023-11-29 03:21:06,929 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:06,929 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1846513920] [2023-11-29 03:21:06,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:06,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:06,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:06,992 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:06,992 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:06,993 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1846513920] [2023-11-29 03:21:06,993 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1846513920] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:06,993 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:06,993 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:06,993 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [129799396] [2023-11-29 03:21:06,993 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:06,994 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:06,994 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:06,994 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:06,994 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:06,994 INFO L87 Difference]: Start difference. First operand 2032 states and 2994 transitions. cyclomatic complexity: 963 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:07,035 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:07,035 INFO L93 Difference]: Finished difference Result 2032 states and 2993 transitions. [2023-11-29 03:21:07,035 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2993 transitions. [2023-11-29 03:21:07,045 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:07,059 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2993 transitions. [2023-11-29 03:21:07,059 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:07,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:07,062 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2993 transitions. [2023-11-29 03:21:07,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:07,065 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2993 transitions. [2023-11-29 03:21:07,070 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2993 transitions. [2023-11-29 03:21:07,096 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:07,101 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4729330708661417) internal successors, (2993), 2031 states have internal predecessors, (2993), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:07,107 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2993 transitions. [2023-11-29 03:21:07,107 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2993 transitions. [2023-11-29 03:21:07,107 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:07,108 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2993 transitions. [2023-11-29 03:21:07,108 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 03:21:07,108 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2993 transitions. [2023-11-29 03:21:07,116 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:07,117 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:07,117 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:07,120 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:07,120 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:07,120 INFO L748 eck$LassoCheckResult]: Stem: 36984#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 36985#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 37971#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 37972#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38671#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 37565#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 37566#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 37636#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 37637#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38074#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38075#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 37600#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 37405#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 37406#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 37864#L947-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 37865#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 37744#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 37745#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 37379#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 37380#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 38595#L1279-2 assume !(0 == ~T1_E~0); 37005#L1284-1 assume !(0 == ~T2_E~0); 37006#L1289-1 assume !(0 == ~T3_E~0); 37741#L1294-1 assume !(0 == ~T4_E~0); 37742#L1299-1 assume !(0 == ~T5_E~0); 37753#L1304-1 assume !(0 == ~T6_E~0); 38670#L1309-1 assume !(0 == ~T7_E~0); 38672#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 36929#L1319-1 assume !(0 == ~T9_E~0); 36930#L1324-1 assume !(0 == ~T10_E~0); 37103#L1329-1 assume !(0 == ~T11_E~0); 37104#L1334-1 assume !(0 == ~T12_E~0); 38513#L1339-1 assume !(0 == ~T13_E~0); 38585#L1344-1 assume !(0 == ~E_M~0); 38586#L1349-1 assume !(0 == ~E_1~0); 37930#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 37931#L1359-1 assume !(0 == ~E_3~0); 38338#L1364-1 assume !(0 == ~E_4~0); 37229#L1369-1 assume !(0 == ~E_5~0); 37230#L1374-1 assume !(0 == ~E_6~0); 37937#L1379-1 assume !(0 == ~E_7~0); 37938#L1384-1 assume !(0 == ~E_8~0); 38015#L1389-1 assume !(0 == ~E_9~0); 38532#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 38533#L1399-1 assume !(0 == ~E_11~0); 38626#L1404-1 assume !(0 == ~E_12~0); 37327#L1409-1 assume !(0 == ~E_13~0); 37328#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38621#L628 assume !(1 == ~m_pc~0); 37228#L628-2 is_master_triggered_~__retres1~0#1 := 0; 37227#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 37812#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37813#L1591 assume !(0 != activate_threads_~tmp~1#1); 38634#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 37793#L647 assume 1 == ~t1_pc~0; 37153#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37154#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37844#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38301#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 38573#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38574#L666 assume 1 == ~t2_pc~0; 37002#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 37003#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 37144#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 37145#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 38126#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38127#L685 assume !(1 == ~t3_pc~0); 38221#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 38220#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38290#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 37979#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 37980#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 37453#L704 assume 1 == ~t4_pc~0; 37454#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 37991#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36793#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 36794#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 37842#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 37843#L723 assume !(1 == ~t5_pc~0); 37975#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 38193#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38331#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 38105#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 38106#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37211#L742 assume 1 == ~t6_pc~0; 37212#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37368#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37135#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 36898#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 36899#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37289#L761 assume !(1 == ~t7_pc~0); 37290#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 37165#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37166#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37982#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 37983#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36921#L780 assume 1 == ~t8_pc~0; 36922#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37201#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37202#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 37944#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 37945#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38061#L799 assume 1 == ~t9_pc~0; 38163#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 36924#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 36925#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 37196#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 38264#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 38087#L818 assume !(1 == ~t10_pc~0); 36708#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 36709#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38156#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 38090#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 38091#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38133#L837 assume 1 == ~t11_pc~0; 38134#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 37969#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 38577#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 38054#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 38055#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37801#L856 assume !(1 == ~t12_pc~0); 37802#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 38436#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 36726#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 36727#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 38414#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 38598#L875 assume 1 == ~t13_pc~0; 37751#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37369#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37370#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 37307#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 37308#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38155#L1427 assume !(1 == ~M_E~0); 38140#L1427-2 assume !(1 == ~T1_E~0); 37276#L1432-1 assume !(1 == ~T2_E~0); 37277#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 38343#L1442-1 assume !(1 == ~T4_E~0); 38344#L1447-1 assume !(1 == ~T5_E~0); 38202#L1452-1 assume !(1 == ~T6_E~0); 36845#L1457-1 assume !(1 == ~T7_E~0); 36846#L1462-1 assume !(1 == ~T8_E~0); 38361#L1467-1 assume !(1 == ~T9_E~0); 38382#L1472-1 assume !(1 == ~T10_E~0); 38383#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 38151#L1482-1 assume !(1 == ~T12_E~0); 38152#L1487-1 assume !(1 == ~T13_E~0); 37176#L1492-1 assume !(1 == ~E_M~0); 37177#L1497-1 assume !(1 == ~E_1~0); 37547#L1502-1 assume !(1 == ~E_2~0); 37548#L1507-1 assume !(1 == ~E_3~0); 37053#L1512-1 assume !(1 == ~E_4~0); 37054#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 38455#L1522-1 assume !(1 == ~E_6~0); 37790#L1527-1 assume !(1 == ~E_7~0); 37791#L1532-1 assume !(1 == ~E_8~0); 38656#L1537-1 assume !(1 == ~E_9~0); 37998#L1542-1 assume !(1 == ~E_10~0); 37819#L1547-1 assume !(1 == ~E_11~0); 37820#L1552-1 assume !(1 == ~E_12~0); 36749#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 36750#L1562-1 assume { :end_inline_reset_delta_events } true; 37359#L1928-2 [2023-11-29 03:21:07,121 INFO L750 eck$LassoCheckResult]: Loop: 37359#L1928-2 assume !false; 37857#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 37434#L1254-1 assume !false; 37666#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37078#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37079#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37278#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 38441#L1067 assume !(0 != eval_~tmp~0#1); 37731#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 37336#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 37337#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37567#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37551#L1284-3 assume !(0 == ~T2_E~0); 37552#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 37532#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 37533#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37925#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 37926#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37413#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 37414#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 38404#L1324-3 assume !(0 == ~T10_E~0); 37051#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 37052#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 37825#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 37826#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 38130#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37397#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37398#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 38138#L1364-3 assume !(0 == ~E_4~0); 38655#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 38547#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37180#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 37181#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 37395#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 37396#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 37702#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 38557#L1404-3 assume !(0 == ~E_12~0); 38522#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 38523#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38027#L628-45 assume 1 == ~m_pc~0; 37697#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 37699#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38210#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 37431#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 37432#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38162#L647-45 assume 1 == ~t1_pc~0; 36999#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 37000#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37943#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 37109#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 37110#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 37320#L666-45 assume !(1 == ~t2_pc~0); 37321#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 37811#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38208#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 38209#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 38274#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36861#L685-45 assume 1 == ~t3_pc~0; 36862#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 37939#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38587#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 38453#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38454#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38596#L704-45 assume !(1 == ~t4_pc~0); 36728#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 36729#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37597#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38478#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 38684#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38056#L723-45 assume !(1 == ~t5_pc~0); 38057#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 38534#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38646#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 37409#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 37410#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38424#L742-45 assume 1 == ~t6_pc~0; 38425#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37674#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37884#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 37885#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38167#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38253#L761-45 assume !(1 == ~t7_pc~0); 38254#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 37668#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 37669#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 37057#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 37058#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38526#L780-45 assume 1 == ~t8_pc~0; 37435#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 37068#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 37069#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 38653#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 37037#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 37038#L799-45 assume !(1 == ~t9_pc~0); 37256#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 37257#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38319#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 38203#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38204#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 36979#L818-45 assume 1 == ~t10_pc~0; 36980#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 37097#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 38180#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 37595#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 37596#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 38299#L837-45 assume !(1 == ~t11_pc~0); 37525#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 37526#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 37049#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 37050#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 37118#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 37119#L856-45 assume !(1 == ~t12_pc~0); 37120#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 37121#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 38350#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 38351#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 37941#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 37942#L875-45 assume 1 == ~t13_pc~0; 37909#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 37910#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 37970#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 38311#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 38567#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38511#L1427-3 assume !(1 == ~M_E~0); 37736#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 37737#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38261#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 37928#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 37929#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 36766#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 36767#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38439#L1462-3 assume !(1 == ~T8_E~0); 38440#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 38307#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 38308#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 37021#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 37022#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 37164#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 37334#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 37335#L1502-3 assume !(1 == ~E_2~0); 38281#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38402#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37373#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37061#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 37062#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 37028#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 37029#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 38139#L1542-3 assume !(1 == ~E_10~0); 38267#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 37912#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 37913#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 37232#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 37233#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 36654#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 37091#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 37092#L1947 assume !(0 == start_simulation_~tmp~3#1); 38045#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 38235#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 37293#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 36716#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 36717#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38370#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38371#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 38531#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 37359#L1928-2 [2023-11-29 03:21:07,121 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:07,121 INFO L85 PathProgramCache]: Analyzing trace with hash -1779154231, now seen corresponding path program 1 times [2023-11-29 03:21:07,121 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:07,121 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1815294465] [2023-11-29 03:21:07,121 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:07,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:07,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:07,170 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:07,170 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:07,170 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1815294465] [2023-11-29 03:21:07,170 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1815294465] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:07,170 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:07,171 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:07,171 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1590662598] [2023-11-29 03:21:07,171 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:07,171 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:07,172 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:07,172 INFO L85 PathProgramCache]: Analyzing trace with hash 1650149743, now seen corresponding path program 2 times [2023-11-29 03:21:07,172 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:07,172 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [734765897] [2023-11-29 03:21:07,172 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:07,172 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:07,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:07,253 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:07,253 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:07,253 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [734765897] [2023-11-29 03:21:07,254 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [734765897] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:07,254 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:07,254 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:07,254 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [24990483] [2023-11-29 03:21:07,254 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:07,255 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:07,255 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:07,255 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:07,255 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:07,255 INFO L87 Difference]: Start difference. First operand 2032 states and 2993 transitions. cyclomatic complexity: 962 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:07,293 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:07,294 INFO L93 Difference]: Finished difference Result 2032 states and 2992 transitions. [2023-11-29 03:21:07,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2992 transitions. [2023-11-29 03:21:07,303 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:07,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2992 transitions. [2023-11-29 03:21:07,314 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:07,316 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:07,316 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2992 transitions. [2023-11-29 03:21:07,319 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:07,320 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2992 transitions. [2023-11-29 03:21:07,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2992 transitions. [2023-11-29 03:21:07,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:07,353 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4724409448818898) internal successors, (2992), 2031 states have internal predecessors, (2992), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:07,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2992 transitions. [2023-11-29 03:21:07,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2992 transitions. [2023-11-29 03:21:07,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:07,359 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2992 transitions. [2023-11-29 03:21:07,359 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 03:21:07,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2992 transitions. [2023-11-29 03:21:07,366 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:07,366 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:07,366 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:07,369 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:07,369 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:07,369 INFO L748 eck$LassoCheckResult]: Stem: 41055#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 41056#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 42042#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 42043#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 42742#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 41636#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41637#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41707#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 41708#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 42145#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 42146#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 41671#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 41476#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 41477#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 41935#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 41936#L952-1 assume !(1 == ~t11_i~0);~t11_st~0 := 2; 41815#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 41816#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 41450#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 41451#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 42666#L1279-2 assume !(0 == ~T1_E~0); 41076#L1284-1 assume !(0 == ~T2_E~0); 41077#L1289-1 assume !(0 == ~T3_E~0); 41812#L1294-1 assume !(0 == ~T4_E~0); 41813#L1299-1 assume !(0 == ~T5_E~0); 41824#L1304-1 assume !(0 == ~T6_E~0); 42741#L1309-1 assume !(0 == ~T7_E~0); 42743#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41000#L1319-1 assume !(0 == ~T9_E~0); 41001#L1324-1 assume !(0 == ~T10_E~0); 41174#L1329-1 assume !(0 == ~T11_E~0); 41175#L1334-1 assume !(0 == ~T12_E~0); 42584#L1339-1 assume !(0 == ~T13_E~0); 42656#L1344-1 assume !(0 == ~E_M~0); 42657#L1349-1 assume !(0 == ~E_1~0); 42001#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 42002#L1359-1 assume !(0 == ~E_3~0); 42409#L1364-1 assume !(0 == ~E_4~0); 41300#L1369-1 assume !(0 == ~E_5~0); 41301#L1374-1 assume !(0 == ~E_6~0); 42008#L1379-1 assume !(0 == ~E_7~0); 42009#L1384-1 assume !(0 == ~E_8~0); 42086#L1389-1 assume !(0 == ~E_9~0); 42603#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 42604#L1399-1 assume !(0 == ~E_11~0); 42697#L1404-1 assume !(0 == ~E_12~0); 41398#L1409-1 assume !(0 == ~E_13~0); 41399#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42692#L628 assume !(1 == ~m_pc~0); 41299#L628-2 is_master_triggered_~__retres1~0#1 := 0; 41298#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 41883#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41884#L1591 assume !(0 != activate_threads_~tmp~1#1); 42705#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 41864#L647 assume 1 == ~t1_pc~0; 41224#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 41225#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 41915#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 42372#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 42644#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42645#L666 assume 1 == ~t2_pc~0; 41073#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 41074#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41215#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 41216#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 42197#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42198#L685 assume !(1 == ~t3_pc~0); 42292#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 42291#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42361#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42050#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42051#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 41524#L704 assume 1 == ~t4_pc~0; 41525#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 42062#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40864#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 40865#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 41913#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 41914#L723 assume !(1 == ~t5_pc~0); 42046#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 42264#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42402#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 42176#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 42177#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 41282#L742 assume 1 == ~t6_pc~0; 41283#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41439#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41206#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 40969#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 40970#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 41360#L761 assume !(1 == ~t7_pc~0); 41361#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 41236#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41237#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 42053#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 42054#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 40992#L780 assume 1 == ~t8_pc~0; 40993#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41272#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41273#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42015#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 42016#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 42132#L799 assume 1 == ~t9_pc~0; 42234#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 40995#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 40996#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 41267#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 42335#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 42158#L818 assume !(1 == ~t10_pc~0); 40779#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 40780#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42227#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 42161#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 42162#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42204#L837 assume 1 == ~t11_pc~0; 42205#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 42040#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 42648#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 42125#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 42126#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41872#L856 assume !(1 == ~t12_pc~0); 41873#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 42507#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 40797#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 40798#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 42485#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42669#L875 assume 1 == ~t13_pc~0; 41822#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41440#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 41441#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 41378#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 41379#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42226#L1427 assume !(1 == ~M_E~0); 42211#L1427-2 assume !(1 == ~T1_E~0); 41347#L1432-1 assume !(1 == ~T2_E~0); 41348#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42414#L1442-1 assume !(1 == ~T4_E~0); 42415#L1447-1 assume !(1 == ~T5_E~0); 42273#L1452-1 assume !(1 == ~T6_E~0); 40916#L1457-1 assume !(1 == ~T7_E~0); 40917#L1462-1 assume !(1 == ~T8_E~0); 42432#L1467-1 assume !(1 == ~T9_E~0); 42453#L1472-1 assume !(1 == ~T10_E~0); 42454#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 42222#L1482-1 assume !(1 == ~T12_E~0); 42223#L1487-1 assume !(1 == ~T13_E~0); 41247#L1492-1 assume !(1 == ~E_M~0); 41248#L1497-1 assume !(1 == ~E_1~0); 41618#L1502-1 assume !(1 == ~E_2~0); 41619#L1507-1 assume !(1 == ~E_3~0); 41124#L1512-1 assume !(1 == ~E_4~0); 41125#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 42526#L1522-1 assume !(1 == ~E_6~0); 41861#L1527-1 assume !(1 == ~E_7~0); 41862#L1532-1 assume !(1 == ~E_8~0); 42727#L1537-1 assume !(1 == ~E_9~0); 42069#L1542-1 assume !(1 == ~E_10~0); 41890#L1547-1 assume !(1 == ~E_11~0); 41891#L1552-1 assume !(1 == ~E_12~0); 40820#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 40821#L1562-1 assume { :end_inline_reset_delta_events } true; 41430#L1928-2 [2023-11-29 03:21:07,370 INFO L750 eck$LassoCheckResult]: Loop: 41430#L1928-2 assume !false; 41928#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 41505#L1254-1 assume !false; 41737#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41149#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41150#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41349#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 42512#L1067 assume !(0 != eval_~tmp~0#1); 41802#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 41407#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 41408#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 41638#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 41622#L1284-3 assume !(0 == ~T2_E~0); 41623#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 41603#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 41604#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 41996#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 41997#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 41484#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 41485#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42475#L1324-3 assume !(0 == ~T10_E~0); 41122#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 41123#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 41896#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 41897#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 42201#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 41468#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 41469#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 42209#L1364-3 assume !(0 == ~E_4~0); 42726#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42618#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 41251#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 41252#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 41466#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 41467#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 41773#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 42628#L1404-3 assume !(0 == ~E_12~0); 42593#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 42594#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42098#L628-45 assume 1 == ~m_pc~0; 41768#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 41770#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42281#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 41502#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 41503#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42233#L647-45 assume !(1 == ~t1_pc~0); 41072#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 41071#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42014#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 41180#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 41181#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 41391#L666-45 assume !(1 == ~t2_pc~0); 41392#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 41882#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42279#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 42280#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42345#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40932#L685-45 assume 1 == ~t3_pc~0; 40933#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42010#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42658#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 42524#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42525#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42667#L704-45 assume 1 == ~t4_pc~0; 42548#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 40800#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 41668#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 42549#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42755#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 42127#L723-45 assume !(1 == ~t5_pc~0); 42128#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 42605#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42717#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 41480#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 41481#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42495#L742-45 assume 1 == ~t6_pc~0; 42496#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 41745#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41955#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 41956#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 42238#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 42324#L761-45 assume !(1 == ~t7_pc~0); 42325#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 41739#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 41740#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 41128#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 41129#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 42597#L780-45 assume 1 == ~t8_pc~0; 41506#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 41139#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 41140#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 42724#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 41108#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 41109#L799-45 assume 1 == ~t9_pc~0; 41894#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 41328#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 42390#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 42274#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 42275#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 41050#L818-45 assume 1 == ~t10_pc~0; 41051#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 41168#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 42251#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 41666#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 41667#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 42370#L837-45 assume !(1 == ~t11_pc~0); 41596#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 41597#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 41120#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 41121#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 41189#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 41190#L856-45 assume !(1 == ~t12_pc~0); 41191#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 41192#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 42421#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 42422#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 42012#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 42013#L875-45 assume 1 == ~t13_pc~0; 41980#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 41981#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 42041#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 42382#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 42638#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42582#L1427-3 assume !(1 == ~M_E~0); 41807#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 41808#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 42332#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 41999#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42000#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 40837#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 40838#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 42510#L1462-3 assume !(1 == ~T8_E~0); 42511#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 42378#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 42379#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 41092#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 41093#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 41235#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 41405#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 41406#L1502-3 assume !(1 == ~E_2~0); 42352#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 42473#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 41444#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 41132#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 41133#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 41099#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 41100#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 42210#L1542-3 assume !(1 == ~E_10~0); 42338#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 41983#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 41984#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 41303#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 41304#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 40725#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 41162#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 41163#L1947 assume !(0 == start_simulation_~tmp~3#1); 42116#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 42306#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 41364#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 40787#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 40788#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 42441#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 42442#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 42602#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 41430#L1928-2 [2023-11-29 03:21:07,370 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:07,370 INFO L85 PathProgramCache]: Analyzing trace with hash 584687431, now seen corresponding path program 1 times [2023-11-29 03:21:07,370 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:07,370 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [206112622] [2023-11-29 03:21:07,370 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:07,371 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:07,386 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:07,417 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:07,417 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:07,418 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [206112622] [2023-11-29 03:21:07,418 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [206112622] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:07,418 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:07,418 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:07,418 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1942041105] [2023-11-29 03:21:07,418 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:07,419 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:07,419 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:07,419 INFO L85 PathProgramCache]: Analyzing trace with hash -1084600146, now seen corresponding path program 1 times [2023-11-29 03:21:07,419 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:07,419 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [306300574] [2023-11-29 03:21:07,420 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:07,420 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:07,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:07,480 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:07,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:07,481 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [306300574] [2023-11-29 03:21:07,481 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [306300574] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:07,481 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:07,481 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:07,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [609549821] [2023-11-29 03:21:07,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:07,482 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:07,482 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:07,482 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:07,482 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:07,482 INFO L87 Difference]: Start difference. First operand 2032 states and 2992 transitions. cyclomatic complexity: 961 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:07,520 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:07,520 INFO L93 Difference]: Finished difference Result 2032 states and 2991 transitions. [2023-11-29 03:21:07,520 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2991 transitions. [2023-11-29 03:21:07,529 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:07,539 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2991 transitions. [2023-11-29 03:21:07,540 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:07,542 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:07,542 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2991 transitions. [2023-11-29 03:21:07,545 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:07,545 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2991 transitions. [2023-11-29 03:21:07,549 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2991 transitions. [2023-11-29 03:21:07,573 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:07,577 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4719488188976377) internal successors, (2991), 2031 states have internal predecessors, (2991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:07,582 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2991 transitions. [2023-11-29 03:21:07,582 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2991 transitions. [2023-11-29 03:21:07,582 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:07,583 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2991 transitions. [2023-11-29 03:21:07,583 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 03:21:07,583 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2991 transitions. [2023-11-29 03:21:07,589 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:07,590 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:07,590 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:07,592 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:07,592 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:07,592 INFO L748 eck$LassoCheckResult]: Stem: 45126#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 45127#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 46113#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 46114#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 46813#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 45707#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 45708#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 45778#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 45779#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 46216#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 46217#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 45742#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 45547#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 45548#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 46006#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 46007#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 45886#L957-1 assume !(1 == ~t12_i~0);~t12_st~0 := 2; 45887#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 45521#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 45522#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 46737#L1279-2 assume !(0 == ~T1_E~0); 45147#L1284-1 assume !(0 == ~T2_E~0); 45148#L1289-1 assume !(0 == ~T3_E~0); 45883#L1294-1 assume !(0 == ~T4_E~0); 45884#L1299-1 assume !(0 == ~T5_E~0); 45895#L1304-1 assume !(0 == ~T6_E~0); 46812#L1309-1 assume !(0 == ~T7_E~0); 46814#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45071#L1319-1 assume !(0 == ~T9_E~0); 45072#L1324-1 assume !(0 == ~T10_E~0); 45245#L1329-1 assume !(0 == ~T11_E~0); 45246#L1334-1 assume !(0 == ~T12_E~0); 46655#L1339-1 assume !(0 == ~T13_E~0); 46727#L1344-1 assume !(0 == ~E_M~0); 46728#L1349-1 assume !(0 == ~E_1~0); 46072#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 46073#L1359-1 assume !(0 == ~E_3~0); 46480#L1364-1 assume !(0 == ~E_4~0); 45371#L1369-1 assume !(0 == ~E_5~0); 45372#L1374-1 assume !(0 == ~E_6~0); 46079#L1379-1 assume !(0 == ~E_7~0); 46080#L1384-1 assume !(0 == ~E_8~0); 46157#L1389-1 assume !(0 == ~E_9~0); 46674#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 46675#L1399-1 assume !(0 == ~E_11~0); 46768#L1404-1 assume !(0 == ~E_12~0); 45469#L1409-1 assume !(0 == ~E_13~0); 45470#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46763#L628 assume !(1 == ~m_pc~0); 45370#L628-2 is_master_triggered_~__retres1~0#1 := 0; 45369#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 45954#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45955#L1591 assume !(0 != activate_threads_~tmp~1#1); 46776#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 45935#L647 assume 1 == ~t1_pc~0; 45295#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45296#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 45986#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 46443#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 46715#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 46716#L666 assume 1 == ~t2_pc~0; 45144#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 45145#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 45286#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 45287#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 46268#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 46269#L685 assume !(1 == ~t3_pc~0); 46363#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 46362#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46432#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46121#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46122#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 45595#L704 assume 1 == ~t4_pc~0; 45596#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 46133#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 44935#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 44936#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 45984#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 45985#L723 assume !(1 == ~t5_pc~0); 46117#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 46335#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46473#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 46247#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 46248#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45353#L742 assume 1 == ~t6_pc~0; 45354#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45510#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 45277#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 45040#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 45041#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 45431#L761 assume !(1 == ~t7_pc~0); 45432#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 45307#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45308#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 46124#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 46125#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 45063#L780 assume 1 == ~t8_pc~0; 45064#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45343#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45344#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46086#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 46087#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 46203#L799 assume 1 == ~t9_pc~0; 46305#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 45066#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 45067#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 45338#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 46406#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 46229#L818 assume !(1 == ~t10_pc~0); 44850#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 44851#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46298#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 46232#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 46233#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46275#L837 assume 1 == ~t11_pc~0; 46276#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 46111#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 46719#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 46196#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 46197#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45943#L856 assume !(1 == ~t12_pc~0); 45944#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 46578#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 44868#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 44869#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 46556#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46740#L875 assume 1 == ~t13_pc~0; 45893#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 45511#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 45512#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 45449#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 45450#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46297#L1427 assume !(1 == ~M_E~0); 46282#L1427-2 assume !(1 == ~T1_E~0); 45418#L1432-1 assume !(1 == ~T2_E~0); 45419#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46485#L1442-1 assume !(1 == ~T4_E~0); 46486#L1447-1 assume !(1 == ~T5_E~0); 46344#L1452-1 assume !(1 == ~T6_E~0); 44987#L1457-1 assume !(1 == ~T7_E~0); 44988#L1462-1 assume !(1 == ~T8_E~0); 46503#L1467-1 assume !(1 == ~T9_E~0); 46524#L1472-1 assume !(1 == ~T10_E~0); 46525#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 46293#L1482-1 assume !(1 == ~T12_E~0); 46294#L1487-1 assume !(1 == ~T13_E~0); 45318#L1492-1 assume !(1 == ~E_M~0); 45319#L1497-1 assume !(1 == ~E_1~0); 45689#L1502-1 assume !(1 == ~E_2~0); 45690#L1507-1 assume !(1 == ~E_3~0); 45195#L1512-1 assume !(1 == ~E_4~0); 45196#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 46597#L1522-1 assume !(1 == ~E_6~0); 45932#L1527-1 assume !(1 == ~E_7~0); 45933#L1532-1 assume !(1 == ~E_8~0); 46798#L1537-1 assume !(1 == ~E_9~0); 46140#L1542-1 assume !(1 == ~E_10~0); 45961#L1547-1 assume !(1 == ~E_11~0); 45962#L1552-1 assume !(1 == ~E_12~0); 44891#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 44892#L1562-1 assume { :end_inline_reset_delta_events } true; 45501#L1928-2 [2023-11-29 03:21:07,592 INFO L750 eck$LassoCheckResult]: Loop: 45501#L1928-2 assume !false; 45999#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 45576#L1254-1 assume !false; 45808#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45220#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45221#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45420#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 46583#L1067 assume !(0 != eval_~tmp~0#1); 45873#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 45478#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 45479#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 45709#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 45693#L1284-3 assume !(0 == ~T2_E~0); 45694#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 45674#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 45675#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 46067#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 46068#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 45555#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 45556#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 46546#L1324-3 assume !(0 == ~T10_E~0); 45193#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 45194#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 45967#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 45968#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 46272#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 45539#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 45540#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 46280#L1364-3 assume !(0 == ~E_4~0); 46797#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 46689#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 45322#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 45323#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 45537#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 45538#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 45844#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 46699#L1404-3 assume !(0 == ~E_12~0); 46664#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 46665#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 46169#L628-45 assume !(1 == ~m_pc~0); 45840#L628-47 is_master_triggered_~__retres1~0#1 := 0; 45841#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 46352#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 45573#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 45574#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 46304#L647-45 assume 1 == ~t1_pc~0; 45141#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 45142#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 46085#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 45251#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 45252#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 45462#L666-45 assume !(1 == ~t2_pc~0); 45463#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 45953#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 46350#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 46351#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 46416#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 45003#L685-45 assume 1 == ~t3_pc~0; 45004#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 46081#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 46729#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 46595#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 46596#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 46738#L704-45 assume !(1 == ~t4_pc~0); 44870#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 44871#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 45739#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 46620#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46826#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46198#L723-45 assume !(1 == ~t5_pc~0); 46199#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 46676#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46788#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 45551#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 45552#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46566#L742-45 assume 1 == ~t6_pc~0; 46567#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 45816#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46026#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 46027#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46309#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 46395#L761-45 assume !(1 == ~t7_pc~0); 46396#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 45810#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 45811#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 45199#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 45200#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 46668#L780-45 assume 1 == ~t8_pc~0; 45577#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 45210#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 45211#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 46795#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 45179#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 45180#L799-45 assume !(1 == ~t9_pc~0); 45398#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 45399#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 46461#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 46345#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 46346#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 45121#L818-45 assume 1 == ~t10_pc~0; 45122#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 45239#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 46322#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 45737#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 45738#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 46441#L837-45 assume !(1 == ~t11_pc~0); 45667#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 45668#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 45191#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 45192#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 45260#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 45261#L856-45 assume 1 == ~t12_pc~0; 46736#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 45263#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 46492#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 46493#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 46083#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 46084#L875-45 assume 1 == ~t13_pc~0; 46051#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 46052#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 46112#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 46453#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 46709#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46653#L1427-3 assume !(1 == ~M_E~0); 45878#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 45879#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46403#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 46070#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46071#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 44908#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 44909#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 46581#L1462-3 assume !(1 == ~T8_E~0); 46582#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 46449#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 46450#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 45163#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 45164#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 45306#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 45476#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 45477#L1502-3 assume !(1 == ~E_2~0); 46423#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46544#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 45515#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 45203#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 45204#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 45170#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 45171#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 46281#L1542-3 assume !(1 == ~E_10~0); 46409#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 46054#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 46055#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 45374#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 45375#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 44796#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 45233#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 45234#L1947 assume !(0 == start_simulation_~tmp~3#1); 46187#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 46377#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 45435#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 44858#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 44859#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46512#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46513#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 46673#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 45501#L1928-2 [2023-11-29 03:21:07,593 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:07,593 INFO L85 PathProgramCache]: Analyzing trace with hash 1907866377, now seen corresponding path program 1 times [2023-11-29 03:21:07,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:07,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205584213] [2023-11-29 03:21:07,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:07,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:07,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:07,643 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:07,644 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:07,644 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1205584213] [2023-11-29 03:21:07,644 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1205584213] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:07,644 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:07,644 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:07,644 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [767237361] [2023-11-29 03:21:07,644 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:07,645 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:07,645 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:07,645 INFO L85 PathProgramCache]: Analyzing trace with hash 144470127, now seen corresponding path program 1 times [2023-11-29 03:21:07,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:07,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1302350850] [2023-11-29 03:21:07,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:07,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:07,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:07,723 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:07,723 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:07,723 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1302350850] [2023-11-29 03:21:07,723 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1302350850] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:07,723 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:07,723 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:07,724 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1753647933] [2023-11-29 03:21:07,724 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:07,724 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:07,724 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:07,725 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:07,725 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:07,725 INFO L87 Difference]: Start difference. First operand 2032 states and 2991 transitions. cyclomatic complexity: 960 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:07,757 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:07,758 INFO L93 Difference]: Finished difference Result 2032 states and 2990 transitions. [2023-11-29 03:21:07,758 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2990 transitions. [2023-11-29 03:21:07,765 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:07,773 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2990 transitions. [2023-11-29 03:21:07,773 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:07,774 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:07,775 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2990 transitions. [2023-11-29 03:21:07,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:07,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2990 transitions. [2023-11-29 03:21:07,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2990 transitions. [2023-11-29 03:21:07,801 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:07,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4714566929133859) internal successors, (2990), 2031 states have internal predecessors, (2990), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:07,808 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2990 transitions. [2023-11-29 03:21:07,808 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2990 transitions. [2023-11-29 03:21:07,809 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:07,809 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2990 transitions. [2023-11-29 03:21:07,809 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 03:21:07,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2990 transitions. [2023-11-29 03:21:07,817 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:07,817 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:07,817 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:07,819 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:07,819 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:07,820 INFO L748 eck$LassoCheckResult]: Stem: 49197#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 49198#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 50184#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 50185#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 50884#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 49778#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 49779#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 49849#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 49850#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 50287#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 50288#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 49813#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 49618#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 49619#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 50077#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 50078#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 49957#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 49958#L962-1 assume !(1 == ~t13_i~0);~t13_st~0 := 2; 49592#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 49593#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 50808#L1279-2 assume !(0 == ~T1_E~0); 49218#L1284-1 assume !(0 == ~T2_E~0); 49219#L1289-1 assume !(0 == ~T3_E~0); 49954#L1294-1 assume !(0 == ~T4_E~0); 49955#L1299-1 assume !(0 == ~T5_E~0); 49966#L1304-1 assume !(0 == ~T6_E~0); 50883#L1309-1 assume !(0 == ~T7_E~0); 50885#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49142#L1319-1 assume !(0 == ~T9_E~0); 49143#L1324-1 assume !(0 == ~T10_E~0); 49316#L1329-1 assume !(0 == ~T11_E~0); 49317#L1334-1 assume !(0 == ~T12_E~0); 50726#L1339-1 assume !(0 == ~T13_E~0); 50798#L1344-1 assume !(0 == ~E_M~0); 50799#L1349-1 assume !(0 == ~E_1~0); 50143#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 50144#L1359-1 assume !(0 == ~E_3~0); 50551#L1364-1 assume !(0 == ~E_4~0); 49442#L1369-1 assume !(0 == ~E_5~0); 49443#L1374-1 assume !(0 == ~E_6~0); 50150#L1379-1 assume !(0 == ~E_7~0); 50151#L1384-1 assume !(0 == ~E_8~0); 50228#L1389-1 assume !(0 == ~E_9~0); 50745#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 50746#L1399-1 assume !(0 == ~E_11~0); 50839#L1404-1 assume !(0 == ~E_12~0); 49540#L1409-1 assume !(0 == ~E_13~0); 49541#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50834#L628 assume !(1 == ~m_pc~0); 49441#L628-2 is_master_triggered_~__retres1~0#1 := 0; 49440#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50025#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 50026#L1591 assume !(0 != activate_threads_~tmp~1#1); 50847#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50006#L647 assume 1 == ~t1_pc~0; 49366#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49367#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50057#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 50514#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 50786#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 50787#L666 assume 1 == ~t2_pc~0; 49215#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49216#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49357#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49358#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 50339#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 50340#L685 assume !(1 == ~t3_pc~0); 50434#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 50433#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50503#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50192#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50193#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49666#L704 assume 1 == ~t4_pc~0; 49667#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 50204#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49006#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49007#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 50055#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50056#L723 assume !(1 == ~t5_pc~0); 50188#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 50406#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50544#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 50318#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 50319#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49424#L742 assume 1 == ~t6_pc~0; 49425#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49581#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49348#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49111#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 49112#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49502#L761 assume !(1 == ~t7_pc~0); 49503#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 49378#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49379#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 50195#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 50196#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49134#L780 assume 1 == ~t8_pc~0; 49135#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49414#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49415#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50157#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 50158#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 50274#L799 assume 1 == ~t9_pc~0; 50376#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49137#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49138#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 49409#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 50477#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 50300#L818 assume !(1 == ~t10_pc~0); 48921#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 48922#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50369#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 50303#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 50304#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50346#L837 assume 1 == ~t11_pc~0; 50347#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 50182#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 50790#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 50267#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 50268#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 50014#L856 assume !(1 == ~t12_pc~0); 50015#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 50649#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 48939#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 48940#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 50627#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50811#L875 assume 1 == ~t13_pc~0; 49964#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 49582#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 49583#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 49520#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 49521#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50368#L1427 assume !(1 == ~M_E~0); 50353#L1427-2 assume !(1 == ~T1_E~0); 49489#L1432-1 assume !(1 == ~T2_E~0); 49490#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50556#L1442-1 assume !(1 == ~T4_E~0); 50557#L1447-1 assume !(1 == ~T5_E~0); 50415#L1452-1 assume !(1 == ~T6_E~0); 49058#L1457-1 assume !(1 == ~T7_E~0); 49059#L1462-1 assume !(1 == ~T8_E~0); 50574#L1467-1 assume !(1 == ~T9_E~0); 50595#L1472-1 assume !(1 == ~T10_E~0); 50596#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 50364#L1482-1 assume !(1 == ~T12_E~0); 50365#L1487-1 assume !(1 == ~T13_E~0); 49389#L1492-1 assume !(1 == ~E_M~0); 49390#L1497-1 assume !(1 == ~E_1~0); 49760#L1502-1 assume !(1 == ~E_2~0); 49761#L1507-1 assume !(1 == ~E_3~0); 49266#L1512-1 assume !(1 == ~E_4~0); 49267#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 50668#L1522-1 assume !(1 == ~E_6~0); 50003#L1527-1 assume !(1 == ~E_7~0); 50004#L1532-1 assume !(1 == ~E_8~0); 50869#L1537-1 assume !(1 == ~E_9~0); 50211#L1542-1 assume !(1 == ~E_10~0); 50032#L1547-1 assume !(1 == ~E_11~0); 50033#L1552-1 assume !(1 == ~E_12~0); 48962#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 48963#L1562-1 assume { :end_inline_reset_delta_events } true; 49572#L1928-2 [2023-11-29 03:21:07,820 INFO L750 eck$LassoCheckResult]: Loop: 49572#L1928-2 assume !false; 50070#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 49647#L1254-1 assume !false; 49879#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49291#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49292#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49491#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 50654#L1067 assume !(0 != eval_~tmp~0#1); 49944#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 49549#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 49550#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 49780#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 49764#L1284-3 assume !(0 == ~T2_E~0); 49765#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 49745#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49746#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 50138#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 50139#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49626#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 49627#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 50617#L1324-3 assume !(0 == ~T10_E~0); 49264#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 49265#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 50038#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 50039#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 50343#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 49610#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49611#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 50351#L1364-3 assume !(0 == ~E_4~0); 50868#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 50760#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 49393#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49394#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49608#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 49609#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49915#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 50770#L1404-3 assume !(0 == ~E_12~0); 50735#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 50736#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 50240#L628-45 assume 1 == ~m_pc~0; 49910#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 49912#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 50423#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49644#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 49645#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 50375#L647-45 assume 1 == ~t1_pc~0; 49212#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49213#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 50156#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49322#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49323#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49533#L666-45 assume !(1 == ~t2_pc~0); 49534#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 50024#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 50421#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 50422#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 50487#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49074#L685-45 assume 1 == ~t3_pc~0; 49075#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 50152#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 50800#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 50666#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 50667#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 50809#L704-45 assume 1 == ~t4_pc~0; 50690#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 48942#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49810#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 50691#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 50897#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 50269#L723-45 assume !(1 == ~t5_pc~0); 50270#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 50747#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 50859#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49622#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 49623#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 50637#L742-45 assume 1 == ~t6_pc~0; 50638#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 49887#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 50097#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 50098#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 50380#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 50466#L761-45 assume !(1 == ~t7_pc~0); 50467#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 49881#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49882#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 49270#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49271#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 50739#L780-45 assume 1 == ~t8_pc~0; 49648#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 49281#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49282#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 50866#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49250#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49251#L799-45 assume 1 == ~t9_pc~0; 50036#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49470#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 50532#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 50416#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 50417#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49192#L818-45 assume 1 == ~t10_pc~0; 49193#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49310#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 50393#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 49808#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49809#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 50512#L837-45 assume !(1 == ~t11_pc~0); 49738#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 49739#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 49262#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 49263#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 49331#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 49332#L856-45 assume !(1 == ~t12_pc~0); 49333#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 49334#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 50563#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 50564#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 50154#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 50155#L875-45 assume 1 == ~t13_pc~0; 50122#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 50123#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 50183#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 50524#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 50780#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 50724#L1427-3 assume !(1 == ~M_E~0); 49949#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49950#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 50474#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 50141#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 50142#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 48979#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48980#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 50652#L1462-3 assume !(1 == ~T8_E~0); 50653#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 50520#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 50521#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 49234#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 49235#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 49377#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 49547#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 49548#L1502-3 assume !(1 == ~E_2~0); 50494#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 50615#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49586#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49274#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49275#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49241#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49242#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 50352#L1542-3 assume !(1 == ~E_10~0); 50480#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 50125#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 50126#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 49445#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 49446#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 48867#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 49304#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 49305#L1947 assume !(0 == start_simulation_~tmp~3#1); 50258#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 50448#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 49506#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 48929#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 48930#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 50583#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 50584#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 50744#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 49572#L1928-2 [2023-11-29 03:21:07,820 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:07,821 INFO L85 PathProgramCache]: Analyzing trace with hash 10886919, now seen corresponding path program 1 times [2023-11-29 03:21:07,821 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:07,821 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2068686106] [2023-11-29 03:21:07,821 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:07,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:07,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:07,860 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:07,861 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:07,861 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2068686106] [2023-11-29 03:21:07,861 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2068686106] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:07,861 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:07,861 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:07,861 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1602578177] [2023-11-29 03:21:07,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:07,862 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:07,862 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:07,862 INFO L85 PathProgramCache]: Analyzing trace with hash 340495405, now seen corresponding path program 1 times [2023-11-29 03:21:07,862 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:07,862 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [44543702] [2023-11-29 03:21:07,863 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:07,863 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:07,874 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:07,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:07,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:07,903 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [44543702] [2023-11-29 03:21:07,903 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [44543702] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:07,903 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:07,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:07,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1335755846] [2023-11-29 03:21:07,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:07,904 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:07,904 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:07,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:07,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:07,905 INFO L87 Difference]: Start difference. First operand 2032 states and 2990 transitions. cyclomatic complexity: 959 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:07,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:07,929 INFO L93 Difference]: Finished difference Result 2032 states and 2989 transitions. [2023-11-29 03:21:07,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2032 states and 2989 transitions. [2023-11-29 03:21:07,935 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:07,943 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2032 states to 2032 states and 2989 transitions. [2023-11-29 03:21:07,944 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2032 [2023-11-29 03:21:07,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2032 [2023-11-29 03:21:07,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2032 states and 2989 transitions. [2023-11-29 03:21:07,947 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:07,947 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2989 transitions. [2023-11-29 03:21:07,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2032 states and 2989 transitions. [2023-11-29 03:21:07,970 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2032 to 2032. [2023-11-29 03:21:07,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2032 states, 2032 states have (on average 1.4709645669291338) internal successors, (2989), 2031 states have internal predecessors, (2989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:07,976 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2032 states to 2032 states and 2989 transitions. [2023-11-29 03:21:07,976 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2032 states and 2989 transitions. [2023-11-29 03:21:07,976 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:07,977 INFO L428 stractBuchiCegarLoop]: Abstraction has 2032 states and 2989 transitions. [2023-11-29 03:21:07,977 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 03:21:07,977 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2032 states and 2989 transitions. [2023-11-29 03:21:07,984 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1857 [2023-11-29 03:21:07,984 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:07,984 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:07,986 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:07,986 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:07,986 INFO L748 eck$LassoCheckResult]: Stem: 53268#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 53269#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 54255#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54256#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54955#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 53849#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53850#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 53920#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53921#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 54358#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 54359#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53884#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53689#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53690#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 54148#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 54149#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 54028#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 54029#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 53663#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53664#L1279 assume 0 == ~M_E~0;~M_E~0 := 1; 54879#L1279-2 assume !(0 == ~T1_E~0); 53289#L1284-1 assume !(0 == ~T2_E~0); 53290#L1289-1 assume !(0 == ~T3_E~0); 54025#L1294-1 assume !(0 == ~T4_E~0); 54026#L1299-1 assume !(0 == ~T5_E~0); 54037#L1304-1 assume !(0 == ~T6_E~0); 54954#L1309-1 assume !(0 == ~T7_E~0); 54956#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53213#L1319-1 assume !(0 == ~T9_E~0); 53214#L1324-1 assume !(0 == ~T10_E~0); 53387#L1329-1 assume !(0 == ~T11_E~0); 53388#L1334-1 assume !(0 == ~T12_E~0); 54797#L1339-1 assume !(0 == ~T13_E~0); 54869#L1344-1 assume !(0 == ~E_M~0); 54870#L1349-1 assume !(0 == ~E_1~0); 54214#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 54215#L1359-1 assume !(0 == ~E_3~0); 54622#L1364-1 assume !(0 == ~E_4~0); 53513#L1369-1 assume !(0 == ~E_5~0); 53514#L1374-1 assume !(0 == ~E_6~0); 54221#L1379-1 assume !(0 == ~E_7~0); 54222#L1384-1 assume !(0 == ~E_8~0); 54299#L1389-1 assume !(0 == ~E_9~0); 54816#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 54817#L1399-1 assume !(0 == ~E_11~0); 54910#L1404-1 assume !(0 == ~E_12~0); 53611#L1409-1 assume !(0 == ~E_13~0); 53612#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54905#L628 assume !(1 == ~m_pc~0); 53512#L628-2 is_master_triggered_~__retres1~0#1 := 0; 53511#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54096#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 54097#L1591 assume !(0 != activate_threads_~tmp~1#1); 54918#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54077#L647 assume 1 == ~t1_pc~0; 53437#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53438#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54128#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 54585#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 54857#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54858#L666 assume 1 == ~t2_pc~0; 53286#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 53287#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53428#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53429#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 54410#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 54411#L685 assume !(1 == ~t3_pc~0); 54505#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54504#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54574#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54263#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54264#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53737#L704 assume 1 == ~t4_pc~0; 53738#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 54275#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53077#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 53078#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 54126#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54127#L723 assume !(1 == ~t5_pc~0); 54259#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 54477#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54615#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 54389#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 54390#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 53495#L742 assume 1 == ~t6_pc~0; 53496#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53652#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53419#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 53182#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 53183#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53573#L761 assume !(1 == ~t7_pc~0); 53574#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53449#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53450#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 54266#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 54267#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53205#L780 assume 1 == ~t8_pc~0; 53206#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53485#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53486#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54228#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 54229#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 54345#L799 assume 1 == ~t9_pc~0; 54447#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 53208#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 53209#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 53480#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 54548#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 54371#L818 assume !(1 == ~t10_pc~0); 52992#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 52993#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54440#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 54374#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 54375#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54417#L837 assume 1 == ~t11_pc~0; 54418#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 54253#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 54861#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 54338#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 54339#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 54085#L856 assume !(1 == ~t12_pc~0); 54086#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 54720#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 53010#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 53011#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 54698#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54882#L875 assume 1 == ~t13_pc~0; 54035#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 53653#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 53654#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 53591#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 53592#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54439#L1427 assume !(1 == ~M_E~0); 54424#L1427-2 assume !(1 == ~T1_E~0); 53560#L1432-1 assume !(1 == ~T2_E~0); 53561#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54627#L1442-1 assume !(1 == ~T4_E~0); 54628#L1447-1 assume !(1 == ~T5_E~0); 54486#L1452-1 assume !(1 == ~T6_E~0); 53129#L1457-1 assume !(1 == ~T7_E~0); 53130#L1462-1 assume !(1 == ~T8_E~0); 54645#L1467-1 assume !(1 == ~T9_E~0); 54666#L1472-1 assume !(1 == ~T10_E~0); 54667#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 54435#L1482-1 assume !(1 == ~T12_E~0); 54436#L1487-1 assume !(1 == ~T13_E~0); 53460#L1492-1 assume !(1 == ~E_M~0); 53461#L1497-1 assume !(1 == ~E_1~0); 53831#L1502-1 assume !(1 == ~E_2~0); 53832#L1507-1 assume !(1 == ~E_3~0); 53337#L1512-1 assume !(1 == ~E_4~0); 53338#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 54739#L1522-1 assume !(1 == ~E_6~0); 54074#L1527-1 assume !(1 == ~E_7~0); 54075#L1532-1 assume !(1 == ~E_8~0); 54940#L1537-1 assume !(1 == ~E_9~0); 54282#L1542-1 assume !(1 == ~E_10~0); 54103#L1547-1 assume !(1 == ~E_11~0); 54104#L1552-1 assume !(1 == ~E_12~0); 53033#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 53034#L1562-1 assume { :end_inline_reset_delta_events } true; 53643#L1928-2 [2023-11-29 03:21:07,986 INFO L750 eck$LassoCheckResult]: Loop: 53643#L1928-2 assume !false; 54141#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53718#L1254-1 assume !false; 53950#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53362#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53363#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53562#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 54725#L1067 assume !(0 != eval_~tmp~0#1); 54015#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 53620#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 53621#L1279-3 assume 0 == ~M_E~0;~M_E~0 := 1; 53851#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 53835#L1284-3 assume !(0 == ~T2_E~0); 53836#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 53816#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 53817#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 54209#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 54210#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 53697#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 53698#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 54688#L1324-3 assume !(0 == ~T10_E~0); 53335#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 53336#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 54109#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 54110#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 54414#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 53681#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 53682#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 54422#L1364-3 assume !(0 == ~E_4~0); 54939#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 54831#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 53464#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 53465#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 53679#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 53680#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 53986#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 54841#L1404-3 assume !(0 == ~E_12~0); 54806#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 54807#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 54311#L628-45 assume 1 == ~m_pc~0; 53981#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 53983#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54494#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53715#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 53716#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 54446#L647-45 assume 1 == ~t1_pc~0; 53283#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 53284#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 54227#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53393#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 53394#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53604#L666-45 assume !(1 == ~t2_pc~0); 53605#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 54095#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 54492#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 54493#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 54558#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53145#L685-45 assume 1 == ~t3_pc~0; 53146#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 54223#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54871#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 54737#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 54738#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 54880#L704-45 assume !(1 == ~t4_pc~0); 53012#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 53013#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53881#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 54762#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 54968#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 54340#L723-45 assume !(1 == ~t5_pc~0); 54341#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 54818#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 54930#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 53693#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 53694#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54708#L742-45 assume 1 == ~t6_pc~0; 54709#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53958#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 54168#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 54169#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 54451#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 54537#L761-45 assume !(1 == ~t7_pc~0); 54538#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 53952#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53953#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 53341#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 53342#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 54810#L780-45 assume 1 == ~t8_pc~0; 53719#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53352#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53353#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 54937#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 53321#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 53322#L799-45 assume !(1 == ~t9_pc~0); 53540#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 53541#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 54603#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 54487#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 54488#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 53263#L818-45 assume 1 == ~t10_pc~0; 53264#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 53381#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 54464#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 53879#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 53880#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 54583#L837-45 assume !(1 == ~t11_pc~0); 53809#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 53810#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 53333#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 53334#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 53402#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 53403#L856-45 assume !(1 == ~t12_pc~0); 53404#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 53405#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 54634#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 54635#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 54225#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 54226#L875-45 assume 1 == ~t13_pc~0; 54193#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 54194#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 54254#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 54595#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 54851#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 54795#L1427-3 assume !(1 == ~M_E~0); 54020#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54021#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54545#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 54212#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 54213#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 53050#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 53051#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 54723#L1462-3 assume !(1 == ~T8_E~0); 54724#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 54591#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 54592#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 53305#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 53306#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 53448#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 53618#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53619#L1502-3 assume !(1 == ~E_2~0); 54565#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 54686#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53657#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 53345#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53346#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53312#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53313#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 54423#L1542-3 assume !(1 == ~E_10~0); 54551#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 54196#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 54197#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 53516#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 53517#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 52938#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53375#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 53376#L1947 assume !(0 == start_simulation_~tmp~3#1); 54329#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 54519#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 53577#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 53000#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 53001#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 54654#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 54655#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 54815#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 53643#L1928-2 [2023-11-29 03:21:07,987 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:07,987 INFO L85 PathProgramCache]: Analyzing trace with hash -327400631, now seen corresponding path program 1 times [2023-11-29 03:21:07,987 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:07,987 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250033524] [2023-11-29 03:21:07,987 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:07,987 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:07,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:08,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:08,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:08,044 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250033524] [2023-11-29 03:21:08,044 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250033524] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:08,044 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:08,044 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:21:08,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [269818338] [2023-11-29 03:21:08,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:08,045 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:08,045 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:08,046 INFO L85 PathProgramCache]: Analyzing trace with hash 1650149743, now seen corresponding path program 3 times [2023-11-29 03:21:08,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:08,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1576917965] [2023-11-29 03:21:08,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:08,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:08,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:08,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:08,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:08,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1576917965] [2023-11-29 03:21:08,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1576917965] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:08,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:08,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:08,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [737714874] [2023-11-29 03:21:08,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:08,090 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:08,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:08,090 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:08,090 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:08,091 INFO L87 Difference]: Start difference. First operand 2032 states and 2989 transitions. cyclomatic complexity: 958 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:08,200 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:08,201 INFO L93 Difference]: Finished difference Result 3789 states and 5556 transitions. [2023-11-29 03:21:08,201 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3789 states and 5556 transitions. [2023-11-29 03:21:08,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2023-11-29 03:21:08,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3789 states to 3789 states and 5556 transitions. [2023-11-29 03:21:08,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3789 [2023-11-29 03:21:08,225 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3789 [2023-11-29 03:21:08,225 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3789 states and 5556 transitions. [2023-11-29 03:21:08,229 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:08,229 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5556 transitions. [2023-11-29 03:21:08,233 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3789 states and 5556 transitions. [2023-11-29 03:21:08,283 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3789 to 3789. [2023-11-29 03:21:08,287 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.466349960411718) internal successors, (5556), 3788 states have internal predecessors, (5556), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:08,293 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5556 transitions. [2023-11-29 03:21:08,294 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5556 transitions. [2023-11-29 03:21:08,294 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:08,294 INFO L428 stractBuchiCegarLoop]: Abstraction has 3789 states and 5556 transitions. [2023-11-29 03:21:08,295 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 03:21:08,295 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5556 transitions. [2023-11-29 03:21:08,304 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2023-11-29 03:21:08,304 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:08,304 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:08,305 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:08,306 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:08,306 INFO L748 eck$LassoCheckResult]: Stem: 59096#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 59097#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 60102#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60103#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60913#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 59681#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 59682#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 59753#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 59754#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60214#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60215#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 59719#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 59520#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 59521#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 59986#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 59987#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 59869#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 59870#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 59494#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 59495#L1279 assume !(0 == ~M_E~0); 60799#L1279-2 assume !(0 == ~T1_E~0); 59117#L1284-1 assume !(0 == ~T2_E~0); 59118#L1289-1 assume !(0 == ~T3_E~0); 59861#L1294-1 assume !(0 == ~T4_E~0); 59862#L1299-1 assume !(0 == ~T5_E~0); 59873#L1304-1 assume !(0 == ~T6_E~0); 60912#L1309-1 assume !(0 == ~T7_E~0); 60914#L1314-1 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59043#L1319-1 assume !(0 == ~T9_E~0); 59044#L1324-1 assume !(0 == ~T10_E~0); 59217#L1329-1 assume !(0 == ~T11_E~0); 59218#L1334-1 assume !(0 == ~T12_E~0); 60702#L1339-1 assume !(0 == ~T13_E~0); 60785#L1344-1 assume !(0 == ~E_M~0); 60786#L1349-1 assume !(0 == ~E_1~0); 60057#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 60058#L1359-1 assume !(0 == ~E_3~0); 60496#L1364-1 assume !(0 == ~E_4~0); 59343#L1369-1 assume !(0 == ~E_5~0); 59344#L1374-1 assume !(0 == ~E_6~0); 60065#L1379-1 assume !(0 == ~E_7~0); 60066#L1384-1 assume !(0 == ~E_8~0); 60148#L1389-1 assume !(0 == ~E_9~0); 60723#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 60724#L1399-1 assume !(0 == ~E_11~0); 60839#L1404-1 assume !(0 == ~E_12~0); 59442#L1409-1 assume !(0 == ~E_13~0); 59443#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60832#L628 assume !(1 == ~m_pc~0); 59342#L628-2 is_master_triggered_~__retres1~0#1 := 0; 59341#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59933#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59934#L1591 assume !(0 != activate_threads_~tmp~1#1); 60847#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59913#L647 assume 1 == ~t1_pc~0; 59267#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59268#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59966#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60455#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 60771#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60772#L666 assume 1 == ~t2_pc~0; 59114#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59115#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 59260#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 59261#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 60264#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60265#L685 assume !(1 == ~t3_pc~0); 60369#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60368#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60441#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60111#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60112#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59568#L704 assume 1 == ~t4_pc~0; 59569#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 60124#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 58905#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 58906#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 59964#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59965#L723 assume !(1 == ~t5_pc~0); 60108#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 60342#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60489#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 60246#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 60247#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59326#L742 assume 1 == ~t6_pc~0; 59327#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59483#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59249#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 59012#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 59013#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59404#L761 assume !(1 == ~t7_pc~0); 59405#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59281#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59282#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60115#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 60116#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 59033#L780 assume 1 == ~t8_pc~0; 59034#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59316#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59317#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60072#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 60073#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60201#L799 assume 1 == ~t9_pc~0; 60310#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59036#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59037#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 59310#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 60414#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60225#L818 assume !(1 == ~t10_pc~0); 58820#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 58821#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60298#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 60228#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 60229#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60272#L837 assume 1 == ~t11_pc~0; 60273#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 60101#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 60775#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 60191#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 60192#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59924#L856 assume !(1 == ~t12_pc~0); 59925#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 60606#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 58838#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 58839#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 60585#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60803#L875 assume 1 == ~t13_pc~0; 59871#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 59484#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 59485#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 59422#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 59423#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60297#L1427 assume !(1 == ~M_E~0); 60283#L1427-2 assume !(1 == ~T1_E~0); 59390#L1432-1 assume !(1 == ~T2_E~0); 59391#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60503#L1442-1 assume !(1 == ~T4_E~0); 60504#L1447-1 assume !(1 == ~T5_E~0); 60351#L1452-1 assume !(1 == ~T6_E~0); 58957#L1457-1 assume !(1 == ~T7_E~0); 58958#L1462-1 assume !(1 == ~T8_E~0); 60524#L1467-1 assume !(1 == ~T9_E~0); 60547#L1472-1 assume !(1 == ~T10_E~0); 60548#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 60293#L1482-1 assume !(1 == ~T12_E~0); 60294#L1487-1 assume !(1 == ~T13_E~0); 59290#L1492-1 assume !(1 == ~E_M~0); 59291#L1497-1 assume !(1 == ~E_1~0); 59663#L1502-1 assume !(1 == ~E_2~0); 59664#L1507-1 assume !(1 == ~E_3~0); 59166#L1512-1 assume !(1 == ~E_4~0); 59167#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 60634#L1522-1 assume !(1 == ~E_6~0); 59911#L1527-1 assume !(1 == ~E_7~0); 59912#L1532-1 assume !(1 == ~E_8~0); 60889#L1537-1 assume !(1 == ~E_9~0); 60131#L1542-1 assume !(1 == ~E_10~0); 59941#L1547-1 assume !(1 == ~E_11~0); 59942#L1552-1 assume !(1 == ~E_12~0); 58863#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 58864#L1562-1 assume { :end_inline_reset_delta_events } true; 59474#L1928-2 [2023-11-29 03:21:08,306 INFO L750 eck$LassoCheckResult]: Loop: 59474#L1928-2 assume !false; 60104#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 59783#L1254-1 assume !false; 59784#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59191#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 59192#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 60647#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 60648#L1067 assume !(0 != eval_~tmp~0#1); 59855#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 59451#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 59452#L1279-3 assume !(0 == ~M_E~0); 60994#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 59668#L1284-3 assume !(0 == ~T2_E~0); 59669#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60993#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60992#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 60048#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60049#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 59529#L1314-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 59530#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60935#L1324-3 assume !(0 == ~T10_E~0); 60990#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 60989#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 59951#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 59952#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 60325#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 59512#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 59513#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 60279#L1364-3 assume !(0 == ~E_4~0); 60911#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60739#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 59292#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 59293#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 59510#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 59511#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 59821#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 60930#L1404-3 assume !(0 == ~E_12~0); 60713#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 60714#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60160#L628-45 assume !(1 == ~m_pc~0); 60161#L628-47 is_master_triggered_~__retres1~0#1 := 0; 60879#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60880#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59546#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 59547#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60304#L647-45 assume 1 == ~t1_pc~0; 59111#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 59112#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60980#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60979#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60796#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 59435#L666-45 assume !(1 == ~t2_pc~0); 59436#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 60861#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60862#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60429#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60430#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60977#L685-45 assume !(1 == ~t3_pc~0); 60064#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 60063#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60976#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60630#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60631#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60838#L704-45 assume 1 == ~t4_pc~0; 60663#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58841#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59714#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60972#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60971#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60193#L723-45 assume !(1 == ~t5_pc~0); 60194#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 60725#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60968#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 59524#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 59525#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60924#L742-45 assume 1 == ~t6_pc~0; 60965#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60277#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60278#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 60311#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 60312#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60401#L761-45 assume !(1 == ~t7_pc~0); 60402#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 59786#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 59787#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 60961#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60960#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60717#L780-45 assume 1 == ~t8_pc~0; 59550#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 59181#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59182#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 60887#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60888#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59944#L799-45 assume 1 == ~t9_pc~0; 59945#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59371#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 60941#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 60349#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 60350#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 60953#L818-45 assume 1 == ~t10_pc~0; 60454#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 59209#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 60565#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 59711#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 59712#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 60780#L837-45 assume !(1 == ~t11_pc~0); 60781#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 59788#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 59162#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 59163#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 59232#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 59233#L856-45 assume !(1 == ~t12_pc~0); 60944#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 60626#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 60627#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 60947#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 60068#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 60069#L875-45 assume 1 == ~t13_pc~0; 60032#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 60033#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 60465#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 60466#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 60946#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60700#L1427-3 assume !(1 == ~M_E~0); 59856#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 59857#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60409#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60050#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60051#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 58878#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 58879#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 60610#L1462-3 assume !(1 == ~T8_E~0); 60611#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 60461#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 60462#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 59134#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 59135#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 59278#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 59449#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 59450#L1502-3 assume !(1 == ~E_2~0); 60432#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 60570#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 59488#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 59174#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 59175#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 59141#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 59142#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 60280#L1542-3 assume !(1 == ~E_10~0); 60415#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 60035#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 60036#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 59346#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 59347#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 58766#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 59204#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 59205#L1947 assume !(0 == start_simulation_~tmp~3#1); 60180#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 60383#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 61034#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 61033#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 61032#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 61031#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 61030#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 61029#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 59474#L1928-2 [2023-11-29 03:21:08,306 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:08,307 INFO L85 PathProgramCache]: Analyzing trace with hash -867830137, now seen corresponding path program 1 times [2023-11-29 03:21:08,307 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:08,307 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1155623483] [2023-11-29 03:21:08,307 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:08,307 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:08,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:08,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:08,366 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:08,366 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1155623483] [2023-11-29 03:21:08,366 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1155623483] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:08,366 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:08,366 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:08,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [225778809] [2023-11-29 03:21:08,367 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:08,367 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:08,367 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:08,368 INFO L85 PathProgramCache]: Analyzing trace with hash -679170003, now seen corresponding path program 1 times [2023-11-29 03:21:08,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:08,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1127185871] [2023-11-29 03:21:08,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:08,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:08,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:08,410 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:08,410 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:08,411 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1127185871] [2023-11-29 03:21:08,411 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1127185871] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:08,411 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:08,411 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:08,411 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1359241594] [2023-11-29 03:21:08,411 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:08,411 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:08,412 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:08,412 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:21:08,412 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:21:08,412 INFO L87 Difference]: Start difference. First operand 3789 states and 5556 transitions. cyclomatic complexity: 1768 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:08,533 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:08,533 INFO L93 Difference]: Finished difference Result 5538 states and 8105 transitions. [2023-11-29 03:21:08,533 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5538 states and 8105 transitions. [2023-11-29 03:21:08,550 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5343 [2023-11-29 03:21:08,565 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5538 states to 5538 states and 8105 transitions. [2023-11-29 03:21:08,566 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5538 [2023-11-29 03:21:08,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5538 [2023-11-29 03:21:08,570 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5538 states and 8105 transitions. [2023-11-29 03:21:08,574 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:08,574 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5538 states and 8105 transitions. [2023-11-29 03:21:08,581 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5538 states and 8105 transitions. [2023-11-29 03:21:08,681 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5538 to 3789. [2023-11-29 03:21:08,685 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.4655581947743468) internal successors, (5553), 3788 states have internal predecessors, (5553), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:08,693 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5553 transitions. [2023-11-29 03:21:08,693 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5553 transitions. [2023-11-29 03:21:08,693 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:21:08,694 INFO L428 stractBuchiCegarLoop]: Abstraction has 3789 states and 5553 transitions. [2023-11-29 03:21:08,694 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 03:21:08,694 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5553 transitions. [2023-11-29 03:21:08,704 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2023-11-29 03:21:08,704 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:08,704 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:08,706 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:08,706 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:08,706 INFO L748 eck$LassoCheckResult]: Stem: 68433#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 68434#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 69424#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 69425#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70147#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 69015#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 69016#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 69086#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 69087#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 69529#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 69530#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 69052#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 68854#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 68855#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 69315#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 69316#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 69200#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 69201#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 68828#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 68829#L1279 assume !(0 == ~M_E~0); 70057#L1279-2 assume !(0 == ~T1_E~0); 68454#L1284-1 assume !(0 == ~T2_E~0); 68455#L1289-1 assume !(0 == ~T3_E~0); 69192#L1294-1 assume !(0 == ~T4_E~0); 69193#L1299-1 assume !(0 == ~T5_E~0); 69204#L1304-1 assume !(0 == ~T6_E~0); 70144#L1309-1 assume !(0 == ~T7_E~0); 70148#L1314-1 assume !(0 == ~T8_E~0); 68380#L1319-1 assume !(0 == ~T9_E~0); 68381#L1324-1 assume !(0 == ~T10_E~0); 68552#L1329-1 assume !(0 == ~T11_E~0); 68553#L1334-1 assume !(0 == ~T12_E~0); 69972#L1339-1 assume !(0 == ~T13_E~0); 70047#L1344-1 assume !(0 == ~E_M~0); 70048#L1349-1 assume !(0 == ~E_1~0); 69385#L1354-1 assume 0 == ~E_2~0;~E_2~0 := 1; 69386#L1359-1 assume !(0 == ~E_3~0); 69791#L1364-1 assume !(0 == ~E_4~0); 68678#L1369-1 assume !(0 == ~E_5~0); 68679#L1374-1 assume !(0 == ~E_6~0); 69392#L1379-1 assume !(0 == ~E_7~0); 69393#L1384-1 assume !(0 == ~E_8~0); 69468#L1389-1 assume !(0 == ~E_9~0); 69992#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 69993#L1399-1 assume !(0 == ~E_11~0); 70092#L1404-1 assume !(0 == ~E_12~0); 68776#L1409-1 assume !(0 == ~E_13~0); 68777#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70085#L628 assume !(1 == ~m_pc~0); 68677#L628-2 is_master_triggered_~__retres1~0#1 := 0; 68676#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69263#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 69264#L1591 assume !(0 != activate_threads_~tmp~1#1); 70101#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69244#L647 assume 1 == ~t1_pc~0; 68605#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68606#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69295#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 69754#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 70035#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70036#L666 assume 1 == ~t2_pc~0; 68451#L667 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 68452#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 68595#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 68596#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 69579#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 69580#L685 assume !(1 == ~t3_pc~0); 69674#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 69673#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 69743#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69433#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69434#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 68902#L704 assume 1 == ~t4_pc~0; 68903#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 69444#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 68242#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 68243#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 69293#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69294#L723 assume !(1 == ~t5_pc~0); 69429#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 69648#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 69784#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 69561#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 69562#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 68661#L742 assume 1 == ~t6_pc~0; 68662#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 68817#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 68584#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 68349#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 68350#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 68738#L761 assume !(1 == ~t7_pc~0); 68739#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 68616#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 68617#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 69435#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 69436#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 68370#L780 assume 1 == ~t8_pc~0; 68371#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 68651#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68652#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 69397#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 69398#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 69517#L799 assume 1 == ~t9_pc~0; 69619#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 68373#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 68374#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 68645#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 69719#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 69540#L818 assume !(1 == ~t10_pc~0); 68157#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 68158#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69611#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69543#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69544#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69586#L837 assume 1 == ~t11_pc~0; 69587#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 69423#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 70039#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 69507#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 69508#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 69255#L856 assume !(1 == ~t12_pc~0); 69256#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 69892#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 68175#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 68176#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 69872#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 70060#L875 assume 1 == ~t13_pc~0; 69202#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 68818#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 68819#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 68756#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 68757#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69608#L1427 assume !(1 == ~M_E~0); 69595#L1427-2 assume !(1 == ~T1_E~0); 68725#L1432-1 assume !(1 == ~T2_E~0); 68726#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69796#L1442-1 assume !(1 == ~T4_E~0); 69797#L1447-1 assume !(1 == ~T5_E~0); 69657#L1452-1 assume !(1 == ~T6_E~0); 68294#L1457-1 assume !(1 == ~T7_E~0); 68295#L1462-1 assume !(1 == ~T8_E~0); 69817#L1467-1 assume !(1 == ~T9_E~0); 69837#L1472-1 assume !(1 == ~T10_E~0); 69838#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 69604#L1482-1 assume !(1 == ~T12_E~0); 69605#L1487-1 assume !(1 == ~T13_E~0); 68625#L1492-1 assume !(1 == ~E_M~0); 68626#L1497-1 assume !(1 == ~E_1~0); 68997#L1502-1 assume !(1 == ~E_2~0); 68998#L1507-1 assume !(1 == ~E_3~0); 68502#L1512-1 assume !(1 == ~E_4~0); 68503#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 69912#L1522-1 assume !(1 == ~E_6~0); 69242#L1527-1 assume !(1 == ~E_7~0); 69243#L1532-1 assume !(1 == ~E_8~0); 70128#L1537-1 assume !(1 == ~E_9~0); 69454#L1542-1 assume !(1 == ~E_10~0); 69271#L1547-1 assume !(1 == ~E_11~0); 69272#L1552-1 assume !(1 == ~E_12~0); 68200#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 68201#L1562-1 assume { :end_inline_reset_delta_events } true; 68808#L1928-2 [2023-11-29 03:21:08,706 INFO L750 eck$LassoCheckResult]: Loop: 68808#L1928-2 assume !false; 69308#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 68883#L1254-1 assume !false; 69116#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68527#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68528#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68727#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 69897#L1067 assume !(0 != eval_~tmp~0#1); 69186#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 68785#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 68786#L1279-3 assume !(0 == ~M_E~0); 69017#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 69001#L1284-3 assume !(0 == ~T2_E~0); 69002#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 68982#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 68983#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 69378#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 69379#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 68863#L1314-3 assume !(0 == ~T8_E~0); 68864#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 69860#L1324-3 assume !(0 == ~T10_E~0); 68500#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 68501#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 69277#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 69278#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 69583#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 68846#L1354-3 assume 0 == ~E_2~0;~E_2~0 := 1; 68847#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 69591#L1364-3 assume !(0 == ~E_4~0); 70127#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 70007#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 68629#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 68630#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 68844#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 68845#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 69152#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 70017#L1404-3 assume !(0 == ~E_12~0); 69982#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 69983#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 69480#L628-45 assume 1 == ~m_pc~0; 69147#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 69149#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 69663#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 68880#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 68881#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 69615#L647-45 assume 1 == ~t1_pc~0; 68448#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 68449#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 69396#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 68558#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 68559#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 68769#L666-45 assume 1 == ~t2_pc~0; 68771#L667-15 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 69262#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 69661#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 69662#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 69727#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 68310#L685-45 assume 1 == ~t3_pc~0; 68311#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 69391#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70049#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 69910#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 69911#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70059#L704-45 assume !(1 == ~t4_pc~0); 68180#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 68181#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 69047#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 69935#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 70160#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 69509#L723-45 assume 1 == ~t5_pc~0; 69511#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 69994#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70117#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 68858#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 68859#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 69880#L742-45 assume !(1 == ~t6_pc~0); 69124#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 69125#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 69335#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 69336#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 69620#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 69707#L761-45 assume 1 == ~t7_pc~0; 69709#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 69118#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 69119#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 68506#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 68507#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 69986#L780-45 assume !(1 == ~t8_pc~0); 68885#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 68515#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 68516#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 70125#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 68486#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 68487#L799-45 assume !(1 == ~t9_pc~0); 68704#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 68705#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 69772#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 69655#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 69656#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 68425#L818-45 assume !(1 == ~t10_pc~0); 68427#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 68544#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 69633#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 69042#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 69043#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 69752#L837-45 assume 1 == ~t11_pc~0; 70044#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 68975#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 68496#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 68497#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 68567#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 68568#L856-45 assume !(1 == ~t12_pc~0); 68569#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 68570#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 69804#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 69805#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 69394#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 69395#L875-45 assume 1 == ~t13_pc~0; 69362#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 69363#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 69421#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 69763#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 70025#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 69970#L1427-3 assume !(1 == ~M_E~0); 69187#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 69188#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 69714#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 69380#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69381#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 68215#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 68216#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 69895#L1462-3 assume !(1 == ~T8_E~0); 69896#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 69760#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 69761#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 68470#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 68471#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 68613#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 68783#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 68784#L1502-3 assume !(1 == ~E_2~0); 69734#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69858#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 68822#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 68510#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 68511#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 68477#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 68478#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 69592#L1542-3 assume !(1 == ~E_10~0); 69720#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 69365#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 69366#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 68681#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 68682#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68103#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68538#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 68539#L1947 assume !(0 == start_simulation_~tmp~3#1); 69498#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 69688#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 68742#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 68165#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 68166#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 69825#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 69826#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 69990#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 68808#L1928-2 [2023-11-29 03:21:08,707 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:08,707 INFO L85 PathProgramCache]: Analyzing trace with hash 1809696709, now seen corresponding path program 1 times [2023-11-29 03:21:08,707 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:08,707 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267478144] [2023-11-29 03:21:08,707 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:08,707 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:08,719 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:08,754 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:08,754 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:08,755 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [267478144] [2023-11-29 03:21:08,755 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [267478144] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:08,755 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:08,755 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:21:08,755 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [139019444] [2023-11-29 03:21:08,755 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:08,755 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:08,756 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:08,756 INFO L85 PathProgramCache]: Analyzing trace with hash -1593720982, now seen corresponding path program 1 times [2023-11-29 03:21:08,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:08,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [236529606] [2023-11-29 03:21:08,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:08,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:08,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:08,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:08,803 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:08,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [236529606] [2023-11-29 03:21:08,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [236529606] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:08,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:08,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:08,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1997123992] [2023-11-29 03:21:08,803 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:08,804 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:08,804 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:08,804 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:08,804 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:08,804 INFO L87 Difference]: Start difference. First operand 3789 states and 5553 transitions. cyclomatic complexity: 1765 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:08,901 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:08,901 INFO L93 Difference]: Finished difference Result 3789 states and 5515 transitions. [2023-11-29 03:21:08,901 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3789 states and 5515 transitions. [2023-11-29 03:21:08,911 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2023-11-29 03:21:08,919 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3789 states to 3789 states and 5515 transitions. [2023-11-29 03:21:08,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3789 [2023-11-29 03:21:08,922 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3789 [2023-11-29 03:21:08,922 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3789 states and 5515 transitions. [2023-11-29 03:21:08,924 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:08,924 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5515 transitions. [2023-11-29 03:21:08,928 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3789 states and 5515 transitions. [2023-11-29 03:21:08,961 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3789 to 3789. [2023-11-29 03:21:08,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.4555291633676433) internal successors, (5515), 3788 states have internal predecessors, (5515), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:08,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5515 transitions. [2023-11-29 03:21:08,972 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5515 transitions. [2023-11-29 03:21:08,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:08,973 INFO L428 stractBuchiCegarLoop]: Abstraction has 3789 states and 5515 transitions. [2023-11-29 03:21:08,973 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 03:21:08,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5515 transitions. [2023-11-29 03:21:08,981 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2023-11-29 03:21:08,981 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:08,981 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:08,983 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:08,983 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:08,983 INFO L748 eck$LassoCheckResult]: Stem: 76017#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 76018#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 77012#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 77013#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 77785#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 76599#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 76600#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 76671#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 76672#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 77121#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 77122#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 76636#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 76437#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 76438#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 76900#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 76901#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 76785#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 76786#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 76411#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 76412#L1279 assume !(0 == ~M_E~0); 77682#L1279-2 assume !(0 == ~T1_E~0); 76037#L1284-1 assume !(0 == ~T2_E~0); 76038#L1289-1 assume !(0 == ~T3_E~0); 76777#L1294-1 assume !(0 == ~T4_E~0); 76778#L1299-1 assume !(0 == ~T5_E~0); 76789#L1304-1 assume !(0 == ~T6_E~0); 77783#L1309-1 assume !(0 == ~T7_E~0); 77786#L1314-1 assume !(0 == ~T8_E~0); 75964#L1319-1 assume !(0 == ~T9_E~0); 75965#L1324-1 assume !(0 == ~T10_E~0); 76135#L1329-1 assume !(0 == ~T11_E~0); 76136#L1334-1 assume !(0 == ~T12_E~0); 77588#L1339-1 assume !(0 == ~T13_E~0); 77670#L1344-1 assume !(0 == ~E_M~0); 77671#L1349-1 assume !(0 == ~E_1~0); 76970#L1354-1 assume !(0 == ~E_2~0); 76971#L1359-1 assume !(0 == ~E_3~0); 77391#L1364-1 assume !(0 == ~E_4~0); 76261#L1369-1 assume !(0 == ~E_5~0); 76262#L1374-1 assume !(0 == ~E_6~0); 76977#L1379-1 assume !(0 == ~E_7~0); 76978#L1384-1 assume !(0 == ~E_8~0); 77058#L1389-1 assume !(0 == ~E_9~0); 77609#L1394-1 assume 0 == ~E_10~0;~E_10~0 := 1; 77610#L1399-1 assume !(0 == ~E_11~0); 77721#L1404-1 assume !(0 == ~E_12~0); 76359#L1409-1 assume !(0 == ~E_13~0); 76360#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77713#L628 assume !(1 == ~m_pc~0); 76260#L628-2 is_master_triggered_~__retres1~0#1 := 0; 76259#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76848#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76849#L1591 assume !(0 != activate_threads_~tmp~1#1); 77730#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76829#L647 assume 1 == ~t1_pc~0; 76188#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76189#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76880#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 77351#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 77656#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77657#L666 assume !(1 == ~t2_pc~0); 76036#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 76203#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76177#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76178#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 77171#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77172#L685 assume !(1 == ~t3_pc~0); 77267#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 77266#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77338#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77022#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77023#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76485#L704 assume 1 == ~t4_pc~0; 76486#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 77033#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 75827#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 75828#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 76878#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76879#L723 assume !(1 == ~t5_pc~0); 77018#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 77241#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77384#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 77153#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 77154#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76244#L742 assume 1 == ~t6_pc~0; 76245#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 76400#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76166#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 75933#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 75934#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76322#L761 assume !(1 == ~t7_pc~0); 76323#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 76199#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76200#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 77024#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 77025#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 75954#L780 assume 1 == ~t8_pc~0; 75955#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76234#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76235#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 76982#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 76983#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 77108#L799 assume 1 == ~t9_pc~0; 77212#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 75957#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 75958#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 76229#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 77312#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 77132#L818 assume !(1 == ~t10_pc~0); 75742#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 75743#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77204#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 77135#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 77136#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77178#L837 assume 1 == ~t11_pc~0; 77179#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 77010#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 77660#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 77098#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 77099#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76840#L856 assume !(1 == ~t12_pc~0); 76841#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 77493#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 75760#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 75761#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 77473#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 77687#L875 assume 1 == ~t13_pc~0; 76787#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 76401#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 76402#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 76340#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 76341#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77201#L1427 assume !(1 == ~M_E~0); 77187#L1427-2 assume !(1 == ~T1_E~0); 76308#L1432-1 assume !(1 == ~T2_E~0); 76309#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 77396#L1442-1 assume !(1 == ~T4_E~0); 77397#L1447-1 assume !(1 == ~T5_E~0); 77250#L1452-1 assume !(1 == ~T6_E~0); 75878#L1457-1 assume !(1 == ~T7_E~0); 75879#L1462-1 assume !(1 == ~T8_E~0); 77416#L1467-1 assume !(1 == ~T9_E~0); 77438#L1472-1 assume !(1 == ~T10_E~0); 77439#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 77197#L1482-1 assume !(1 == ~T12_E~0); 77198#L1487-1 assume !(1 == ~T13_E~0); 76209#L1492-1 assume !(1 == ~E_M~0); 76210#L1497-1 assume !(1 == ~E_1~0); 76581#L1502-1 assume !(1 == ~E_2~0); 76582#L1507-1 assume !(1 == ~E_3~0); 76085#L1512-1 assume !(1 == ~E_4~0); 76086#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 77514#L1522-1 assume !(1 == ~E_6~0); 76827#L1527-1 assume !(1 == ~E_7~0); 76828#L1532-1 assume !(1 == ~E_8~0); 77766#L1537-1 assume !(1 == ~E_9~0); 77043#L1542-1 assume !(1 == ~E_10~0); 76856#L1547-1 assume !(1 == ~E_11~0); 76857#L1552-1 assume !(1 == ~E_12~0); 75785#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 75786#L1562-1 assume { :end_inline_reset_delta_events } true; 76391#L1928-2 [2023-11-29 03:21:08,984 INFO L750 eck$LassoCheckResult]: Loop: 76391#L1928-2 assume !false; 77011#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 76701#L1254-1 assume !false; 76702#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 76110#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76111#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77530#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 77531#L1067 assume !(0 != eval_~tmp~0#1); 77811#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77810#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77712#L1279-3 assume !(0 == ~M_E~0); 76601#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 76585#L1284-3 assume !(0 == ~T2_E~0); 76586#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 76565#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76566#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 76963#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76964#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 76445#L1314-3 assume !(0 == ~T8_E~0); 76446#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 77460#L1324-3 assume !(0 == ~T10_E~0); 76083#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 76084#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 76861#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 76862#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 77175#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 76429#L1354-3 assume !(0 == ~E_2~0); 76430#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 77183#L1364-3 assume !(0 == ~E_4~0); 77763#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77626#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76213#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 76214#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 76427#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 76428#L1394-3 assume 0 == ~E_10~0;~E_10~0 := 1; 76738#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 77636#L1404-3 assume !(0 == ~E_12~0); 77599#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 77600#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77070#L628-45 assume 1 == ~m_pc~0; 76733#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 76735#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77256#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76463#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 76464#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77208#L647-45 assume 1 == ~t1_pc~0; 76032#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 76033#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76981#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76140#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76141#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76352#L666-45 assume !(1 == ~t2_pc~0); 76353#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 76847#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77254#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 77255#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77320#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 75894#L685-45 assume 1 == ~t3_pc~0; 75895#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76976#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77672#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 77512#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77513#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77683#L704-45 assume !(1 == ~t4_pc~0); 75765#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 75766#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76631#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 77546#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77805#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77100#L723-45 assume !(1 == ~t5_pc~0); 77101#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 77611#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77745#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 76441#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 76442#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77481#L742-45 assume !(1 == ~t6_pc~0); 76710#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 76711#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76921#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 76922#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77213#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 77299#L761-45 assume 1 == ~t7_pc~0; 77301#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 76704#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76705#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 76089#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 76090#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 77603#L780-45 assume 1 == ~t8_pc~0; 76467#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76102#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76103#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 77758#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 76069#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 76070#L799-45 assume !(1 == ~t9_pc~0); 76291#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 76292#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 77372#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 77248#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 77249#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 76012#L818-45 assume 1 == ~t10_pc~0; 76013#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 76131#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 77226#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 76629#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 76630#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 77348#L837-45 assume !(1 == ~t11_pc~0); 76561#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 76562#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 76081#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 76082#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 76152#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 76153#L856-45 assume 1 == ~t12_pc~0; 77681#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 76155#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 77511#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 78077#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 78075#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 78073#L875-45 assume 1 == ~t13_pc~0; 78071#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 78068#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 78066#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 78064#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 78062#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 78060#L1427-3 assume !(1 == ~M_E~0); 77586#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 78057#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 78055#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 78053#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 78051#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 78049#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 78047#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 78045#L1462-3 assume !(1 == ~T8_E~0); 78043#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 78041#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 78039#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 78038#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 78037#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 78036#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 78035#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 78034#L1502-3 assume !(1 == ~E_2~0); 78033#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 78032#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 78031#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 78030#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 78029#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 78028#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 78027#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 78026#L1542-3 assume !(1 == ~E_10~0); 78025#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 78024#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 78023#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 78022#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77984#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 77976#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 77974#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 77972#L1947 assume !(0 == start_simulation_~tmp~3#1); 77969#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 77403#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 76326#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 75750#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 75751#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77422#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77423#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 77607#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 76391#L1928-2 [2023-11-29 03:21:08,984 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:08,984 INFO L85 PathProgramCache]: Analyzing trace with hash 350046660, now seen corresponding path program 1 times [2023-11-29 03:21:08,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:08,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [474432463] [2023-11-29 03:21:08,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:08,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:08,996 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:09,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:09,044 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:09,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [474432463] [2023-11-29 03:21:09,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [474432463] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:09,045 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:09,045 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:09,045 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690471408] [2023-11-29 03:21:09,045 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:09,045 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:09,046 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:09,046 INFO L85 PathProgramCache]: Analyzing trace with hash -2132936536, now seen corresponding path program 1 times [2023-11-29 03:21:09,046 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:09,046 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2036366424] [2023-11-29 03:21:09,046 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:09,046 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:09,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:09,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:09,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:09,140 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2036366424] [2023-11-29 03:21:09,140 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2036366424] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:09,140 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:09,140 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:09,141 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [305853357] [2023-11-29 03:21:09,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:09,141 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:09,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:09,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:21:09,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:21:09,142 INFO L87 Difference]: Start difference. First operand 3789 states and 5515 transitions. cyclomatic complexity: 1727 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:09,334 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:09,334 INFO L93 Difference]: Finished difference Result 5423 states and 7875 transitions. [2023-11-29 03:21:09,334 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5423 states and 7875 transitions. [2023-11-29 03:21:09,350 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 5243 [2023-11-29 03:21:09,362 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5423 states to 5423 states and 7875 transitions. [2023-11-29 03:21:09,363 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5423 [2023-11-29 03:21:09,366 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5423 [2023-11-29 03:21:09,366 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5423 states and 7875 transitions. [2023-11-29 03:21:09,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:09,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5423 states and 7875 transitions. [2023-11-29 03:21:09,376 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5423 states and 7875 transitions. [2023-11-29 03:21:09,414 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5423 to 3789. [2023-11-29 03:21:09,418 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3789 states, 3789 states have (on average 1.4547373977302718) internal successors, (5512), 3788 states have internal predecessors, (5512), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:09,424 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3789 states to 3789 states and 5512 transitions. [2023-11-29 03:21:09,424 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3789 states and 5512 transitions. [2023-11-29 03:21:09,425 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:21:09,425 INFO L428 stractBuchiCegarLoop]: Abstraction has 3789 states and 5512 transitions. [2023-11-29 03:21:09,425 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 03:21:09,426 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3789 states and 5512 transitions. [2023-11-29 03:21:09,434 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 3614 [2023-11-29 03:21:09,434 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:09,434 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:09,436 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:09,436 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:09,436 INFO L748 eck$LassoCheckResult]: Stem: 85242#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 85243#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 86248#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 86249#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 87012#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 85830#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 85831#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 85902#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 85903#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 86353#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 86354#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 85868#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 85666#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 85667#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 86134#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 86135#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 86019#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 86020#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 85639#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 85640#L1279 assume !(0 == ~M_E~0); 86911#L1279-2 assume !(0 == ~T1_E~0); 85262#L1284-1 assume !(0 == ~T2_E~0); 85263#L1289-1 assume !(0 == ~T3_E~0); 86011#L1294-1 assume !(0 == ~T4_E~0); 86012#L1299-1 assume !(0 == ~T5_E~0); 86023#L1304-1 assume !(0 == ~T6_E~0); 87011#L1309-1 assume !(0 == ~T7_E~0); 87013#L1314-1 assume !(0 == ~T8_E~0); 85188#L1319-1 assume !(0 == ~T9_E~0); 85189#L1324-1 assume !(0 == ~T10_E~0); 85360#L1329-1 assume !(0 == ~T11_E~0); 85361#L1334-1 assume !(0 == ~T12_E~0); 86817#L1339-1 assume !(0 == ~T13_E~0); 86898#L1344-1 assume !(0 == ~E_M~0); 86899#L1349-1 assume !(0 == ~E_1~0); 86205#L1354-1 assume !(0 == ~E_2~0); 86206#L1359-1 assume !(0 == ~E_3~0); 86629#L1364-1 assume !(0 == ~E_4~0); 85488#L1369-1 assume !(0 == ~E_5~0); 85489#L1374-1 assume !(0 == ~E_6~0); 86212#L1379-1 assume !(0 == ~E_7~0); 86213#L1384-1 assume !(0 == ~E_8~0); 86292#L1389-1 assume !(0 == ~E_9~0); 86840#L1394-1 assume !(0 == ~E_10~0); 86841#L1399-1 assume !(0 == ~E_11~0); 86948#L1404-1 assume !(0 == ~E_12~0); 85586#L1409-1 assume !(0 == ~E_13~0); 85587#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86940#L628 assume !(1 == ~m_pc~0); 85487#L628-2 is_master_triggered_~__retres1~0#1 := 0; 85486#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86082#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86083#L1591 assume !(0 != activate_threads_~tmp~1#1); 86957#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86063#L647 assume 1 == ~t1_pc~0; 85414#L648 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85415#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86114#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 86591#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 86886#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 86887#L666 assume !(1 == ~t2_pc~0); 85261#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 85429#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 85404#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 85405#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 86405#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 86406#L685 assume !(1 == ~t3_pc~0); 86505#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 86504#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86576#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86257#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86258#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 85714#L704 assume 1 == ~t4_pc~0; 85715#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 86268#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85049#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 85050#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 86112#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86113#L723 assume !(1 == ~t5_pc~0); 86253#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 86476#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86622#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 86387#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 86388#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 85471#L742 assume 1 == ~t6_pc~0; 85472#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85628#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85393#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 85157#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 85158#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 85548#L761 assume !(1 == ~t7_pc~0); 85549#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 85425#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85426#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 86259#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 86260#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 85178#L780 assume 1 == ~t8_pc~0; 85179#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 85461#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85462#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86217#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 86218#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 86341#L799 assume 1 == ~t9_pc~0; 86447#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 85181#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 85182#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 85456#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 86550#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 86364#L818 assume !(1 == ~t10_pc~0); 84964#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 84965#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86439#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 86367#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86368#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86412#L837 assume 1 == ~t11_pc~0; 86413#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 86247#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 86890#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 86331#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 86332#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 86074#L856 assume !(1 == ~t12_pc~0); 86075#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 86737#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 84982#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 84983#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 86716#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86914#L875 assume 1 == ~t13_pc~0; 86021#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 85629#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 85630#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 85567#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 85568#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86434#L1427 assume !(1 == ~M_E~0); 86421#L1427-2 assume !(1 == ~T1_E~0); 85535#L1432-1 assume !(1 == ~T2_E~0); 85536#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86634#L1442-1 assume !(1 == ~T4_E~0); 86635#L1447-1 assume !(1 == ~T5_E~0); 86485#L1452-1 assume !(1 == ~T6_E~0); 85101#L1457-1 assume !(1 == ~T7_E~0); 85102#L1462-1 assume !(1 == ~T8_E~0); 86657#L1467-1 assume !(1 == ~T9_E~0); 86677#L1472-1 assume !(1 == ~T10_E~0); 86678#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 86430#L1482-1 assume !(1 == ~T12_E~0); 86431#L1487-1 assume !(1 == ~T13_E~0); 85435#L1492-1 assume !(1 == ~E_M~0); 85436#L1497-1 assume !(1 == ~E_1~0); 85811#L1502-1 assume !(1 == ~E_2~0); 85812#L1507-1 assume !(1 == ~E_3~0); 85310#L1512-1 assume !(1 == ~E_4~0); 85311#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 86756#L1522-1 assume !(1 == ~E_6~0); 86061#L1527-1 assume !(1 == ~E_7~0); 86062#L1532-1 assume !(1 == ~E_8~0); 86984#L1537-1 assume !(1 == ~E_9~0); 86278#L1542-1 assume !(1 == ~E_10~0); 86090#L1547-1 assume !(1 == ~E_11~0); 86091#L1552-1 assume !(1 == ~E_12~0); 85007#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 85008#L1562-1 assume { :end_inline_reset_delta_events } true; 85618#L1928-2 [2023-11-29 03:21:09,436 INFO L750 eck$LassoCheckResult]: Loop: 85618#L1928-2 assume !false; 86127#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 85695#L1254-1 assume !false; 85934#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85335#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85336#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85537#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 86742#L1067 assume !(0 != eval_~tmp~0#1); 86005#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 85595#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 85596#L1279-3 assume !(0 == ~M_E~0); 85834#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 85815#L1284-3 assume !(0 == ~T2_E~0); 85816#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 85795#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 85796#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 86198#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 86199#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 85675#L1314-3 assume !(0 == ~T8_E~0); 85676#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 86702#L1324-3 assume !(0 == ~T10_E~0); 85308#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 85309#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 86096#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 86097#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 86409#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 85658#L1354-3 assume !(0 == ~E_2~0); 85659#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 86417#L1364-3 assume !(0 == ~E_4~0); 86983#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 86856#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 85439#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 85440#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 85656#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 85657#L1394-3 assume !(0 == ~E_10~0); 85970#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 86866#L1404-3 assume !(0 == ~E_12~0); 86830#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 86831#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 86304#L628-45 assume !(1 == ~m_pc~0); 85968#L628-47 is_master_triggered_~__retres1~0#1 := 0; 85969#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 86494#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 85692#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 85693#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 86443#L647-45 assume 1 == ~t1_pc~0; 85257#L648-15 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 85258#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 86216#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 85367#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 85368#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 85579#L666-45 assume !(1 == ~t2_pc~0); 85580#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 86081#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 86492#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 86493#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 86558#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 85117#L685-45 assume !(1 == ~t3_pc~0); 85119#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 86211#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 86903#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 86754#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 86755#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 86913#L704-45 assume !(1 == ~t4_pc~0); 84987#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 84988#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 85863#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 86781#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87032#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 86333#L723-45 assume 1 == ~t5_pc~0; 86335#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 86842#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 86969#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 85670#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 85671#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 86724#L742-45 assume 1 == ~t6_pc~0; 86725#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 85942#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 86154#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86155#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 86448#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86537#L761-45 assume 1 == ~t7_pc~0; 86539#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 85936#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 85937#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 85314#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 85315#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 86833#L780-45 assume !(1 == ~t8_pc~0); 85697#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 85323#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 85324#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 86977#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 85294#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 85295#L799-45 assume !(1 == ~t9_pc~0); 85514#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 85515#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 86610#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 86483#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 86484#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 85235#L818-45 assume !(1 == ~t10_pc~0); 85237#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 85352#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86461#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 85860#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 85861#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 86586#L837-45 assume !(1 == ~t11_pc~0); 85787#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 85788#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 85304#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 85305#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 85376#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 85377#L856-45 assume !(1 == ~t12_pc~0); 85378#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 85379#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 86642#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 86643#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 86214#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 86215#L875-45 assume 1 == ~t13_pc~0; 86182#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 86183#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 86245#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 86600#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 86878#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86815#L1427-3 assume !(1 == ~M_E~0); 86006#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86007#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 86545#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86200#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86201#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 85022#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85023#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86740#L1462-3 assume !(1 == ~T8_E~0); 86741#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86597#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86598#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 85278#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 85279#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 85422#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 85593#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 85594#L1502-3 assume !(1 == ~E_2~0); 86565#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86700#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 85633#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 85318#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 85319#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 85285#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 85286#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 86418#L1542-3 assume !(1 == ~E_10~0); 86551#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 86185#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 86186#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 85491#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 85492#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 84910#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 85348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 85349#L1947 assume !(0 == start_simulation_~tmp~3#1); 86322#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 86519#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 85552#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 84972#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 84973#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86665#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86666#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 86838#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 85618#L1928-2 [2023-11-29 03:21:09,437 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:09,437 INFO L85 PathProgramCache]: Analyzing trace with hash -1492429054, now seen corresponding path program 1 times [2023-11-29 03:21:09,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:09,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1835381716] [2023-11-29 03:21:09,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:09,437 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:09,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:09,488 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:09,489 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:09,489 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1835381716] [2023-11-29 03:21:09,489 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1835381716] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:09,489 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:09,489 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:21:09,489 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2068994266] [2023-11-29 03:21:09,489 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:09,490 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:09,490 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:09,490 INFO L85 PathProgramCache]: Analyzing trace with hash -2090864471, now seen corresponding path program 1 times [2023-11-29 03:21:09,490 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:09,490 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1765148450] [2023-11-29 03:21:09,490 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:09,491 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:09,503 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:09,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:09,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:09,550 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1765148450] [2023-11-29 03:21:09,550 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1765148450] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:09,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:09,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:21:09,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996915069] [2023-11-29 03:21:09,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:09,551 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:09,551 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:09,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:09,551 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:09,551 INFO L87 Difference]: Start difference. First operand 3789 states and 5512 transitions. cyclomatic complexity: 1724 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:09,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:09,722 INFO L93 Difference]: Finished difference Result 7171 states and 10378 transitions. [2023-11-29 03:21:09,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7171 states and 10378 transitions. [2023-11-29 03:21:09,752 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6993 [2023-11-29 03:21:09,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7171 states to 7171 states and 10378 transitions. [2023-11-29 03:21:09,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7171 [2023-11-29 03:21:09,789 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7171 [2023-11-29 03:21:09,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7171 states and 10378 transitions. [2023-11-29 03:21:09,796 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:09,797 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7171 states and 10378 transitions. [2023-11-29 03:21:09,806 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7171 states and 10378 transitions. [2023-11-29 03:21:09,913 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7171 to 7167. [2023-11-29 03:21:09,925 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7167 states, 7167 states have (on average 1.4474675596483884) internal successors, (10374), 7166 states have internal predecessors, (10374), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:09,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7167 states to 7167 states and 10374 transitions. [2023-11-29 03:21:09,949 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7167 states and 10374 transitions. [2023-11-29 03:21:09,950 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:09,950 INFO L428 stractBuchiCegarLoop]: Abstraction has 7167 states and 10374 transitions. [2023-11-29 03:21:09,950 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 03:21:09,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7167 states and 10374 transitions. [2023-11-29 03:21:09,978 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 6989 [2023-11-29 03:21:09,979 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:09,979 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:09,982 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:09,982 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:09,982 INFO L748 eck$LassoCheckResult]: Stem: 96207#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 96208#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 97210#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 97211#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 98021#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 96788#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 96789#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 96861#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 96862#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 97319#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 97320#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 96826#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 96628#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 96629#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 97098#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 97099#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 96972#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 96973#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 96603#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 96604#L1279 assume !(0 == ~M_E~0); 97909#L1279-2 assume !(0 == ~T1_E~0); 96229#L1284-1 assume !(0 == ~T2_E~0); 96230#L1289-1 assume !(0 == ~T3_E~0); 96969#L1294-1 assume !(0 == ~T4_E~0); 96970#L1299-1 assume !(0 == ~T5_E~0); 96981#L1304-1 assume !(0 == ~T6_E~0); 98020#L1309-1 assume !(0 == ~T7_E~0); 98022#L1314-1 assume !(0 == ~T8_E~0); 96152#L1319-1 assume !(0 == ~T9_E~0); 96153#L1324-1 assume !(0 == ~T10_E~0); 96328#L1329-1 assume !(0 == ~T11_E~0); 96329#L1334-1 assume !(0 == ~T12_E~0); 97809#L1339-1 assume !(0 == ~T13_E~0); 97896#L1344-1 assume !(0 == ~E_M~0); 97897#L1349-1 assume !(0 == ~E_1~0); 97166#L1354-1 assume !(0 == ~E_2~0); 97167#L1359-1 assume !(0 == ~E_3~0); 97607#L1364-1 assume !(0 == ~E_4~0); 96450#L1369-1 assume !(0 == ~E_5~0); 96451#L1374-1 assume !(0 == ~E_6~0); 97173#L1379-1 assume !(0 == ~E_7~0); 97174#L1384-1 assume !(0 == ~E_8~0); 97257#L1389-1 assume !(0 == ~E_9~0); 97834#L1394-1 assume !(0 == ~E_10~0); 97835#L1399-1 assume !(0 == ~E_11~0); 97945#L1404-1 assume !(0 == ~E_12~0); 96549#L1409-1 assume !(0 == ~E_13~0); 96550#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97939#L628 assume !(1 == ~m_pc~0); 96449#L628-2 is_master_triggered_~__retres1~0#1 := 0; 96448#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97042#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 97043#L1591 assume !(0 != activate_threads_~tmp~1#1); 97956#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97022#L647 assume !(1 == ~t1_pc~0); 97023#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 97077#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 97078#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 97566#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 97882#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 97883#L666 assume !(1 == ~t2_pc~0); 96228#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 96390#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96368#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 96369#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 97373#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 97374#L685 assume !(1 == ~t3_pc~0); 97476#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 97475#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 97550#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 97220#L1615 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 97221#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96676#L704 assume 1 == ~t4_pc~0; 96677#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 97233#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96018#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 96019#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 97075#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 97076#L723 assume !(1 == ~t5_pc~0); 97216#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 97448#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 97600#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 97352#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 97353#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96432#L742 assume 1 == ~t6_pc~0; 96433#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 96592#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96359#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 96122#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 96123#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 96512#L761 assume !(1 == ~t7_pc~0); 96513#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 96386#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 96387#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 97223#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 97224#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 96144#L780 assume 1 == ~t8_pc~0; 96145#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 96423#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 96424#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 97180#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 97181#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 97306#L799 assume 1 == ~t9_pc~0; 97415#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 96147#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 96148#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 96418#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 97521#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 97332#L818 assume !(1 == ~t10_pc~0); 95933#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 95934#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 97405#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 97335#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 97336#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 97382#L837 assume 1 == ~t11_pc~0; 97383#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 97208#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 97888#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 97299#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 97300#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 97031#L856 assume !(1 == ~t12_pc~0); 97032#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 97720#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 95951#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 95952#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 97695#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 97912#L875 assume 1 == ~t13_pc~0; 96979#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 96593#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 96594#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 96530#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 96531#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 97404#L1427 assume !(1 == ~M_E~0); 97389#L1427-2 assume !(1 == ~T1_E~0); 96498#L1432-1 assume !(1 == ~T2_E~0); 96499#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 97614#L1442-1 assume !(1 == ~T4_E~0); 97615#L1447-1 assume !(1 == ~T5_E~0); 97457#L1452-1 assume !(1 == ~T6_E~0); 96069#L1457-1 assume !(1 == ~T7_E~0); 96070#L1462-1 assume !(1 == ~T8_E~0); 97637#L1467-1 assume !(1 == ~T9_E~0); 97660#L1472-1 assume !(1 == ~T10_E~0); 97661#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 97400#L1482-1 assume !(1 == ~T12_E~0); 97401#L1487-1 assume !(1 == ~T13_E~0); 96398#L1492-1 assume !(1 == ~E_M~0); 96399#L1497-1 assume !(1 == ~E_1~0); 96770#L1502-1 assume !(1 == ~E_2~0); 96771#L1507-1 assume !(1 == ~E_3~0); 96278#L1512-1 assume !(1 == ~E_4~0); 96279#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 97742#L1522-1 assume !(1 == ~E_6~0); 97019#L1527-1 assume !(1 == ~E_7~0); 97020#L1532-1 assume !(1 == ~E_8~0); 97993#L1537-1 assume !(1 == ~E_9~0); 97240#L1542-1 assume !(1 == ~E_10~0); 97049#L1547-1 assume !(1 == ~E_11~0); 97050#L1552-1 assume !(1 == ~E_12~0); 95974#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 95975#L1562-1 assume { :end_inline_reset_delta_events } true; 96583#L1928-2 [2023-11-29 03:21:09,983 INFO L750 eck$LassoCheckResult]: Loop: 96583#L1928-2 assume !false; 98603#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 97765#L1254-1 assume !false; 98408#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 98400#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98154#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98155#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 98137#L1067 assume !(0 != eval_~tmp~0#1); 98138#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 101377#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 101376#L1279-3 assume !(0 == ~M_E~0); 101375#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 101374#L1284-3 assume !(0 == ~T2_E~0); 101373#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 101372#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 101371#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 101370#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 101369#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 101368#L1314-3 assume !(0 == ~T8_E~0); 101367#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 101366#L1324-3 assume !(0 == ~T10_E~0); 101365#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 101364#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 101363#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 97434#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 97379#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 96621#L1354-3 assume !(0 == ~E_2~0); 96622#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 97387#L1364-3 assume !(0 == ~E_4~0); 101359#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 101358#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 101357#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 101356#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 101355#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 101354#L1394-3 assume !(0 == ~E_10~0); 101353#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 101352#L1404-3 assume !(0 == ~E_12~0); 101351#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 101350#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 101349#L628-45 assume !(1 == ~m_pc~0); 96923#L628-47 is_master_triggered_~__retres1~0#1 := 0; 96924#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 97465#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 96654#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 96655#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 97413#L647-45 assume !(1 == ~t1_pc~0); 97414#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 100050#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 100043#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100034#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 100026#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100018#L666-45 assume !(1 == ~t2_pc~0); 100010#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 100001#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 99994#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 99985#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 99977#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 99970#L685-45 assume 1 == ~t3_pc~0; 99961#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 99952#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99945#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 99936#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 99928#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99921#L704-45 assume 1 == ~t4_pc~0; 99913#L705-15 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 99903#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99896#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 99887#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 99879#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 99872#L723-45 assume 1 == ~t5_pc~0; 99863#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 99854#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99847#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 99838#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 99830#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 99823#L742-45 assume !(1 == ~t6_pc~0); 99815#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 99780#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 99769#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 99766#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 99764#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 99762#L761-45 assume !(1 == ~t7_pc~0); 99760#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 99757#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 99755#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 99752#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 99750#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 99748#L780-45 assume !(1 == ~t8_pc~0); 99745#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 99742#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 99739#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 99737#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 99735#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 99733#L799-45 assume 1 == ~t9_pc~0; 99731#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 99729#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 99728#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 98692#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 98689#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 98687#L818-45 assume !(1 == ~t10_pc~0); 98685#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 98682#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 98680#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 98678#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 98675#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 98673#L837-45 assume !(1 == ~t11_pc~0); 98669#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 98667#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 98665#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 98662#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 98660#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 98658#L856-45 assume !(1 == ~t12_pc~0); 98656#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 98653#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 98652#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 98651#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 98647#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 98645#L875-45 assume 1 == ~t13_pc~0; 98643#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 98641#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 98638#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 98637#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 98410#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 98261#L1427-3 assume !(1 == ~M_E~0); 98259#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 98256#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 98254#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 98252#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 98250#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 98247#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 98248#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 98880#L1462-3 assume !(1 == ~T8_E~0); 98878#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 98237#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 98234#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 98232#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 98233#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 98869#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 98867#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 98215#L1502-3 assume !(1 == ~E_2~0); 98212#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 98210#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 98208#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 98205#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 98203#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 98159#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 98151#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 98143#L1542-3 assume !(1 == ~E_10~0); 98134#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 98135#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 98121#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 98114#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 98115#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98456#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98455#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 98060#L1947 assume !(0 == start_simulation_~tmp~3#1); 98061#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 98626#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 98618#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 98616#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 98614#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 98610#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 98608#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 98606#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 96583#L1928-2 [2023-11-29 03:21:09,983 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:09,983 INFO L85 PathProgramCache]: Analyzing trace with hash -121367293, now seen corresponding path program 1 times [2023-11-29 03:21:09,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:09,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1834091939] [2023-11-29 03:21:09,984 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:09,984 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:10,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:10,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:10,087 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:10,087 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1834091939] [2023-11-29 03:21:10,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1834091939] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:10,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:10,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:21:10,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1475976146] [2023-11-29 03:21:10,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:10,088 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:10,088 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:10,088 INFO L85 PathProgramCache]: Analyzing trace with hash -393570519, now seen corresponding path program 1 times [2023-11-29 03:21:10,088 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:10,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119885824] [2023-11-29 03:21:10,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:10,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:10,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:10,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:10,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:10,185 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119885824] [2023-11-29 03:21:10,185 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119885824] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:10,186 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:10,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:21:10,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [405763215] [2023-11-29 03:21:10,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:10,186 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:10,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:10,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:21:10,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:21:10,187 INFO L87 Difference]: Start difference. First operand 7167 states and 10374 transitions. cyclomatic complexity: 3209 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:10,704 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:10,705 INFO L93 Difference]: Finished difference Result 18414 states and 26443 transitions. [2023-11-29 03:21:10,705 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18414 states and 26443 transitions. [2023-11-29 03:21:10,800 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 18058 [2023-11-29 03:21:10,843 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18414 states to 18414 states and 26443 transitions. [2023-11-29 03:21:10,843 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18414 [2023-11-29 03:21:10,855 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18414 [2023-11-29 03:21:10,855 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18414 states and 26443 transitions. [2023-11-29 03:21:10,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:10,866 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18414 states and 26443 transitions. [2023-11-29 03:21:10,881 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18414 states and 26443 transitions. [2023-11-29 03:21:10,978 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18414 to 7350. [2023-11-29 03:21:10,988 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7350 states, 7350 states have (on average 1.4363265306122448) internal successors, (10557), 7349 states have internal predecessors, (10557), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:11,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7350 states to 7350 states and 10557 transitions. [2023-11-29 03:21:11,002 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7350 states and 10557 transitions. [2023-11-29 03:21:11,002 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:21:11,002 INFO L428 stractBuchiCegarLoop]: Abstraction has 7350 states and 10557 transitions. [2023-11-29 03:21:11,003 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 03:21:11,003 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7350 states and 10557 transitions. [2023-11-29 03:21:11,024 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 7169 [2023-11-29 03:21:11,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:11,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:11,026 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:11,027 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:11,027 INFO L748 eck$LassoCheckResult]: Stem: 121804#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 121805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 122856#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122857#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 123866#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 122412#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122413#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 122487#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 122488#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 122975#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122976#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 122448#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122240#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 122241#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 122733#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 122734#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 122602#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 122603#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 122213#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 122214#L1279 assume !(0 == ~M_E~0); 123695#L1279-2 assume !(0 == ~T1_E~0); 121825#L1284-1 assume !(0 == ~T2_E~0); 121826#L1289-1 assume !(0 == ~T3_E~0); 122599#L1294-1 assume !(0 == ~T4_E~0); 122600#L1299-1 assume !(0 == ~T5_E~0); 122611#L1304-1 assume !(0 == ~T6_E~0); 123863#L1309-1 assume !(0 == ~T7_E~0); 123868#L1314-1 assume !(0 == ~T8_E~0); 121749#L1319-1 assume !(0 == ~T9_E~0); 121750#L1324-1 assume !(0 == ~T10_E~0); 121927#L1329-1 assume !(0 == ~T11_E~0); 121928#L1334-1 assume !(0 == ~T12_E~0); 123561#L1339-1 assume !(0 == ~T13_E~0); 123680#L1344-1 assume !(0 == ~E_M~0); 123681#L1349-1 assume !(0 == ~E_1~0); 122807#L1354-1 assume !(0 == ~E_2~0); 122808#L1359-1 assume !(0 == ~E_3~0); 123308#L1364-1 assume !(0 == ~E_4~0); 122054#L1369-1 assume !(0 == ~E_5~0); 122055#L1374-1 assume !(0 == ~E_6~0); 122815#L1379-1 assume !(0 == ~E_7~0); 122816#L1384-1 assume !(0 == ~E_8~0); 122906#L1389-1 assume !(0 == ~E_9~0); 123590#L1394-1 assume !(0 == ~E_10~0); 123591#L1399-1 assume !(0 == ~E_11~0); 123751#L1404-1 assume !(0 == ~E_12~0); 122158#L1409-1 assume !(0 == ~E_13~0); 122159#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 123742#L628 assume !(1 == ~m_pc~0); 122053#L628-2 is_master_triggered_~__retres1~0#1 := 0; 122052#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122676#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 122677#L1591 assume !(0 != activate_threads_~tmp~1#1); 123761#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122653#L647 assume !(1 == ~t1_pc~0); 122654#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 122711#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 122712#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 123251#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 123666#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 123667#L666 assume !(1 == ~t2_pc~0); 121824#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 121991#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121969#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 121970#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 123033#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 123034#L685 assume !(1 == ~t3_pc~0); 123144#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 123223#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 123778#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 122865#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 122866#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122296#L704 assume 1 == ~t4_pc~0; 122297#L705 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 122878#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121614#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 121615#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 122709#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 122710#L723 assume !(1 == ~t5_pc~0); 122861#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 123110#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 123300#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 123011#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 123012#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122036#L742 assume 1 == ~t6_pc~0; 122037#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 122202#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121960#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 121719#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 121720#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122119#L761 assume !(1 == ~t7_pc~0); 122120#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 121987#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 121988#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 122868#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 122869#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 121741#L780 assume 1 == ~t8_pc~0; 121742#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 122027#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 122028#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 122826#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 122827#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 122959#L799 assume 1 == ~t9_pc~0; 123077#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 121744#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 121745#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 122022#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 123193#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 122989#L818 assume !(1 == ~t10_pc~0); 121529#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 121530#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 123068#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 122994#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 122995#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 123042#L837 assume 1 == ~t11_pc~0; 123043#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 122854#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 123671#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 122951#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 122952#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 122662#L856 assume !(1 == ~t12_pc~0); 122663#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 123446#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 121547#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 121548#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 123414#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 123698#L875 assume 1 == ~t13_pc~0; 122609#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 122203#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 122204#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 122139#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 122140#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 123067#L1427 assume !(1 == ~M_E~0); 123050#L1427-2 assume !(1 == ~T1_E~0); 122105#L1432-1 assume !(1 == ~T2_E~0); 122106#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 123316#L1442-1 assume !(1 == ~T4_E~0); 123317#L1447-1 assume !(1 == ~T5_E~0); 123122#L1452-1 assume !(1 == ~T6_E~0); 121665#L1457-1 assume !(1 == ~T7_E~0); 121666#L1462-1 assume !(1 == ~T8_E~0); 123343#L1467-1 assume !(1 == ~T9_E~0); 123367#L1472-1 assume !(1 == ~T10_E~0); 123368#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 123063#L1482-1 assume !(1 == ~T12_E~0); 123064#L1487-1 assume !(1 == ~T13_E~0); 121999#L1492-1 assume !(1 == ~E_M~0); 122000#L1497-1 assume !(1 == ~E_1~0); 122393#L1502-1 assume !(1 == ~E_2~0); 122394#L1507-1 assume !(1 == ~E_3~0); 121875#L1512-1 assume !(1 == ~E_4~0); 121876#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 123473#L1522-1 assume !(1 == ~E_6~0); 122650#L1527-1 assume !(1 == ~E_7~0); 122651#L1532-1 assume !(1 == ~E_8~0); 123815#L1537-1 assume !(1 == ~E_9~0); 122885#L1542-1 assume !(1 == ~E_10~0); 122683#L1547-1 assume !(1 == ~E_11~0); 122684#L1552-1 assume !(1 == ~E_12~0); 121570#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 121571#L1562-1 assume { :end_inline_reset_delta_events } true; 122192#L1928-2 [2023-11-29 03:21:11,027 INFO L750 eck$LassoCheckResult]: Loop: 122192#L1928-2 assume !false; 124785#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 124781#L1254-1 assume !false; 123071#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 121900#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 121901#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 122107#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 124764#L1067 assume !(0 != eval_~tmp~0#1); 124763#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 124762#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 124761#L1279-3 assume !(0 == ~M_E~0); 124760#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 124759#L1284-3 assume !(0 == ~T2_E~0); 124758#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 124757#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 124756#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 124755#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 124754#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 124753#L1314-3 assume !(0 == ~T8_E~0); 124752#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 124751#L1324-3 assume !(0 == ~T10_E~0); 124750#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 124749#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 124748#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 124747#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 124746#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 124606#L1354-3 assume !(0 == ~E_2~0); 124607#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 124600#L1364-3 assume !(0 == ~E_4~0); 124601#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 124590#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 124591#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 124584#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 124585#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 124744#L1394-3 assume !(0 == ~E_10~0); 124743#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 124742#L1404-3 assume !(0 == ~E_12~0); 124741#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 124740#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 124739#L628-45 assume !(1 == ~m_pc~0); 124737#L628-47 is_master_triggered_~__retres1~0#1 := 0; 124736#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 123131#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123132#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 124735#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 123075#L647-45 assume !(1 == ~t1_pc~0); 123076#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 126109#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 126108#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 126107#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 126106#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 126104#L666-45 assume !(1 == ~t2_pc~0); 126103#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 126102#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 126101#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 126100#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 126099#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 126098#L685-45 assume !(1 == ~t3_pc~0); 126097#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 126095#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 126093#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 126091#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 126082#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 126076#L704-45 assume !(1 == ~t4_pc~0); 126067#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 126060#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 126055#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 126027#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 126020#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 126013#L723-45 assume !(1 == ~t5_pc~0); 126005#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 125996#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 125957#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 125934#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 125927#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 125918#L742-45 assume 1 == ~t6_pc~0; 125909#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 125902#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 125893#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 125885#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 125878#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 125869#L761-45 assume !(1 == ~t7_pc~0); 125861#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 125853#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 125845#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 125844#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 125544#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 125348#L780-45 assume 1 == ~t8_pc~0; 125345#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 125343#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 125340#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 125338#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 125336#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 125334#L799-45 assume !(1 == ~t9_pc~0); 125331#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 125329#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 125326#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 125324#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 125322#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 125320#L818-45 assume 1 == ~t10_pc~0; 125317#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 125315#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 125312#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 125310#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 125308#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 125306#L837-45 assume !(1 == ~t11_pc~0); 125303#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 125301#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 125298#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 125296#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 125294#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 125292#L856-45 assume 1 == ~t12_pc~0; 125289#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 125287#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 125286#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 125285#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 125284#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 125283#L875-45 assume !(1 == ~t13_pc~0); 125107#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 125105#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 125103#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 124745#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 124723#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 124634#L1427-3 assume !(1 == ~M_E~0); 124635#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 124999#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 124998#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 124997#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 124996#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 124995#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 124994#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 124993#L1462-3 assume !(1 == ~T8_E~0); 124992#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 124991#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 124990#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 124989#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 124988#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 124987#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 124986#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 124985#L1502-3 assume !(1 == ~E_2~0); 124984#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 124983#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 124982#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 124981#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 124980#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 124979#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 124978#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 124977#L1542-3 assume !(1 == ~E_10~0); 124976#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 124531#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 124532#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 124525#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 124526#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 123596#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 121913#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 121914#L1947 assume !(0 == start_simulation_~tmp~3#1); 122942#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 123160#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 122123#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 121537#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 121538#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 123354#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 123355#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 123589#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 122192#L1928-2 [2023-11-29 03:21:11,028 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:11,028 INFO L85 PathProgramCache]: Analyzing trace with hash -2061949307, now seen corresponding path program 1 times [2023-11-29 03:21:11,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:11,029 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1987407963] [2023-11-29 03:21:11,029 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:11,029 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:11,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:11,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:11,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:11,092 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1987407963] [2023-11-29 03:21:11,092 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1987407963] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:11,092 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:11,092 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:21:11,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127192076] [2023-11-29 03:21:11,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:11,093 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:11,093 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:11,094 INFO L85 PathProgramCache]: Analyzing trace with hash 1358363628, now seen corresponding path program 1 times [2023-11-29 03:21:11,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:11,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1046233839] [2023-11-29 03:21:11,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:11,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:11,110 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:11,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:11,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:11,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1046233839] [2023-11-29 03:21:11,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1046233839] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:11,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:11,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:11,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [794653383] [2023-11-29 03:21:11,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:11,148 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:11,148 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:11,149 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:11,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:11,149 INFO L87 Difference]: Start difference. First operand 7350 states and 10557 transitions. cyclomatic complexity: 3209 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:11,294 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:11,294 INFO L93 Difference]: Finished difference Result 14052 states and 20097 transitions. [2023-11-29 03:21:11,294 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14052 states and 20097 transitions. [2023-11-29 03:21:11,338 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13860 [2023-11-29 03:21:11,364 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14052 states to 14052 states and 20097 transitions. [2023-11-29 03:21:11,364 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14052 [2023-11-29 03:21:11,370 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14052 [2023-11-29 03:21:11,371 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14052 states and 20097 transitions. [2023-11-29 03:21:11,380 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:11,380 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14052 states and 20097 transitions. [2023-11-29 03:21:11,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14052 states and 20097 transitions. [2023-11-29 03:21:11,511 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14052 to 14044. [2023-11-29 03:21:11,524 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 14044 states, 14044 states have (on average 1.4304329250925663) internal successors, (20089), 14043 states have internal predecessors, (20089), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:11,639 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 14044 states to 14044 states and 20089 transitions. [2023-11-29 03:21:11,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 14044 states and 20089 transitions. [2023-11-29 03:21:11,640 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:11,640 INFO L428 stractBuchiCegarLoop]: Abstraction has 14044 states and 20089 transitions. [2023-11-29 03:21:11,640 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 03:21:11,641 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 14044 states and 20089 transitions. [2023-11-29 03:21:11,670 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 13852 [2023-11-29 03:21:11,670 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:11,670 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:11,672 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:11,672 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:11,672 INFO L748 eck$LassoCheckResult]: Stem: 143216#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 143217#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 144224#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 144225#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 145114#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 143797#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 143798#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 143869#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 143870#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 144334#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 144335#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 143836#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 143633#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 143634#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 144107#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 144108#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 143987#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 143988#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 143608#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 143609#L1279 assume !(0 == ~M_E~0); 144975#L1279-2 assume !(0 == ~T1_E~0); 143237#L1284-1 assume !(0 == ~T2_E~0); 143238#L1289-1 assume !(0 == ~T3_E~0); 143978#L1294-1 assume !(0 == ~T4_E~0); 143979#L1299-1 assume !(0 == ~T5_E~0); 143991#L1304-1 assume !(0 == ~T6_E~0); 145111#L1309-1 assume !(0 == ~T7_E~0); 145117#L1314-1 assume !(0 == ~T8_E~0); 143162#L1319-1 assume !(0 == ~T9_E~0); 143163#L1324-1 assume !(0 == ~T10_E~0); 143336#L1329-1 assume !(0 == ~T11_E~0); 143337#L1334-1 assume !(0 == ~T12_E~0); 144865#L1339-1 assume !(0 == ~T13_E~0); 144961#L1344-1 assume !(0 == ~E_M~0); 144962#L1349-1 assume !(0 == ~E_1~0); 144180#L1354-1 assume !(0 == ~E_2~0); 144181#L1359-1 assume !(0 == ~E_3~0); 144639#L1364-1 assume !(0 == ~E_4~0); 143460#L1369-1 assume !(0 == ~E_5~0); 143461#L1374-1 assume !(0 == ~E_6~0); 144187#L1379-1 assume !(0 == ~E_7~0); 144188#L1384-1 assume !(0 == ~E_8~0); 144270#L1389-1 assume !(0 == ~E_9~0); 144885#L1394-1 assume !(0 == ~E_10~0); 144886#L1399-1 assume !(0 == ~E_11~0); 145025#L1404-1 assume !(0 == ~E_12~0); 143557#L1409-1 assume !(0 == ~E_13~0); 143558#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 145013#L628 assume !(1 == ~m_pc~0); 143459#L628-2 is_master_triggered_~__retres1~0#1 := 0; 143458#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144053#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 144054#L1591 assume !(0 != activate_threads_~tmp~1#1); 145035#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 144033#L647 assume !(1 == ~t1_pc~0); 144034#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 144086#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144087#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 144591#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 144946#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144947#L666 assume !(1 == ~t2_pc~0); 143236#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 143400#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 143378#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 143379#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 144387#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 144388#L685 assume !(1 == ~t3_pc~0); 144497#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 144571#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 145049#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 144233#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 144234#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 143681#L704 assume !(1 == ~t4_pc~0); 143682#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 144246#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 143023#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 143024#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 144084#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144085#L723 assume !(1 == ~t5_pc~0); 144229#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 144468#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144632#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 144369#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 144370#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143441#L742 assume 1 == ~t6_pc~0; 143442#L743 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 143597#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 143367#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 143130#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 143131#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 143520#L761 assume !(1 == ~t7_pc~0); 143521#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 143396#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 143397#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 144235#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 144236#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 143152#L780 assume 1 == ~t8_pc~0; 143153#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 143431#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 143432#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 144194#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 144195#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 144322#L799 assume 1 == ~t9_pc~0; 144435#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 143155#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 143156#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 143426#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 144549#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 144345#L818 assume !(1 == ~t10_pc~0); 142938#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 142939#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 144426#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 144348#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 144349#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 144398#L837 assume 1 == ~t11_pc~0; 144399#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 144222#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 144951#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 144312#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 144313#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 144045#L856 assume !(1 == ~t12_pc~0); 144046#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 144768#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 142956#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 142957#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 144741#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 144979#L875 assume 1 == ~t13_pc~0; 143989#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 143598#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 143599#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 143538#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 143539#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 144423#L1427 assume !(1 == ~M_E~0); 144408#L1427-2 assume !(1 == ~T1_E~0); 143507#L1432-1 assume !(1 == ~T2_E~0); 143508#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 144648#L1442-1 assume !(1 == ~T4_E~0); 144649#L1447-1 assume !(1 == ~T5_E~0); 144480#L1452-1 assume !(1 == ~T6_E~0); 143074#L1457-1 assume !(1 == ~T7_E~0); 143075#L1462-1 assume !(1 == ~T8_E~0); 144674#L1467-1 assume !(1 == ~T9_E~0); 144696#L1472-1 assume !(1 == ~T10_E~0); 144697#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 144419#L1482-1 assume !(1 == ~T12_E~0); 144420#L1487-1 assume !(1 == ~T13_E~0); 143406#L1492-1 assume !(1 == ~E_M~0); 143407#L1497-1 assume !(1 == ~E_1~0); 143779#L1502-1 assume !(1 == ~E_2~0); 143780#L1507-1 assume !(1 == ~E_3~0); 143286#L1512-1 assume !(1 == ~E_4~0); 143287#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 144790#L1522-1 assume !(1 == ~E_6~0); 144031#L1527-1 assume !(1 == ~E_7~0); 144032#L1532-1 assume !(1 == ~E_8~0); 145078#L1537-1 assume !(1 == ~E_9~0); 144256#L1542-1 assume !(1 == ~E_10~0); 144062#L1547-1 assume !(1 == ~E_11~0); 144063#L1552-1 assume !(1 == ~E_12~0); 142981#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 142982#L1562-1 assume { :end_inline_reset_delta_events } true; 143588#L1928-2 [2023-11-29 03:21:11,673 INFO L750 eck$LassoCheckResult]: Loop: 143588#L1928-2 assume !false; 149272#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 149267#L1254-1 assume !false; 149219#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 148044#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 148035#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 148033#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 148030#L1067 assume !(0 != eval_~tmp~0#1); 148031#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 154738#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 154736#L1279-3 assume !(0 == ~M_E~0); 154734#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 154732#L1284-3 assume !(0 == ~T2_E~0); 154730#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 154728#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 154726#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 154724#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 154722#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 154720#L1314-3 assume !(0 == ~T8_E~0); 154719#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 154718#L1324-3 assume !(0 == ~T10_E~0); 154717#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 154716#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 154715#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 154714#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 154713#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 154712#L1354-3 assume !(0 == ~E_2~0); 154711#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 154710#L1364-3 assume !(0 == ~E_4~0); 154709#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 154708#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 154707#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 154706#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 154705#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 154704#L1394-3 assume !(0 == ~E_10~0); 154703#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 154702#L1404-3 assume !(0 == ~E_12~0); 154701#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 154700#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 154699#L628-45 assume 1 == ~m_pc~0; 154698#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 154695#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154694#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 154693#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 154692#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154691#L647-45 assume !(1 == ~t1_pc~0); 154690#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 154689#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 154688#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 154686#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 154685#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 154683#L666-45 assume !(1 == ~t2_pc~0); 154681#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 154679#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154677#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 154675#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 154673#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 154671#L685-45 assume !(1 == ~t3_pc~0); 154667#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 154665#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154663#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 154661#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 154658#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154656#L704-45 assume !(1 == ~t4_pc~0); 154654#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 154652#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 154650#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 154648#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 154646#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154644#L723-45 assume !(1 == ~t5_pc~0); 154642#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 154639#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154637#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 154635#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 154633#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154631#L742-45 assume 1 == ~t6_pc~0; 154628#L743-15 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 154627#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154624#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 154622#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 154620#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 154618#L761-45 assume 1 == ~t7_pc~0; 154615#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 154613#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 154611#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 154609#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 154607#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 154605#L780-45 assume 1 == ~t8_pc~0; 154602#L781-15 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 154601#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 154598#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 154596#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 154594#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 154592#L799-45 assume !(1 == ~t9_pc~0); 154588#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 154584#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 154582#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 154580#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 154578#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 154575#L818-45 assume 1 == ~t10_pc~0; 154572#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 154570#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 154568#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 154566#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 154564#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 154562#L837-45 assume 1 == ~t11_pc~0; 154560#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 154557#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 154554#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 154552#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 154550#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 154548#L856-45 assume !(1 == ~t12_pc~0); 154546#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 154543#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 154540#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 154538#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 154536#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 154534#L875-45 assume !(1 == ~t13_pc~0); 154531#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 154529#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 154526#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 154524#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 154522#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154446#L1427-3 assume !(1 == ~M_E~0); 154444#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 154442#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 154440#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 154438#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 154436#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 154434#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 154432#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 154429#L1462-3 assume !(1 == ~T8_E~0); 154427#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 154425#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 154423#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 154421#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 154419#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 154416#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 154414#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 154412#L1502-3 assume !(1 == ~E_2~0); 154410#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 154408#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 154406#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 154403#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 154401#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 154399#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 154397#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 154395#L1542-3 assume !(1 == ~E_10~0); 154393#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 154390#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 154388#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 154386#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 154363#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 154355#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 154353#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 154350#L1947 assume !(0 == start_simulation_~tmp~3#1); 154347#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 154319#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 154311#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 154309#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 154308#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 154305#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 154304#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 154300#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 143588#L1928-2 [2023-11-29 03:21:11,673 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:11,673 INFO L85 PathProgramCache]: Analyzing trace with hash 846336710, now seen corresponding path program 1 times [2023-11-29 03:21:11,673 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:11,674 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1415327114] [2023-11-29 03:21:11,674 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:11,674 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:11,690 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:11,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:11,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:11,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1415327114] [2023-11-29 03:21:11,736 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1415327114] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:11,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:11,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:21:11,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1363432060] [2023-11-29 03:21:11,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:11,737 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:11,738 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:11,738 INFO L85 PathProgramCache]: Analyzing trace with hash 1000554474, now seen corresponding path program 1 times [2023-11-29 03:21:11,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:11,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [968665794] [2023-11-29 03:21:11,738 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:11,738 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:11,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:11,788 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:11,788 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:11,788 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [968665794] [2023-11-29 03:21:11,788 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [968665794] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:11,788 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:11,788 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:11,788 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2009017713] [2023-11-29 03:21:11,788 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:11,789 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:11,789 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:11,789 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:11,789 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:11,790 INFO L87 Difference]: Start difference. First operand 14044 states and 20089 transitions. cyclomatic complexity: 6049 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:12,030 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:12,031 INFO L93 Difference]: Finished difference Result 26979 states and 38442 transitions. [2023-11-29 03:21:12,031 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26979 states and 38442 transitions. [2023-11-29 03:21:12,133 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26756 [2023-11-29 03:21:12,183 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26979 states to 26979 states and 38442 transitions. [2023-11-29 03:21:12,183 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26979 [2023-11-29 03:21:12,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26979 [2023-11-29 03:21:12,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26979 states and 38442 transitions. [2023-11-29 03:21:12,221 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:12,221 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26979 states and 38442 transitions. [2023-11-29 03:21:12,240 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26979 states and 38442 transitions. [2023-11-29 03:21:12,545 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26979 to 26963. [2023-11-29 03:21:12,566 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26963 states, 26963 states have (on average 1.4251381522827578) internal successors, (38426), 26962 states have internal predecessors, (38426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:12,632 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26963 states to 26963 states and 38426 transitions. [2023-11-29 03:21:12,632 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26963 states and 38426 transitions. [2023-11-29 03:21:12,632 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:12,633 INFO L428 stractBuchiCegarLoop]: Abstraction has 26963 states and 38426 transitions. [2023-11-29 03:21:12,633 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 03:21:12,633 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26963 states and 38426 transitions. [2023-11-29 03:21:12,713 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 26740 [2023-11-29 03:21:12,713 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:12,713 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:12,716 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:12,716 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:12,717 INFO L748 eck$LassoCheckResult]: Stem: 184245#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 184246#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 185249#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 185250#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 186098#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 184824#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 184825#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 184895#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 184896#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 185359#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 185360#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 184859#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 184665#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 184666#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 185138#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 185139#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 185013#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 185014#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 184640#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 184641#L1279 assume !(0 == ~M_E~0); 185974#L1279-2 assume !(0 == ~T1_E~0); 184266#L1284-1 assume !(0 == ~T2_E~0); 184267#L1289-1 assume !(0 == ~T3_E~0); 185010#L1294-1 assume !(0 == ~T4_E~0); 185011#L1299-1 assume !(0 == ~T5_E~0); 185024#L1304-1 assume !(0 == ~T6_E~0); 186096#L1309-1 assume !(0 == ~T7_E~0); 186100#L1314-1 assume !(0 == ~T8_E~0); 184190#L1319-1 assume !(0 == ~T9_E~0); 184191#L1324-1 assume !(0 == ~T10_E~0); 184365#L1329-1 assume !(0 == ~T11_E~0); 184366#L1334-1 assume !(0 == ~T12_E~0); 185859#L1339-1 assume !(0 == ~T13_E~0); 185964#L1344-1 assume !(0 == ~E_M~0); 185965#L1349-1 assume !(0 == ~E_1~0); 185208#L1354-1 assume !(0 == ~E_2~0); 185209#L1359-1 assume !(0 == ~E_3~0); 185647#L1364-1 assume !(0 == ~E_4~0); 184489#L1369-1 assume !(0 == ~E_5~0); 184490#L1374-1 assume !(0 == ~E_6~0); 185215#L1379-1 assume !(0 == ~E_7~0); 185216#L1384-1 assume !(0 == ~E_8~0); 185295#L1389-1 assume !(0 == ~E_9~0); 185884#L1394-1 assume !(0 == ~E_10~0); 185885#L1399-1 assume !(0 == ~E_11~0); 186018#L1404-1 assume !(0 == ~E_12~0); 184587#L1409-1 assume !(0 == ~E_13~0); 184588#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186007#L628 assume !(1 == ~m_pc~0); 184488#L628-2 is_master_triggered_~__retres1~0#1 := 0; 184487#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 185084#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 185085#L1591 assume !(0 != activate_threads_~tmp~1#1); 186029#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 185064#L647 assume !(1 == ~t1_pc~0); 185065#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 185116#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 185117#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 185606#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 185950#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 185951#L666 assume !(1 == ~t2_pc~0); 184265#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 184427#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 184405#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 184406#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 185412#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 185413#L685 assume !(1 == ~t3_pc~0); 185517#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 185585#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 186039#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 185259#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 185260#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 184714#L704 assume !(1 == ~t4_pc~0); 184715#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 185271#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 184053#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 184054#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 185114#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 185115#L723 assume !(1 == ~t5_pc~0); 185255#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 185486#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 185640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 185390#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 185391#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 184472#L742 assume !(1 == ~t6_pc~0); 184473#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 184629#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 184396#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 184159#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 184160#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 184549#L761 assume !(1 == ~t7_pc~0); 184550#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 184423#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 184424#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 185262#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 185263#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 184182#L780 assume 1 == ~t8_pc~0; 184183#L781 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 184463#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 184464#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 185222#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 185223#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 185345#L799 assume 1 == ~t9_pc~0; 185453#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 184185#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 184186#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 184458#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 185562#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 185372#L818 assume !(1 == ~t10_pc~0); 183968#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 183969#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 185446#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 185375#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 185376#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 185422#L837 assume 1 == ~t11_pc~0; 185423#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 185247#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 185956#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 185338#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 185339#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 185073#L856 assume !(1 == ~t12_pc~0); 185074#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 185763#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 183986#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 183987#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 185737#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 185977#L875 assume 1 == ~t13_pc~0; 185020#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 184630#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 184631#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 184568#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 184569#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 185445#L1427 assume !(1 == ~M_E~0); 185430#L1427-2 assume !(1 == ~T1_E~0); 184536#L1432-1 assume !(1 == ~T2_E~0); 184537#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 185652#L1442-1 assume !(1 == ~T4_E~0); 185653#L1447-1 assume !(1 == ~T5_E~0); 185498#L1452-1 assume !(1 == ~T6_E~0); 184104#L1457-1 assume !(1 == ~T7_E~0); 184105#L1462-1 assume !(1 == ~T8_E~0); 185678#L1467-1 assume !(1 == ~T9_E~0); 185700#L1472-1 assume !(1 == ~T10_E~0); 185701#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 185441#L1482-1 assume !(1 == ~T12_E~0); 185442#L1487-1 assume !(1 == ~T13_E~0); 184436#L1492-1 assume !(1 == ~E_M~0); 184437#L1497-1 assume !(1 == ~E_1~0); 184807#L1502-1 assume !(1 == ~E_2~0); 184808#L1507-1 assume !(1 == ~E_3~0); 184315#L1512-1 assume !(1 == ~E_4~0); 184316#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 185787#L1522-1 assume !(1 == ~E_6~0); 185061#L1527-1 assume !(1 == ~E_7~0); 185062#L1532-1 assume !(1 == ~E_8~0); 186071#L1537-1 assume !(1 == ~E_9~0); 185278#L1542-1 assume !(1 == ~E_10~0); 185091#L1547-1 assume !(1 == ~E_11~0); 185092#L1552-1 assume !(1 == ~E_12~0); 184009#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 184010#L1562-1 assume { :end_inline_reset_delta_events } true; 184620#L1928-2 [2023-11-29 03:21:12,718 INFO L750 eck$LassoCheckResult]: Loop: 184620#L1928-2 assume !false; 193566#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 193560#L1254-1 assume !false; 193558#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 193506#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 193492#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 193486#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 193478#L1067 assume !(0 != eval_~tmp~0#1); 193479#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 198707#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 198706#L1279-3 assume !(0 == ~M_E~0); 198705#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 198704#L1284-3 assume !(0 == ~T2_E~0); 198703#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 198702#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 198701#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 198700#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 198699#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 198698#L1314-3 assume !(0 == ~T8_E~0); 198697#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 198696#L1324-3 assume !(0 == ~T10_E~0); 198695#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 198694#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 198693#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 198692#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 198691#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 198690#L1354-3 assume !(0 == ~E_2~0); 198689#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 198688#L1364-3 assume !(0 == ~E_4~0); 198687#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 198686#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 198685#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 198684#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 198683#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 198682#L1394-3 assume !(0 == ~E_10~0); 198681#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 198680#L1404-3 assume !(0 == ~E_12~0); 198679#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 198678#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 198677#L628-45 assume !(1 == ~m_pc~0); 198675#L628-47 is_master_triggered_~__retres1~0#1 := 0; 198674#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 198673#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 198672#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 198671#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 198670#L647-45 assume !(1 == ~t1_pc~0); 198669#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 198668#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 198667#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 198666#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 198665#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 198663#L666-45 assume !(1 == ~t2_pc~0); 198662#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 198661#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198660#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 198659#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 198658#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 198657#L685-45 assume !(1 == ~t3_pc~0); 198656#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 198654#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 198652#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 198650#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 198648#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 198647#L704-45 assume !(1 == ~t4_pc~0); 198646#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 198645#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 198644#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 198643#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 198642#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 198641#L723-45 assume !(1 == ~t5_pc~0); 198640#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 198638#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 198637#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 198636#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 198635#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 198634#L742-45 assume !(1 == ~t6_pc~0); 198633#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 198632#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198631#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 198630#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 198629#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 198628#L761-45 assume !(1 == ~t7_pc~0); 198627#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 198625#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 198624#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 198622#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 198621#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 198620#L780-45 assume !(1 == ~t8_pc~0); 198619#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 198617#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 198615#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 198612#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 198610#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 198608#L799-45 assume 1 == ~t9_pc~0; 198606#L800-15 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 198603#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 198601#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 198598#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 198596#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 198594#L818-45 assume !(1 == ~t10_pc~0); 198592#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 198589#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 198586#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 198584#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 198582#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 198580#L837-45 assume 1 == ~t11_pc~0; 198578#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 198575#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 198573#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 198570#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 198567#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 198564#L856-45 assume !(1 == ~t12_pc~0); 198561#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 198558#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 198556#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 198554#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 198552#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 198550#L875-45 assume !(1 == ~t13_pc~0); 198547#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 198545#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 198543#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 198540#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 198538#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198536#L1427-3 assume !(1 == ~M_E~0); 193947#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 198533#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 198531#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 198528#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 198526#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 198524#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 198522#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 198520#L1462-3 assume !(1 == ~T8_E~0); 198518#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 198515#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 198513#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 198511#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 198508#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 198504#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 198501#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 198497#L1502-3 assume !(1 == ~E_2~0); 198493#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 198479#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 198473#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 198467#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 198460#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 186474#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 186473#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 186472#L1542-3 assume !(1 == ~E_10~0); 186471#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 186470#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 186469#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 186468#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 186460#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 186452#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 186453#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 193848#L1947 assume !(0 == start_simulation_~tmp~3#1); 193845#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 193626#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 193618#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 193615#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 193613#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 193611#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 193594#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 193584#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 184620#L1928-2 [2023-11-29 03:21:12,718 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:12,718 INFO L85 PathProgramCache]: Analyzing trace with hash -995977081, now seen corresponding path program 1 times [2023-11-29 03:21:12,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:12,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1818787845] [2023-11-29 03:21:12,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:12,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:12,739 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:12,802 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:12,802 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:12,803 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1818787845] [2023-11-29 03:21:12,803 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1818787845] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:12,803 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:12,803 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:21:12,803 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1919822505] [2023-11-29 03:21:12,804 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:12,804 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:12,804 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:12,805 INFO L85 PathProgramCache]: Analyzing trace with hash 1219884910, now seen corresponding path program 1 times [2023-11-29 03:21:12,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:12,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [296897777] [2023-11-29 03:21:12,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:12,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:12,819 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:12,967 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:12,967 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:12,967 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [296897777] [2023-11-29 03:21:12,968 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [296897777] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:12,968 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:12,968 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:21:12,968 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2056021553] [2023-11-29 03:21:12,968 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:12,968 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:12,969 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:12,969 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:12,969 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:12,969 INFO L87 Difference]: Start difference. First operand 26963 states and 38426 transitions. cyclomatic complexity: 11471 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:13,193 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:13,193 INFO L93 Difference]: Finished difference Result 51902 states and 73699 transitions. [2023-11-29 03:21:13,193 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51902 states and 73699 transitions. [2023-11-29 03:21:13,370 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51600 [2023-11-29 03:21:13,602 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51902 states to 51902 states and 73699 transitions. [2023-11-29 03:21:13,602 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51902 [2023-11-29 03:21:13,619 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51902 [2023-11-29 03:21:13,620 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51902 states and 73699 transitions. [2023-11-29 03:21:13,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:13,632 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51902 states and 73699 transitions. [2023-11-29 03:21:13,650 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51902 states and 73699 transitions. [2023-11-29 03:21:13,987 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51902 to 51870. [2023-11-29 03:21:14,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51870 states, 51870 states have (on average 1.4202236360131097) internal successors, (73667), 51869 states have internal predecessors, (73667), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:14,101 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51870 states to 51870 states and 73667 transitions. [2023-11-29 03:21:14,101 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51870 states and 73667 transitions. [2023-11-29 03:21:14,102 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:14,102 INFO L428 stractBuchiCegarLoop]: Abstraction has 51870 states and 73667 transitions. [2023-11-29 03:21:14,102 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 03:21:14,102 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51870 states and 73667 transitions. [2023-11-29 03:21:14,221 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 51568 [2023-11-29 03:21:14,221 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:14,221 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:14,223 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:14,223 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:14,223 INFO L748 eck$LassoCheckResult]: Stem: 263118#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 263119#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 264132#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 264133#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 265026#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 263698#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 263699#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 263770#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 263771#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 264241#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 264242#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 263735#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 263532#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 263533#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 264011#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 264012#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 263885#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 263886#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 263506#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 263507#L1279 assume !(0 == ~M_E~0); 264873#L1279-2 assume !(0 == ~T1_E~0); 263139#L1284-1 assume !(0 == ~T2_E~0); 263140#L1289-1 assume !(0 == ~T3_E~0); 263882#L1294-1 assume !(0 == ~T4_E~0); 263883#L1299-1 assume !(0 == ~T5_E~0); 263894#L1304-1 assume !(0 == ~T6_E~0); 265024#L1309-1 assume !(0 == ~T7_E~0); 265028#L1314-1 assume !(0 == ~T8_E~0); 263063#L1319-1 assume !(0 == ~T9_E~0); 263064#L1324-1 assume !(0 == ~T10_E~0); 263238#L1329-1 assume !(0 == ~T11_E~0); 263239#L1334-1 assume !(0 == ~T12_E~0); 264768#L1339-1 assume !(0 == ~T13_E~0); 264862#L1344-1 assume !(0 == ~E_M~0); 264863#L1349-1 assume !(0 == ~E_1~0); 264084#L1354-1 assume !(0 == ~E_2~0); 264085#L1359-1 assume !(0 == ~E_3~0); 264556#L1364-1 assume !(0 == ~E_4~0); 263359#L1369-1 assume !(0 == ~E_5~0); 263360#L1374-1 assume !(0 == ~E_6~0); 264091#L1379-1 assume !(0 == ~E_7~0); 264092#L1384-1 assume !(0 == ~E_8~0); 264178#L1389-1 assume !(0 == ~E_9~0); 264791#L1394-1 assume !(0 == ~E_10~0); 264792#L1399-1 assume !(0 == ~E_11~0); 264925#L1404-1 assume !(0 == ~E_12~0); 263456#L1409-1 assume !(0 == ~E_13~0); 263457#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 264911#L628 assume !(1 == ~m_pc~0); 263358#L628-2 is_master_triggered_~__retres1~0#1 := 0; 263357#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 263958#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 263959#L1591 assume !(0 != activate_threads_~tmp~1#1); 264940#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 263935#L647 assume !(1 == ~t1_pc~0); 263936#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 263990#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 263991#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 264505#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 264848#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 264849#L666 assume !(1 == ~t2_pc~0); 263138#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 263300#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 263278#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 263279#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 264298#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 264299#L685 assume !(1 == ~t3_pc~0); 264407#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 264479#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 264951#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 264142#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 264143#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 263583#L704 assume !(1 == ~t4_pc~0); 263584#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 264154#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 262927#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 262928#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 263988#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 263989#L723 assume !(1 == ~t5_pc~0); 264138#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 264374#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 264549#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 264277#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 264278#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 263342#L742 assume !(1 == ~t6_pc~0); 263343#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 263495#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 263269#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 263031#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 263032#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 263419#L761 assume !(1 == ~t7_pc~0); 263420#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 263296#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 263297#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 264145#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 264146#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 263056#L780 assume !(1 == ~t8_pc~0); 263057#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 263333#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 263334#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 264101#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 264102#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 264228#L799 assume 1 == ~t9_pc~0; 264339#L800 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 263058#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 263059#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 263328#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 264454#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 264254#L818 assume !(1 == ~t10_pc~0); 262842#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 262843#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 264330#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 264257#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 264258#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 264306#L837 assume 1 == ~t11_pc~0; 264307#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 264131#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 264853#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 264221#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 264222#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 263945#L856 assume !(1 == ~t12_pc~0); 263946#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 264675#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 262860#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 262861#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 264647#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 264876#L875 assume 1 == ~t13_pc~0; 263892#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 263496#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 263497#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 263438#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 263439#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 264329#L1427 assume !(1 == ~M_E~0); 264313#L1427-2 assume !(1 == ~T1_E~0); 263406#L1432-1 assume !(1 == ~T2_E~0); 263407#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 264562#L1442-1 assume !(1 == ~T4_E~0); 264563#L1447-1 assume !(1 == ~T5_E~0); 264385#L1452-1 assume !(1 == ~T6_E~0); 262979#L1457-1 assume !(1 == ~T7_E~0); 262980#L1462-1 assume !(1 == ~T8_E~0); 264584#L1467-1 assume !(1 == ~T9_E~0); 264609#L1472-1 assume !(1 == ~T10_E~0); 264610#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 264325#L1482-1 assume !(1 == ~T12_E~0); 264326#L1487-1 assume !(1 == ~T13_E~0); 263308#L1492-1 assume !(1 == ~E_M~0); 263309#L1497-1 assume !(1 == ~E_1~0); 263678#L1502-1 assume !(1 == ~E_2~0); 263679#L1507-1 assume !(1 == ~E_3~0); 263188#L1512-1 assume !(1 == ~E_4~0); 263189#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 264698#L1522-1 assume !(1 == ~E_6~0); 263931#L1527-1 assume !(1 == ~E_7~0); 263932#L1532-1 assume !(1 == ~E_8~0); 264985#L1537-1 assume !(1 == ~E_9~0); 264161#L1542-1 assume !(1 == ~E_10~0); 263965#L1547-1 assume !(1 == ~E_11~0); 263966#L1552-1 assume !(1 == ~E_12~0); 262883#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 262884#L1562-1 assume { :end_inline_reset_delta_events } true; 263486#L1928-2 [2023-11-29 03:21:14,224 INFO L750 eck$LassoCheckResult]: Loop: 263486#L1928-2 assume !false; 270454#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 270449#L1254-1 assume !false; 270447#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 270439#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 270430#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 270428#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 270426#L1067 assume !(0 != eval_~tmp~0#1); 270427#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 271562#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 271560#L1279-3 assume !(0 == ~M_E~0); 271558#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 271556#L1284-3 assume !(0 == ~T2_E~0); 271554#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 271552#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 271550#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 271548#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 271546#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 271544#L1314-3 assume !(0 == ~T8_E~0); 271542#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 271540#L1324-3 assume !(0 == ~T10_E~0); 271538#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 271536#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 271534#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 271532#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 271529#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 271527#L1354-3 assume !(0 == ~E_2~0); 271525#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 271523#L1364-3 assume !(0 == ~E_4~0); 271521#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 271519#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 271517#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 271515#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 271513#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 271511#L1394-3 assume !(0 == ~E_10~0); 271509#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 271506#L1404-3 assume !(0 == ~E_12~0); 271504#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 271502#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 271500#L628-45 assume !(1 == ~m_pc~0); 271497#L628-47 is_master_triggered_~__retres1~0#1 := 0; 271495#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 271493#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 271490#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 271487#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 271484#L647-45 assume !(1 == ~t1_pc~0); 271481#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 271479#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 271477#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 271475#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 271473#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 271470#L666-45 assume !(1 == ~t2_pc~0); 271468#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 271466#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 271464#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 271461#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 271459#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 271457#L685-45 assume 1 == ~t3_pc~0; 271454#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 271451#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 271448#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 271445#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 271443#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 271441#L704-45 assume !(1 == ~t4_pc~0); 271439#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 271436#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 271432#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 271428#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 271425#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 271422#L723-45 assume 1 == ~t5_pc~0; 271418#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 271415#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 271412#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 271409#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 271406#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 271403#L742-45 assume !(1 == ~t6_pc~0); 271400#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 271395#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 271391#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 271386#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 271382#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 271378#L761-45 assume !(1 == ~t7_pc~0); 271372#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 271366#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 271360#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 271353#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 271346#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 271340#L780-45 assume !(1 == ~t8_pc~0); 271335#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 271330#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 271325#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 271319#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 271314#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 271309#L799-45 assume !(1 == ~t9_pc~0); 271303#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 271298#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 271292#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 271285#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 271280#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 271275#L818-45 assume 1 == ~t10_pc~0; 271269#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 271264#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 271259#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 271257#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 271256#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 271255#L837-45 assume !(1 == ~t11_pc~0); 271253#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 271251#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 271250#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 271249#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 271248#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 271244#L856-45 assume 1 == ~t12_pc~0; 271241#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 271239#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 271237#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 271234#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 271232#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 271230#L875-45 assume 1 == ~t13_pc~0; 271228#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 271225#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 271223#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 271221#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 271219#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 271202#L1427-3 assume !(1 == ~M_E~0); 271200#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 271198#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 271196#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 271178#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 271174#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 271170#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 271164#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 271160#L1462-3 assume !(1 == ~T8_E~0); 271156#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 271151#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 271146#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 271140#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 271135#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 271130#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 271125#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 271120#L1502-3 assume !(1 == ~E_2~0); 271115#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 271110#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 271104#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 271098#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 271092#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 271087#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 271081#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 271076#L1542-3 assume !(1 == ~E_10~0); 271070#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 271065#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 271062#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 271060#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 270744#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 270728#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 270722#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 270715#L1947 assume !(0 == start_simulation_~tmp~3#1); 270712#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 270533#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 270518#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 270508#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 270499#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 270489#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 270478#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 270469#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 263486#L1928-2 [2023-11-29 03:21:14,224 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:14,224 INFO L85 PathProgramCache]: Analyzing trace with hash -618334264, now seen corresponding path program 1 times [2023-11-29 03:21:14,224 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:14,225 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598229018] [2023-11-29 03:21:14,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:14,225 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:14,237 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:14,271 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:14,271 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:14,271 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [598229018] [2023-11-29 03:21:14,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [598229018] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:14,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:14,272 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:21:14,272 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1853691526] [2023-11-29 03:21:14,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:14,272 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:14,272 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:14,273 INFO L85 PathProgramCache]: Analyzing trace with hash 812219497, now seen corresponding path program 1 times [2023-11-29 03:21:14,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:14,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138945348] [2023-11-29 03:21:14,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:14,273 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:14,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:14,449 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:14,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:14,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [138945348] [2023-11-29 03:21:14,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [138945348] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:14,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:14,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:14,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [504668192] [2023-11-29 03:21:14,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:14,450 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:14,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:14,451 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:14,451 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:14,451 INFO L87 Difference]: Start difference. First operand 51870 states and 73667 transitions. cyclomatic complexity: 21813 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:14,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:14,892 INFO L93 Difference]: Finished difference Result 99901 states and 141392 transitions. [2023-11-29 03:21:14,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 99901 states and 141392 transitions. [2023-11-29 03:21:15,280 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99408 [2023-11-29 03:21:15,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 99901 states to 99901 states and 141392 transitions. [2023-11-29 03:21:15,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 99901 [2023-11-29 03:21:15,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 99901 [2023-11-29 03:21:15,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 99901 states and 141392 transitions. [2023-11-29 03:21:15,698 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:15,699 INFO L218 hiAutomatonCegarLoop]: Abstraction has 99901 states and 141392 transitions. [2023-11-29 03:21:15,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 99901 states and 141392 transitions. [2023-11-29 03:21:16,497 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 99901 to 99837. [2023-11-29 03:21:16,557 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 99837 states, 99837 states have (on average 1.415587407474183) internal successors, (141328), 99836 states have internal predecessors, (141328), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:16,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 99837 states to 99837 states and 141328 transitions. [2023-11-29 03:21:16,761 INFO L240 hiAutomatonCegarLoop]: Abstraction has 99837 states and 141328 transitions. [2023-11-29 03:21:16,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:16,761 INFO L428 stractBuchiCegarLoop]: Abstraction has 99837 states and 141328 transitions. [2023-11-29 03:21:16,762 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 03:21:16,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 99837 states and 141328 transitions. [2023-11-29 03:21:17,172 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 99344 [2023-11-29 03:21:17,172 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:17,172 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:17,174 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:17,174 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:17,174 INFO L748 eck$LassoCheckResult]: Stem: 414898#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 414899#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 415929#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 415930#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 416815#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 415484#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 415485#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 415557#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 415558#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 416038#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 416039#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 415520#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 415320#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 415321#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 415803#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 415804#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 415675#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 415676#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 415295#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 415296#L1279 assume !(0 == ~M_E~0); 416692#L1279-2 assume !(0 == ~T1_E~0); 414920#L1284-1 assume !(0 == ~T2_E~0); 414921#L1289-1 assume !(0 == ~T3_E~0); 415668#L1294-1 assume !(0 == ~T4_E~0); 415669#L1299-1 assume !(0 == ~T5_E~0); 415684#L1304-1 assume !(0 == ~T6_E~0); 416814#L1309-1 assume !(0 == ~T7_E~0); 416816#L1314-1 assume !(0 == ~T8_E~0); 414841#L1319-1 assume !(0 == ~T9_E~0); 414842#L1324-1 assume !(0 == ~T10_E~0); 415020#L1329-1 assume !(0 == ~T11_E~0); 415021#L1334-1 assume !(0 == ~T12_E~0); 416564#L1339-1 assume !(0 == ~T13_E~0); 416675#L1344-1 assume !(0 == ~E_M~0); 416676#L1349-1 assume !(0 == ~E_1~0); 415881#L1354-1 assume !(0 == ~E_2~0); 415882#L1359-1 assume !(0 == ~E_3~0); 416342#L1364-1 assume !(0 == ~E_4~0); 415143#L1369-1 assume !(0 == ~E_5~0); 415144#L1374-1 assume !(0 == ~E_6~0); 415888#L1379-1 assume !(0 == ~E_7~0); 415889#L1384-1 assume !(0 == ~E_8~0); 415974#L1389-1 assume !(0 == ~E_9~0); 416591#L1394-1 assume !(0 == ~E_10~0); 416592#L1399-1 assume !(0 == ~E_11~0); 416732#L1404-1 assume !(0 == ~E_12~0); 415240#L1409-1 assume !(0 == ~E_13~0); 415241#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 416723#L628 assume !(1 == ~m_pc~0); 415142#L628-2 is_master_triggered_~__retres1~0#1 := 0; 415141#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 415747#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 415748#L1591 assume !(0 != activate_threads_~tmp~1#1); 416743#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 415725#L647 assume !(1 == ~t1_pc~0); 415726#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 415782#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 415783#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 416298#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 416657#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 416658#L666 assume !(1 == ~t2_pc~0); 414919#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 415083#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 415061#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 415062#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 416096#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 416097#L685 assume !(1 == ~t3_pc~0); 416199#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 416270#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 416754#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 415938#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 415939#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 415371#L704 assume !(1 == ~t4_pc~0); 415372#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 415950#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 414704#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 414705#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 415780#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 415781#L723 assume !(1 == ~t5_pc~0); 415934#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 416166#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 416335#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 416074#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 416075#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 415125#L742 assume !(1 == ~t6_pc~0); 415126#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 415284#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 415052#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 414812#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 414813#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 415203#L761 assume !(1 == ~t7_pc~0); 415204#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 415079#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 415080#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 415941#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 415942#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 414834#L780 assume !(1 == ~t8_pc~0); 414835#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 415116#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 415117#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 415896#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 415897#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 416025#L799 assume !(1 == ~t9_pc~0); 415341#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 414836#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 414837#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 415111#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 416247#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 416052#L818 assume !(1 == ~t10_pc~0); 414620#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 414621#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 416127#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 416055#L1671 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 416056#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 416104#L837 assume 1 == ~t11_pc~0; 416105#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 415927#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 416662#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 416016#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 416017#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 415736#L856 assume !(1 == ~t12_pc~0); 415737#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 416467#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 414638#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 414639#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 416442#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 416695#L875 assume 1 == ~t13_pc~0; 415682#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 415285#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 415286#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 415221#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 415222#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 416126#L1427 assume !(1 == ~M_E~0); 416111#L1427-2 assume !(1 == ~T1_E~0); 415191#L1432-1 assume !(1 == ~T2_E~0); 415192#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 416350#L1442-1 assume !(1 == ~T4_E~0); 416351#L1447-1 assume !(1 == ~T5_E~0); 416179#L1452-1 assume !(1 == ~T6_E~0); 414756#L1457-1 assume !(1 == ~T7_E~0); 414757#L1462-1 assume !(1 == ~T8_E~0); 416373#L1467-1 assume !(1 == ~T9_E~0); 416397#L1472-1 assume !(1 == ~T10_E~0); 416398#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 416122#L1482-1 assume !(1 == ~T12_E~0); 416123#L1487-1 assume !(1 == ~T13_E~0); 415091#L1492-1 assume !(1 == ~E_M~0); 415092#L1497-1 assume !(1 == ~E_1~0); 415465#L1502-1 assume !(1 == ~E_2~0); 415466#L1507-1 assume !(1 == ~E_3~0); 414971#L1512-1 assume !(1 == ~E_4~0); 414972#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 416493#L1522-1 assume !(1 == ~E_6~0); 415721#L1527-1 assume !(1 == ~E_7~0); 415722#L1532-1 assume !(1 == ~E_8~0); 416785#L1537-1 assume !(1 == ~E_9~0); 415957#L1542-1 assume !(1 == ~E_10~0); 415754#L1547-1 assume !(1 == ~E_11~0); 415755#L1552-1 assume !(1 == ~E_12~0); 414660#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 414661#L1562-1 assume { :end_inline_reset_delta_events } true; 415275#L1928-2 [2023-11-29 03:21:17,174 INFO L750 eck$LassoCheckResult]: Loop: 415275#L1928-2 assume !false; 434757#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 434752#L1254-1 assume !false; 434750#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 434671#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 434662#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 434660#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 434657#L1067 assume !(0 != eval_~tmp~0#1); 434653#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 434651#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 434649#L1279-3 assume !(0 == ~M_E~0); 434647#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 434644#L1284-3 assume !(0 == ~T2_E~0); 434642#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 434640#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 434638#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 434636#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 434634#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 434632#L1314-3 assume !(0 == ~T8_E~0); 434630#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 434628#L1324-3 assume !(0 == ~T10_E~0); 434625#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 434623#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 434621#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 434619#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 434617#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 434615#L1354-3 assume !(0 == ~E_2~0); 434613#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 434611#L1364-3 assume !(0 == ~E_4~0); 434609#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 434607#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 434605#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 434603#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 434600#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 434598#L1394-3 assume !(0 == ~E_10~0); 434596#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 434594#L1404-3 assume !(0 == ~E_12~0); 434592#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 434590#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 434588#L628-45 assume 1 == ~m_pc~0; 434586#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 434583#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 434581#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 434579#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 434577#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 434575#L647-45 assume !(1 == ~t1_pc~0); 434573#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 434571#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 434569#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 434567#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 434565#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 434560#L666-45 assume !(1 == ~t2_pc~0); 434558#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 434556#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 434554#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 434552#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 434549#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 434547#L685-45 assume 1 == ~t3_pc~0; 434545#L686-15 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 434546#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 443673#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 434536#L1615-45 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 434533#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 434531#L704-45 assume !(1 == ~t4_pc~0); 434529#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 434527#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 434525#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 434523#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 434520#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 434518#L723-45 assume !(1 == ~t5_pc~0); 434516#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 434513#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 434511#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 434510#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 434509#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 434505#L742-45 assume !(1 == ~t6_pc~0); 434503#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 434501#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 434500#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 434497#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 434496#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 434495#L761-45 assume !(1 == ~t7_pc~0); 434494#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 434492#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 434491#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 434490#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 434489#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 434488#L780-45 assume !(1 == ~t8_pc~0); 434487#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 434486#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 434485#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 434484#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 434483#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 434482#L799-45 assume !(1 == ~t9_pc~0); 434481#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 434479#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 434478#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 434477#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 434472#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 434466#L818-45 assume !(1 == ~t10_pc~0); 434460#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 434457#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 434453#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 434451#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 434449#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 434447#L837-45 assume 1 == ~t11_pc~0; 434444#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 434441#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 434439#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 434437#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 434435#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 434433#L856-45 assume 1 == ~t12_pc~0; 434430#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 434428#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 434426#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 434423#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 434421#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 434419#L875-45 assume !(1 == ~t13_pc~0); 434416#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 434414#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 434412#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 434410#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 434408#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 434406#L1427-3 assume !(1 == ~M_E~0); 434034#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 434403#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 434401#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 434398#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 434396#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 434394#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 434392#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 434390#L1462-3 assume !(1 == ~T8_E~0); 434388#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 434386#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 434384#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 434382#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 434380#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 434378#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 434376#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 434374#L1502-3 assume !(1 == ~E_2~0); 434372#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 434370#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 434368#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 434366#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 434364#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 434361#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 434359#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 434357#L1542-3 assume !(1 == ~E_10~0); 434355#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 434353#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 434351#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 434348#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 434309#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 434301#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 434300#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 434296#L1947 assume !(0 == start_simulation_~tmp~3#1); 434297#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 434782#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 434772#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 434768#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 434764#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 434763#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 434762#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 434761#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 415275#L1928-2 [2023-11-29 03:21:17,175 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:17,175 INFO L85 PathProgramCache]: Analyzing trace with hash -1649665079, now seen corresponding path program 1 times [2023-11-29 03:21:17,175 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:17,175 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [386161731] [2023-11-29 03:21:17,175 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:17,175 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:17,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:17,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:17,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:17,236 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [386161731] [2023-11-29 03:21:17,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [386161731] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:17,237 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:17,237 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:21:17,237 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [842401666] [2023-11-29 03:21:17,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:17,237 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:17,237 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:17,238 INFO L85 PathProgramCache]: Analyzing trace with hash 1980132586, now seen corresponding path program 1 times [2023-11-29 03:21:17,238 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:17,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1354291442] [2023-11-29 03:21:17,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:17,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:17,248 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:17,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:17,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:17,289 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1354291442] [2023-11-29 03:21:17,289 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1354291442] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:17,289 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:17,289 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:21:17,289 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751647420] [2023-11-29 03:21:17,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:17,290 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:17,290 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:17,290 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:21:17,290 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:21:17,291 INFO L87 Difference]: Start difference. First operand 99837 states and 141328 transitions. cyclomatic complexity: 41523 Second operand has 5 states, 5 states have (on average 32.2) internal successors, (161), 5 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:18,169 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:18,170 INFO L93 Difference]: Finished difference Result 215385 states and 303320 transitions. [2023-11-29 03:21:18,170 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 215385 states and 303320 transitions. [2023-11-29 03:21:19,115 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 214496 [2023-11-29 03:21:19,584 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 215385 states to 215385 states and 303320 transitions. [2023-11-29 03:21:19,584 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 215385 [2023-11-29 03:21:19,670 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 215385 [2023-11-29 03:21:19,670 INFO L73 IsDeterministic]: Start isDeterministic. Operand 215385 states and 303320 transitions. [2023-11-29 03:21:19,755 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:19,755 INFO L218 hiAutomatonCegarLoop]: Abstraction has 215385 states and 303320 transitions. [2023-11-29 03:21:19,849 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215385 states and 303320 transitions. [2023-11-29 03:21:21,009 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215385 to 102336. [2023-11-29 03:21:21,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 102336 states, 102336 states have (on average 1.4054389462163852) internal successors, (143827), 102335 states have internal predecessors, (143827), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:21,217 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 102336 states to 102336 states and 143827 transitions. [2023-11-29 03:21:21,217 INFO L240 hiAutomatonCegarLoop]: Abstraction has 102336 states and 143827 transitions. [2023-11-29 03:21:21,218 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 03:21:21,218 INFO L428 stractBuchiCegarLoop]: Abstraction has 102336 states and 143827 transitions. [2023-11-29 03:21:21,218 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-29 03:21:21,218 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 102336 states and 143827 transitions. [2023-11-29 03:21:21,447 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101840 [2023-11-29 03:21:21,447 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:21,447 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:21,449 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:21,449 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:21,450 INFO L748 eck$LassoCheckResult]: Stem: 730131#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 730132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 731143#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 731144#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 732039#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 730710#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 730711#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 730783#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 730784#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 731253#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 731254#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 730749#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 730550#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 730551#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 731025#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 731026#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 730901#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 730902#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 730524#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 730525#L1279 assume !(0 == ~M_E~0); 731898#L1279-2 assume !(0 == ~T1_E~0); 730152#L1284-1 assume !(0 == ~T2_E~0); 730153#L1289-1 assume !(0 == ~T3_E~0); 730893#L1294-1 assume !(0 == ~T4_E~0); 730894#L1299-1 assume !(0 == ~T5_E~0); 730905#L1304-1 assume !(0 == ~T6_E~0); 732034#L1309-1 assume !(0 == ~T7_E~0); 732040#L1314-1 assume !(0 == ~T8_E~0); 730076#L1319-1 assume !(0 == ~T9_E~0); 730077#L1324-1 assume !(0 == ~T10_E~0); 730253#L1329-1 assume !(0 == ~T11_E~0); 730254#L1334-1 assume !(0 == ~T12_E~0); 731783#L1339-1 assume !(0 == ~T13_E~0); 731883#L1344-1 assume !(0 == ~E_M~0); 731884#L1349-1 assume !(0 == ~E_1~0); 731099#L1354-1 assume !(0 == ~E_2~0); 731100#L1359-1 assume !(0 == ~E_3~0); 731553#L1364-1 assume !(0 == ~E_4~0); 730375#L1369-1 assume !(0 == ~E_5~0); 730376#L1374-1 assume !(0 == ~E_6~0); 731106#L1379-1 assume !(0 == ~E_7~0); 731107#L1384-1 assume !(0 == ~E_8~0); 731189#L1389-1 assume !(0 == ~E_9~0); 731807#L1394-1 assume !(0 == ~E_10~0); 731808#L1399-1 assume !(0 == ~E_11~0); 731939#L1404-1 assume !(0 == ~E_12~0); 730472#L1409-1 assume !(0 == ~E_13~0); 730473#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 731929#L628 assume !(1 == ~m_pc~0); 730374#L628-2 is_master_triggered_~__retres1~0#1 := 0; 730373#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 730971#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 730972#L1591 assume !(0 != activate_threads_~tmp~1#1); 731951#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 730948#L647 assume !(1 == ~t1_pc~0); 730949#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 731003#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 731004#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 731513#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 731869#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 731870#L666 assume !(1 == ~t2_pc~0); 730151#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 730317#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 730295#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 730296#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 731307#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 731308#L685 assume !(1 == ~t3_pc~0); 731414#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 731487#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 731964#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 731153#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 731154#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 730599#L704 assume !(1 == ~t4_pc~0); 730600#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 731164#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 729942#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 729943#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 731001#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 731002#L723 assume !(1 == ~t5_pc~0); 731149#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 731386#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 731546#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 731285#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 731286#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 730358#L742 assume !(1 == ~t6_pc~0); 730359#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 730513#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 730284#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 730047#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 730048#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 730435#L761 assume !(1 == ~t7_pc~0); 730436#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 730313#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 730314#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 731155#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 731156#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 730067#L780 assume !(1 == ~t8_pc~0); 730068#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 730348#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 730349#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 731112#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 731113#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 731241#L799 assume !(1 == ~t9_pc~0); 730571#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 730069#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 730070#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 730343#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 731465#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 731264#L818 assume !(1 == ~t10_pc~0); 729857#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 729858#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 731346#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 731267#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 731268#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 731316#L837 assume 1 == ~t11_pc~0; 731317#L838 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 731141#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 731873#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 731231#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 731232#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 730962#L856 assume !(1 == ~t12_pc~0); 730963#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 731683#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 729875#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 729876#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 731657#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 731901#L875 assume 1 == ~t13_pc~0; 730903#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 730514#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 730515#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 730453#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 730454#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 731342#L1427 assume !(1 == ~M_E~0); 731328#L1427-2 assume !(1 == ~T1_E~0); 730423#L1432-1 assume !(1 == ~T2_E~0); 730424#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 731561#L1442-1 assume !(1 == ~T4_E~0); 731562#L1447-1 assume !(1 == ~T5_E~0); 731397#L1452-1 assume !(1 == ~T6_E~0); 729993#L1457-1 assume !(1 == ~T7_E~0); 729994#L1462-1 assume !(1 == ~T8_E~0); 731590#L1467-1 assume !(1 == ~T9_E~0); 731616#L1472-1 assume !(1 == ~T10_E~0); 731617#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 731338#L1482-1 assume !(1 == ~T12_E~0); 731339#L1487-1 assume !(1 == ~T13_E~0); 730323#L1492-1 assume !(1 == ~E_M~0); 730324#L1497-1 assume !(1 == ~E_1~0); 730691#L1502-1 assume !(1 == ~E_2~0); 730692#L1507-1 assume !(1 == ~E_3~0); 730202#L1512-1 assume !(1 == ~E_4~0); 730203#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 731711#L1522-1 assume !(1 == ~E_6~0); 730946#L1527-1 assume !(1 == ~E_7~0); 730947#L1532-1 assume !(1 == ~E_8~0); 731997#L1537-1 assume !(1 == ~E_9~0); 731174#L1542-1 assume !(1 == ~E_10~0); 730979#L1547-1 assume !(1 == ~E_11~0); 730980#L1552-1 assume !(1 == ~E_12~0); 729900#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 729901#L1562-1 assume { :end_inline_reset_delta_events } true; 730503#L1928-2 [2023-11-29 03:21:21,450 INFO L750 eck$LassoCheckResult]: Loop: 730503#L1928-2 assume !false; 747102#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 747098#L1254-1 assume !false; 747097#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 747090#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 747081#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 747078#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 747070#L1067 assume !(0 != eval_~tmp~0#1); 747071#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 747412#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 747411#L1279-3 assume !(0 == ~M_E~0); 747410#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 747409#L1284-3 assume !(0 == ~T2_E~0); 747408#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 747407#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 747406#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 747405#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 747404#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 747403#L1314-3 assume !(0 == ~T8_E~0); 747402#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 747401#L1324-3 assume !(0 == ~T10_E~0); 747400#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 747399#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 747398#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 747397#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 747396#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 747395#L1354-3 assume !(0 == ~E_2~0); 747394#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 747393#L1364-3 assume !(0 == ~E_4~0); 747392#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 747391#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 747390#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 747389#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 747388#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 747387#L1394-3 assume !(0 == ~E_10~0); 747386#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 747385#L1404-3 assume !(0 == ~E_12~0); 747384#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 747383#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 747382#L628-45 assume 1 == ~m_pc~0; 747381#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 747379#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 747378#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 747377#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 747376#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 747375#L647-45 assume !(1 == ~t1_pc~0); 747374#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 747373#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 747372#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 747371#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 747370#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 747368#L666-45 assume !(1 == ~t2_pc~0); 747367#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 747366#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 747365#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 747364#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 747363#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 747362#L685-45 assume !(1 == ~t3_pc~0); 747361#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 747359#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 747357#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 747355#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 747353#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 747352#L704-45 assume !(1 == ~t4_pc~0); 747351#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 747350#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 747349#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 747348#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 747347#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 747346#L723-45 assume !(1 == ~t5_pc~0); 747345#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 747343#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 747342#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 747341#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 747340#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 747339#L742-45 assume !(1 == ~t6_pc~0); 747338#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 747337#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 747336#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 747335#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 747334#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 747333#L761-45 assume 1 == ~t7_pc~0; 747331#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 747330#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 747329#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 747328#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 747327#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 747326#L780-45 assume !(1 == ~t8_pc~0); 747325#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 747324#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 747323#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 747322#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 747321#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 747320#L799-45 assume !(1 == ~t9_pc~0); 747319#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 747318#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 747317#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 747316#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 747315#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 747314#L818-45 assume !(1 == ~t10_pc~0); 747313#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 747311#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 747309#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 747307#L1671-45 assume !(0 != activate_threads_~tmp___9~0#1); 747304#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 747302#L837-45 assume 1 == ~t11_pc~0; 747299#L838-15 assume 1 == ~E_11~0;is_transmit11_triggered_~__retres1~11#1 := 1; 747296#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 747294#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 747292#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 747290#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 747288#L856-45 assume !(1 == ~t12_pc~0); 747285#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 747282#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 747280#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 747278#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 747276#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 747274#L875-45 assume 1 == ~t13_pc~0; 747271#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 747268#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 747266#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 747264#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 747262#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 747259#L1427-3 assume !(1 == ~M_E~0); 747258#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 747257#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 747256#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 747255#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 747254#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 747252#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 747249#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 747247#L1462-3 assume !(1 == ~T8_E~0); 747245#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 747243#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 747241#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 747239#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 747237#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 747235#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 747233#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 747231#L1502-3 assume !(1 == ~E_2~0); 747229#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 747227#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 747225#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 747223#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 747221#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 747219#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 747217#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 747215#L1542-3 assume !(1 == ~E_10~0); 747213#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 747211#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 747209#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 747207#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 747196#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 747188#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 747186#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 747183#L1947 assume !(0 == start_simulation_~tmp~3#1); 747181#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 747168#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 747159#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 747152#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 747144#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 747133#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 747122#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 747114#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 730503#L1928-2 [2023-11-29 03:21:21,451 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:21,451 INFO L85 PathProgramCache]: Analyzing trace with hash -1665183797, now seen corresponding path program 1 times [2023-11-29 03:21:21,451 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:21,451 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517999758] [2023-11-29 03:21:21,451 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:21,451 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:21,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:21,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:21,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:21,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1517999758] [2023-11-29 03:21:21,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1517999758] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:21,519 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:21,519 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:21,519 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [141510256] [2023-11-29 03:21:21,519 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:21,519 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:21,520 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:21,520 INFO L85 PathProgramCache]: Analyzing trace with hash 2004219054, now seen corresponding path program 1 times [2023-11-29 03:21:21,520 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:21,520 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280578927] [2023-11-29 03:21:21,520 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:21,520 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:21,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:21,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:21,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:21,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1280578927] [2023-11-29 03:21:21,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1280578927] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:21,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:21,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:21:21,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1792456467] [2023-11-29 03:21:21,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:21,572 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:21,572 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:21,572 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:21:21,572 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:21:21,572 INFO L87 Difference]: Start difference. First operand 102336 states and 143827 transitions. cyclomatic complexity: 41523 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:22,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:22,612 INFO L93 Difference]: Finished difference Result 283579 states and 396169 transitions. [2023-11-29 03:21:22,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 283579 states and 396169 transitions. [2023-11-29 03:21:23,909 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 281936 [2023-11-29 03:21:24,704 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 283579 states to 283579 states and 396169 transitions. [2023-11-29 03:21:24,704 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 283579 [2023-11-29 03:21:24,780 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 283579 [2023-11-29 03:21:24,780 INFO L73 IsDeterministic]: Start isDeterministic. Operand 283579 states and 396169 transitions. [2023-11-29 03:21:24,851 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:24,851 INFO L218 hiAutomatonCegarLoop]: Abstraction has 283579 states and 396169 transitions. [2023-11-29 03:21:24,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 283579 states and 396169 transitions. [2023-11-29 03:21:26,743 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 283579 to 281787. [2023-11-29 03:21:26,895 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 281787 states, 281787 states have (on average 1.397740137053874) internal successors, (393865), 281786 states have internal predecessors, (393865), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:27,892 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 281787 states to 281787 states and 393865 transitions. [2023-11-29 03:21:27,892 INFO L240 hiAutomatonCegarLoop]: Abstraction has 281787 states and 393865 transitions. [2023-11-29 03:21:27,893 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:21:27,893 INFO L428 stractBuchiCegarLoop]: Abstraction has 281787 states and 393865 transitions. [2023-11-29 03:21:27,893 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-29 03:21:27,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 281787 states and 393865 transitions. [2023-11-29 03:21:28,561 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 280528 [2023-11-29 03:21:28,561 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:28,561 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:28,564 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:28,564 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:28,564 INFO L748 eck$LassoCheckResult]: Stem: 1116056#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1116057#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1117094#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1117095#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1118047#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 1116645#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1116646#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1116718#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1116719#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1117206#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1117207#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1116684#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1116478#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1116479#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1116973#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1116974#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1116848#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1116849#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1116454#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1116455#L1279 assume !(0 == ~M_E~0); 1117876#L1279-2 assume !(0 == ~T1_E~0); 1116078#L1284-1 assume !(0 == ~T2_E~0); 1116079#L1289-1 assume !(0 == ~T3_E~0); 1116837#L1294-1 assume !(0 == ~T4_E~0); 1116838#L1299-1 assume !(0 == ~T5_E~0); 1116852#L1304-1 assume !(0 == ~T6_E~0); 1118042#L1309-1 assume !(0 == ~T7_E~0); 1118049#L1314-1 assume !(0 == ~T8_E~0); 1116000#L1319-1 assume !(0 == ~T9_E~0); 1116001#L1324-1 assume !(0 == ~T10_E~0); 1116179#L1329-1 assume !(0 == ~T11_E~0); 1116180#L1334-1 assume !(0 == ~T12_E~0); 1117756#L1339-1 assume !(0 == ~T13_E~0); 1117862#L1344-1 assume !(0 == ~E_M~0); 1117863#L1349-1 assume !(0 == ~E_1~0); 1117047#L1354-1 assume !(0 == ~E_2~0); 1117048#L1359-1 assume !(0 == ~E_3~0); 1117514#L1364-1 assume !(0 == ~E_4~0); 1116303#L1369-1 assume !(0 == ~E_5~0); 1116304#L1374-1 assume !(0 == ~E_6~0); 1117057#L1379-1 assume !(0 == ~E_7~0); 1117058#L1384-1 assume !(0 == ~E_8~0); 1117143#L1389-1 assume !(0 == ~E_9~0); 1117786#L1394-1 assume !(0 == ~E_10~0); 1117787#L1399-1 assume !(0 == ~E_11~0); 1117925#L1404-1 assume !(0 == ~E_12~0); 1116400#L1409-1 assume !(0 == ~E_13~0); 1116401#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1117916#L628 assume !(1 == ~m_pc~0); 1116302#L628-2 is_master_triggered_~__retres1~0#1 := 0; 1116301#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1116917#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1116918#L1591 assume !(0 != activate_threads_~tmp~1#1); 1117936#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1116892#L647 assume !(1 == ~t1_pc~0); 1116893#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1116952#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1116953#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1117468#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 1117843#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1117844#L666 assume !(1 == ~t2_pc~0); 1116077#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1116243#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1116223#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1116224#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 1117262#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1117263#L685 assume !(1 == ~t3_pc~0); 1117445#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1117446#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1117454#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1117105#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 1117106#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1116531#L704 assume !(1 == ~t4_pc~0); 1116532#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1117118#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1115868#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1115869#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 1116950#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1116951#L723 assume !(1 == ~t5_pc~0); 1117102#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1117342#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1117506#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1117241#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 1117242#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1116287#L742 assume !(1 == ~t6_pc~0); 1116288#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1116443#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1116212#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1115972#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 1115973#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1116366#L761 assume !(1 == ~t7_pc~0); 1116367#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1116241#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1116242#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1117108#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 1117109#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1115993#L780 assume !(1 == ~t8_pc~0); 1115994#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1116277#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1116278#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1117065#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 1117066#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1117194#L799 assume !(1 == ~t9_pc~0); 1116500#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1115995#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1115996#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1116272#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 1117424#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1117217#L818 assume !(1 == ~t10_pc~0); 1115783#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1115784#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1117298#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1117220#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 1117221#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1117273#L837 assume !(1 == ~t11_pc~0); 1117092#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1117093#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1117849#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1117184#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 1117185#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1116905#L856 assume !(1 == ~t12_pc~0); 1116906#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1117653#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1115801#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1115802#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 1117621#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1117880#L875 assume 1 == ~t13_pc~0; 1116850#L876 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1116444#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1116445#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1116382#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 1116383#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1117297#L1427 assume !(1 == ~M_E~0); 1117282#L1427-2 assume !(1 == ~T1_E~0); 1116352#L1432-1 assume !(1 == ~T2_E~0); 1116353#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1117521#L1442-1 assume !(1 == ~T4_E~0); 1117522#L1447-1 assume !(1 == ~T5_E~0); 1117357#L1452-1 assume !(1 == ~T6_E~0); 1115919#L1457-1 assume !(1 == ~T7_E~0); 1115920#L1462-1 assume !(1 == ~T8_E~0); 1117549#L1467-1 assume !(1 == ~T9_E~0); 1117578#L1472-1 assume !(1 == ~T10_E~0); 1117579#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1117293#L1482-1 assume !(1 == ~T12_E~0); 1117294#L1487-1 assume !(1 == ~T13_E~0); 1116252#L1492-1 assume !(1 == ~E_M~0); 1116253#L1497-1 assume !(1 == ~E_1~0); 1116626#L1502-1 assume !(1 == ~E_2~0); 1116627#L1507-1 assume !(1 == ~E_3~0); 1116128#L1512-1 assume !(1 == ~E_4~0); 1116129#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1117676#L1522-1 assume !(1 == ~E_6~0); 1116890#L1527-1 assume !(1 == ~E_7~0); 1116891#L1532-1 assume !(1 == ~E_8~0); 1118004#L1537-1 assume !(1 == ~E_9~0); 1117125#L1542-1 assume !(1 == ~E_10~0); 1116926#L1547-1 assume !(1 == ~E_11~0); 1116927#L1552-1 assume !(1 == ~E_12~0); 1115826#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1115827#L1562-1 assume { :end_inline_reset_delta_events } true; 1116433#L1928-2 [2023-11-29 03:21:28,564 INFO L750 eck$LassoCheckResult]: Loop: 1116433#L1928-2 assume !false; 1228133#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1228126#L1254-1 assume !false; 1228122#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1228107#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1228099#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1228098#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 1228096#L1067 assume !(0 != eval_~tmp~0#1); 1228095#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1220643#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1220640#L1279-3 assume !(0 == ~M_E~0); 1220638#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1220636#L1284-3 assume !(0 == ~T2_E~0); 1220634#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1220632#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1220630#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1220627#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1220625#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1220623#L1314-3 assume !(0 == ~T8_E~0); 1220621#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1220619#L1324-3 assume !(0 == ~T10_E~0); 1220617#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 1220615#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 1220613#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 1220611#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 1220609#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1220607#L1354-3 assume !(0 == ~E_2~0); 1220603#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1220601#L1364-3 assume !(0 == ~E_4~0); 1220599#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1220597#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1220594#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1220592#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1220590#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 1220589#L1394-3 assume !(0 == ~E_10~0); 1220587#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 1220585#L1404-3 assume !(0 == ~E_12~0); 1220583#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 1220581#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1220579#L628-45 assume !(1 == ~m_pc~0); 1220562#L628-47 is_master_triggered_~__retres1~0#1 := 0; 1220560#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1220557#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1220555#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1220553#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1220552#L647-45 assume !(1 == ~t1_pc~0); 1220537#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 1220535#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1220533#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1220531#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1220529#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1220525#L666-45 assume !(1 == ~t2_pc~0); 1220523#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 1220520#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1220518#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1220516#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1220514#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1220512#L685-45 assume !(1 == ~t3_pc~0); 1220510#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 1220508#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1220506#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1220504#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 1220502#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1220500#L704-45 assume !(1 == ~t4_pc~0); 1220498#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 1220496#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1220494#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1220492#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1220490#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1220488#L723-45 assume !(1 == ~t5_pc~0); 1220486#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 1220483#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1220480#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1220478#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 1220476#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1220474#L742-45 assume !(1 == ~t6_pc~0); 1220472#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 1220470#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1220468#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1220466#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1220464#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1220462#L761-45 assume 1 == ~t7_pc~0; 1220459#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1220457#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1220454#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1220452#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1220450#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1220448#L780-45 assume !(1 == ~t8_pc~0); 1220446#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 1220444#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1220442#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1220440#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1220438#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1220436#L799-45 assume !(1 == ~t9_pc~0); 1220434#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 1220432#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1220430#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1220428#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1220426#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1220424#L818-45 assume 1 == ~t10_pc~0; 1220422#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1220423#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1220740#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1220411#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1220409#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1220406#L837-45 assume !(1 == ~t11_pc~0); 1220404#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 1220402#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1220400#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1220398#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 1220396#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1220394#L856-45 assume 1 == ~t12_pc~0; 1220391#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 1220389#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1220386#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1220384#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 1220382#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1220380#L875-45 assume 1 == ~t13_pc~0; 1220378#L876-15 assume 1 == ~E_13~0;is_transmit13_triggered_~__retres1~13#1 := 1; 1220375#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1220372#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1220370#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 1220368#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1220366#L1427-3 assume !(1 == ~M_E~0); 1220023#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1220364#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1220360#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1220358#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1220356#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1220355#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1220352#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1220351#L1462-3 assume !(1 == ~T8_E~0); 1220350#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1220347#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1220343#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1220339#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 1220335#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 1220331#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 1220327#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1220326#L1502-3 assume !(1 == ~E_2~0); 1220324#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1220320#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1220316#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1220312#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1220308#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1220304#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1220303#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 1220302#L1542-3 assume !(1 == ~E_10~0); 1220301#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 1220300#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 1220299#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 1220298#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1220290#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1220283#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1220282#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 1220280#L1947 assume !(0 == start_simulation_~tmp~3#1); 1220281#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 1228159#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 1228151#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 1228148#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 1228146#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1228144#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1228142#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 1228140#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 1116433#L1928-2 [2023-11-29 03:21:28,565 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:28,565 INFO L85 PathProgramCache]: Analyzing trace with hash 736341324, now seen corresponding path program 1 times [2023-11-29 03:21:28,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:28,565 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1856575323] [2023-11-29 03:21:28,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:28,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:28,581 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:28,642 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:28,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:28,642 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1856575323] [2023-11-29 03:21:28,643 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1856575323] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:28,643 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:28,643 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:21:28,643 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [724543655] [2023-11-29 03:21:28,643 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:28,644 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:28,644 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:28,644 INFO L85 PathProgramCache]: Analyzing trace with hash 1422958444, now seen corresponding path program 1 times [2023-11-29 03:21:28,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:28,645 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1270466234] [2023-11-29 03:21:28,645 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:28,645 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:28,663 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:28,704 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:28,704 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:28,704 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1270466234] [2023-11-29 03:21:28,704 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1270466234] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:28,705 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:28,705 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:28,705 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1324897161] [2023-11-29 03:21:28,705 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:28,705 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:28,706 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:28,706 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:21:28,706 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:21:28,706 INFO L87 Difference]: Start difference. First operand 281787 states and 393865 transitions. cyclomatic complexity: 112142 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:30,861 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:30,861 INFO L93 Difference]: Finished difference Result 541610 states and 754806 transitions. [2023-11-29 03:21:30,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 541610 states and 754806 transitions. [2023-11-29 03:21:33,007 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 538880 [2023-11-29 03:21:34,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 541610 states to 541610 states and 754806 transitions. [2023-11-29 03:21:34,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 541610 [2023-11-29 03:21:34,580 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 541610 [2023-11-29 03:21:34,580 INFO L73 IsDeterministic]: Start isDeterministic. Operand 541610 states and 754806 transitions. [2023-11-29 03:21:34,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:34,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 541610 states and 754806 transitions. [2023-11-29 03:21:35,031 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541610 states and 754806 transitions. [2023-11-29 03:21:38,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541610 to 541226. [2023-11-29 03:21:39,426 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 541226 states, 541226 states have (on average 1.3939130788247422) internal successors, (754422), 541225 states have internal predecessors, (754422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:40,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 541226 states to 541226 states and 754422 transitions. [2023-11-29 03:21:40,791 INFO L240 hiAutomatonCegarLoop]: Abstraction has 541226 states and 754422 transitions. [2023-11-29 03:21:40,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:21:40,791 INFO L428 stractBuchiCegarLoop]: Abstraction has 541226 states and 754422 transitions. [2023-11-29 03:21:40,792 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-29 03:21:40,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 541226 states and 754422 transitions. [2023-11-29 03:21:42,436 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 538496 [2023-11-29 03:21:42,436 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:21:42,436 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:21:42,438 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:42,438 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:21:42,439 INFO L748 eck$LassoCheckResult]: Stem: 1939458#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 1939459#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 1940498#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1940499#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1941490#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 1940046#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1940047#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1940121#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1940122#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1940612#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1940613#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1940082#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1939880#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1939881#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1940371#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1940372#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 1940244#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 1940245#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 1939855#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1939856#L1279 assume !(0 == ~M_E~0); 1941319#L1279-2 assume !(0 == ~T1_E~0); 1939480#L1284-1 assume !(0 == ~T2_E~0); 1939481#L1289-1 assume !(0 == ~T3_E~0); 1940241#L1294-1 assume !(0 == ~T4_E~0); 1940242#L1299-1 assume !(0 == ~T5_E~0); 1940252#L1304-1 assume !(0 == ~T6_E~0); 1941486#L1309-1 assume !(0 == ~T7_E~0); 1941492#L1314-1 assume !(0 == ~T8_E~0); 1939404#L1319-1 assume !(0 == ~T9_E~0); 1939405#L1324-1 assume !(0 == ~T10_E~0); 1939580#L1329-1 assume !(0 == ~T11_E~0); 1939581#L1334-1 assume !(0 == ~T12_E~0); 1941191#L1339-1 assume !(0 == ~T13_E~0); 1941305#L1344-1 assume !(0 == ~E_M~0); 1941306#L1349-1 assume !(0 == ~E_1~0); 1940449#L1354-1 assume !(0 == ~E_2~0); 1940450#L1359-1 assume !(0 == ~E_3~0); 1940935#L1364-1 assume !(0 == ~E_4~0); 1939700#L1369-1 assume !(0 == ~E_5~0); 1939701#L1374-1 assume !(0 == ~E_6~0); 1940457#L1379-1 assume !(0 == ~E_7~0); 1940458#L1384-1 assume !(0 == ~E_8~0); 1940546#L1389-1 assume !(0 == ~E_9~0); 1941222#L1394-1 assume !(0 == ~E_10~0); 1941223#L1399-1 assume !(0 == ~E_11~0); 1941379#L1404-1 assume !(0 == ~E_12~0); 1939800#L1409-1 assume !(0 == ~E_13~0); 1939801#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1941368#L628 assume !(1 == ~m_pc~0); 1939699#L628-2 is_master_triggered_~__retres1~0#1 := 0; 1939698#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1940316#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1940317#L1591 assume !(0 != activate_threads_~tmp~1#1); 1941390#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1940292#L647 assume !(1 == ~t1_pc~0); 1940293#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1940348#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1940349#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1940888#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 1941285#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1941286#L666 assume !(1 == ~t2_pc~0); 1939479#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1939641#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1939620#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1939621#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 1940676#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1940677#L685 assume !(1 == ~t3_pc~0); 1940860#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1940861#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1940870#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1940507#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 1940508#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1939932#L704 assume !(1 == ~t4_pc~0); 1939933#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1940520#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1939271#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1939272#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 1940346#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1940347#L723 assume !(1 == ~t5_pc~0); 1940503#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1940759#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1940927#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1940649#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 1940650#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1939683#L742 assume !(1 == ~t6_pc~0); 1939684#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1939844#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1939611#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1939375#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 1939376#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1939763#L761 assume !(1 == ~t7_pc~0); 1939764#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1939637#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1939638#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 1940510#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 1940511#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1939397#L780 assume !(1 == ~t8_pc~0); 1939398#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1939674#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1939675#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 1940466#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 1940467#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1940599#L799 assume !(1 == ~t9_pc~0); 1939901#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1939399#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1939400#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 1939669#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 1940833#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1940629#L818 assume !(1 == ~t10_pc~0); 1939187#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1939188#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1940712#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 1940632#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 1940633#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 1940684#L837 assume !(1 == ~t11_pc~0); 1940495#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 1940496#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 1941290#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 1940592#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 1940593#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 1940302#L856 assume !(1 == ~t12_pc~0); 1940303#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 1941075#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 1939205#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 1939206#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 1941039#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 1941326#L875 assume !(1 == ~t13_pc~0); 1941297#L875-2 is_transmit13_triggered_~__retres1~13#1 := 0; 1939845#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 1939846#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 1939781#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 1939782#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1940711#L1427 assume !(1 == ~M_E~0); 1940693#L1427-2 assume !(1 == ~T1_E~0); 1939750#L1432-1 assume !(1 == ~T2_E~0); 1939751#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1940941#L1442-1 assume !(1 == ~T4_E~0); 1940942#L1447-1 assume !(1 == ~T5_E~0); 1940772#L1452-1 assume !(1 == ~T6_E~0); 1939322#L1457-1 assume !(1 == ~T7_E~0); 1939323#L1462-1 assume !(1 == ~T8_E~0); 1940970#L1467-1 assume !(1 == ~T9_E~0); 1941000#L1472-1 assume !(1 == ~T10_E~0); 1941001#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 1940707#L1482-1 assume !(1 == ~T12_E~0); 1940708#L1487-1 assume !(1 == ~T13_E~0); 1939649#L1492-1 assume !(1 == ~E_M~0); 1939650#L1497-1 assume !(1 == ~E_1~0); 1940027#L1502-1 assume !(1 == ~E_2~0); 1940028#L1507-1 assume !(1 == ~E_3~0); 1939530#L1512-1 assume !(1 == ~E_4~0); 1939531#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 1941098#L1522-1 assume !(1 == ~E_6~0); 1940288#L1527-1 assume !(1 == ~E_7~0); 1940289#L1532-1 assume !(1 == ~E_8~0); 1941449#L1537-1 assume !(1 == ~E_9~0); 1940528#L1542-1 assume !(1 == ~E_10~0); 1940323#L1547-1 assume !(1 == ~E_11~0); 1940324#L1552-1 assume !(1 == ~E_12~0); 1939227#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 1939228#L1562-1 assume { :end_inline_reset_delta_events } true; 1939834#L1928-2 [2023-11-29 03:21:42,439 INFO L750 eck$LassoCheckResult]: Loop: 1939834#L1928-2 assume !false; 2207403#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2207398#L1254-1 assume !false; 2207396#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2207377#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2207368#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2207366#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 2207362#L1067 assume !(0 != eval_~tmp~0#1); 2207360#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2207358#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2207356#L1279-3 assume !(0 == ~M_E~0); 2207354#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2207352#L1284-3 assume !(0 == ~T2_E~0); 2207350#L1289-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2207348#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2207346#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2207343#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2207341#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2207339#L1314-3 assume !(0 == ~T8_E~0); 2207337#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2207335#L1324-3 assume !(0 == ~T10_E~0); 2207333#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 2207331#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 2207329#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 2207327#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 2207325#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2207323#L1354-3 assume !(0 == ~E_2~0); 2207322#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2207318#L1364-3 assume !(0 == ~E_4~0); 2207316#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2207314#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2207313#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2207310#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2207309#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2207307#L1394-3 assume !(0 == ~E_10~0); 2207306#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 2207305#L1404-3 assume !(0 == ~E_12~0); 2207304#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 2207303#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2207302#L628-45 assume !(1 == ~m_pc~0); 2207299#L628-47 is_master_triggered_~__retres1~0#1 := 0; 2207298#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2207297#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2207296#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2207295#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2207293#L647-45 assume !(1 == ~t1_pc~0); 2207292#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 2207291#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2207290#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2207289#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2207288#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2207286#L666-45 assume !(1 == ~t2_pc~0); 2207285#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 2207284#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2207283#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2207281#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2207278#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2207276#L685-45 assume !(1 == ~t3_pc~0); 2207274#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 2207272#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2207270#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2207268#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 2207266#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2207264#L704-45 assume !(1 == ~t4_pc~0); 2207262#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 2207260#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2207258#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2207255#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2207253#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2207251#L723-45 assume !(1 == ~t5_pc~0); 2207249#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 2207246#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2207244#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2207242#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 2207240#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2207238#L742-45 assume !(1 == ~t6_pc~0); 2207236#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 2207234#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2207232#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2207230#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2207228#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2207226#L761-45 assume 1 == ~t7_pc~0; 2207223#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2207221#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2207219#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 2207217#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2207214#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2207212#L780-45 assume !(1 == ~t8_pc~0); 2207210#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 2207208#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2207206#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 2207204#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2207202#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2207200#L799-45 assume !(1 == ~t9_pc~0); 2207198#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 2207196#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2207194#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 2207192#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2207189#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2207187#L818-45 assume 1 == ~t10_pc~0; 2207185#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2207186#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2207294#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 2207176#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2207174#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 2207172#L837-45 assume !(1 == ~t11_pc~0); 2207170#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 2207168#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 2207166#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 2207164#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 2207162#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 2207160#L856-45 assume 1 == ~t12_pc~0; 2207157#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 2207155#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 2207153#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 2207149#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 2207147#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 2207145#L875-45 assume !(1 == ~t13_pc~0); 2207143#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 2207140#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 2207138#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 2207136#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 2207134#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2207132#L1427-3 assume !(1 == ~M_E~0); 2206787#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2207129#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2207127#L1437-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2207125#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2207122#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2207120#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2207118#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2207116#L1462-3 assume !(1 == ~T8_E~0); 2207114#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2207112#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2207110#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 2207108#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 2207106#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 2207104#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 2207102#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2207101#L1502-3 assume !(1 == ~E_2~0); 2207097#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2207095#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2207093#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2207092#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2207089#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2207088#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2207087#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2207084#L1542-3 assume !(1 == ~E_10~0); 2207083#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 2207082#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 2207081#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 2207080#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2207072#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2207064#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2207060#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 2207055#L1947 assume !(0 == start_simulation_~tmp~3#1); 2207056#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 2207425#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 2207417#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 2207414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 2207412#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2207410#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2207408#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 2207406#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 1939834#L1928-2 [2023-11-29 03:21:42,439 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:42,440 INFO L85 PathProgramCache]: Analyzing trace with hash 1787790413, now seen corresponding path program 1 times [2023-11-29 03:21:42,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:42,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [564773623] [2023-11-29 03:21:42,440 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:42,440 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:42,454 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:42,523 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:42,523 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:42,524 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [564773623] [2023-11-29 03:21:42,524 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [564773623] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:42,524 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:42,524 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:42,524 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1518022889] [2023-11-29 03:21:42,524 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:42,524 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:21:42,525 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:21:42,525 INFO L85 PathProgramCache]: Analyzing trace with hash -470483731, now seen corresponding path program 1 times [2023-11-29 03:21:42,525 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:21:42,525 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1891058360] [2023-11-29 03:21:42,525 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:21:42,526 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:21:42,540 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:21:42,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:21:42,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:21:42,573 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1891058360] [2023-11-29 03:21:42,573 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1891058360] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:21:42,573 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:21:42,573 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:21:42,573 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1021872537] [2023-11-29 03:21:42,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:21:42,574 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:21:42,574 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:21:42,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:21:42,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:21:42,575 INFO L87 Difference]: Start difference. First operand 541226 states and 754422 transitions. cyclomatic complexity: 213324 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:45,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:21:45,326 INFO L93 Difference]: Finished difference Result 845981 states and 1178383 transitions. [2023-11-29 03:21:45,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 845981 states and 1178383 transitions. [2023-11-29 03:21:49,316 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 841824 [2023-11-29 03:21:51,240 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 845981 states to 845981 states and 1178383 transitions. [2023-11-29 03:21:51,240 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 845981 [2023-11-29 03:21:51,730 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 845981 [2023-11-29 03:21:51,730 INFO L73 IsDeterministic]: Start isDeterministic. Operand 845981 states and 1178383 transitions. [2023-11-29 03:21:52,017 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:21:52,017 INFO L218 hiAutomatonCegarLoop]: Abstraction has 845981 states and 1178383 transitions. [2023-11-29 03:21:52,404 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 845981 states and 1178383 transitions. [2023-11-29 03:21:57,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 845981 to 590500. [2023-11-29 03:21:57,965 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 590500 states, 590500 states have (on average 1.3969974597798476) internal successors, (824927), 590499 states have internal predecessors, (824927), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:21:59,471 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 590500 states to 590500 states and 824927 transitions. [2023-11-29 03:21:59,471 INFO L240 hiAutomatonCegarLoop]: Abstraction has 590500 states and 824927 transitions. [2023-11-29 03:21:59,471 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:21:59,472 INFO L428 stractBuchiCegarLoop]: Abstraction has 590500 states and 824927 transitions. [2023-11-29 03:21:59,472 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-29 03:21:59,472 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 590500 states and 824927 transitions. [2023-11-29 03:22:01,510 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 587648 [2023-11-29 03:22:01,510 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:22:01,510 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:22:01,512 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:22:01,512 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:22:01,512 INFO L748 eck$LassoCheckResult]: Stem: 3326678#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 3326679#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 3327693#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3327694#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3328610#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 3327262#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3327263#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3327336#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3327337#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3327801#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3327802#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3327296#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3327097#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3327098#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3327574#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3327575#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 3327446#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 3327447#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 3327071#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3327072#L1279 assume !(0 == ~M_E~0); 3328452#L1279-2 assume !(0 == ~T1_E~0); 3326699#L1284-1 assume !(0 == ~T2_E~0); 3326700#L1289-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3327443#L1294-1 assume !(0 == ~T4_E~0); 3327444#L1299-1 assume !(0 == ~T5_E~0); 3328604#L1304-1 assume !(0 == ~T6_E~0); 3328605#L1309-1 assume !(0 == ~T7_E~0); 3328613#L1314-1 assume !(0 == ~T8_E~0); 3326623#L1319-1 assume !(0 == ~T9_E~0); 3326624#L1324-1 assume !(0 == ~T10_E~0); 3326797#L1329-1 assume !(0 == ~T11_E~0); 3326798#L1334-1 assume !(0 == ~T12_E~0); 3328591#L1339-1 assume !(0 == ~T13_E~0); 3328592#L1344-1 assume !(0 == ~E_M~0); 3328638#L1349-1 assume !(0 == ~E_1~0); 3328639#L1354-1 assume !(0 == ~E_2~0); 3328113#L1359-1 assume !(0 == ~E_3~0); 3328114#L1364-1 assume !(0 == ~E_4~0); 3326921#L1369-1 assume !(0 == ~E_5~0); 3326922#L1374-1 assume !(0 == ~E_6~0); 3327656#L1379-1 assume !(0 == ~E_7~0); 3327657#L1384-1 assume !(0 == ~E_8~0); 3328699#L1389-1 assume !(0 == ~E_9~0); 3328358#L1394-1 assume !(0 == ~E_10~0); 3328359#L1399-1 assume !(0 == ~E_11~0); 3328501#L1404-1 assume !(0 == ~E_12~0); 3328502#L1409-1 assume !(0 == ~E_13~0); 3328493#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3328494#L628 assume !(1 == ~m_pc~0); 3326920#L628-2 is_master_triggered_~__retres1~0#1 := 0; 3326919#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3327519#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3327520#L1591 assume !(0 != activate_threads_~tmp~1#1); 3328618#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3328619#L647 assume !(1 == ~t1_pc~0); 3327846#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3327847#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3328061#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3328062#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 3328420#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3328421#L666 assume !(1 == ~t2_pc~0); 3328482#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3328483#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3326838#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3326839#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 3327858#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3327859#L685 assume !(1 == ~t3_pc~0); 3328697#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3328531#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3328532#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3327703#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 3327704#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3327146#L704 assume !(1 == ~t4_pc~0); 3327147#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3328696#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3328695#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3328581#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 3328582#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3327698#L723 assume !(1 == ~t5_pc~0); 3327699#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3328102#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3328103#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3327835#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 3327836#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3326904#L742 assume !(1 == ~t6_pc~0); 3326905#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3327059#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3327060#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3326594#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 3326595#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3326981#L761 assume !(1 == ~t7_pc~0); 3326982#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3326855#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3326856#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3327706#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 3327707#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3328694#L780 assume !(1 == ~t8_pc~0); 3328413#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3328414#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3328486#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3328487#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 3327788#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3327789#L799 assume !(1 == ~t9_pc~0); 3327118#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3326618#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3326619#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3328692#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 3328690#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3328689#L818 assume !(1 == ~t10_pc~0); 3328688#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3328686#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3328684#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3328682#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 3328090#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3327868#L837 assume !(1 == ~t11_pc~0); 3327690#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 3327691#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3328426#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3327781#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 3327782#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3327507#L856 assume !(1 == ~t12_pc~0); 3327508#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 3328240#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3328241#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3328670#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 3328669#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 3328668#L875 assume !(1 == ~t13_pc~0); 3328667#L875-2 is_transmit13_triggered_~__retres1~13#1 := 0; 3328666#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 3328665#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3328664#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 3328663#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3328662#L1427 assume !(1 == ~M_E~0); 3328661#L1427-2 assume !(1 == ~T1_E~0); 3328660#L1432-1 assume !(1 == ~T2_E~0); 3328659#L1437-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3328121#L1442-1 assume !(1 == ~T4_E~0); 3328122#L1447-1 assume !(1 == ~T5_E~0); 3327949#L1452-1 assume !(1 == ~T6_E~0); 3326540#L1457-1 assume !(1 == ~T7_E~0); 3326541#L1462-1 assume !(1 == ~T8_E~0); 3328142#L1467-1 assume !(1 == ~T9_E~0); 3328170#L1472-1 assume !(1 == ~T10_E~0); 3328171#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3327888#L1482-1 assume !(1 == ~T12_E~0); 3327889#L1487-1 assume !(1 == ~T13_E~0); 3326868#L1492-1 assume !(1 == ~E_M~0); 3326869#L1497-1 assume !(1 == ~E_1~0); 3327241#L1502-1 assume !(1 == ~E_2~0); 3327242#L1507-1 assume !(1 == ~E_3~0); 3326747#L1512-1 assume !(1 == ~E_4~0); 3326748#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 3328263#L1522-1 assume !(1 == ~E_6~0); 3327493#L1527-1 assume !(1 == ~E_7~0); 3327494#L1532-1 assume !(1 == ~E_8~0); 3328567#L1537-1 assume !(1 == ~E_9~0); 3327725#L1542-1 assume !(1 == ~E_10~0); 3327526#L1547-1 assume !(1 == ~E_11~0); 3327527#L1552-1 assume !(1 == ~E_12~0); 3326445#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 3326446#L1562-1 assume { :end_inline_reset_delta_events } true; 3327049#L1928-2 [2023-11-29 03:22:01,513 INFO L750 eck$LassoCheckResult]: Loop: 3327049#L1928-2 assume !false; 3431255#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3431249#L1254-1 assume !false; 3431247#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3431229#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3431220#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3431218#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 3431215#L1067 assume !(0 != eval_~tmp~0#1); 3431213#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3431211#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3431209#L1279-3 assume !(0 == ~M_E~0); 3431207#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3431205#L1284-3 assume !(0 == ~T2_E~0); 3431202#L1289-3 assume !(0 == ~T3_E~0); 3431201#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3431199#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3431196#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3431194#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3431192#L1314-3 assume !(0 == ~T8_E~0); 3431190#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3431188#L1324-3 assume !(0 == ~T10_E~0); 3431186#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 3431184#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 3431182#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 3431180#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 3431178#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3431176#L1354-3 assume !(0 == ~E_2~0); 3431174#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3431172#L1364-3 assume !(0 == ~E_4~0); 3431170#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3431168#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3431166#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3431164#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3431162#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3431160#L1394-3 assume !(0 == ~E_10~0); 3431158#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 3431156#L1404-3 assume !(0 == ~E_12~0); 3431154#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 3431152#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3431150#L628-45 assume 1 == ~m_pc~0; 3431148#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 3431145#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3431144#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3431143#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3431142#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3431141#L647-45 assume !(1 == ~t1_pc~0); 3431140#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 3431139#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3431138#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3431137#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3431136#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3431119#L666-45 assume !(1 == ~t2_pc~0); 3431117#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 3431114#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3431112#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3431110#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3431108#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3431106#L685-45 assume !(1 == ~t3_pc~0); 3431104#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 3431101#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3431099#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3431097#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 3431095#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3431093#L704-45 assume !(1 == ~t4_pc~0); 3431091#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 3431088#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3431086#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3431084#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3431083#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3431082#L723-45 assume 1 == ~t5_pc~0; 3431079#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3431076#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3431074#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3431071#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 3431068#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3431066#L742-45 assume !(1 == ~t6_pc~0); 3431064#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 3431062#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3431060#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3431058#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3431055#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3431053#L761-45 assume 1 == ~t7_pc~0; 3431050#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3431048#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3431046#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 3431044#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3431042#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3431040#L780-45 assume !(1 == ~t8_pc~0); 3431038#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 3431036#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3431034#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 3431032#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3431031#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3431029#L799-45 assume !(1 == ~t9_pc~0); 3431028#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 3431027#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3431026#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 3431024#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 3431023#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3431022#L818-45 assume !(1 == ~t10_pc~0); 3431020#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 3431018#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3431016#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 3431015#L1671-45 assume !(0 != activate_threads_~tmp___9~0#1); 3431013#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 3431012#L837-45 assume !(1 == ~t11_pc~0); 3431011#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 3431010#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 3431008#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 3431007#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 3431006#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 3431005#L856-45 assume !(1 == ~t12_pc~0); 3431004#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 3431002#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 3431001#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 3431000#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 3430999#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 3430998#L875-45 assume !(1 == ~t13_pc~0); 3430997#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 3430996#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 3430995#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 3430994#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 3430993#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3430992#L1427-3 assume !(1 == ~M_E~0); 3347212#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3430991#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3430990#L1437-3 assume !(1 == ~T3_E~0); 3430988#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3430987#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3430986#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3430985#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3430984#L1462-3 assume !(1 == ~T8_E~0); 3430983#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3430982#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3430981#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 3430980#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 3430979#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 3430601#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 3430600#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3430599#L1502-3 assume !(1 == ~E_2~0); 3430598#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3430597#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3430596#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3430595#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3430594#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3430593#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3430592#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3430591#L1542-3 assume !(1 == ~E_10~0); 3430590#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 3430589#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 3430588#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 3430587#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3430579#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3430558#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3430556#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 3347714#L1947 assume !(0 == start_simulation_~tmp~3#1); 3347715#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 3431278#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 3431270#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 3431268#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 3431266#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3431264#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3431260#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 3431258#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 3327049#L1928-2 [2023-11-29 03:22:01,513 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:22:01,513 INFO L85 PathProgramCache]: Analyzing trace with hash -719307061, now seen corresponding path program 1 times [2023-11-29 03:22:01,513 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:22:01,513 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1121489619] [2023-11-29 03:22:01,514 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:22:01,514 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:22:01,523 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:22:01,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:22:01,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:22:01,573 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1121489619] [2023-11-29 03:22:01,574 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1121489619] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:22:01,574 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:22:01,574 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:22:01,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [182391745] [2023-11-29 03:22:01,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:22:01,575 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:22:01,575 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:22:01,575 INFO L85 PathProgramCache]: Analyzing trace with hash -376255889, now seen corresponding path program 1 times [2023-11-29 03:22:01,575 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:22:01,575 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [782475098] [2023-11-29 03:22:01,576 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:22:01,576 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:22:01,590 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:22:01,648 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:22:01,649 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:22:01,649 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [782475098] [2023-11-29 03:22:01,649 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [782475098] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:22:01,649 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:22:01,649 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:22:01,649 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [772459951] [2023-11-29 03:22:01,650 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:22:01,650 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:22:01,650 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:22:01,651 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:22:01,651 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:22:01,651 INFO L87 Difference]: Start difference. First operand 590500 states and 824927 transitions. cyclomatic complexity: 234555 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:22:04,487 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:22:04,487 INFO L93 Difference]: Finished difference Result 796682 states and 1106484 transitions. [2023-11-29 03:22:04,487 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 796682 states and 1106484 transitions. [2023-11-29 03:22:07,954 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 792672 [2023-11-29 03:22:09,838 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 796682 states to 796682 states and 1106484 transitions. [2023-11-29 03:22:09,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 796682 [2023-11-29 03:22:10,023 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 796682 [2023-11-29 03:22:10,023 INFO L73 IsDeterministic]: Start isDeterministic. Operand 796682 states and 1106484 transitions. [2023-11-29 03:22:10,244 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:22:10,244 INFO L218 hiAutomatonCegarLoop]: Abstraction has 796682 states and 1106484 transitions. [2023-11-29 03:22:10,594 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 796682 states and 1106484 transitions. [2023-11-29 03:22:14,691 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 796682 to 541226. [2023-11-29 03:22:14,972 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 541226 states, 541226 states have (on average 1.3917808826626954) internal successors, (753268), 541225 states have internal predecessors, (753268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:22:16,867 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 541226 states to 541226 states and 753268 transitions. [2023-11-29 03:22:16,867 INFO L240 hiAutomatonCegarLoop]: Abstraction has 541226 states and 753268 transitions. [2023-11-29 03:22:16,868 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:22:16,868 INFO L428 stractBuchiCegarLoop]: Abstraction has 541226 states and 753268 transitions. [2023-11-29 03:22:16,868 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-29 03:22:16,868 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 541226 states and 753268 transitions. [2023-11-29 03:22:18,247 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 538496 [2023-11-29 03:22:18,247 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:22:18,247 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:22:18,249 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:22:18,249 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:22:18,249 INFO L748 eck$LassoCheckResult]: Stem: 4713870#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 4713871#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 4714879#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4714880#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4715777#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 4714450#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4714451#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4714520#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4714521#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4714987#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4714988#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4714486#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4714287#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4714288#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4714759#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4714760#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 4714639#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 4714640#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 4714261#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4714262#L1279 assume !(0 == ~M_E~0); 4715636#L1279-2 assume !(0 == ~T1_E~0); 4713891#L1284-1 assume !(0 == ~T2_E~0); 4713892#L1289-1 assume !(0 == ~T3_E~0); 4714628#L1294-1 assume !(0 == ~T4_E~0); 4714629#L1299-1 assume !(0 == ~T5_E~0); 4714641#L1304-1 assume !(0 == ~T6_E~0); 4715772#L1309-1 assume !(0 == ~T7_E~0); 4715778#L1314-1 assume !(0 == ~T8_E~0); 4713817#L1319-1 assume !(0 == ~T9_E~0); 4713818#L1324-1 assume !(0 == ~T10_E~0); 4713989#L1329-1 assume !(0 == ~T11_E~0); 4713990#L1334-1 assume !(0 == ~T12_E~0); 4715511#L1339-1 assume !(0 == ~T13_E~0); 4715626#L1344-1 assume !(0 == ~E_M~0); 4715627#L1349-1 assume !(0 == ~E_1~0); 4714834#L1354-1 assume !(0 == ~E_2~0); 4714835#L1359-1 assume !(0 == ~E_3~0); 4715288#L1364-1 assume !(0 == ~E_4~0); 4714109#L1369-1 assume !(0 == ~E_5~0); 4714110#L1374-1 assume !(0 == ~E_6~0); 4714843#L1379-1 assume !(0 == ~E_7~0); 4714844#L1384-1 assume !(0 == ~E_8~0); 4714926#L1389-1 assume !(0 == ~E_9~0); 4715540#L1394-1 assume !(0 == ~E_10~0); 4715541#L1399-1 assume !(0 == ~E_11~0); 4715681#L1404-1 assume !(0 == ~E_12~0); 4714205#L1409-1 assume !(0 == ~E_13~0); 4714206#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4715672#L628 assume !(1 == ~m_pc~0); 4714108#L628-2 is_master_triggered_~__retres1~0#1 := 0; 4714107#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4714705#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4714706#L1591 assume !(0 != activate_threads_~tmp~1#1); 4715691#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4714683#L647 assume !(1 == ~t1_pc~0); 4714684#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4714738#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4714739#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4715244#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 4715606#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4715607#L666 assume !(1 == ~t2_pc~0); 4713890#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4714052#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4714031#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4714032#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 4715042#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4715043#L685 assume !(1 == ~t3_pc~0); 4715218#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4715219#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4715225#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4714888#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 4714889#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4714338#L704 assume !(1 == ~t4_pc~0); 4714339#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4714900#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4713682#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4713683#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 4714736#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4714737#L723 assume !(1 == ~t5_pc~0); 4714884#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4715120#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4715279#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4715022#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 4715023#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4714093#L742 assume !(1 == ~t6_pc~0); 4714094#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4714250#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4714020#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4713788#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 4713789#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4714169#L761 assume !(1 == ~t7_pc~0); 4714170#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4714048#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4714049#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4714890#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 4714891#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4713810#L780 assume !(1 == ~t8_pc~0); 4713811#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4714083#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4714084#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4714849#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 4714850#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4714975#L799 assume !(1 == ~t9_pc~0); 4714308#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4713808#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4713809#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4714078#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 4715196#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4714999#L818 assume !(1 == ~t10_pc~0); 4713598#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4713599#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4715078#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4715002#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 4715003#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4715051#L837 assume !(1 == ~t11_pc~0); 4714876#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 4714877#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4715611#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4714965#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 4714966#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4714695#L856 assume !(1 == ~t12_pc~0); 4714696#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 4715416#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4713616#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4713617#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 4715386#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4715639#L875 assume !(1 == ~t13_pc~0); 4715619#L875-2 is_transmit13_triggered_~__retres1~13#1 := 0; 4714251#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4714252#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4714186#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 4714187#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4715075#L1427 assume !(1 == ~M_E~0); 4715061#L1427-2 assume !(1 == ~T1_E~0); 4714156#L1432-1 assume !(1 == ~T2_E~0); 4714157#L1437-1 assume !(1 == ~T3_E~0); 4715293#L1442-1 assume !(1 == ~T4_E~0); 4715294#L1447-1 assume !(1 == ~T5_E~0); 4715133#L1452-1 assume !(1 == ~T6_E~0); 4713733#L1457-1 assume !(1 == ~T7_E~0); 4713734#L1462-1 assume !(1 == ~T8_E~0); 4715320#L1467-1 assume !(1 == ~T9_E~0); 4715345#L1472-1 assume !(1 == ~T10_E~0); 4715346#L1477-1 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4715071#L1482-1 assume !(1 == ~T12_E~0); 4715072#L1487-1 assume !(1 == ~T13_E~0); 4714058#L1492-1 assume !(1 == ~E_M~0); 4714059#L1497-1 assume !(1 == ~E_1~0); 4714432#L1502-1 assume !(1 == ~E_2~0); 4714433#L1507-1 assume !(1 == ~E_3~0); 4713939#L1512-1 assume !(1 == ~E_4~0); 4713940#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4715441#L1522-1 assume !(1 == ~E_6~0); 4714681#L1527-1 assume !(1 == ~E_7~0); 4714682#L1532-1 assume !(1 == ~E_8~0); 4715739#L1537-1 assume !(1 == ~E_9~0); 4714912#L1542-1 assume !(1 == ~E_10~0); 4714713#L1547-1 assume !(1 == ~E_11~0); 4714714#L1552-1 assume !(1 == ~E_12~0); 4713640#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 4713641#L1562-1 assume { :end_inline_reset_delta_events } true; 4714240#L1928-2 [2023-11-29 03:22:18,250 INFO L750 eck$LassoCheckResult]: Loop: 4714240#L1928-2 assume !false; 4772328#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4772320#L1254-1 assume !false; 4772318#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4772253#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4772242#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4772238#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 4772233#L1067 assume !(0 != eval_~tmp~0#1); 4772234#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4777812#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4777806#L1279-3 assume !(0 == ~M_E~0); 4777799#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4777790#L1284-3 assume !(0 == ~T2_E~0); 4777784#L1289-3 assume !(0 == ~T3_E~0); 4777778#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4777772#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4777766#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4777758#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4777749#L1314-3 assume !(0 == ~T8_E~0); 4777742#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4777734#L1324-3 assume !(0 == ~T10_E~0); 4777727#L1329-3 assume 0 == ~T11_E~0;~T11_E~0 := 1; 4777720#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 4777713#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 4777704#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 4777695#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4777686#L1354-3 assume !(0 == ~E_2~0); 4777333#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4777237#L1364-3 assume !(0 == ~E_4~0); 4777230#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4777227#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4777224#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4777222#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4777219#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4777214#L1394-3 assume !(0 == ~E_10~0); 4777210#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 4777206#L1404-3 assume !(0 == ~E_12~0); 4777202#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 4777198#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4777194#L628-45 assume !(1 == ~m_pc~0); 4777189#L628-47 is_master_triggered_~__retres1~0#1 := 0; 4777185#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4777181#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4777177#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4777173#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4777168#L647-45 assume !(1 == ~t1_pc~0); 4777164#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 4777160#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4777156#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4777152#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4777148#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4777143#L666-45 assume !(1 == ~t2_pc~0); 4777139#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 4777135#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4777131#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4777127#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4777123#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4777119#L685-45 assume !(1 == ~t3_pc~0); 4777115#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 4777112#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4772104#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4772101#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 4772099#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4772097#L704-45 assume !(1 == ~t4_pc~0); 4772095#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 4772093#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4772091#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4772088#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4772086#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4772084#L723-45 assume 1 == ~t5_pc~0; 4772081#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4772079#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4772077#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4772074#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 4772072#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4772070#L742-45 assume !(1 == ~t6_pc~0); 4772068#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 4772066#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4772064#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4772062#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4772060#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4772058#L761-45 assume !(1 == ~t7_pc~0); 4772056#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 4772053#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4772051#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 4772049#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4772047#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4772045#L780-45 assume !(1 == ~t8_pc~0); 4772043#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 4772041#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4772037#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 4772035#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4772033#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4772031#L799-45 assume !(1 == ~t9_pc~0); 4772028#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 4772026#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4772024#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 4772022#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4772020#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4772018#L818-45 assume !(1 == ~t10_pc~0); 4772014#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 4772012#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4772010#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 4772007#L1671-45 assume !(0 != activate_threads_~tmp___9~0#1); 4772004#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 4772002#L837-45 assume !(1 == ~t11_pc~0); 4772000#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 4771998#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 4771996#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 4771994#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 4771992#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 4771990#L856-45 assume 1 == ~t12_pc~0; 4771987#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 4771985#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 4771983#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 4771982#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 4771980#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 4771978#L875-45 assume !(1 == ~t13_pc~0); 4771976#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 4771974#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 4771972#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 4771970#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 4771968#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4771966#L1427-3 assume !(1 == ~M_E~0); 4730665#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4771963#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4771961#L1437-3 assume !(1 == ~T3_E~0); 4771959#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4771957#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4771955#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4771953#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4771951#L1462-3 assume !(1 == ~T8_E~0); 4771949#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4771947#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4771945#L1477-3 assume 1 == ~T11_E~0;~T11_E~0 := 2; 4771943#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 4771941#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 4771939#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 4771937#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4771935#L1502-3 assume !(1 == ~E_2~0); 4771933#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4771931#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4771929#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4771928#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4771927#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4771926#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4771925#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4771924#L1542-3 assume !(1 == ~E_10~0); 4771923#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 4771922#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 4771921#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 4771876#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4771268#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4771260#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4771256#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 4730860#L1947 assume !(0 == start_simulation_~tmp~3#1); 4730861#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 4772382#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 4772371#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 4772365#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 4772360#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4772353#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4772348#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 4772342#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 4714240#L1928-2 [2023-11-29 03:22:18,250 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:22:18,250 INFO L85 PathProgramCache]: Analyzing trace with hash 1849830027, now seen corresponding path program 1 times [2023-11-29 03:22:18,250 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:22:18,250 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [446142590] [2023-11-29 03:22:18,251 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:22:18,251 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:22:18,263 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:22:18,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:22:18,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:22:18,327 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [446142590] [2023-11-29 03:22:18,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [446142590] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:22:18,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:22:18,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 03:22:18,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [656681869] [2023-11-29 03:22:18,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:22:18,328 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:22:18,328 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:22:18,329 INFO L85 PathProgramCache]: Analyzing trace with hash 1012884080, now seen corresponding path program 1 times [2023-11-29 03:22:18,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:22:18,329 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [325611308] [2023-11-29 03:22:18,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:22:18,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:22:18,347 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:22:18,406 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:22:18,407 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:22:18,407 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [325611308] [2023-11-29 03:22:18,407 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [325611308] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:22:18,407 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:22:18,407 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:22:18,407 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [854255110] [2023-11-29 03:22:18,408 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:22:18,408 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:22:18,408 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:22:18,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:22:18,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:22:18,409 INFO L87 Difference]: Start difference. First operand 541226 states and 753268 transitions. cyclomatic complexity: 212170 Second operand has 3 states, 3 states have (on average 53.666666666666664) internal successors, (161), 2 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:22:20,921 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:22:20,921 INFO L93 Difference]: Finished difference Result 541226 states and 752114 transitions. [2023-11-29 03:22:20,922 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 541226 states and 752114 transitions. [2023-11-29 03:22:23,244 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 538496 [2023-11-29 03:22:24,443 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 541226 states to 541226 states and 752114 transitions. [2023-11-29 03:22:24,443 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 541226 [2023-11-29 03:22:24,684 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 541226 [2023-11-29 03:22:24,684 INFO L73 IsDeterministic]: Start isDeterministic. Operand 541226 states and 752114 transitions. [2023-11-29 03:22:25,201 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:22:25,201 INFO L218 hiAutomatonCegarLoop]: Abstraction has 541226 states and 752114 transitions. [2023-11-29 03:22:25,442 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 541226 states and 752114 transitions. [2023-11-29 03:22:29,165 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 541226 to 541226. [2023-11-29 03:22:29,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 541226 states, 541226 states have (on average 1.3896486865006485) internal successors, (752114), 541225 states have internal predecessors, (752114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:22:30,524 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 541226 states to 541226 states and 752114 transitions. [2023-11-29 03:22:30,524 INFO L240 hiAutomatonCegarLoop]: Abstraction has 541226 states and 752114 transitions. [2023-11-29 03:22:30,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:22:30,525 INFO L428 stractBuchiCegarLoop]: Abstraction has 541226 states and 752114 transitions. [2023-11-29 03:22:30,525 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-29 03:22:30,525 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 541226 states and 752114 transitions. [2023-11-29 03:22:32,204 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 538496 [2023-11-29 03:22:32,204 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:22:32,204 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:22:32,205 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:22:32,205 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:22:32,206 INFO L748 eck$LassoCheckResult]: Stem: 5796331#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 5796332#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 5797357#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5797358#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5798262#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 5796916#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5796917#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5796988#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5796989#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5797468#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5797469#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5796950#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5796748#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5796749#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5797236#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 5797237#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 5797107#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 5797108#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 5796724#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5796725#L1279 assume !(0 == ~M_E~0); 5798119#L1279-2 assume !(0 == ~T1_E~0); 5796352#L1284-1 assume !(0 == ~T2_E~0); 5796353#L1289-1 assume !(0 == ~T3_E~0); 5797102#L1294-1 assume !(0 == ~T4_E~0); 5797103#L1299-1 assume !(0 == ~T5_E~0); 5797115#L1304-1 assume !(0 == ~T6_E~0); 5798259#L1309-1 assume !(0 == ~T7_E~0); 5798263#L1314-1 assume !(0 == ~T8_E~0); 5796277#L1319-1 assume !(0 == ~T9_E~0); 5796278#L1324-1 assume !(0 == ~T10_E~0); 5796451#L1329-1 assume !(0 == ~T11_E~0); 5796452#L1334-1 assume !(0 == ~T12_E~0); 5797993#L1339-1 assume !(0 == ~T13_E~0); 5798107#L1344-1 assume !(0 == ~E_M~0); 5798108#L1349-1 assume !(0 == ~E_1~0); 5797310#L1354-1 assume !(0 == ~E_2~0); 5797311#L1359-1 assume !(0 == ~E_3~0); 5797767#L1364-1 assume !(0 == ~E_4~0); 5796573#L1369-1 assume !(0 == ~E_5~0); 5796574#L1374-1 assume !(0 == ~E_6~0); 5797318#L1379-1 assume !(0 == ~E_7~0); 5797319#L1384-1 assume !(0 == ~E_8~0); 5797406#L1389-1 assume !(0 == ~E_9~0); 5798023#L1394-1 assume !(0 == ~E_10~0); 5798024#L1399-1 assume !(0 == ~E_11~0); 5798173#L1404-1 assume !(0 == ~E_12~0); 5796668#L1409-1 assume !(0 == ~E_13~0); 5796669#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5798164#L628 assume !(1 == ~m_pc~0); 5796572#L628-2 is_master_triggered_~__retres1~0#1 := 0; 5796571#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5797179#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5797180#L1591 assume !(0 != activate_threads_~tmp~1#1); 5798182#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5797156#L647 assume !(1 == ~t1_pc~0); 5797157#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5797215#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5797216#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5797725#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 5798085#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5798086#L666 assume !(1 == ~t2_pc~0); 5796351#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5796512#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5796491#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5796492#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 5797527#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5797528#L685 assume !(1 == ~t3_pc~0); 5797697#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5797698#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5797705#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5797368#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 5797369#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5796800#L704 assume !(1 == ~t4_pc~0); 5796801#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5797381#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5796143#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5796144#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 5797213#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5797214#L723 assume !(1 == ~t5_pc~0); 5797364#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5797598#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5797759#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5797501#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 5797502#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5796556#L742 assume !(1 == ~t6_pc~0); 5796557#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5796713#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5796482#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5796248#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 5796249#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5796633#L761 assume !(1 == ~t7_pc~0); 5796634#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5796508#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5796509#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5797371#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 5797372#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5796270#L780 assume !(1 == ~t8_pc~0); 5796271#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5796547#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5796548#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5797325#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 5797326#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5797456#L799 assume !(1 == ~t9_pc~0); 5796770#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5796272#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5796273#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5796542#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 5797673#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5797483#L818 assume !(1 == ~t10_pc~0); 5796059#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5796060#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5797558#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5797486#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 5797487#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5797535#L837 assume !(1 == ~t11_pc~0); 5797354#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 5797355#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5798090#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5797449#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 5797450#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5797166#L856 assume !(1 == ~t12_pc~0); 5797167#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 5797888#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5796077#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5796078#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 5797855#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5798124#L875 assume !(1 == ~t13_pc~0); 5798099#L875-2 is_transmit13_triggered_~__retres1~13#1 := 0; 5796714#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5796715#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5796649#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 5796650#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5797557#L1427 assume !(1 == ~M_E~0); 5797541#L1427-2 assume !(1 == ~T1_E~0); 5796620#L1432-1 assume !(1 == ~T2_E~0); 5796621#L1437-1 assume !(1 == ~T3_E~0); 5797772#L1442-1 assume !(1 == ~T4_E~0); 5797773#L1447-1 assume !(1 == ~T5_E~0); 5797610#L1452-1 assume !(1 == ~T6_E~0); 5796194#L1457-1 assume !(1 == ~T7_E~0); 5796195#L1462-1 assume !(1 == ~T8_E~0); 5797794#L1467-1 assume !(1 == ~T9_E~0); 5797820#L1472-1 assume !(1 == ~T10_E~0); 5797821#L1477-1 assume !(1 == ~T11_E~0); 5797553#L1482-1 assume !(1 == ~T12_E~0); 5797554#L1487-1 assume !(1 == ~T13_E~0); 5796520#L1492-1 assume !(1 == ~E_M~0); 5796521#L1497-1 assume !(1 == ~E_1~0); 5796896#L1502-1 assume !(1 == ~E_2~0); 5796897#L1507-1 assume !(1 == ~E_3~0); 5796401#L1512-1 assume !(1 == ~E_4~0); 5796402#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 5797915#L1522-1 assume !(1 == ~E_6~0); 5797153#L1527-1 assume !(1 == ~E_7~0); 5797154#L1532-1 assume !(1 == ~E_8~0); 5798230#L1537-1 assume !(1 == ~E_9~0); 5797389#L1542-1 assume !(1 == ~E_10~0); 5797186#L1547-1 assume !(1 == ~E_11~0); 5797187#L1552-1 assume !(1 == ~E_12~0); 5796099#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 5796100#L1562-1 assume { :end_inline_reset_delta_events } true; 5796703#L1928-2 [2023-11-29 03:22:32,206 INFO L750 eck$LassoCheckResult]: Loop: 5796703#L1928-2 assume !false; 5974604#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5974599#L1254-1 assume !false; 5974597#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5974581#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 5974573#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5974570#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 5974566#L1067 assume !(0 != eval_~tmp~0#1); 5974562#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5974558#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5974554#L1279-3 assume !(0 == ~M_E~0); 5974550#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5974546#L1284-3 assume !(0 == ~T2_E~0); 5974542#L1289-3 assume !(0 == ~T3_E~0); 5974538#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5974537#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5974536#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5974535#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5974534#L1314-3 assume !(0 == ~T8_E~0); 5974533#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5974531#L1324-3 assume !(0 == ~T10_E~0); 5974530#L1329-3 assume !(0 == ~T11_E~0); 5974529#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 5974527#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 5974526#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 5974525#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5974524#L1354-3 assume !(0 == ~E_2~0); 5974523#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5974522#L1364-3 assume !(0 == ~E_4~0); 5974521#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5974520#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5974519#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5974518#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5974517#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 5974516#L1394-3 assume !(0 == ~E_10~0); 5974514#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 5974512#L1404-3 assume !(0 == ~E_12~0); 5974510#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 5974507#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5974505#L628-45 assume 1 == ~m_pc~0; 5974503#L629-15 assume 1 == ~E_M~0;is_master_triggered_~__retres1~0#1 := 1; 5974500#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5974498#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5974496#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5974494#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5974492#L647-45 assume !(1 == ~t1_pc~0); 5974490#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 5974488#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5974486#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5974483#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5974481#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5974477#L666-45 assume !(1 == ~t2_pc~0); 5974475#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 5974473#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5974471#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5974469#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5974467#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5974465#L685-45 assume !(1 == ~t3_pc~0); 5974463#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 5974461#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5974459#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5974457#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 5974455#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5974453#L704-45 assume !(1 == ~t4_pc~0); 5974451#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 5974449#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5974447#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5974444#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5974442#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5974440#L723-45 assume !(1 == ~t5_pc~0); 5974438#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 5974435#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5974433#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5974431#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 5974429#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5974427#L742-45 assume !(1 == ~t6_pc~0); 5974425#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 5974423#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5974421#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5974418#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5974416#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5974414#L761-45 assume 1 == ~t7_pc~0; 5974411#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5974409#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5974407#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 5974404#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5974402#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5974400#L780-45 assume !(1 == ~t8_pc~0); 5974398#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 5974396#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5974394#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 5974392#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5974390#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5974388#L799-45 assume !(1 == ~t9_pc~0); 5974386#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 5974384#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5974383#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 5974379#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 5974377#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5974375#L818-45 assume !(1 == ~t10_pc~0); 5974371#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 5974368#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5974366#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 5974364#L1671-45 assume !(0 != activate_threads_~tmp___9~0#1); 5974361#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 5974359#L837-45 assume !(1 == ~t11_pc~0); 5974357#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 5974355#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 5974353#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 5974351#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 5974348#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 5974346#L856-45 assume !(1 == ~t12_pc~0); 5974344#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 5974341#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 5974339#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 5974337#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 5974335#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 5974333#L875-45 assume !(1 == ~t13_pc~0); 5974331#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 5974329#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 5974327#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 5974326#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 5974325#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5973785#L1427-3 assume !(1 == ~M_E~0); 5973783#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5973781#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5973779#L1437-3 assume !(1 == ~T3_E~0); 5973777#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5973775#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5973772#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5973770#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5973768#L1462-3 assume !(1 == ~T8_E~0); 5973766#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5973764#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5973762#L1477-3 assume !(1 == ~T11_E~0); 5973759#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 5973757#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 5973755#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 5973751#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5973749#L1502-3 assume !(1 == ~E_2~0); 5973747#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5973746#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5973743#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5973739#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5973735#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5973731#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5973727#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 5973723#L1542-3 assume !(1 == ~E_10~0); 5973722#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 5973721#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 5973720#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 5973719#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5973711#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 5973704#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5973703#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 5973701#L1947 assume !(0 == start_simulation_~tmp~3#1); 5973702#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 5974626#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 5974618#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 5974616#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 5974614#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5974612#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5974610#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 5974608#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 5796703#L1928-2 [2023-11-29 03:22:32,206 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:22:32,206 INFO L85 PathProgramCache]: Analyzing trace with hash -144314679, now seen corresponding path program 1 times [2023-11-29 03:22:32,207 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:22:32,207 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [935905813] [2023-11-29 03:22:32,207 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:22:32,207 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:22:32,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:22:32,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:22:32,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:22:32,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [935905813] [2023-11-29 03:22:32,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [935905813] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:22:32,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:22:32,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:22:32,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [804350045] [2023-11-29 03:22:32,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:22:32,274 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:22:32,274 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:22:32,274 INFO L85 PathProgramCache]: Analyzing trace with hash -54145616, now seen corresponding path program 1 times [2023-11-29 03:22:32,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:22:32,274 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1173459781] [2023-11-29 03:22:32,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:22:32,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:22:32,288 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:22:32,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:22:32,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:22:32,348 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1173459781] [2023-11-29 03:22:32,348 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1173459781] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:22:32,348 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:22:32,348 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:22:32,349 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [318369086] [2023-11-29 03:22:32,349 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:22:32,349 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:22:32,349 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:22:32,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:22:32,350 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:22:32,350 INFO L87 Difference]: Start difference. First operand 541226 states and 752114 transitions. cyclomatic complexity: 211016 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:22:35,494 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:22:35,494 INFO L93 Difference]: Finished difference Result 848364 states and 1171623 transitions. [2023-11-29 03:22:35,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 848364 states and 1171623 transitions. [2023-11-29 03:22:39,707 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 844048 [2023-11-29 03:22:41,954 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 848364 states to 848364 states and 1171623 transitions. [2023-11-29 03:22:41,954 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 848364 [2023-11-29 03:22:42,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 848364 [2023-11-29 03:22:42,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 848364 states and 1171623 transitions. [2023-11-29 03:22:42,543 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:22:42,543 INFO L218 hiAutomatonCegarLoop]: Abstraction has 848364 states and 1171623 transitions. [2023-11-29 03:22:43,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 848364 states and 1171623 transitions. [2023-11-29 03:22:47,825 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 848364 to 590500. [2023-11-29 03:22:48,090 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 590500 states, 590500 states have (on average 1.3852819644369179) internal successors, (818009), 590499 states have internal predecessors, (818009), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:22:49,871 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 590500 states to 590500 states and 818009 transitions. [2023-11-29 03:22:49,871 INFO L240 hiAutomatonCegarLoop]: Abstraction has 590500 states and 818009 transitions. [2023-11-29 03:22:49,871 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:22:49,872 INFO L428 stractBuchiCegarLoop]: Abstraction has 590500 states and 818009 transitions. [2023-11-29 03:22:49,872 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-29 03:22:49,872 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 590500 states and 818009 transitions. [2023-11-29 03:22:51,371 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 587648 [2023-11-29 03:22:51,371 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:22:51,371 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:22:51,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:22:51,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:22:51,373 INFO L748 eck$LassoCheckResult]: Stem: 7185935#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 7185936#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 7186977#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7186978#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7187932#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 7186523#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7186524#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7186600#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7186601#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7187086#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7187087#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7186562#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7186360#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7186361#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7186847#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 7186848#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 7186719#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 7186720#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 7186336#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7186337#L1279 assume !(0 == ~M_E~0); 7187769#L1279-2 assume !(0 == ~T1_E~0); 7185956#L1284-1 assume !(0 == ~T2_E~0); 7185957#L1289-1 assume !(0 == ~T3_E~0); 7186716#L1294-1 assume !(0 == ~T4_E~0); 7186717#L1299-1 assume !(0 == ~T5_E~0); 7186728#L1304-1 assume !(0 == ~T6_E~0); 7187928#L1309-1 assume !(0 == ~T7_E~0); 7187937#L1314-1 assume !(0 == ~T8_E~0); 7185878#L1319-1 assume !(0 == ~T9_E~0); 7185879#L1324-1 assume !(0 == ~T10_E~0); 7186058#L1329-1 assume !(0 == ~T11_E~0); 7186059#L1334-1 assume !(0 == ~T12_E~0); 7187640#L1339-1 assume !(0 == ~T13_E~0); 7187753#L1344-1 assume !(0 == ~E_M~0); 7187754#L1349-1 assume !(0 == ~E_1~0); 7186929#L1354-1 assume !(0 == ~E_2~0); 7186930#L1359-1 assume !(0 == ~E_3~0); 7187401#L1364-1 assume !(0 == ~E_4~0); 7186183#L1369-1 assume 0 == ~E_5~0;~E_5~0 := 1; 7186184#L1374-1 assume !(0 == ~E_6~0); 7186937#L1379-1 assume !(0 == ~E_7~0); 7186938#L1384-1 assume !(0 == ~E_8~0); 7188080#L1389-1 assume !(0 == ~E_9~0); 7187667#L1394-1 assume !(0 == ~E_10~0); 7187668#L1399-1 assume !(0 == ~E_11~0); 7187818#L1404-1 assume !(0 == ~E_12~0); 7187819#L1409-1 assume !(0 == ~E_13~0); 7187806#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7187807#L628 assume !(1 == ~m_pc~0); 7187969#L628-2 is_master_triggered_~__retres1~0#1 := 0; 7187207#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7187208#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7187829#L1591 assume !(0 != activate_threads_~tmp~1#1); 7187830#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7186771#L647 assume !(1 == ~t1_pc~0); 7186772#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7186825#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7186826#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7187817#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 7187729#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7187730#L666 assume !(1 == ~t2_pc~0); 7187799#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7186120#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7186121#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7187756#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 7187757#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7187929#L685 assume !(1 == ~t3_pc~0); 7187322#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7187323#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7187329#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7187330#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 7187356#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7187357#L704 assume !(1 == ~t4_pc~0); 7187917#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7186999#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7187000#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7188070#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 7188069#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7188068#L723 assume !(1 == ~t5_pc~0); 7188066#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7188065#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7188064#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7188063#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 7188062#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7188061#L742 assume !(1 == ~t6_pc~0); 7188060#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7188059#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7188058#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7188057#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 7188056#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7188055#L761 assume !(1 == ~t7_pc~0); 7188053#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7188052#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7188051#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7188050#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 7188049#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7188048#L780 assume !(1 == ~t8_pc~0); 7188047#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7188046#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7188045#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7188044#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 7188043#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7188042#L799 assume !(1 == ~t9_pc~0); 7188041#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 7188040#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7188039#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7188038#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 7188037#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7188036#L818 assume !(1 == ~t10_pc~0); 7188035#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7188074#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7188071#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7188030#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 7188029#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7188028#L837 assume !(1 == ~t11_pc~0); 7188027#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 7188026#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7188025#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7188024#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 7188023#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7188022#L856 assume !(1 == ~t12_pc~0); 7188021#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 7188019#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7188018#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7188017#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 7188016#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 7188015#L875 assume !(1 == ~t13_pc~0); 7188014#L875-2 is_transmit13_triggered_~__retres1~13#1 := 0; 7188013#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 7188012#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 7188011#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 7188010#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7188009#L1427 assume !(1 == ~M_E~0); 7188008#L1427-2 assume !(1 == ~T1_E~0); 7188007#L1432-1 assume !(1 == ~T2_E~0); 7188006#L1437-1 assume !(1 == ~T3_E~0); 7188005#L1442-1 assume !(1 == ~T4_E~0); 7188004#L1447-1 assume !(1 == ~T5_E~0); 7188003#L1452-1 assume !(1 == ~T6_E~0); 7188002#L1457-1 assume !(1 == ~T7_E~0); 7188001#L1462-1 assume !(1 == ~T8_E~0); 7188000#L1467-1 assume !(1 == ~T9_E~0); 7187999#L1472-1 assume !(1 == ~T10_E~0); 7187998#L1477-1 assume !(1 == ~T11_E~0); 7187997#L1482-1 assume !(1 == ~T12_E~0); 7187996#L1487-1 assume !(1 == ~T13_E~0); 7187995#L1492-1 assume !(1 == ~E_M~0); 7187994#L1497-1 assume !(1 == ~E_1~0); 7187993#L1502-1 assume !(1 == ~E_2~0); 7187992#L1507-1 assume !(1 == ~E_3~0); 7187991#L1512-1 assume !(1 == ~E_4~0); 7187990#L1517-1 assume 1 == ~E_5~0;~E_5~0 := 2; 7187567#L1522-1 assume !(1 == ~E_6~0); 7186767#L1527-1 assume !(1 == ~E_7~0); 7186768#L1532-1 assume !(1 == ~E_8~0); 7187893#L1537-1 assume !(1 == ~E_9~0); 7187007#L1542-1 assume !(1 == ~E_10~0); 7186800#L1547-1 assume !(1 == ~E_11~0); 7186801#L1552-1 assume !(1 == ~E_12~0); 7185701#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 7185702#L1562-1 assume { :end_inline_reset_delta_events } true; 7186315#L1928-2 [2023-11-29 03:22:51,373 INFO L750 eck$LassoCheckResult]: Loop: 7186315#L1928-2 assume !false; 7291468#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7291336#L1254-1 assume !false; 7291465#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 7291441#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 7291432#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 7291430#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 7291427#L1067 assume !(0 != eval_~tmp~0#1); 7291428#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7368396#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7368394#L1279-3 assume !(0 == ~M_E~0); 7368392#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7368390#L1284-3 assume !(0 == ~T2_E~0); 7368388#L1289-3 assume !(0 == ~T3_E~0); 7368387#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7368383#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7368381#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7368379#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7368377#L1314-3 assume !(0 == ~T8_E~0); 7368374#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7368372#L1324-3 assume !(0 == ~T10_E~0); 7368370#L1329-3 assume !(0 == ~T11_E~0); 7368368#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 7368366#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 7368364#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 7368362#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7368360#L1354-3 assume !(0 == ~E_2~0); 7368358#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7368355#L1364-3 assume !(0 == ~E_4~0); 7368352#L1369-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7368353#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7401341#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7401334#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7401333#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 7401323#L1394-3 assume !(0 == ~E_10~0); 7401315#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 7401309#L1404-3 assume !(0 == ~E_12~0); 7401303#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 7401296#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7401289#L628-45 assume !(1 == ~m_pc~0); 7401282#L628-47 is_master_triggered_~__retres1~0#1 := 0; 7401275#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7401267#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7401258#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7401250#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7401243#L647-45 assume !(1 == ~t1_pc~0); 7401237#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 7401229#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7401223#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7401217#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7401212#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7401193#L666-45 assume !(1 == ~t2_pc~0); 7401046#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 7401045#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7401044#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7401043#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7401042#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7401040#L685-45 assume !(1 == ~t3_pc~0); 7401039#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 7401038#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7401037#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7401035#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 7401034#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7401033#L704-45 assume !(1 == ~t4_pc~0); 7401032#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 7401031#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7401030#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7401029#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7401027#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7401026#L723-45 assume 1 == ~t5_pc~0; 7401024#L724-15 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7401023#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7401022#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7401020#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 7401019#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7401018#L742-45 assume !(1 == ~t6_pc~0); 7401017#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 7401016#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7401015#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7401014#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7400429#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7399901#L761-45 assume 1 == ~t7_pc~0; 7399898#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7399895#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7399892#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 7399889#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7399885#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7399883#L780-45 assume !(1 == ~t8_pc~0); 7399880#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 7399877#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7399874#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 7399871#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7399869#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7399866#L799-45 assume !(1 == ~t9_pc~0); 7399864#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 7399862#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7399859#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 7399855#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 7399852#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7399850#L818-45 assume 1 == ~t10_pc~0; 7399846#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7399843#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7399840#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 7399837#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7399834#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 7399831#L837-45 assume !(1 == ~t11_pc~0); 7399827#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 7399824#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 7399821#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 7399818#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 7399815#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 7399811#L856-45 assume !(1 == ~t12_pc~0); 7399808#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 7399804#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 7399802#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 7399800#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 7399797#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 7399794#L875-45 assume !(1 == ~t13_pc~0); 7399791#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 7399787#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 7399784#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 7399781#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 7399778#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7399775#L1427-3 assume !(1 == ~M_E~0); 7230784#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7399769#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7399766#L1437-3 assume !(1 == ~T3_E~0); 7399763#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7399760#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7399758#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7399755#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7399752#L1462-3 assume !(1 == ~T8_E~0); 7399749#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7399746#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7399743#L1477-3 assume !(1 == ~T11_E~0); 7399740#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 7399737#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 7399734#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 7399731#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7399728#L1502-3 assume !(1 == ~E_2~0); 7399724#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7395014#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7365236#L1517-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7365230#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7365227#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7365224#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7365221#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 7365217#L1542-3 assume !(1 == ~E_10~0); 7365214#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 7365211#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 7365208#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 7365205#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 7365172#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 7365163#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 7365160#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 7231159#L1947 assume !(0 == start_simulation_~tmp~3#1); 7231160#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 7291489#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 7291481#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 7291479#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 7291477#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7291475#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7291473#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 7291471#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 7186315#L1928-2 [2023-11-29 03:22:51,374 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:22:51,374 INFO L85 PathProgramCache]: Analyzing trace with hash -1006148281, now seen corresponding path program 1 times [2023-11-29 03:22:51,374 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:22:51,374 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1372001657] [2023-11-29 03:22:51,374 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:22:51,374 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:22:51,384 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:22:51,435 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:22:51,436 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:22:51,436 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1372001657] [2023-11-29 03:22:51,436 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1372001657] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:22:51,436 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:22:51,436 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:22:51,436 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2103993457] [2023-11-29 03:22:51,436 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:22:51,437 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:22:51,437 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:22:51,437 INFO L85 PathProgramCache]: Analyzing trace with hash 249222573, now seen corresponding path program 1 times [2023-11-29 03:22:51,437 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:22:51,437 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550985997] [2023-11-29 03:22:51,437 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:22:51,438 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:22:51,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:22:51,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:22:51,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:22:51,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550985997] [2023-11-29 03:22:51,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [550985997] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:22:51,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:22:51,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:22:51,480 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [289467566] [2023-11-29 03:22:51,480 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:22:51,480 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:22:51,481 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:22:51,481 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:22:51,481 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:22:51,481 INFO L87 Difference]: Start difference. First operand 590500 states and 818009 transitions. cyclomatic complexity: 227637 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:22:53,994 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:22:53,994 INFO L93 Difference]: Finished difference Result 787034 states and 1084287 transitions. [2023-11-29 03:22:53,994 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 787034 states and 1084287 transitions. [2023-11-29 03:22:57,497 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 782928 [2023-11-29 03:22:59,181 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 787034 states to 787034 states and 1084287 transitions. [2023-11-29 03:22:59,182 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 787034 [2023-11-29 03:22:59,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 787034 [2023-11-29 03:22:59,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 787034 states and 1084287 transitions. [2023-11-29 03:22:59,560 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:22:59,560 INFO L218 hiAutomatonCegarLoop]: Abstraction has 787034 states and 1084287 transitions. [2023-11-29 03:22:59,908 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 787034 states and 1084287 transitions. [2023-11-29 03:23:03,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 787034 to 541226. [2023-11-29 03:23:04,000 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 541226 states, 541226 states have (on average 1.3797101395720088) internal successors, (746735), 541225 states have internal predecessors, (746735), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:23:05,868 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 541226 states to 541226 states and 746735 transitions. [2023-11-29 03:23:05,868 INFO L240 hiAutomatonCegarLoop]: Abstraction has 541226 states and 746735 transitions. [2023-11-29 03:23:05,869 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:23:05,869 INFO L428 stractBuchiCegarLoop]: Abstraction has 541226 states and 746735 transitions. [2023-11-29 03:23:05,869 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-29 03:23:05,869 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 541226 states and 746735 transitions. [2023-11-29 03:23:07,194 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 538496 [2023-11-29 03:23:07,194 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:23:07,194 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:23:07,196 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:23:07,196 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:23:07,196 INFO L748 eck$LassoCheckResult]: Stem: 8563478#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 8563479#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 8564516#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8564517#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8565501#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 8564064#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8564065#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8564138#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8564139#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8564630#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8564631#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8564101#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 8563898#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 8563899#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8564383#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 8564384#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 8564263#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 8564264#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 8563873#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8563874#L1279 assume !(0 == ~M_E~0); 8565339#L1279-2 assume !(0 == ~T1_E~0); 8563499#L1284-1 assume !(0 == ~T2_E~0); 8563500#L1289-1 assume !(0 == ~T3_E~0); 8564252#L1294-1 assume !(0 == ~T4_E~0); 8564253#L1299-1 assume !(0 == ~T5_E~0); 8564265#L1304-1 assume !(0 == ~T6_E~0); 8565498#L1309-1 assume !(0 == ~T7_E~0); 8565503#L1314-1 assume !(0 == ~T8_E~0); 8563422#L1319-1 assume !(0 == ~T9_E~0); 8563423#L1324-1 assume !(0 == ~T10_E~0); 8563598#L1329-1 assume !(0 == ~T11_E~0); 8563599#L1334-1 assume !(0 == ~T12_E~0); 8565192#L1339-1 assume !(0 == ~T13_E~0); 8565324#L1344-1 assume !(0 == ~E_M~0); 8565325#L1349-1 assume !(0 == ~E_1~0); 8564466#L1354-1 assume !(0 == ~E_2~0); 8564467#L1359-1 assume !(0 == ~E_3~0); 8564936#L1364-1 assume !(0 == ~E_4~0); 8563720#L1369-1 assume !(0 == ~E_5~0); 8563721#L1374-1 assume !(0 == ~E_6~0); 8564474#L1379-1 assume !(0 == ~E_7~0); 8564475#L1384-1 assume !(0 == ~E_8~0); 8564566#L1389-1 assume !(0 == ~E_9~0); 8565225#L1394-1 assume !(0 == ~E_10~0); 8565226#L1399-1 assume !(0 == ~E_11~0); 8565393#L1404-1 assume !(0 == ~E_12~0); 8563816#L1409-1 assume !(0 == ~E_13~0); 8563817#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8565382#L628 assume !(1 == ~m_pc~0); 8563719#L628-2 is_master_triggered_~__retres1~0#1 := 0; 8563718#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8564328#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8564329#L1591 assume !(0 != activate_threads_~tmp~1#1); 8565405#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8564306#L647 assume !(1 == ~t1_pc~0); 8564307#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8564361#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8564362#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8564889#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 8565299#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8565300#L666 assume !(1 == ~t2_pc~0); 8563498#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8563659#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8563640#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8563641#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 8564681#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8564682#L685 assume !(1 == ~t3_pc~0); 8564860#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8564861#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8564867#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8564526#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 8564527#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8563949#L704 assume !(1 == ~t4_pc~0); 8563950#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8564541#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8563288#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8563289#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 8564359#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8564360#L723 assume !(1 == ~t5_pc~0); 8564522#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8564759#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8564928#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8564663#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 8564664#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8563703#L742 assume !(1 == ~t6_pc~0); 8563704#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8563862#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8563629#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8563395#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 8563396#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8563779#L761 assume !(1 == ~t7_pc~0); 8563780#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8563657#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8563658#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8564530#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 8564531#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8563417#L780 assume !(1 == ~t8_pc~0); 8563418#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8563692#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8563693#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8564480#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 8564481#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8564618#L799 assume !(1 == ~t9_pc~0); 8563919#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8563415#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8563416#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8563687#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 8564835#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8564642#L818 assume !(1 == ~t10_pc~0); 8563204#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8563205#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8564715#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8564645#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 8564646#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8564689#L837 assume !(1 == ~t11_pc~0); 8564514#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 8564515#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8565305#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8564607#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 8564608#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8564318#L856 assume !(1 == ~t12_pc~0); 8564319#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 8565079#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8563222#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8563223#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 8565052#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8565343#L875 assume !(1 == ~t13_pc~0); 8565314#L875-2 is_transmit13_triggered_~__retres1~13#1 := 0; 8563863#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8563864#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8563797#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 8563798#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8564714#L1427 assume !(1 == ~M_E~0); 8564700#L1427-2 assume !(1 == ~T1_E~0); 8563767#L1432-1 assume !(1 == ~T2_E~0); 8563768#L1437-1 assume !(1 == ~T3_E~0); 8564944#L1442-1 assume !(1 == ~T4_E~0); 8564945#L1447-1 assume !(1 == ~T5_E~0); 8564769#L1452-1 assume !(1 == ~T6_E~0); 8563339#L1457-1 assume !(1 == ~T7_E~0); 8563340#L1462-1 assume !(1 == ~T8_E~0); 8564975#L1467-1 assume !(1 == ~T9_E~0); 8565005#L1472-1 assume !(1 == ~T10_E~0); 8565006#L1477-1 assume !(1 == ~T11_E~0); 8564710#L1482-1 assume !(1 == ~T12_E~0); 8564711#L1487-1 assume !(1 == ~T13_E~0); 8563667#L1492-1 assume !(1 == ~E_M~0); 8563668#L1497-1 assume !(1 == ~E_1~0); 8564043#L1502-1 assume !(1 == ~E_2~0); 8564044#L1507-1 assume !(1 == ~E_3~0); 8563547#L1512-1 assume !(1 == ~E_4~0); 8563548#L1517-1 assume !(1 == ~E_5~0); 8565105#L1522-1 assume !(1 == ~E_6~0); 8564304#L1527-1 assume !(1 == ~E_7~0); 8564305#L1532-1 assume !(1 == ~E_8~0); 8565461#L1537-1 assume !(1 == ~E_9~0); 8564549#L1542-1 assume !(1 == ~E_10~0); 8564336#L1547-1 assume !(1 == ~E_11~0); 8564337#L1552-1 assume !(1 == ~E_12~0); 8563246#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 8563247#L1562-1 assume { :end_inline_reset_delta_events } true; 8563852#L1928-2 [2023-11-29 03:23:07,197 INFO L750 eck$LassoCheckResult]: Loop: 8563852#L1928-2 assume !false; 8617926#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8617921#L1254-1 assume !false; 8617918#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8617902#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8617893#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8617891#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 8617889#L1067 assume !(0 != eval_~tmp~0#1); 8617890#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8618237#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8618235#L1279-3 assume !(0 == ~M_E~0); 8618233#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8618231#L1284-3 assume !(0 == ~T2_E~0); 8618228#L1289-3 assume !(0 == ~T3_E~0); 8618226#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8618224#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8618222#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8618220#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8618218#L1314-3 assume !(0 == ~T8_E~0); 8618216#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8618214#L1324-3 assume !(0 == ~T10_E~0); 8618212#L1329-3 assume !(0 == ~T11_E~0); 8618210#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 8618208#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 8618206#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 8618204#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8618201#L1354-3 assume !(0 == ~E_2~0); 8618199#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8618197#L1364-3 assume !(0 == ~E_4~0); 8618195#L1369-3 assume !(0 == ~E_5~0); 8618193#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8618191#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8618188#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8618186#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8618184#L1394-3 assume !(0 == ~E_10~0); 8618182#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 8618180#L1404-3 assume !(0 == ~E_12~0); 8618178#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 8618176#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8618174#L628-45 assume !(1 == ~m_pc~0); 8618171#L628-47 is_master_triggered_~__retres1~0#1 := 0; 8618169#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8618167#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8618166#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8618162#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8618160#L647-45 assume !(1 == ~t1_pc~0); 8618158#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 8618156#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8618153#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8618151#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8618149#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8618145#L666-45 assume !(1 == ~t2_pc~0); 8618143#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 8618141#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8618139#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8618137#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8618134#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8618132#L685-45 assume !(1 == ~t3_pc~0); 8618130#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 8618128#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8618126#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8618124#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 8618121#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8618119#L704-45 assume !(1 == ~t4_pc~0); 8618117#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 8618115#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8618113#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8618112#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8618111#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8618110#L723-45 assume !(1 == ~t5_pc~0); 8618108#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 8618107#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8618105#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8618104#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 8618103#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8618102#L742-45 assume !(1 == ~t6_pc~0); 8618101#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 8618100#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8618099#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8618098#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8618095#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8618093#L761-45 assume !(1 == ~t7_pc~0); 8618091#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 8618088#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8618085#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 8618083#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8618081#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8618079#L780-45 assume !(1 == ~t8_pc~0); 8618077#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 8618075#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8618073#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 8618071#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8618069#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8618067#L799-45 assume !(1 == ~t9_pc~0); 8618065#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 8618062#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8618060#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 8618058#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8618056#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8618054#L818-45 assume !(1 == ~t10_pc~0); 8618050#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 8618048#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8618046#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 8618044#L1671-45 assume !(0 != activate_threads_~tmp___9~0#1); 8618041#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 8618039#L837-45 assume !(1 == ~t11_pc~0); 8618037#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 8618035#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 8618033#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 8618031#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 8618029#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 8618027#L856-45 assume !(1 == ~t12_pc~0); 8618025#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 8618023#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 8618020#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 8618018#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 8618016#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 8618014#L875-45 assume !(1 == ~t13_pc~0); 8618012#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 8618010#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 8618008#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 8618006#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 8618004#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8618002#L1427-3 assume !(1 == ~M_E~0); 8574524#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8617999#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8617997#L1437-3 assume !(1 == ~T3_E~0); 8615102#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8615101#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8615100#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8615099#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8615098#L1462-3 assume !(1 == ~T8_E~0); 8615097#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8615096#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8615095#L1477-3 assume !(1 == ~T11_E~0); 8615094#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 8615093#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 8615092#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 8615077#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8615075#L1502-3 assume !(1 == ~E_2~0); 8615073#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8615071#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8615069#L1517-3 assume !(1 == ~E_5~0); 8615067#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8615065#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8615063#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8615058#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 8615056#L1542-3 assume !(1 == ~E_10~0); 8615054#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 8615053#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 8615052#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 8615051#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8607984#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8607977#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8607962#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 8574838#L1947 assume !(0 == start_simulation_~tmp~3#1); 8574839#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 8617948#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 8617939#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 8617937#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 8617935#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8617933#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8617931#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 8617929#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 8563852#L1928-2 [2023-11-29 03:23:07,197 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:23:07,197 INFO L85 PathProgramCache]: Analyzing trace with hash -537341689, now seen corresponding path program 1 times [2023-11-29 03:23:07,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:23:07,197 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143856612] [2023-11-29 03:23:07,197 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:23:07,197 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:23:07,208 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:23:07,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:23:07,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:23:07,278 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143856612] [2023-11-29 03:23:07,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143856612] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:23:07,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:23:07,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:23:07,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [549722740] [2023-11-29 03:23:07,279 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:23:07,279 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:23:07,279 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:23:07,280 INFO L85 PathProgramCache]: Analyzing trace with hash -1615943118, now seen corresponding path program 1 times [2023-11-29 03:23:07,280 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:23:07,280 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1691418593] [2023-11-29 03:23:07,280 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:23:07,280 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:23:07,294 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:23:07,348 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:23:07,348 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:23:07,349 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1691418593] [2023-11-29 03:23:07,349 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1691418593] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:23:07,349 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:23:07,349 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:23:07,349 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [853302189] [2023-11-29 03:23:07,350 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:23:07,350 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:23:07,350 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:23:07,350 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:23:07,351 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:23:07,351 INFO L87 Difference]: Start difference. First operand 541226 states and 746735 transitions. cyclomatic complexity: 205637 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:23:10,353 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:23:10,353 INFO L93 Difference]: Finished difference Result 827909 states and 1139655 transitions. [2023-11-29 03:23:10,353 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 827909 states and 1139655 transitions. [2023-11-29 03:23:14,547 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 823584 [2023-11-29 03:23:16,514 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 827909 states to 827909 states and 1139655 transitions. [2023-11-29 03:23:16,514 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 827909 [2023-11-29 03:23:16,756 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 827909 [2023-11-29 03:23:16,756 INFO L73 IsDeterministic]: Start isDeterministic. Operand 827909 states and 1139655 transitions. [2023-11-29 03:23:17,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:23:17,015 INFO L218 hiAutomatonCegarLoop]: Abstraction has 827909 states and 1139655 transitions. [2023-11-29 03:23:17,364 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 827909 states and 1139655 transitions. [2023-11-29 03:23:21,534 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 827909 to 590500. [2023-11-29 03:23:21,862 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 590500 states, 590500 states have (on average 1.379099068585944) internal successors, (814358), 590499 states have internal predecessors, (814358), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:23:23,521 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 590500 states to 590500 states and 814358 transitions. [2023-11-29 03:23:23,521 INFO L240 hiAutomatonCegarLoop]: Abstraction has 590500 states and 814358 transitions. [2023-11-29 03:23:23,521 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:23:23,522 INFO L428 stractBuchiCegarLoop]: Abstraction has 590500 states and 814358 transitions. [2023-11-29 03:23:23,522 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2023-11-29 03:23:23,522 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 590500 states and 814358 transitions. [2023-11-29 03:23:25,279 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 587648 [2023-11-29 03:23:25,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:23:25,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:23:25,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:23:25,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:23:25,281 INFO L748 eck$LassoCheckResult]: Stem: 9932622#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 9932623#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 9933646#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9933647#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9934617#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 9933215#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9933216#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9933290#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9933291#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9933756#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9933757#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9933253#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 9933050#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 9933051#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9933527#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 9933528#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 9933401#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 9933402#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 9933025#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9933026#L1279 assume !(0 == ~M_E~0); 9934445#L1279-2 assume !(0 == ~T1_E~0); 9932643#L1284-1 assume !(0 == ~T2_E~0); 9932644#L1289-1 assume !(0 == ~T3_E~0); 9933398#L1294-1 assume !(0 == ~T4_E~0); 9933399#L1299-1 assume !(0 == ~T5_E~0); 9933409#L1304-1 assume !(0 == ~T6_E~0); 9934609#L1309-1 assume !(0 == ~T7_E~0); 9934618#L1314-1 assume !(0 == ~T8_E~0); 9932567#L1319-1 assume !(0 == ~T9_E~0); 9932568#L1324-1 assume !(0 == ~T10_E~0); 9932742#L1329-1 assume !(0 == ~T11_E~0); 9932743#L1334-1 assume !(0 == ~T12_E~0); 9934302#L1339-1 assume !(0 == ~T13_E~0); 9934429#L1344-1 assume !(0 == ~E_M~0); 9934430#L1349-1 assume !(0 == ~E_1~0); 9933600#L1354-1 assume !(0 == ~E_2~0); 9933601#L1359-1 assume !(0 == ~E_3~0); 9934076#L1364-1 assume !(0 == ~E_4~0); 9932867#L1369-1 assume !(0 == ~E_5~0); 9932868#L1374-1 assume !(0 == ~E_6~0); 9933607#L1379-1 assume !(0 == ~E_7~0); 9933608#L1384-1 assume !(0 == ~E_8~0); 9933695#L1389-1 assume !(0 == ~E_9~0); 9934338#L1394-1 assume !(0 == ~E_10~0); 9934339#L1399-1 assume !(0 == ~E_11~0); 9934503#L1404-1 assume !(0 == ~E_12~0); 9932967#L1409-1 assume 0 == ~E_13~0;~E_13~0 := 1; 9932968#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9934496#L628 assume !(1 == ~m_pc~0); 9932866#L628-2 is_master_triggered_~__retres1~0#1 := 0; 9932865#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9933473#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9933474#L1591 assume !(0 != activate_threads_~tmp~1#1); 9934626#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9934627#L647 assume !(1 == ~t1_pc~0); 9933803#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9933804#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9934023#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9934024#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 9934405#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9934406#L666 assume !(1 == ~t2_pc~0); 9934484#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9934485#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9932784#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9932785#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 9933814#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9933815#L685 assume !(1 == ~t3_pc~0); 9933996#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9933997#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9934004#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9934005#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 9934028#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9934029#L704 assume !(1 == ~t4_pc~0); 9934596#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9934597#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9932433#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9932434#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 9933503#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9933504#L723 assume !(1 == ~t5_pc~0); 9933896#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9933897#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9934510#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9934511#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 9933819#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9933820#L742 assume !(1 == ~t6_pc~0); 9934486#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9934487#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9932774#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9932775#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 9934295#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9934296#L761 assume !(1 == ~t7_pc~0); 9932942#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9932943#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9934654#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9934655#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 9934453#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9934454#L780 assume !(1 == ~t8_pc~0); 9934397#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9934398#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9934488#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9934489#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 9933743#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9933744#L799 assume !(1 == ~t9_pc~0); 9933071#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9932562#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9932563#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9934685#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 9934643#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9934644#L818 assume !(1 == ~t10_pc~0); 9934371#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9933853#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9933854#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9933775#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 9933776#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9933825#L837 assume !(1 == ~t11_pc~0); 9933826#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 9934471#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9934472#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9933736#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 9933737#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9933462#L856 assume !(1 == ~t12_pc~0); 9933463#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 9934195#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9934196#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9934166#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 9934167#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9934449#L875 assume !(1 == ~t13_pc~0); 9934450#L875-2 is_transmit13_triggered_~__retres1~13#1 := 0; 9933015#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9933016#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9932948#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 9932949#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9934633#L1427 assume !(1 == ~M_E~0); 9934634#L1427-2 assume !(1 == ~T1_E~0); 9932915#L1432-1 assume !(1 == ~T2_E~0); 9932916#L1437-1 assume !(1 == ~T3_E~0); 9934081#L1442-1 assume !(1 == ~T4_E~0); 9934082#L1447-1 assume !(1 == ~T5_E~0); 9933908#L1452-1 assume !(1 == ~T6_E~0); 9933909#L1457-1 assume !(1 == ~T7_E~0); 9934100#L1462-1 assume !(1 == ~T8_E~0); 9934101#L1467-1 assume !(1 == ~T9_E~0); 9934683#L1472-1 assume !(1 == ~T10_E~0); 9934682#L1477-1 assume !(1 == ~T11_E~0); 9934681#L1482-1 assume !(1 == ~T12_E~0); 9934247#L1487-1 assume !(1 == ~T13_E~0); 9932814#L1492-1 assume !(1 == ~E_M~0); 9932815#L1497-1 assume !(1 == ~E_1~0); 9933195#L1502-1 assume !(1 == ~E_2~0); 9933196#L1507-1 assume !(1 == ~E_3~0); 9932692#L1512-1 assume !(1 == ~E_4~0); 9932693#L1517-1 assume !(1 == ~E_5~0); 9934318#L1522-1 assume !(1 == ~E_6~0); 9934319#L1527-1 assume !(1 == ~E_7~0); 9934571#L1532-1 assume !(1 == ~E_8~0); 9934572#L1537-1 assume !(1 == ~E_9~0); 9934669#L1542-1 assume !(1 == ~E_10~0); 9933480#L1547-1 assume !(1 == ~E_11~0); 9933481#L1552-1 assume !(1 == ~E_12~0); 9934587#L1557-1 assume 1 == ~E_13~0;~E_13~0 := 2; 9932391#L1562-1 assume { :end_inline_reset_delta_events } true; 9933002#L1928-2 [2023-11-29 03:23:25,281 INFO L750 eck$LassoCheckResult]: Loop: 9933002#L1928-2 assume !false; 9973409#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9973397#L1254-1 assume !false; 9973390#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9973117#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 9973095#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9973093#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 9973090#L1067 assume !(0 != eval_~tmp~0#1); 9973087#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9973085#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9973083#L1279-3 assume !(0 == ~M_E~0); 9973081#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9973079#L1284-3 assume !(0 == ~T2_E~0); 9973077#L1289-3 assume !(0 == ~T3_E~0); 9973075#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9973073#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9973071#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9973069#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9973067#L1314-3 assume !(0 == ~T8_E~0); 9973065#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9973063#L1324-3 assume !(0 == ~T10_E~0); 9973061#L1329-3 assume !(0 == ~T11_E~0); 9973059#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 9973057#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 9973055#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 9973053#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9973051#L1354-3 assume !(0 == ~E_2~0); 9973049#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9973047#L1364-3 assume !(0 == ~E_4~0); 9973045#L1369-3 assume !(0 == ~E_5~0); 9973043#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9973041#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9973039#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9973037#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9973035#L1394-3 assume !(0 == ~E_10~0); 9972928#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 9972922#L1404-3 assume !(0 == ~E_12~0); 9972915#L1409-3 assume 0 == ~E_13~0;~E_13~0 := 1; 9972912#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9972910#L628-45 assume !(1 == ~m_pc~0); 9972907#L628-47 is_master_triggered_~__retres1~0#1 := 0; 9972904#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9972902#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9972900#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9972898#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9972896#L647-45 assume !(1 == ~t1_pc~0); 9972894#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 9972891#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9972889#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9972887#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9972885#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9972882#L666-45 assume !(1 == ~t2_pc~0); 9972879#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 9972877#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9972875#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9972873#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9972871#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9972869#L685-45 assume !(1 == ~t3_pc~0); 9972867#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 9972865#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9972863#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9972861#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 9972859#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9972857#L704-45 assume !(1 == ~t4_pc~0); 9972855#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 9972853#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9972851#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9972849#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9972846#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9972843#L723-45 assume !(1 == ~t5_pc~0); 9972838#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 9972835#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9972832#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9972829#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 9972826#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9972823#L742-45 assume !(1 == ~t6_pc~0); 9972820#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 9972817#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9972814#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9972811#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9972808#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9972805#L761-45 assume 1 == ~t7_pc~0; 9972801#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9972797#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9972794#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 9972791#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9972788#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9972785#L780-45 assume !(1 == ~t8_pc~0); 9972782#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 9972777#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9972773#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 9972769#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9972764#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9972760#L799-45 assume !(1 == ~t9_pc~0); 9972756#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 9972752#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9972747#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 9972743#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9972739#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9972734#L818-45 assume 1 == ~t10_pc~0; 9972729#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 9972723#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9972717#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 9972710#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9972705#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 9972701#L837-45 assume !(1 == ~t11_pc~0); 9972697#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 9972693#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 9972689#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 9972685#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 9972679#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 9972674#L856-45 assume 1 == ~t12_pc~0; 9972668#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 9972662#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 9972658#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 9972653#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 9972646#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 9972640#L875-45 assume !(1 == ~t13_pc~0); 9972634#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 9972628#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 9972622#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 9972617#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 9972611#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9972605#L1427-3 assume !(1 == ~M_E~0); 9955764#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9972597#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9972592#L1437-3 assume !(1 == ~T3_E~0); 9972586#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9972580#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9972575#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9972570#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9972565#L1462-3 assume !(1 == ~T8_E~0); 9972560#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9972555#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9972548#L1477-3 assume !(1 == ~T11_E~0); 9972542#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 9972536#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 9972530#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 9972525#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9972520#L1502-3 assume !(1 == ~E_2~0); 9972513#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9972507#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9972502#L1517-3 assume !(1 == ~E_5~0); 9972497#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9972492#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9972486#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9972483#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9972480#L1542-3 assume !(1 == ~E_10~0); 9972476#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 9972472#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 9972468#L1557-3 assume 1 == ~E_13~0;~E_13~0 := 2; 9972464#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9962121#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 9962113#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9962111#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 9956165#L1947 assume !(0 == start_simulation_~tmp~3#1); 9956166#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 9974993#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 9974985#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 9974983#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 9974981#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9974979#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9974976#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 9973429#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 9933002#L1928-2 [2023-11-29 03:23:25,281 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:23:25,281 INFO L85 PathProgramCache]: Analyzing trace with hash 1828693381, now seen corresponding path program 1 times [2023-11-29 03:23:25,281 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:23:25,281 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [865068522] [2023-11-29 03:23:25,281 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:23:25,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:23:25,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:23:25,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:23:25,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:23:25,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [865068522] [2023-11-29 03:23:25,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [865068522] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:23:25,328 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:23:25,328 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:23:25,328 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [430991905] [2023-11-29 03:23:25,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:23:25,329 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 03:23:25,329 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:23:25,329 INFO L85 PathProgramCache]: Analyzing trace with hash 2013732909, now seen corresponding path program 1 times [2023-11-29 03:23:25,329 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:23:25,329 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [637570395] [2023-11-29 03:23:25,329 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:23:25,329 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:23:25,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:23:25,364 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:23:25,365 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:23:25,365 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [637570395] [2023-11-29 03:23:25,365 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [637570395] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:23:25,365 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:23:25,365 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:23:25,365 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1127134816] [2023-11-29 03:23:25,365 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:23:25,366 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:23:25,366 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:23:25,366 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 03:23:25,366 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 03:23:25,366 INFO L87 Difference]: Start difference. First operand 590500 states and 814358 transitions. cyclomatic complexity: 223986 Second operand has 4 states, 4 states have (on average 40.25) internal successors, (161), 3 states have internal predecessors, (161), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:23:27,813 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:23:27,813 INFO L93 Difference]: Finished difference Result 777482 states and 1067229 transitions. [2023-11-29 03:23:27,813 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 777482 states and 1067229 transitions. [2023-11-29 03:23:31,474 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 773280 [2023-11-29 03:23:33,257 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 777482 states to 777482 states and 1067229 transitions. [2023-11-29 03:23:33,257 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 777482 [2023-11-29 03:23:33,494 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 777482 [2023-11-29 03:23:33,494 INFO L73 IsDeterministic]: Start isDeterministic. Operand 777482 states and 1067229 transitions. [2023-11-29 03:23:33,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:23:33,684 INFO L218 hiAutomatonCegarLoop]: Abstraction has 777482 states and 1067229 transitions. [2023-11-29 03:23:34,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 777482 states and 1067229 transitions. [2023-11-29 03:23:38,076 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 777482 to 541226. [2023-11-29 03:23:38,336 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 541226 states, 541226 states have (on average 1.3736756918551585) internal successors, (743469), 541225 states have internal predecessors, (743469), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:23:39,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 541226 states to 541226 states and 743469 transitions. [2023-11-29 03:23:39,927 INFO L240 hiAutomatonCegarLoop]: Abstraction has 541226 states and 743469 transitions. [2023-11-29 03:23:39,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 03:23:39,928 INFO L428 stractBuchiCegarLoop]: Abstraction has 541226 states and 743469 transitions. [2023-11-29 03:23:39,928 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2023-11-29 03:23:39,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 541226 states and 743469 transitions. [2023-11-29 03:23:41,451 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 538496 [2023-11-29 03:23:41,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:23:41,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:23:41,453 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:23:41,453 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:23:41,454 INFO L748 eck$LassoCheckResult]: Stem: 11300614#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 11300615#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 11301619#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11301620#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11302467#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 11301187#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11301188#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11301259#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11301260#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11301724#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11301725#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11301222#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11301024#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 11301025#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11301501#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 11301502#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 11301376#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 11301377#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 11300999#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11301000#L1279 assume !(0 == ~M_E~0); 11302337#L1279-2 assume !(0 == ~T1_E~0); 11300635#L1284-1 assume !(0 == ~T2_E~0); 11300636#L1289-1 assume !(0 == ~T3_E~0); 11301373#L1294-1 assume !(0 == ~T4_E~0); 11301374#L1299-1 assume !(0 == ~T5_E~0); 11301384#L1304-1 assume !(0 == ~T6_E~0); 11302463#L1309-1 assume !(0 == ~T7_E~0); 11302468#L1314-1 assume !(0 == ~T8_E~0); 11300559#L1319-1 assume !(0 == ~T9_E~0); 11300560#L1324-1 assume !(0 == ~T10_E~0); 11300733#L1329-1 assume !(0 == ~T11_E~0); 11300734#L1334-1 assume !(0 == ~T12_E~0); 11302223#L1339-1 assume !(0 == ~T13_E~0); 11302324#L1344-1 assume !(0 == ~E_M~0); 11302325#L1349-1 assume !(0 == ~E_1~0); 11301574#L1354-1 assume !(0 == ~E_2~0); 11301575#L1359-1 assume !(0 == ~E_3~0); 11302007#L1364-1 assume !(0 == ~E_4~0); 11300852#L1369-1 assume !(0 == ~E_5~0); 11300853#L1374-1 assume !(0 == ~E_6~0); 11301581#L1379-1 assume !(0 == ~E_7~0); 11301582#L1384-1 assume !(0 == ~E_8~0); 11301666#L1389-1 assume !(0 == ~E_9~0); 11302247#L1394-1 assume !(0 == ~E_10~0); 11302248#L1399-1 assume !(0 == ~E_11~0); 11302376#L1404-1 assume !(0 == ~E_12~0); 11300947#L1409-1 assume !(0 == ~E_13~0); 11300948#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11302369#L628 assume !(1 == ~m_pc~0); 11300851#L628-2 is_master_triggered_~__retres1~0#1 := 0; 11300850#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11301447#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11301448#L1591 assume !(0 != activate_threads_~tmp~1#1); 11302385#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11301425#L647 assume !(1 == ~t1_pc~0); 11301426#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11301480#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11301481#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11301965#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 11302301#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11302302#L666 assume !(1 == ~t2_pc~0); 11300634#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11300794#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11300773#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11300774#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 11301776#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11301777#L685 assume !(1 == ~t3_pc~0); 11301943#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 11301944#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11301951#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11301628#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 11301629#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11301075#L704 assume !(1 == ~t4_pc~0); 11301076#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 11301642#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11300426#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11300427#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 11301478#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11301479#L723 assume !(1 == ~t5_pc~0); 11301624#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11301849#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11301999#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11301756#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 11301757#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11300835#L742 assume !(1 == ~t6_pc~0); 11300836#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 11300988#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11300764#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11300530#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 11300531#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11300912#L761 assume !(1 == ~t7_pc~0); 11300913#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11300790#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11300791#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11301631#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 11301632#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11300554#L780 assume !(1 == ~t8_pc~0); 11300555#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 11300827#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11300828#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11301590#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 11301591#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11301712#L799 assume !(1 == ~t9_pc~0); 11301045#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11300552#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11300553#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11300822#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 11301920#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11301738#L818 assume !(1 == ~t10_pc~0); 11300342#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 11300343#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11301811#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11301741#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 11301742#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11301784#L837 assume !(1 == ~t11_pc~0); 11301616#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 11301617#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11302307#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11301705#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 11301706#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11301435#L856 assume !(1 == ~t12_pc~0); 11301436#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 11302137#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11300360#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11300361#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 11302102#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 11302340#L875 assume !(1 == ~t13_pc~0); 11302317#L875-2 is_transmit13_triggered_~__retres1~13#1 := 0; 11300989#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 11300990#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 11300929#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 11300930#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11301808#L1427 assume !(1 == ~M_E~0); 11301791#L1427-2 assume !(1 == ~T1_E~0); 11300899#L1432-1 assume !(1 == ~T2_E~0); 11300900#L1437-1 assume !(1 == ~T3_E~0); 11302016#L1442-1 assume !(1 == ~T4_E~0); 11302017#L1447-1 assume !(1 == ~T5_E~0); 11301861#L1452-1 assume !(1 == ~T6_E~0); 11300477#L1457-1 assume !(1 == ~T7_E~0); 11300478#L1462-1 assume !(1 == ~T8_E~0); 11302036#L1467-1 assume !(1 == ~T9_E~0); 11302061#L1472-1 assume !(1 == ~T10_E~0); 11302062#L1477-1 assume !(1 == ~T11_E~0); 11301804#L1482-1 assume !(1 == ~T12_E~0); 11301805#L1487-1 assume !(1 == ~T13_E~0); 11300802#L1492-1 assume !(1 == ~E_M~0); 11300803#L1497-1 assume !(1 == ~E_1~0); 11301168#L1502-1 assume !(1 == ~E_2~0); 11301169#L1507-1 assume !(1 == ~E_3~0); 11300683#L1512-1 assume !(1 == ~E_4~0); 11300684#L1517-1 assume !(1 == ~E_5~0); 11302159#L1522-1 assume !(1 == ~E_6~0); 11301422#L1527-1 assume !(1 == ~E_7~0); 11301423#L1532-1 assume !(1 == ~E_8~0); 11302435#L1537-1 assume !(1 == ~E_9~0); 11301652#L1542-1 assume !(1 == ~E_10~0); 11301454#L1547-1 assume !(1 == ~E_11~0); 11301455#L1552-1 assume !(1 == ~E_12~0); 11300383#L1557-1 assume !(1 == ~E_13~0); 11300384#L1562-1 assume { :end_inline_reset_delta_events } true; 11300978#L1928-2 [2023-11-29 03:23:41,454 INFO L750 eck$LassoCheckResult]: Loop: 11300978#L1928-2 assume !false; 11409003#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11408996#L1254-1 assume !false; 11408895#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 11329129#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11329120#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11329119#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 11329117#L1067 assume !(0 != eval_~tmp~0#1); 11329116#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11329115#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11329114#L1279-3 assume !(0 == ~M_E~0); 11329113#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11329112#L1284-3 assume !(0 == ~T2_E~0); 11329111#L1289-3 assume !(0 == ~T3_E~0); 11329110#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11329095#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11329093#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11329091#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11329089#L1314-3 assume !(0 == ~T8_E~0); 11329087#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11329085#L1324-3 assume !(0 == ~T10_E~0); 11329083#L1329-3 assume !(0 == ~T11_E~0); 11329081#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 11329076#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 11329074#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 11329072#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11329071#L1354-3 assume !(0 == ~E_2~0); 11329070#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11329069#L1364-3 assume !(0 == ~E_4~0); 11329068#L1369-3 assume !(0 == ~E_5~0); 11329067#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11329066#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11329065#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11329064#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11329063#L1394-3 assume !(0 == ~E_10~0); 11329062#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 11329061#L1404-3 assume !(0 == ~E_12~0); 11329060#L1409-3 assume !(0 == ~E_13~0); 11329058#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11329057#L628-45 assume !(1 == ~m_pc~0); 11329055#L628-47 is_master_triggered_~__retres1~0#1 := 0; 11329054#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11329052#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11329051#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 11329050#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11329049#L647-45 assume !(1 == ~t1_pc~0); 11329048#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 11329047#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11329046#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11329045#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11329044#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11329041#L666-45 assume !(1 == ~t2_pc~0); 11329038#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 11329036#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11329034#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11329032#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11329030#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11329028#L685-45 assume !(1 == ~t3_pc~0); 11329026#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 11329024#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11329022#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11329020#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 11329018#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11329016#L704-45 assume !(1 == ~t4_pc~0); 11329014#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 11329011#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11329009#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11329007#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11329005#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11329003#L723-45 assume !(1 == ~t5_pc~0); 11329001#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 11328998#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11328996#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11328994#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 11328992#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11328990#L742-45 assume !(1 == ~t6_pc~0); 11328988#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 11328986#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11328984#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11328982#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11328980#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11328978#L761-45 assume 1 == ~t7_pc~0; 11328975#L762-15 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11328973#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11328970#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 11328968#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11328966#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11328964#L780-45 assume !(1 == ~t8_pc~0); 11328962#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 11328960#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11328957#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 11328955#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11328953#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11328951#L799-45 assume !(1 == ~t9_pc~0); 11328949#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 11328947#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11328945#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 11328943#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11328941#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11328939#L818-45 assume 1 == ~t10_pc~0; 11328937#L819-15 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 11328938#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11329053#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 11328926#L1671-45 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11328924#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 11328921#L837-45 assume !(1 == ~t11_pc~0); 11328919#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 11328917#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 11328915#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 11328913#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 11328911#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 11328909#L856-45 assume 1 == ~t12_pc~0; 11328906#L857-15 assume 1 == ~E_12~0;is_transmit12_triggered_~__retres1~12#1 := 1; 11328904#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 11328863#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 11328862#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 11328861#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 11328860#L875-45 assume !(1 == ~t13_pc~0); 11328859#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 11328856#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 11328854#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 11328852#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 11328851#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11328849#L1427-3 assume !(1 == ~M_E~0); 11319540#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11328847#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11328846#L1437-3 assume !(1 == ~T3_E~0); 11328845#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11328844#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11328843#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11328840#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11328839#L1462-3 assume !(1 == ~T8_E~0); 11328838#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11328837#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11328836#L1477-3 assume !(1 == ~T11_E~0); 11328835#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 11328834#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 11328833#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 11328831#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11328830#L1502-3 assume !(1 == ~E_2~0); 11328829#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11328827#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11328826#L1517-3 assume !(1 == ~E_5~0); 11328825#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11328824#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11328823#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11328822#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11328821#L1542-3 assume !(1 == ~E_10~0); 11328820#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 11328819#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 11328818#L1557-3 assume !(1 == ~E_13~0); 11328817#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 11328809#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11328802#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11328801#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 11319733#L1947 assume !(0 == start_simulation_~tmp~3#1); 11319734#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 11412666#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 11412658#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 11412656#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 11412622#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11412614#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11412480#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 11412479#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 11300978#L1928-2 [2023-11-29 03:23:41,454 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:23:41,454 INFO L85 PathProgramCache]: Analyzing trace with hash -537341627, now seen corresponding path program 1 times [2023-11-29 03:23:41,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:23:41,455 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2059558466] [2023-11-29 03:23:41,455 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:23:41,455 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:23:41,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:23:41,469 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:23:41,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:23:41,593 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:23:41,594 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:23:41,594 INFO L85 PathProgramCache]: Analyzing trace with hash 568110061, now seen corresponding path program 1 times [2023-11-29 03:23:41,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:23:41,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867194745] [2023-11-29 03:23:41,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:23:41,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:23:41,606 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:23:41,637 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:23:41,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:23:41,637 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1867194745] [2023-11-29 03:23:41,637 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1867194745] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:23:41,637 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:23:41,637 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 03:23:41,638 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1078933841] [2023-11-29 03:23:41,638 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:23:41,638 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:23:41,638 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:23:41,638 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 03:23:41,639 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 03:23:41,639 INFO L87 Difference]: Start difference. First operand 541226 states and 743469 transitions. cyclomatic complexity: 202371 Second operand has 3 states, 3 states have (on average 54.666666666666664) internal successors, (164), 3 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:23:44,871 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:23:44,871 INFO L93 Difference]: Finished difference Result 1017303 states and 1388690 transitions. [2023-11-29 03:23:44,871 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1017303 states and 1388690 transitions. [2023-11-29 03:23:49,685 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1011968 [2023-11-29 03:23:52,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1017303 states to 1017303 states and 1388690 transitions. [2023-11-29 03:23:52,096 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1017303 [2023-11-29 03:23:52,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1017303 [2023-11-29 03:23:52,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1017303 states and 1388690 transitions. [2023-11-29 03:23:52,781 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:23:52,782 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1017303 states and 1388690 transitions. [2023-11-29 03:23:53,262 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1017303 states and 1388690 transitions. [2023-11-29 03:23:59,882 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1017303 to 1017111. [2023-11-29 03:24:00,926 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1017111 states, 1017111 states have (on average 1.3651391047781412) internal successors, (1388498), 1017110 states have internal predecessors, (1388498), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:24:03,944 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1017111 states to 1017111 states and 1388498 transitions. [2023-11-29 03:24:03,944 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1017111 states and 1388498 transitions. [2023-11-29 03:24:03,944 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 03:24:03,945 INFO L428 stractBuchiCegarLoop]: Abstraction has 1017111 states and 1388498 transitions. [2023-11-29 03:24:03,945 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2023-11-29 03:24:03,945 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1017111 states and 1388498 transitions. [2023-11-29 03:24:08,003 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1011776 [2023-11-29 03:24:08,003 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 03:24:08,003 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 03:24:08,005 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:24:08,005 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 03:24:08,005 INFO L748 eck$LassoCheckResult]: Stem: 12859147#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(22, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~t11_pc~0 := 0;~t12_pc~0 := 0;~t13_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~t11_st~0 := 0;~t12_st~0 := 0;~t13_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~t11_i~0 := 0;~t12_i~0 := 0;~t13_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~T11_E~0 := 2;~T12_E~0 := 2;~T13_E~0 := 2;~E_M~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2;~E_11~0 := 2;~E_12~0 := 2;~E_13~0 := 2;~token~0 := 0;~local~0 := 0; 12859148#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~15#1;havoc main_~__retres1~15#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1;~t11_i~0 := 1;~t12_i~0 := 1;~t13_i~0 := 1; 12860150#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret35#1, start_simulation_#t~ret36#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12860151#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12861046#L902 assume 1 == ~m_i~0;~m_st~0 := 0; 12859721#L902-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12859722#L907-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12859792#L912-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12859793#L917-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12860257#L922-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12860258#L927-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12859757#L932-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12859560#L937-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 12859561#L942-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12860033#L947-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 12860034#L952-1 assume 1 == ~t11_i~0;~t11_st~0 := 0; 12859911#L957-1 assume 1 == ~t12_i~0;~t12_st~0 := 0; 12859912#L962-1 assume 1 == ~t13_i~0;~t13_st~0 := 0; 12859536#L967-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12859537#L1279 assume !(0 == ~M_E~0); 12860909#L1279-2 assume !(0 == ~T1_E~0); 12859168#L1284-1 assume !(0 == ~T2_E~0); 12859169#L1289-1 assume !(0 == ~T3_E~0); 12859903#L1294-1 assume !(0 == ~T4_E~0); 12859904#L1299-1 assume !(0 == ~T5_E~0); 12859913#L1304-1 assume !(0 == ~T6_E~0); 12861040#L1309-1 assume !(0 == ~T7_E~0); 12861048#L1314-1 assume !(0 == ~T8_E~0); 12859094#L1319-1 assume !(0 == ~T9_E~0); 12859095#L1324-1 assume !(0 == ~T10_E~0); 12859267#L1329-1 assume !(0 == ~T11_E~0); 12859268#L1334-1 assume !(0 == ~T12_E~0); 12860783#L1339-1 assume !(0 == ~T13_E~0); 12860893#L1344-1 assume !(0 == ~E_M~0); 12860894#L1349-1 assume !(0 == ~E_1~0); 12860106#L1354-1 assume !(0 == ~E_2~0); 12860107#L1359-1 assume !(0 == ~E_3~0); 12860562#L1364-1 assume !(0 == ~E_4~0); 12859387#L1369-1 assume !(0 == ~E_5~0); 12859388#L1374-1 assume !(0 == ~E_6~0); 12860114#L1379-1 assume !(0 == ~E_7~0); 12860115#L1384-1 assume !(0 == ~E_8~0); 12860198#L1389-1 assume !(0 == ~E_9~0); 12860809#L1394-1 assume !(0 == ~E_10~0); 12860810#L1399-1 assume !(0 == ~E_11~0); 12860960#L1404-1 assume !(0 == ~E_12~0); 12859483#L1409-1 assume !(0 == ~E_13~0); 12859484#L1414-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12860951#L628 assume !(1 == ~m_pc~0); 12859386#L628-2 is_master_triggered_~__retres1~0#1 := 0; 12859385#L639 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12859977#is_master_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12859978#L1591 assume !(0 != activate_threads_~tmp~1#1); 12860969#L1591-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12859955#L647 assume !(1 == ~t1_pc~0); 12859956#L647-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12860010#L658 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12860011#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12860517#L1599 assume !(0 != activate_threads_~tmp___0~0#1); 12860875#L1599-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12860876#L666 assume !(1 == ~t2_pc~0); 12859167#L666-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12859330#L677 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12859309#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12859310#L1607 assume !(0 != activate_threads_~tmp___1~0#1); 12860310#L1607-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12860311#L685 assume !(1 == ~t3_pc~0); 12860488#L685-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12860489#L696 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12860497#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12860160#L1615 assume !(0 != activate_threads_~tmp___2~0#1); 12860161#L1615-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12859609#L704 assume !(1 == ~t4_pc~0); 12859610#L704-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12860174#L715 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12858959#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12858960#L1623 assume !(0 != activate_threads_~tmp___3~0#1); 12860008#L1623-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12860009#L723 assume !(1 == ~t5_pc~0); 12860156#L723-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12860391#L734 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12860554#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12860293#L1631 assume !(0 != activate_threads_~tmp___4~0#1); 12860294#L1631-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12859370#L742 assume !(1 == ~t6_pc~0); 12859371#L742-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12859525#L753 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12859298#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12859065#L1639 assume !(0 != activate_threads_~tmp___5~0#1); 12859066#L1639-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12859447#L761 assume !(1 == ~t7_pc~0); 12859448#L761-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12859326#L772 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12859327#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 12860162#L1647 assume !(0 != activate_threads_~tmp___6~0#1); 12860163#L1647-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12859085#L780 assume !(1 == ~t8_pc~0); 12859086#L780-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12859361#L791 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12859362#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 12860120#L1655 assume !(0 != activate_threads_~tmp___7~0#1); 12860121#L1655-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12860247#L799 assume !(1 == ~t9_pc~0); 12859581#L799-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12859087#L810 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12859088#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 12859356#L1663 assume !(0 != activate_threads_~tmp___8~0#1); 12860466#L1663-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12860273#L818 assume !(1 == ~t10_pc~0); 12858876#L818-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12858877#L829 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12860349#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 12860276#L1671 assume !(0 != activate_threads_~tmp___9~0#1); 12860277#L1671-2 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 12860319#L837 assume !(1 == ~t11_pc~0); 12860320#L837-2 is_transmit11_triggered_~__retres1~11#1 := 0; 12860935#L848 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 12860936#is_transmit11_triggered_returnLabel#1 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 12860237#L1679 assume !(0 != activate_threads_~tmp___10~0#1); 12860238#L1679-2 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 12859967#L856 assume !(1 == ~t12_pc~0); 12859968#L856-2 is_transmit12_triggered_~__retres1~12#1 := 0; 12860687#L867 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 12860688#is_transmit12_triggered_returnLabel#1 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 12860656#L1687 assume !(0 != activate_threads_~tmp___11~0#1); 12860657#L1687-2 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 12860914#L875 assume !(1 == ~t13_pc~0); 12860915#L875-2 is_transmit13_triggered_~__retres1~13#1 := 0; 12859526#L886 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 12859527#is_transmit13_triggered_returnLabel#1 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 12859464#L1695 assume !(0 != activate_threads_~tmp___12~0#1); 12859465#L1695-2 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12861059#L1427 assume !(1 == ~M_E~0); 12861060#L1427-2 assume !(1 == ~T1_E~0); 12859434#L1432-1 assume !(1 == ~T2_E~0); 12859435#L1437-1 assume !(1 == ~T3_E~0); 12860568#L1442-1 assume !(1 == ~T4_E~0); 12860569#L1447-1 assume !(1 == ~T5_E~0); 12860403#L1452-1 assume !(1 == ~T6_E~0); 12860404#L1457-1 assume !(1 == ~T7_E~0); 12860591#L1462-1 assume !(1 == ~T8_E~0); 12860592#L1467-1 assume !(1 == ~T9_E~0); 12860618#L1472-1 assume !(1 == ~T10_E~0); 12860619#L1477-1 assume !(1 == ~T11_E~0); 12860341#L1482-1 assume !(1 == ~T12_E~0); 12860342#L1487-1 assume !(1 == ~T13_E~0); 12859336#L1492-1 assume !(1 == ~E_M~0); 12859337#L1497-1 assume !(1 == ~E_1~0); 12859702#L1502-1 assume !(1 == ~E_2~0); 12859703#L1507-1 assume !(1 == ~E_3~0); 12859217#L1512-1 assume !(1 == ~E_4~0); 12859218#L1517-1 assume !(1 == ~E_5~0); 12860710#L1522-1 assume !(1 == ~E_6~0); 12859953#L1527-1 assume !(1 == ~E_7~0); 12859954#L1532-1 assume !(1 == ~E_8~0); 12861010#L1537-1 assume !(1 == ~E_9~0); 12861083#L1542-1 assume !(1 == ~E_10~0); 12859986#L1547-1 assume !(1 == ~E_11~0); 12859987#L1552-1 assume !(1 == ~E_12~0); 12858919#L1557-1 assume !(1 == ~E_13~0); 12858920#L1562-1 assume { :end_inline_reset_delta_events } true; 12859515#L1928-2 [2023-11-29 03:24:08,005 INFO L750 eck$LassoCheckResult]: Loop: 12859515#L1928-2 assume !false; 12953165#L1929 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12953160#L1254-1 assume !false; 12953158#L1063 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12953140#L980 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12953131#L1052 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12953129#exists_runnable_thread_returnLabel#1 eval_#t~ret5#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret5#1;havoc eval_#t~ret5#1; 12953126#L1067 assume !(0 != eval_~tmp~0#1); 12953127#eval_returnLabel#1 havoc eval_#t~ret5#1, eval_#t~nondet6#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet16#1, eval_~tmp_ndt_11~0#1, eval_#t~nondet17#1, eval_~tmp_ndt_12~0#1, eval_#t~nondet18#1, eval_~tmp_ndt_13~0#1, eval_#t~nondet19#1, eval_~tmp_ndt_14~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13078093#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13078091#L1279-3 assume !(0 == ~M_E~0); 13078089#L1279-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13078087#L1284-3 assume !(0 == ~T2_E~0); 13078085#L1289-3 assume !(0 == ~T3_E~0); 13078083#L1294-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13078081#L1299-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13078079#L1304-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13078077#L1309-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13078075#L1314-3 assume !(0 == ~T8_E~0); 13078073#L1319-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 13078071#L1324-3 assume !(0 == ~T10_E~0); 13078069#L1329-3 assume !(0 == ~T11_E~0); 13078067#L1334-3 assume 0 == ~T12_E~0;~T12_E~0 := 1; 13078065#L1339-3 assume 0 == ~T13_E~0;~T13_E~0 := 1; 13078063#L1344-3 assume 0 == ~E_M~0;~E_M~0 := 1; 13078061#L1349-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13078059#L1354-3 assume !(0 == ~E_2~0); 13078057#L1359-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13078055#L1364-3 assume !(0 == ~E_4~0); 13078053#L1369-3 assume !(0 == ~E_5~0); 13078051#L1374-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13078050#L1379-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13078049#L1384-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13078048#L1389-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13078047#L1394-3 assume !(0 == ~E_10~0); 13078045#L1399-3 assume 0 == ~E_11~0;~E_11~0 := 1; 13078044#L1404-3 assume !(0 == ~E_12~0); 13078043#L1409-3 assume !(0 == ~E_13~0); 13078042#L1414-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp___10~0#1;havoc activate_threads_~tmp___11~0#1;havoc activate_threads_~tmp___12~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13078041#L628-45 assume !(1 == ~m_pc~0); 13078039#L628-47 is_master_triggered_~__retres1~0#1 := 0; 13078038#L639-15 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13078037#is_master_triggered_returnLabel#16 activate_threads_#t~ret20#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13078036#L1591-45 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13078035#L1591-47 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13078033#L647-45 assume !(1 == ~t1_pc~0); 13078030#L647-47 is_transmit1_triggered_~__retres1~1#1 := 0; 13078028#L658-15 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13078026#is_transmit1_triggered_returnLabel#16 activate_threads_#t~ret21#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13078024#L1599-45 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13078022#L1599-47 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13078018#L666-45 assume !(1 == ~t2_pc~0); 13078016#L666-47 is_transmit2_triggered_~__retres1~2#1 := 0; 13078014#L677-15 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13078012#is_transmit2_triggered_returnLabel#16 activate_threads_#t~ret22#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13078010#L1607-45 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13078009#L1607-47 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13078006#L685-45 assume !(1 == ~t3_pc~0); 13078004#L685-47 is_transmit3_triggered_~__retres1~3#1 := 0; 13078002#L696-15 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13078000#is_transmit3_triggered_returnLabel#16 activate_threads_#t~ret23#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 13077998#L1615-45 assume !(0 != activate_threads_~tmp___2~0#1); 13077996#L1615-47 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13077994#L704-45 assume !(1 == ~t4_pc~0); 13077992#L704-47 is_transmit4_triggered_~__retres1~4#1 := 0; 13077990#L715-15 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13077988#is_transmit4_triggered_returnLabel#16 activate_threads_#t~ret24#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13077986#L1623-45 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13077984#L1623-47 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13077982#L723-45 assume !(1 == ~t5_pc~0); 13077979#L723-47 is_transmit5_triggered_~__retres1~5#1 := 0; 13077977#L734-15 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13077975#is_transmit5_triggered_returnLabel#16 activate_threads_#t~ret25#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13077973#L1631-45 assume !(0 != activate_threads_~tmp___4~0#1); 13077971#L1631-47 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13077968#L742-45 assume !(1 == ~t6_pc~0); 13077966#L742-47 is_transmit6_triggered_~__retres1~6#1 := 0; 13077964#L753-15 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13077962#is_transmit6_triggered_returnLabel#16 activate_threads_#t~ret26#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13077960#L1639-45 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13077958#L1639-47 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13077956#L761-45 assume !(1 == ~t7_pc~0); 13077954#L761-47 is_transmit7_triggered_~__retres1~7#1 := 0; 13077951#L772-15 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13077949#is_transmit7_triggered_returnLabel#16 activate_threads_#t~ret27#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret27#1;havoc activate_threads_#t~ret27#1; 13077947#L1647-45 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13077945#L1647-47 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13077943#L780-45 assume !(1 == ~t8_pc~0); 13077940#L780-47 is_transmit8_triggered_~__retres1~8#1 := 0; 13077938#L791-15 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13077936#is_transmit8_triggered_returnLabel#16 activate_threads_#t~ret28#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret28#1;havoc activate_threads_#t~ret28#1; 13077934#L1655-45 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13077932#L1655-47 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13077930#L799-45 assume !(1 == ~t9_pc~0); 13077928#L799-47 is_transmit9_triggered_~__retres1~9#1 := 0; 13077926#L810-15 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13077924#is_transmit9_triggered_returnLabel#16 activate_threads_#t~ret29#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret29#1;havoc activate_threads_#t~ret29#1; 13077922#L1663-45 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13077920#L1663-47 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13077916#L818-45 assume !(1 == ~t10_pc~0); 13077918#L818-47 is_transmit10_triggered_~__retres1~10#1 := 0; 13078137#L829-15 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13078135#is_transmit10_triggered_returnLabel#16 activate_threads_#t~ret30#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret30#1;havoc activate_threads_#t~ret30#1; 13078133#L1671-45 assume !(0 != activate_threads_~tmp___9~0#1); 13078131#L1671-47 assume { :begin_inline_is_transmit11_triggered } true;havoc is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;havoc is_transmit11_triggered_~__retres1~11#1; 13078129#L837-45 assume !(1 == ~t11_pc~0); 13078127#L837-47 is_transmit11_triggered_~__retres1~11#1 := 0; 13078125#L848-15 is_transmit11_triggered_#res#1 := is_transmit11_triggered_~__retres1~11#1; 13078123#is_transmit11_triggered_returnLabel#16 activate_threads_#t~ret31#1 := is_transmit11_triggered_#res#1;havoc is_transmit11_triggered_~__retres1~11#1;assume { :end_inline_is_transmit11_triggered } true;activate_threads_~tmp___10~0#1 := activate_threads_#t~ret31#1;havoc activate_threads_#t~ret31#1; 13078121#L1679-45 assume 0 != activate_threads_~tmp___10~0#1;~t11_st~0 := 0; 13078119#L1679-47 assume { :begin_inline_is_transmit12_triggered } true;havoc is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;havoc is_transmit12_triggered_~__retres1~12#1; 13078117#L856-45 assume !(1 == ~t12_pc~0); 13078115#L856-47 is_transmit12_triggered_~__retres1~12#1 := 0; 13078112#L867-15 is_transmit12_triggered_#res#1 := is_transmit12_triggered_~__retres1~12#1; 13078110#is_transmit12_triggered_returnLabel#16 activate_threads_#t~ret32#1 := is_transmit12_triggered_#res#1;havoc is_transmit12_triggered_~__retres1~12#1;assume { :end_inline_is_transmit12_triggered } true;activate_threads_~tmp___11~0#1 := activate_threads_#t~ret32#1;havoc activate_threads_#t~ret32#1; 13078108#L1687-45 assume 0 != activate_threads_~tmp___11~0#1;~t12_st~0 := 0; 13078105#L1687-47 assume { :begin_inline_is_transmit13_triggered } true;havoc is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;havoc is_transmit13_triggered_~__retres1~13#1; 13078103#L875-45 assume !(1 == ~t13_pc~0); 13078101#L875-47 is_transmit13_triggered_~__retres1~13#1 := 0; 13078099#L886-15 is_transmit13_triggered_#res#1 := is_transmit13_triggered_~__retres1~13#1; 13078098#is_transmit13_triggered_returnLabel#16 activate_threads_#t~ret33#1 := is_transmit13_triggered_#res#1;havoc is_transmit13_triggered_~__retres1~13#1;assume { :end_inline_is_transmit13_triggered } true;activate_threads_~tmp___12~0#1 := activate_threads_#t~ret33#1;havoc activate_threads_#t~ret33#1; 13078097#L1695-45 assume 0 != activate_threads_~tmp___12~0#1;~t13_st~0 := 0; 13078096#L1695-47 havoc activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_#t~ret27#1, activate_threads_#t~ret28#1, activate_threads_#t~ret29#1, activate_threads_#t~ret30#1, activate_threads_#t~ret31#1, activate_threads_#t~ret32#1, activate_threads_#t~ret33#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1, activate_threads_~tmp___10~0#1, activate_threads_~tmp___11~0#1, activate_threads_~tmp___12~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13078095#L1427-3 assume !(1 == ~M_E~0); 12977556#L1427-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13078094#L1432-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13078092#L1437-3 assume !(1 == ~T3_E~0); 13078090#L1442-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13078088#L1447-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13078086#L1452-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13078084#L1457-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13078082#L1462-3 assume !(1 == ~T8_E~0); 13078080#L1467-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 13078078#L1472-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 13078076#L1477-3 assume !(1 == ~T11_E~0); 13078074#L1482-3 assume 1 == ~T12_E~0;~T12_E~0 := 2; 13078072#L1487-3 assume 1 == ~T13_E~0;~T13_E~0 := 2; 13078070#L1492-3 assume 1 == ~E_M~0;~E_M~0 := 2; 13078068#L1497-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13078066#L1502-3 assume !(1 == ~E_2~0); 13078064#L1507-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13078062#L1512-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13078060#L1517-3 assume !(1 == ~E_5~0); 13078058#L1522-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13078056#L1527-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13078054#L1532-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13078052#L1537-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12953251#L1542-3 assume !(1 == ~E_10~0); 12953249#L1547-3 assume 1 == ~E_11~0;~E_11~0 := 2; 12953247#L1552-3 assume 1 == ~E_12~0;~E_12~0 := 2; 12953245#L1557-3 assume !(1 == ~E_13~0); 12953243#L1562-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12953223#L980-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12953215#L1052-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12953213#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret35#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret35#1;havoc start_simulation_#t~ret35#1; 12953210#L1947 assume !(0 == start_simulation_~tmp~3#1); 12953207#L1947-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;havoc exists_runnable_thread_~__retres1~14#1; 12953186#L980-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~14#1 := 1; 12953178#L1052-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~14#1; 12953176#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret34#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~14#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret34#1;havoc stop_simulation_#t~ret34#1; 12953174#L1902 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12953172#L1909 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12953170#stop_simulation_returnLabel#1 start_simulation_#t~ret36#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret34#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret36#1;havoc start_simulation_#t~ret36#1; 12953168#L1960 assume !(0 != start_simulation_~tmp___0~1#1); 12859515#L1928-2 [2023-11-29 03:24:08,006 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:24:08,006 INFO L85 PathProgramCache]: Analyzing trace with hash -537341627, now seen corresponding path program 2 times [2023-11-29 03:24:08,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:24:08,006 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1273164824] [2023-11-29 03:24:08,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:24:08,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:24:08,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:24:08,017 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 03:24:08,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 03:24:08,084 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 03:24:08,085 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 03:24:08,085 INFO L85 PathProgramCache]: Analyzing trace with hash 1233401330, now seen corresponding path program 1 times [2023-11-29 03:24:08,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 03:24:08,086 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1745553899] [2023-11-29 03:24:08,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 03:24:08,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 03:24:08,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 03:24:08,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 03:24:08,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 03:24:08,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1745553899] [2023-11-29 03:24:08,154 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1745553899] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 03:24:08,154 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 03:24:08,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 03:24:08,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2025253319] [2023-11-29 03:24:08,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 03:24:08,155 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 03:24:08,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 03:24:08,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 03:24:08,156 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 03:24:08,156 INFO L87 Difference]: Start difference. First operand 1017111 states and 1388498 transitions. cyclomatic complexity: 371515 Second operand has 5 states, 5 states have (on average 32.8) internal successors, (164), 5 states have internal predecessors, (164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 03:24:14,286 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 03:24:14,286 INFO L93 Difference]: Finished difference Result 1907671 states and 2583794 transitions. [2023-11-29 03:24:14,286 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1907671 states and 2583794 transitions. [2023-11-29 03:24:22,651 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 1897216 [2023-11-29 03:24:27,323 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1907671 states to 1907671 states and 2583794 transitions. [2023-11-29 03:24:27,323 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1907671 [2023-11-29 03:24:28,034 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1907671 [2023-11-29 03:24:28,034 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1907671 states and 2583794 transitions. [2023-11-29 03:24:28,915 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 03:24:28,915 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1907671 states and 2583794 transitions. [2023-11-29 03:24:30,324 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1907671 states and 2583794 transitions.