./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.01.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.01.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 01:38:52,457 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 01:38:52,522 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 01:38:52,527 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 01:38:52,527 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 01:38:52,553 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 01:38:52,554 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 01:38:52,554 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 01:38:52,555 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 01:38:52,556 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 01:38:52,557 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 01:38:52,557 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 01:38:52,558 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 01:38:52,558 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 01:38:52,559 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 01:38:52,559 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 01:38:52,560 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 01:38:52,560 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 01:38:52,561 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 01:38:52,562 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 01:38:52,562 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 01:38:52,563 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 01:38:52,563 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 01:38:52,564 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 01:38:52,564 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 01:38:52,565 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 01:38:52,565 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 01:38:52,566 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 01:38:52,566 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 01:38:52,567 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 01:38:52,567 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 01:38:52,568 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 01:38:52,568 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 01:38:52,568 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 01:38:52,568 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 01:38:52,569 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 01:38:52,569 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 01:38:52,569 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 01:38:52,570 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> ea17b00cb6ed3e05e0ac7861fb220a62ceca6ba97bc4fe703ce3eb0d0ec5cbfe [2023-11-29 01:38:52,773 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 01:38:52,795 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 01:38:52,798 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 01:38:52,799 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 01:38:52,800 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 01:38:52,801 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/transmitter.01.cil.c [2023-11-29 01:38:55,615 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 01:38:55,778 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 01:38:55,778 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/sv-benchmarks/c/systemc/transmitter.01.cil.c [2023-11-29 01:38:55,788 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/data/df2efacb1/20f6f99db04a4b7d82dbc51595e2b4f7/FLAG543caafae [2023-11-29 01:38:55,800 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/data/df2efacb1/20f6f99db04a4b7d82dbc51595e2b4f7 [2023-11-29 01:38:55,802 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 01:38:55,804 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 01:38:55,805 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 01:38:55,805 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 01:38:55,810 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 01:38:55,810 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 01:38:55" (1/1) ... [2023-11-29 01:38:55,811 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@3fba31b3 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:55, skipping insertion in model container [2023-11-29 01:38:55,812 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 01:38:55" (1/1) ... [2023-11-29 01:38:55,845 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 01:38:55,998 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 01:38:56,011 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 01:38:56,045 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 01:38:56,062 INFO L206 MainTranslator]: Completed translation [2023-11-29 01:38:56,062 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56 WrapperNode [2023-11-29 01:38:56,063 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 01:38:56,064 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 01:38:56,064 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 01:38:56,064 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 01:38:56,072 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,080 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,111 INFO L138 Inliner]: procedures = 30, calls = 34, calls flagged for inlining = 29, calls inlined = 35, statements flattened = 361 [2023-11-29 01:38:56,112 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 01:38:56,112 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 01:38:56,112 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 01:38:56,113 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 01:38:56,124 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,124 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,127 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,139 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 01:38:56,139 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,140 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,147 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,154 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,156 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,158 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,162 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 01:38:56,163 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 01:38:56,163 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 01:38:56,164 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 01:38:56,165 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (1/1) ... [2023-11-29 01:38:56,171 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:56,183 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:56,201 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:56,207 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 01:38:56,233 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 01:38:56,233 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 01:38:56,234 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 01:38:56,234 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 01:38:56,307 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 01:38:56,309 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 01:38:56,620 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 01:38:56,632 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 01:38:56,633 INFO L309 CfgBuilder]: Removed 5 assume(true) statements. [2023-11-29 01:38:56,634 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:38:56 BoogieIcfgContainer [2023-11-29 01:38:56,634 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 01:38:56,635 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 01:38:56,635 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 01:38:56,638 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 01:38:56,638 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:38:56,639 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 01:38:55" (1/3) ... [2023-11-29 01:38:56,639 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5e2086f6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 01:38:56, skipping insertion in model container [2023-11-29 01:38:56,639 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:38:56,640 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:38:56" (2/3) ... [2023-11-29 01:38:56,640 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@5e2086f6 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 01:38:56, skipping insertion in model container [2023-11-29 01:38:56,640 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:38:56,640 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:38:56" (3/3) ... [2023-11-29 01:38:56,641 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.01.cil.c [2023-11-29 01:38:56,687 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 01:38:56,687 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 01:38:56,687 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 01:38:56,687 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 01:38:56,687 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 01:38:56,687 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 01:38:56,688 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 01:38:56,688 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 01:38:56,692 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:56,715 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2023-11-29 01:38:56,716 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:38:56,716 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:38:56,722 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:56,722 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:56,722 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 01:38:56,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:56,730 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 103 [2023-11-29 01:38:56,731 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:38:56,731 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:38:56,733 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:56,733 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:56,741 INFO L748 eck$LassoCheckResult]: Stem: 31#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 48#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 134#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 43#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13#L161true assume !(1 == ~m_i~0);~m_st~0 := 2; 5#L161-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 80#L166-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 89#L250true assume !(0 == ~M_E~0); 108#L250-2true assume !(0 == ~T1_E~0); 39#L255-1true assume !(0 == ~E_1~0); 81#L260-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 55#L115true assume !(1 == ~m_pc~0); 59#L115-2true is_master_triggered_~__retres1~0#1 := 0; 69#L126true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8#is_master_triggered_returnLabel#1true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 66#L300true assume !(0 != activate_threads_~tmp~1#1); 107#L300-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 121#L134true assume 1 == ~t1_pc~0; 109#L135true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 57#L145true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10#L308true assume !(0 != activate_threads_~tmp___0~0#1); 62#L308-2true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60#L273true assume !(1 == ~M_E~0); 113#L273-2true assume !(1 == ~T1_E~0); 102#L278-1true assume !(1 == ~E_1~0); 72#L283-1true assume { :end_inline_reset_delta_events } true; 58#L404-2true [2023-11-29 01:38:56,742 INFO L750 eck$LassoCheckResult]: Loop: 58#L404-2true assume !false; 82#L405true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 96#L225-1true assume false; 85#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 117#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 120#L250-3true assume 0 == ~M_E~0;~M_E~0 := 1; 98#L250-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 104#L255-3true assume 0 == ~E_1~0;~E_1~0 := 1; 6#L260-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49#L115-6true assume 1 == ~m_pc~0; 116#L116-2true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 135#L126-2true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 54#is_master_triggered_returnLabel#3true activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 74#L300-6true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 118#L300-8true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 133#L134-6true assume !(1 == ~t1_pc~0); 32#L134-8true is_transmit1_triggered_~__retres1~1#1 := 0; 53#L145-2true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 125#is_transmit1_triggered_returnLabel#3true activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 50#L308-6true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7#L308-8true havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 130#L273-3true assume 1 == ~M_E~0;~M_E~0 := 2; 45#L273-5true assume !(1 == ~T1_E~0); 33#L278-3true assume 1 == ~E_1~0;~E_1~0 := 2; 95#L283-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 76#L179-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 114#L191-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 100#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 19#L423true assume !(0 == start_simulation_~tmp~3#1); 18#L423-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 22#L179-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 73#L191-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 37#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 16#L378true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17#L385true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 136#stop_simulation_returnLabel#1true start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 44#L436true assume !(0 != start_simulation_~tmp___0~1#1); 58#L404-2true [2023-11-29 01:38:56,748 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:56,749 INFO L85 PathProgramCache]: Analyzing trace with hash 920294251, now seen corresponding path program 1 times [2023-11-29 01:38:56,758 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:56,759 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099532487] [2023-11-29 01:38:56,759 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:56,759 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:56,840 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:56,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:56,922 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:56,922 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099532487] [2023-11-29 01:38:56,923 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099532487] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:56,923 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:56,923 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:38:56,925 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [802018815] [2023-11-29 01:38:56,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:56,930 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:38:56,930 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:56,931 INFO L85 PathProgramCache]: Analyzing trace with hash 1288992519, now seen corresponding path program 1 times [2023-11-29 01:38:56,931 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:56,931 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1135049560] [2023-11-29 01:38:56,931 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:56,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:56,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:56,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:56,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:56,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1135049560] [2023-11-29 01:38:56,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1135049560] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:56,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:56,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:38:56,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1140751433] [2023-11-29 01:38:56,961 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:56,962 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:38:56,963 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:38:56,995 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:38:56,996 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:38:56,999 INFO L87 Difference]: Start difference. First operand has 136 states, 135 states have (on average 1.511111111111111) internal successors, (204), 135 states have internal predecessors, (204), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 3 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,026 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:38:57,026 INFO L93 Difference]: Finished difference Result 134 states and 190 transitions. [2023-11-29 01:38:57,028 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 134 states and 190 transitions. [2023-11-29 01:38:57,032 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2023-11-29 01:38:57,037 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 134 states to 128 states and 184 transitions. [2023-11-29 01:38:57,038 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 128 [2023-11-29 01:38:57,039 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 128 [2023-11-29 01:38:57,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 128 states and 184 transitions. [2023-11-29 01:38:57,040 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:38:57,041 INFO L218 hiAutomatonCegarLoop]: Abstraction has 128 states and 184 transitions. [2023-11-29 01:38:57,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 128 states and 184 transitions. [2023-11-29 01:38:57,072 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 128 to 128. [2023-11-29 01:38:57,073 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 128 states, 128 states have (on average 1.4375) internal successors, (184), 127 states have internal predecessors, (184), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,074 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 128 states to 128 states and 184 transitions. [2023-11-29 01:38:57,075 INFO L240 hiAutomatonCegarLoop]: Abstraction has 128 states and 184 transitions. [2023-11-29 01:38:57,076 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:38:57,079 INFO L428 stractBuchiCegarLoop]: Abstraction has 128 states and 184 transitions. [2023-11-29 01:38:57,080 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 01:38:57,080 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 128 states and 184 transitions. [2023-11-29 01:38:57,082 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 99 [2023-11-29 01:38:57,082 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:38:57,082 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:38:57,084 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:57,084 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:57,084 INFO L748 eck$LassoCheckResult]: Stem: 329#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 330#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 352#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 348#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 298#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 283#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 284#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 381#L250 assume !(0 == ~M_E~0); 390#L250-2 assume !(0 == ~T1_E~0); 342#L255-1 assume !(0 == ~E_1~0); 343#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 359#L115 assume !(1 == ~m_pc~0); 325#L115-2 is_master_triggered_~__retres1~0#1 := 0; 326#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 289#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 290#L300 assume !(0 != activate_threads_~tmp~1#1); 368#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 400#L134 assume 1 == ~t1_pc~0; 401#L135 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 361#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 341#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 292#L308 assume !(0 != activate_threads_~tmp___0~0#1); 293#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 363#L273 assume !(1 == ~M_E~0); 364#L273-2 assume !(1 == ~T1_E~0); 398#L278-1 assume !(1 == ~E_1~0); 372#L283-1 assume { :end_inline_reset_delta_events } true; 347#L404-2 [2023-11-29 01:38:57,085 INFO L750 eck$LassoCheckResult]: Loop: 347#L404-2 assume !false; 362#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 380#L225-1 assume !false; 386#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 387#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 328#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 299#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 300#L206 assume !(0 != eval_~tmp~0#1); 338#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 383#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 405#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 395#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 396#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 285#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 286#L115-6 assume !(1 == ~m_pc~0); 353#L115-8 is_master_triggered_~__retres1~0#1 := 0; 404#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 357#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 358#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 373#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 406#L134-6 assume !(1 == ~t1_pc~0); 331#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 332#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 356#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 355#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 287#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 288#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 349#L273-5 assume !(1 == ~T1_E~0); 333#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 334#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 375#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 376#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 397#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 309#L423 assume !(0 == start_simulation_~tmp~3#1); 307#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 308#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 313#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 340#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 301#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 302#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 306#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 346#L436 assume !(0 != start_simulation_~tmp___0~1#1); 347#L404-2 [2023-11-29 01:38:57,085 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:57,085 INFO L85 PathProgramCache]: Analyzing trace with hash -1569234711, now seen corresponding path program 1 times [2023-11-29 01:38:57,086 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:57,086 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196815156] [2023-11-29 01:38:57,086 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:57,086 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:57,103 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:57,155 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:57,155 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:57,155 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [196815156] [2023-11-29 01:38:57,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [196815156] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:57,156 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:57,156 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:38:57,156 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [29761761] [2023-11-29 01:38:57,156 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:57,157 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:38:57,157 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:57,158 INFO L85 PathProgramCache]: Analyzing trace with hash 487194975, now seen corresponding path program 1 times [2023-11-29 01:38:57,158 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:57,158 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [498974448] [2023-11-29 01:38:57,158 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:57,159 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:57,174 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:57,213 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:57,214 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:57,214 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [498974448] [2023-11-29 01:38:57,214 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [498974448] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:57,214 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:57,215 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:38:57,215 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [836896091] [2023-11-29 01:38:57,215 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:57,215 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:38:57,216 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:38:57,216 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:38:57,216 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:38:57,216 INFO L87 Difference]: Start difference. First operand 128 states and 184 transitions. cyclomatic complexity: 57 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,257 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:38:57,257 INFO L93 Difference]: Finished difference Result 222 states and 313 transitions. [2023-11-29 01:38:57,257 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 222 states and 313 transitions. [2023-11-29 01:38:57,261 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 192 [2023-11-29 01:38:57,263 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 222 states to 222 states and 313 transitions. [2023-11-29 01:38:57,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 222 [2023-11-29 01:38:57,264 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 222 [2023-11-29 01:38:57,264 INFO L73 IsDeterministic]: Start isDeterministic. Operand 222 states and 313 transitions. [2023-11-29 01:38:57,266 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:38:57,266 INFO L218 hiAutomatonCegarLoop]: Abstraction has 222 states and 313 transitions. [2023-11-29 01:38:57,267 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 222 states and 313 transitions. [2023-11-29 01:38:57,278 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 222 to 218. [2023-11-29 01:38:57,279 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 218 states, 218 states have (on average 1.4128440366972477) internal successors, (308), 217 states have internal predecessors, (308), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,280 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 308 transitions. [2023-11-29 01:38:57,280 INFO L240 hiAutomatonCegarLoop]: Abstraction has 218 states and 308 transitions. [2023-11-29 01:38:57,281 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:38:57,282 INFO L428 stractBuchiCegarLoop]: Abstraction has 218 states and 308 transitions. [2023-11-29 01:38:57,282 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 01:38:57,282 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 218 states and 308 transitions. [2023-11-29 01:38:57,284 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2023-11-29 01:38:57,284 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:38:57,285 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:38:57,286 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:57,286 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:57,287 INFO L748 eck$LassoCheckResult]: Stem: 688#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 689#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 712#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 708#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 655#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 640#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 641#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 746#L250 assume !(0 == ~M_E~0); 762#L250-2 assume !(0 == ~T1_E~0); 702#L255-1 assume !(0 == ~E_1~0); 703#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 720#L115 assume !(1 == ~m_pc~0); 683#L115-2 is_master_triggered_~__retres1~0#1 := 0; 684#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 646#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 647#L300 assume !(0 != activate_threads_~tmp~1#1); 730#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 770#L134 assume !(1 == ~t1_pc~0); 728#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 721#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 700#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 651#L308 assume !(0 != activate_threads_~tmp___0~0#1); 652#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 724#L273 assume !(1 == ~M_E~0); 725#L273-2 assume !(1 == ~T1_E~0); 768#L278-1 assume !(1 == ~E_1~0); 736#L283-1 assume { :end_inline_reset_delta_events } true; 722#L404-2 [2023-11-29 01:38:57,287 INFO L750 eck$LassoCheckResult]: Loop: 722#L404-2 assume !false; 723#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 814#L225-1 assume !false; 813#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 811#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 810#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 809#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 808#L206 assume !(0 != eval_~tmp~0#1); 806#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 803#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 801#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 799#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 797#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 794#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 792#L115-6 assume 1 == ~m_pc~0; 775#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 776#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 717#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 718#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 737#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 783#L134-6 assume !(1 == ~t1_pc~0); 784#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 850#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 849#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 848#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 846#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 844#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 842#L273-5 assume !(1 == ~T1_E~0); 841#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 840#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 838#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 836#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 834#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 832#L423 assume !(0 == start_simulation_~tmp~3#1); 831#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 670#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 671#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 829#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 828#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 827#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 826#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 825#L436 assume !(0 != start_simulation_~tmp___0~1#1); 722#L404-2 [2023-11-29 01:38:57,288 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:57,288 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 1 times [2023-11-29 01:38:57,288 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:57,288 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957565722] [2023-11-29 01:38:57,288 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:57,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:57,300 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:57,300 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:38:57,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:57,325 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:38:57,326 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:57,326 INFO L85 PathProgramCache]: Analyzing trace with hash 795633984, now seen corresponding path program 1 times [2023-11-29 01:38:57,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:57,327 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1097230090] [2023-11-29 01:38:57,327 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:57,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:57,339 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:57,373 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:57,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:57,374 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1097230090] [2023-11-29 01:38:57,374 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1097230090] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:57,374 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:57,374 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:38:57,374 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [625401917] [2023-11-29 01:38:57,375 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:57,375 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:38:57,375 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:38:57,376 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:38:57,376 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:38:57,376 INFO L87 Difference]: Start difference. First operand 218 states and 308 transitions. cyclomatic complexity: 92 Second operand has 3 states, 3 states have (on average 14.0) internal successors, (42), 3 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,406 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:38:57,406 INFO L93 Difference]: Finished difference Result 270 states and 380 transitions. [2023-11-29 01:38:57,406 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 270 states and 380 transitions. [2023-11-29 01:38:57,409 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 225 [2023-11-29 01:38:57,413 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 270 states to 270 states and 380 transitions. [2023-11-29 01:38:57,413 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 270 [2023-11-29 01:38:57,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 270 [2023-11-29 01:38:57,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 270 states and 380 transitions. [2023-11-29 01:38:57,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:38:57,416 INFO L218 hiAutomatonCegarLoop]: Abstraction has 270 states and 380 transitions. [2023-11-29 01:38:57,417 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 270 states and 380 transitions. [2023-11-29 01:38:57,429 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 270 to 270. [2023-11-29 01:38:57,430 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 270 states, 270 states have (on average 1.4074074074074074) internal successors, (380), 269 states have internal predecessors, (380), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,431 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 270 states to 270 states and 380 transitions. [2023-11-29 01:38:57,431 INFO L240 hiAutomatonCegarLoop]: Abstraction has 270 states and 380 transitions. [2023-11-29 01:38:57,432 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:38:57,433 INFO L428 stractBuchiCegarLoop]: Abstraction has 270 states and 380 transitions. [2023-11-29 01:38:57,433 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 01:38:57,433 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 270 states and 380 transitions. [2023-11-29 01:38:57,435 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 225 [2023-11-29 01:38:57,435 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:38:57,435 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:38:57,436 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:57,437 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:57,437 INFO L748 eck$LassoCheckResult]: Stem: 1181#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1182#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1207#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1201#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1149#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 1134#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1135#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1242#L250 assume !(0 == ~M_E~0); 1254#L250-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1264#L255-1 assume !(0 == ~E_1~0); 1383#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1382#L115 assume !(1 == ~m_pc~0); 1380#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1378#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1288#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1287#L300 assume !(0 != activate_threads_~tmp~1#1); 1286#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1285#L134 assume !(1 == ~t1_pc~0); 1284#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1283#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1282#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1281#L308 assume !(0 != activate_threads_~tmp___0~0#1); 1279#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1221#L273 assume !(1 == ~M_E~0); 1222#L273-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1260#L278-1 assume !(1 == ~E_1~0); 1233#L283-1 assume { :end_inline_reset_delta_events } true; 1200#L404-2 [2023-11-29 01:38:57,437 INFO L750 eck$LassoCheckResult]: Loop: 1200#L404-2 assume !false; 1220#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1241#L225-1 assume !false; 1247#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1248#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1179#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1150#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1151#L206 assume !(0 != eval_~tmp~0#1); 1190#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1244#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1269#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1257#L250-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1258#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1399#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1398#L115-6 assume !(1 == ~m_pc~0); 1396#L115-8 is_master_triggered_~__retres1~0#1 := 0; 1395#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1394#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1393#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1392#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1391#L134-6 assume !(1 == ~t1_pc~0); 1390#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1212#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1213#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1210#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1138#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1139#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1202#L273-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1185#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1186#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1236#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1237#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1256#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 1160#L423 assume !(0 == start_simulation_~tmp~3#1); 1158#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1159#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1164#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1193#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1155#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1156#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1157#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1199#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1200#L404-2 [2023-11-29 01:38:57,438 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:57,438 INFO L85 PathProgramCache]: Analyzing trace with hash 784287684, now seen corresponding path program 1 times [2023-11-29 01:38:57,438 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:57,438 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2107814561] [2023-11-29 01:38:57,439 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:57,439 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:57,448 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:57,479 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:57,480 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:57,480 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2107814561] [2023-11-29 01:38:57,480 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2107814561] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:57,480 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:57,480 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:38:57,481 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [25628951] [2023-11-29 01:38:57,481 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:57,481 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:38:57,482 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:57,482 INFO L85 PathProgramCache]: Analyzing trace with hash 1767058653, now seen corresponding path program 1 times [2023-11-29 01:38:57,482 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:57,482 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1081490288] [2023-11-29 01:38:57,483 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:57,483 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:57,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:57,549 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:57,549 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:57,549 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1081490288] [2023-11-29 01:38:57,549 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1081490288] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:57,550 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:57,550 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:38:57,550 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [566032575] [2023-11-29 01:38:57,550 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:57,550 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:38:57,551 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:38:57,551 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:38:57,551 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:38:57,551 INFO L87 Difference]: Start difference. First operand 270 states and 380 transitions. cyclomatic complexity: 112 Second operand has 3 states, 3 states have (on average 9.0) internal successors, (27), 2 states have internal predecessors, (27), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,569 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:38:57,569 INFO L93 Difference]: Finished difference Result 218 states and 300 transitions. [2023-11-29 01:38:57,569 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 218 states and 300 transitions. [2023-11-29 01:38:57,572 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2023-11-29 01:38:57,574 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 218 states to 218 states and 300 transitions. [2023-11-29 01:38:57,574 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 218 [2023-11-29 01:38:57,574 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 218 [2023-11-29 01:38:57,575 INFO L73 IsDeterministic]: Start isDeterministic. Operand 218 states and 300 transitions. [2023-11-29 01:38:57,576 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:38:57,576 INFO L218 hiAutomatonCegarLoop]: Abstraction has 218 states and 300 transitions. [2023-11-29 01:38:57,576 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 218 states and 300 transitions. [2023-11-29 01:38:57,583 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 218 to 218. [2023-11-29 01:38:57,584 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 218 states, 218 states have (on average 1.3761467889908257) internal successors, (300), 217 states have internal predecessors, (300), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,586 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 218 states to 218 states and 300 transitions. [2023-11-29 01:38:57,586 INFO L240 hiAutomatonCegarLoop]: Abstraction has 218 states and 300 transitions. [2023-11-29 01:38:57,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:38:57,587 INFO L428 stractBuchiCegarLoop]: Abstraction has 218 states and 300 transitions. [2023-11-29 01:38:57,587 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 01:38:57,587 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 218 states and 300 transitions. [2023-11-29 01:38:57,589 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 190 [2023-11-29 01:38:57,589 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:38:57,589 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:38:57,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:57,591 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:57,591 INFO L748 eck$LassoCheckResult]: Stem: 1680#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 1681#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 1706#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1700#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1646#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 1631#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1632#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1737#L250 assume !(0 == ~M_E~0); 1750#L250-2 assume !(0 == ~T1_E~0); 1694#L255-1 assume !(0 == ~E_1~0); 1695#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1714#L115 assume !(1 == ~m_pc~0); 1674#L115-2 is_master_triggered_~__retres1~0#1 := 0; 1675#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1637#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1638#L300 assume !(0 != activate_threads_~tmp~1#1); 1724#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1757#L134 assume !(1 == ~t1_pc~0); 1722#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1716#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1693#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1640#L308 assume !(0 != activate_threads_~tmp___0~0#1); 1641#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1718#L273 assume !(1 == ~M_E~0); 1719#L273-2 assume !(1 == ~T1_E~0); 1755#L278-1 assume !(1 == ~E_1~0); 1727#L283-1 assume { :end_inline_reset_delta_events } true; 1728#L404-2 [2023-11-29 01:38:57,591 INFO L750 eck$LassoCheckResult]: Loop: 1728#L404-2 assume !false; 1802#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1800#L225-1 assume !false; 1798#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1794#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1791#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1789#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1787#L206 assume !(0 != eval_~tmp~0#1); 1739#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1740#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1762#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1753#L250-5 assume !(0 == ~T1_E~0); 1754#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1633#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1634#L115-6 assume !(1 == ~m_pc~0); 1831#L115-8 is_master_triggered_~__retres1~0#1 := 0; 1829#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1712#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 1713#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1729#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1763#L134-6 assume !(1 == ~t1_pc~0); 1682#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 1683#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1711#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 1710#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1635#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1636#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1701#L273-5 assume !(1 == ~T1_E~0); 1684#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1685#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1731#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1732#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1752#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 1657#L423 assume !(0 == start_simulation_~tmp~3#1); 1658#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 1827#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 1825#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 1824#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 1652#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1653#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1654#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 1765#L436 assume !(0 != start_simulation_~tmp___0~1#1); 1728#L404-2 [2023-11-29 01:38:57,592 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:57,592 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 2 times [2023-11-29 01:38:57,592 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:57,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [688696586] [2023-11-29 01:38:57,593 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:57,593 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:57,602 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:57,603 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:38:57,608 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:57,614 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:38:57,615 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:57,615 INFO L85 PathProgramCache]: Analyzing trace with hash 1188794849, now seen corresponding path program 1 times [2023-11-29 01:38:57,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:57,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1185299317] [2023-11-29 01:38:57,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:57,616 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:57,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:57,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:57,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:57,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1185299317] [2023-11-29 01:38:57,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1185299317] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:57,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:57,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:38:57,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [921732945] [2023-11-29 01:38:57,677 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:57,702 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:38:57,703 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:38:57,704 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:38:57,704 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:38:57,704 INFO L87 Difference]: Start difference. First operand 218 states and 300 transitions. cyclomatic complexity: 84 Second operand has 5 states, 5 states have (on average 8.4) internal successors, (42), 5 states have internal predecessors, (42), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,802 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:38:57,803 INFO L93 Difference]: Finished difference Result 365 states and 492 transitions. [2023-11-29 01:38:57,803 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 365 states and 492 transitions. [2023-11-29 01:38:57,805 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 337 [2023-11-29 01:38:57,807 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 365 states to 365 states and 492 transitions. [2023-11-29 01:38:57,808 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 365 [2023-11-29 01:38:57,808 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 365 [2023-11-29 01:38:57,808 INFO L73 IsDeterministic]: Start isDeterministic. Operand 365 states and 492 transitions. [2023-11-29 01:38:57,809 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:38:57,809 INFO L218 hiAutomatonCegarLoop]: Abstraction has 365 states and 492 transitions. [2023-11-29 01:38:57,809 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 365 states and 492 transitions. [2023-11-29 01:38:57,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 365 to 224. [2023-11-29 01:38:57,816 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 224 states, 224 states have (on average 1.3660714285714286) internal successors, (306), 223 states have internal predecessors, (306), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,817 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 224 states to 224 states and 306 transitions. [2023-11-29 01:38:57,817 INFO L240 hiAutomatonCegarLoop]: Abstraction has 224 states and 306 transitions. [2023-11-29 01:38:57,817 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-29 01:38:57,818 INFO L428 stractBuchiCegarLoop]: Abstraction has 224 states and 306 transitions. [2023-11-29 01:38:57,819 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 01:38:57,819 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 224 states and 306 transitions. [2023-11-29 01:38:57,820 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 196 [2023-11-29 01:38:57,821 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:38:57,821 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:38:57,822 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:57,822 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:57,822 INFO L748 eck$LassoCheckResult]: Stem: 2282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 2308#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2301#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2246#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2231#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2232#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2341#L250 assume !(0 == ~M_E~0); 2356#L250-2 assume !(0 == ~T1_E~0); 2295#L255-1 assume !(0 == ~E_1~0); 2296#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2316#L115 assume !(1 == ~m_pc~0); 2275#L115-2 is_master_triggered_~__retres1~0#1 := 0; 2276#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2237#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2238#L300 assume !(0 != activate_threads_~tmp~1#1); 2328#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2366#L134 assume !(1 == ~t1_pc~0); 2325#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2318#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2294#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2240#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2241#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2321#L273 assume !(1 == ~M_E~0); 2322#L273-2 assume !(1 == ~T1_E~0); 2363#L278-1 assume !(1 == ~E_1~0); 2332#L283-1 assume { :end_inline_reset_delta_events } true; 2300#L404-2 [2023-11-29 01:38:57,822 INFO L750 eck$LassoCheckResult]: Loop: 2300#L404-2 assume !false; 2418#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2417#L225-1 assume !false; 2416#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2379#L179 assume !(0 == ~m_st~0); 2277#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2279#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2397#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2395#L206 assume !(0 != eval_~tmp~0#1); 2345#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2346#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2374#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2361#L250-5 assume !(0 == ~T1_E~0); 2362#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2233#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2234#L115-6 assume !(1 == ~m_pc~0); 2309#L115-8 is_master_triggered_~__retres1~0#1 := 0; 2385#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2314#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 2315#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2333#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2375#L134-6 assume !(1 == ~t1_pc~0); 2284#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2285#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2377#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2378#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2235#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2236#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2302#L273-5 assume !(1 == ~T1_E~0); 2303#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2358#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2359#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2440#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2439#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2437#L423 assume !(0 == start_simulation_~tmp~3#1); 2255#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2256#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2428#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2426#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2424#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2422#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2421#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 2299#L436 assume !(0 != start_simulation_~tmp___0~1#1); 2300#L404-2 [2023-11-29 01:38:57,823 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:57,823 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 3 times [2023-11-29 01:38:57,823 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:57,823 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1717711964] [2023-11-29 01:38:57,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:57,824 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:57,830 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:57,830 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:38:57,835 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:57,840 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:38:57,840 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:57,840 INFO L85 PathProgramCache]: Analyzing trace with hash 1260103574, now seen corresponding path program 1 times [2023-11-29 01:38:57,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:57,841 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [928092898] [2023-11-29 01:38:57,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:57,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:57,851 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:57,898 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:57,898 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:57,899 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [928092898] [2023-11-29 01:38:57,899 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [928092898] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:57,899 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:57,899 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:38:57,899 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1267143063] [2023-11-29 01:38:57,900 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:57,900 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:38:57,900 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:38:57,901 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:38:57,901 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:38:57,901 INFO L87 Difference]: Start difference. First operand 224 states and 306 transitions. cyclomatic complexity: 84 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:57,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:38:57,987 INFO L93 Difference]: Finished difference Result 468 states and 621 transitions. [2023-11-29 01:38:57,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 468 states and 621 transitions. [2023-11-29 01:38:57,991 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 419 [2023-11-29 01:38:57,995 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 468 states to 468 states and 621 transitions. [2023-11-29 01:38:57,995 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 468 [2023-11-29 01:38:57,995 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 468 [2023-11-29 01:38:57,995 INFO L73 IsDeterministic]: Start isDeterministic. Operand 468 states and 621 transitions. [2023-11-29 01:38:57,996 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:38:57,996 INFO L218 hiAutomatonCegarLoop]: Abstraction has 468 states and 621 transitions. [2023-11-29 01:38:57,997 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 468 states and 621 transitions. [2023-11-29 01:38:58,001 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 468 to 245. [2023-11-29 01:38:58,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 245 states, 245 states have (on average 1.3346938775510204) internal successors, (327), 244 states have internal predecessors, (327), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:58,003 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245 states to 245 states and 327 transitions. [2023-11-29 01:38:58,003 INFO L240 hiAutomatonCegarLoop]: Abstraction has 245 states and 327 transitions. [2023-11-29 01:38:58,004 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 01:38:58,004 INFO L428 stractBuchiCegarLoop]: Abstraction has 245 states and 327 transitions. [2023-11-29 01:38:58,004 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 01:38:58,005 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 245 states and 327 transitions. [2023-11-29 01:38:58,007 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 214 [2023-11-29 01:38:58,007 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:38:58,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:38:58,008 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:58,008 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:58,008 INFO L748 eck$LassoCheckResult]: Stem: 2985#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 2986#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3010#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3002#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2951#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 2935#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2936#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3049#L250 assume !(0 == ~M_E~0); 3061#L250-2 assume !(0 == ~T1_E~0); 2998#L255-1 assume !(0 == ~E_1~0); 2999#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3019#L115 assume !(1 == ~m_pc~0); 2979#L115-2 is_master_triggered_~__retres1~0#1 := 0; 3025#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3035#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3032#L300 assume !(0 != activate_threads_~tmp~1#1); 3033#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3076#L134 assume !(1 == ~t1_pc~0); 3028#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3023#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2997#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 2945#L308 assume !(0 != activate_threads_~tmp___0~0#1); 2946#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3026#L273 assume !(1 == ~M_E~0); 3027#L273-2 assume !(1 == ~T1_E~0); 3070#L278-1 assume !(1 == ~E_1~0); 3038#L283-1 assume { :end_inline_reset_delta_events } true; 3004#L404-2 [2023-11-29 01:38:58,009 INFO L750 eck$LassoCheckResult]: Loop: 3004#L404-2 assume !false; 3024#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3048#L225-1 assume !false; 3055#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3056#L179 assume !(0 == ~m_st~0); 2981#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 2983#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3141#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3130#L206 assume !(0 != eval_~tmp~0#1); 3121#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3119#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3086#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3067#L250-5 assume !(0 == ~T1_E~0); 3068#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2937#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2938#L115-6 assume 1 == ~m_pc~0; 3081#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3082#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3017#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3018#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3040#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3085#L134-6 assume !(1 == ~t1_pc~0); 2987#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 2988#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3016#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3014#L308-6 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2939#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2940#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3005#L273-5 assume !(1 == ~T1_E~0); 2989#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2990#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3042#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3043#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3069#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 2962#L423 assume !(0 == start_simulation_~tmp~3#1); 2960#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 2961#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 2966#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 2996#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 2957#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2958#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2959#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 3003#L436 assume !(0 != start_simulation_~tmp___0~1#1); 3004#L404-2 [2023-11-29 01:38:58,009 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:58,009 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 4 times [2023-11-29 01:38:58,009 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:58,010 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [609252086] [2023-11-29 01:38:58,010 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:58,010 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:58,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:58,017 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:38:58,021 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:58,026 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:38:58,026 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:58,027 INFO L85 PathProgramCache]: Analyzing trace with hash 1568542583, now seen corresponding path program 1 times [2023-11-29 01:38:58,027 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:58,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013580699] [2023-11-29 01:38:58,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:58,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:58,036 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:58,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:58,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:58,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1013580699] [2023-11-29 01:38:58,087 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1013580699] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:58,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:58,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:38:58,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [241895861] [2023-11-29 01:38:58,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:58,088 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:38:58,088 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:38:58,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:38:58,089 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:38:58,089 INFO L87 Difference]: Start difference. First operand 245 states and 327 transitions. cyclomatic complexity: 84 Second operand has 5 states, 5 states have (on average 8.6) internal successors, (43), 5 states have internal predecessors, (43), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:58,173 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:38:58,173 INFO L93 Difference]: Finished difference Result 350 states and 459 transitions. [2023-11-29 01:38:58,173 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 350 states and 459 transitions. [2023-11-29 01:38:58,176 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 319 [2023-11-29 01:38:58,178 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 350 states to 350 states and 459 transitions. [2023-11-29 01:38:58,179 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 350 [2023-11-29 01:38:58,179 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 350 [2023-11-29 01:38:58,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 350 states and 459 transitions. [2023-11-29 01:38:58,179 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:38:58,179 INFO L218 hiAutomatonCegarLoop]: Abstraction has 350 states and 459 transitions. [2023-11-29 01:38:58,180 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 350 states and 459 transitions. [2023-11-29 01:38:58,182 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 350 to 254. [2023-11-29 01:38:58,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 254 states, 254 states have (on average 1.3070866141732282) internal successors, (332), 253 states have internal predecessors, (332), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:38:58,184 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 254 states to 254 states and 332 transitions. [2023-11-29 01:38:58,184 INFO L240 hiAutomatonCegarLoop]: Abstraction has 254 states and 332 transitions. [2023-11-29 01:38:58,184 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 01:38:58,185 INFO L428 stractBuchiCegarLoop]: Abstraction has 254 states and 332 transitions. [2023-11-29 01:38:58,185 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 01:38:58,185 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 254 states and 332 transitions. [2023-11-29 01:38:58,187 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 223 [2023-11-29 01:38:58,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:38:58,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:38:58,187 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:58,187 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:38:58,188 INFO L748 eck$LassoCheckResult]: Stem: 3591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 3592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 3614#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3607#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3558#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 3542#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3543#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3646#L250 assume !(0 == ~M_E~0); 3656#L250-2 assume !(0 == ~T1_E~0); 3603#L255-1 assume !(0 == ~E_1~0); 3604#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3621#L115 assume !(1 == ~m_pc~0); 3585#L115-2 is_master_triggered_~__retres1~0#1 := 0; 3625#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3548#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3549#L300 assume !(0 != activate_threads_~tmp~1#1); 3632#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3669#L134 assume !(1 == ~t1_pc~0); 3628#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3623#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3602#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3552#L308 assume !(0 != activate_threads_~tmp___0~0#1); 3553#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3626#L273 assume !(1 == ~M_E~0); 3627#L273-2 assume !(1 == ~T1_E~0); 3664#L278-1 assume !(1 == ~E_1~0); 3636#L283-1 assume { :end_inline_reset_delta_events } true; 3637#L404-2 [2023-11-29 01:38:58,188 INFO L750 eck$LassoCheckResult]: Loop: 3637#L404-2 assume !false; 3731#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3730#L225-1 assume !false; 3729#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3728#L179 assume !(0 == ~m_st~0); 3727#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 3725#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3719#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3720#L206 assume !(0 != eval_~tmp~0#1); 3723#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3722#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3721#L250-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3661#L250-5 assume !(0 == ~T1_E~0); 3662#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3666#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3697#L115-6 assume 1 == ~m_pc~0; 3698#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3693#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3691#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 3689#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3685#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3683#L134-6 assume !(1 == ~t1_pc~0); 3684#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 3771#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3770#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 3769#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 3768#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3767#L273-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3765#L273-5 assume !(1 == ~T1_E~0); 3763#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3761#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3759#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3756#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3754#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 3750#L423 assume !(0 == start_simulation_~tmp~3#1); 3749#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 3745#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 3743#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 3741#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 3739#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3738#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3736#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 3734#L436 assume !(0 != start_simulation_~tmp___0~1#1); 3637#L404-2 [2023-11-29 01:38:58,188 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:58,188 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 5 times [2023-11-29 01:38:58,188 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:58,189 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1267043578] [2023-11-29 01:38:58,189 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:58,189 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:58,195 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:58,195 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:38:58,198 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:58,202 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:38:58,203 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:58,203 INFO L85 PathProgramCache]: Analyzing trace with hash -425602123, now seen corresponding path program 1 times [2023-11-29 01:38:58,203 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:58,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1564429233] [2023-11-29 01:38:58,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:58,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:58,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:58,212 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:38:58,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:38:58,220 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:38:58,221 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:58,221 INFO L85 PathProgramCache]: Analyzing trace with hash 1027369614, now seen corresponding path program 1 times [2023-11-29 01:38:58,221 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:38:58,221 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [176759953] [2023-11-29 01:38:58,222 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:38:58,222 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:38:58,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:58,259 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:38:58,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:38:58,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [176759953] [2023-11-29 01:38:58,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [176759953] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:38:58,260 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:38:58,260 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:38:58,261 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [270391780] [2023-11-29 01:38:58,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:38:58,656 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 01:38:58,656 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 01:38:58,657 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 01:38:58,657 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 01:38:58,657 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-29 01:38:58,657 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:58,657 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 01:38:58,657 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 01:38:58,657 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.01.cil.c_Iteration8_Loop [2023-11-29 01:38:58,657 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 01:38:58,657 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 01:38:58,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,693 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,707 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,715 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,727 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,730 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,755 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,758 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,763 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,766 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,773 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,776 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,781 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:58,787 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,019 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 01:38:59,020 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-29 01:38:59,022 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,022 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,027 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,028 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-29 01:38:59,029 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 01:38:59,030 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,049 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 01:38:59,049 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 01:38:59,058 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Ended with exit code 0 [2023-11-29 01:38:59,059 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,059 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,060 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,063 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-29 01:38:59,065 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 01:38:59,065 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,107 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 01:38:59,107 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Honda state: {ULTIMATE.start_stop_simulation_~__retres2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 01:38:59,111 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2023-11-29 01:38:59,112 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,112 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,113 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,116 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-29 01:38:59,117 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 01:38:59,117 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,133 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 01:38:59,133 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 01:38:59,137 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2023-11-29 01:38:59,137 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,137 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,138 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,143 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-29 01:38:59,147 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 01:38:59,147 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,163 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 01:38:59,163 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 01:38:59,167 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Forceful destruction successful, exit code 0 [2023-11-29 01:38:59,168 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,168 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,169 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,171 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-29 01:38:59,173 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 01:38:59,173 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,188 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 01:38:59,189 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_#res#1=1} Honda state: {ULTIMATE.start_is_master_triggered_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 01:38:59,192 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2023-11-29 01:38:59,192 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,193 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,194 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,196 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-29 01:38:59,197 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 01:38:59,197 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,214 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 01:38:59,214 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_~__retres1~2#1=0} Honda state: {ULTIMATE.start_exists_runnable_thread_~__retres1~2#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 01:38:59,218 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2023-11-29 01:38:59,219 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,219 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,220 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,222 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-29 01:38:59,223 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 01:38:59,223 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,239 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 01:38:59,239 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Honda state: {ULTIMATE.start_is_master_triggered_~__retres1~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 01:38:59,242 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-29 01:38:59,243 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,243 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,244 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,246 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-29 01:38:59,247 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 01:38:59,248 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,263 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 01:38:59,264 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 01:38:59,267 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-29 01:38:59,268 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,268 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,269 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,271 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-29 01:38:59,272 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 01:38:59,272 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,294 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 01:38:59,295 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_pc~0=4} Honda state: {~t1_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 01:38:59,299 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2023-11-29 01:38:59,299 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,300 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,300 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,308 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-29 01:38:59,309 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 01:38:59,309 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,327 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-29 01:38:59,328 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,328 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,329 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,331 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-29 01:38:59,336 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-29 01:38:59,336 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 01:38:59,352 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-29 01:38:59,355 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2023-11-29 01:38:59,356 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 01:38:59,356 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 01:38:59,356 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 01:38:59,356 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 01:38:59,356 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-29 01:38:59,356 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,356 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 01:38:59,356 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 01:38:59,356 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.01.cil.c_Iteration8_Loop [2023-11-29 01:38:59,356 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 01:38:59,356 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 01:38:59,359 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,362 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,365 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,367 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,370 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,373 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,375 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,378 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,381 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,386 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,388 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,391 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,394 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,397 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,402 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,405 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,407 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,411 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,415 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,417 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,420 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,423 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,426 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,428 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,431 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,433 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,435 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,437 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,440 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,442 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,445 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,450 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 01:38:59,653 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 01:38:59,657 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-29 01:38:59,659 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,659 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,660 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,662 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-29 01:38:59,663 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 01:38:59,676 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 01:38:59,677 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 01:38:59,677 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 01:38:59,677 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 01:38:59,677 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 01:38:59,679 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 01:38:59,680 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 01:38:59,682 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 01:38:59,686 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2023-11-29 01:38:59,686 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,686 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,687 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,689 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-29 01:38:59,691 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 01:38:59,701 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 01:38:59,702 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 01:38:59,702 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 01:38:59,702 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 01:38:59,702 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 01:38:59,702 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 01:38:59,703 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 01:38:59,704 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 01:38:59,707 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2023-11-29 01:38:59,707 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,707 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,708 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,710 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-29 01:38:59,711 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 01:38:59,722 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 01:38:59,722 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 01:38:59,722 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 01:38:59,722 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 01:38:59,722 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 01:38:59,722 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 01:38:59,723 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 01:38:59,724 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 01:38:59,727 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2023-11-29 01:38:59,727 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,727 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,728 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,730 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-29 01:38:59,731 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 01:38:59,742 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 01:38:59,742 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 01:38:59,742 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 01:38:59,742 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 01:38:59,742 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 01:38:59,743 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 01:38:59,743 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 01:38:59,746 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 01:38:59,749 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2023-11-29 01:38:59,749 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,749 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,750 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,753 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-29 01:38:59,755 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 01:38:59,765 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 01:38:59,765 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 01:38:59,765 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 01:38:59,766 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 01:38:59,766 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 01:38:59,766 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 01:38:59,766 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 01:38:59,767 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 01:38:59,770 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2023-11-29 01:38:59,770 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,770 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,771 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,772 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-29 01:38:59,773 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 01:38:59,784 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 01:38:59,784 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 01:38:59,784 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 01:38:59,784 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 01:38:59,784 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 01:38:59,784 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 01:38:59,784 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 01:38:59,786 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 01:38:59,789 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2023-11-29 01:38:59,790 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,790 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,790 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,791 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-29 01:38:59,793 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 01:38:59,804 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 01:38:59,804 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 01:38:59,804 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 01:38:59,804 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 01:38:59,804 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 01:38:59,805 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 01:38:59,805 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 01:38:59,806 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 01:38:59,809 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2023-11-29 01:38:59,809 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,810 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,810 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,816 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-29 01:38:59,817 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 01:38:59,827 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 01:38:59,827 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 01:38:59,827 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 01:38:59,827 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 01:38:59,828 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 01:38:59,828 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 01:38:59,829 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 01:38:59,838 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 01:38:59,841 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2023-11-29 01:38:59,842 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,842 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,843 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,846 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-29 01:38:59,847 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 01:38:59,857 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 01:38:59,857 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 01:38:59,857 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 01:38:59,857 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 01:38:59,857 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 01:38:59,858 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 01:38:59,858 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 01:38:59,861 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-29 01:38:59,865 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-29 01:38:59,866 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-29 01:38:59,867 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:38:59,867 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:38:59,899 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:38:59,902 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-29 01:38:59,902 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-29 01:38:59,902 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-29 01:38:59,903 INFO L513 LassoAnalysis]: Proved termination. [2023-11-29 01:38:59,903 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2023-11-29 01:38:59,906 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2023-11-29 01:38:59,909 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-29 01:38:59,928 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:38:59,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:38:59,952 INFO L262 TraceCheckSpWp]: Trace formula consists of 83 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-29 01:38:59,954 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 01:39:00,007 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2023-11-29 01:39:00,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:39:00,029 INFO L262 TraceCheckSpWp]: Trace formula consists of 92 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-29 01:39:00,031 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 01:39:00,174 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:39:00,178 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-29 01:39:00,180 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 254 states and 332 transitions. cyclomatic complexity: 80 Second operand has 5 states, 5 states have (on average 14.0) internal successors, (70), 5 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,259 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 254 states and 332 transitions. cyclomatic complexity: 80. Second operand has 5 states, 5 states have (on average 14.0) internal successors, (70), 5 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 618 states and 813 transitions. Complement of second has 5 states. [2023-11-29 01:39:00,260 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-29 01:39:00,260 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 14.0) internal successors, (70), 5 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,261 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 150 transitions. [2023-11-29 01:39:00,263 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 150 transitions. Stem has 27 letters. Loop has 43 letters. [2023-11-29 01:39:00,265 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 01:39:00,266 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 150 transitions. Stem has 70 letters. Loop has 43 letters. [2023-11-29 01:39:00,267 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 01:39:00,267 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 150 transitions. Stem has 27 letters. Loop has 86 letters. [2023-11-29 01:39:00,270 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 01:39:00,270 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 618 states and 813 transitions. [2023-11-29 01:39:00,276 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 400 [2023-11-29 01:39:00,282 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 618 states to 618 states and 813 transitions. [2023-11-29 01:39:00,283 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 432 [2023-11-29 01:39:00,283 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 437 [2023-11-29 01:39:00,283 INFO L73 IsDeterministic]: Start isDeterministic. Operand 618 states and 813 transitions. [2023-11-29 01:39:00,284 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 01:39:00,284 INFO L218 hiAutomatonCegarLoop]: Abstraction has 618 states and 813 transitions. [2023-11-29 01:39:00,285 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 618 states and 813 transitions. [2023-11-29 01:39:00,296 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 618 to 613. [2023-11-29 01:39:00,298 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 613 states, 613 states have (on average 1.3115823817292007) internal successors, (804), 612 states have internal predecessors, (804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,301 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 613 states to 613 states and 804 transitions. [2023-11-29 01:39:00,301 INFO L240 hiAutomatonCegarLoop]: Abstraction has 613 states and 804 transitions. [2023-11-29 01:39:00,301 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:39:00,302 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:39:00,302 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:39:00,302 INFO L87 Difference]: Start difference. First operand 613 states and 804 transitions. Second operand has 3 states, 3 states have (on average 23.333333333333332) internal successors, (70), 3 states have internal predecessors, (70), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,338 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:39:00,338 INFO L93 Difference]: Finished difference Result 976 states and 1235 transitions. [2023-11-29 01:39:00,338 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 976 states and 1235 transitions. [2023-11-29 01:39:00,347 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 656 [2023-11-29 01:39:00,356 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 976 states to 976 states and 1235 transitions. [2023-11-29 01:39:00,356 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 688 [2023-11-29 01:39:00,357 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 688 [2023-11-29 01:39:00,357 INFO L73 IsDeterministic]: Start isDeterministic. Operand 976 states and 1235 transitions. [2023-11-29 01:39:00,357 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 01:39:00,357 INFO L218 hiAutomatonCegarLoop]: Abstraction has 976 states and 1235 transitions. [2023-11-29 01:39:00,359 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 976 states and 1235 transitions. [2023-11-29 01:39:00,375 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 976 to 904. [2023-11-29 01:39:00,377 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 904 states, 904 states have (on average 1.2765486725663717) internal successors, (1154), 903 states have internal predecessors, (1154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,382 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 904 states to 904 states and 1154 transitions. [2023-11-29 01:39:00,382 INFO L240 hiAutomatonCegarLoop]: Abstraction has 904 states and 1154 transitions. [2023-11-29 01:39:00,382 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:39:00,383 INFO L428 stractBuchiCegarLoop]: Abstraction has 904 states and 1154 transitions. [2023-11-29 01:39:00,383 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 01:39:00,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 904 states and 1154 transitions. [2023-11-29 01:39:00,389 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 608 [2023-11-29 01:39:00,389 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:39:00,389 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:39:00,390 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:00,390 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:00,391 INFO L748 eck$LassoCheckResult]: Stem: 6315#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 6316#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 6362#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6348#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6262#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 6237#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6238#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6422#L250 assume !(0 == ~M_E~0); 6448#L250-2 assume !(0 == ~T1_E~0); 6338#L255-1 assume !(0 == ~E_1~0); 6339#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6377#L115 assume !(1 == ~m_pc~0); 6305#L115-2 is_master_triggered_~__retres1~0#1 := 0; 6386#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6247#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6248#L300 assume !(0 != activate_threads_~tmp~1#1); 6397#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6474#L134 assume !(1 == ~t1_pc~0); 6389#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6383#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6337#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6256#L308 assume !(0 != activate_threads_~tmp___0~0#1); 6257#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6387#L273 assume !(1 == ~M_E~0); 6388#L273-2 assume !(1 == ~T1_E~0); 6464#L278-1 assume !(1 == ~E_1~0); 6403#L283-1 assume { :end_inline_reset_delta_events } true; 6404#L404-2 assume !false; 6639#L405 [2023-11-29 01:39:00,391 INFO L750 eck$LassoCheckResult]: Loop: 6639#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7025#L225-1 assume !false; 7036#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7034#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6789#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7032#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7031#L206 assume 0 != eval_~tmp~0#1; 7029#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 6844#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 6298#L41 assume !(0 == ~m_pc~0); 6299#L44 assume 1 == ~m_pc~0; 6252#$Ultimate##91 assume !false; 6253#L61 ~m_pc~0 := 1;~m_st~0 := 2; 6846#master_returnLabel#1 assume { :end_inline_master } true; 6843#L214-2 havoc eval_~tmp_ndt_1~0#1; 6838#L211-1 assume !(0 == ~t1_st~0); 6834#L225-1 assume !false; 6823#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 6788#L179 assume !(0 == ~m_st~0); 6783#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 6779#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 6774#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6771#L206 assume !(0 != eval_~tmp~0#1); 6767#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6765#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6762#L250-3 assume !(0 == ~M_E~0); 6759#L250-5 assume !(0 == ~T1_E~0); 6755#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6752#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6740#L115-6 assume 1 == ~m_pc~0; 6738#L116-2 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6737#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6736#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 6734#L300-6 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6733#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6731#L134-6 assume !(1 == ~t1_pc~0); 6732#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 7055#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7054#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 6715#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 6712#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6710#L273-3 assume !(1 == ~M_E~0); 6711#L273-5 assume !(1 == ~T1_E~0); 6707#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7056#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7053#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6974#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7051#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 7049#L423 assume !(0 == start_simulation_~tmp~3#1); 7048#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 7046#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 6696#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 7044#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 7043#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7042#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7041#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 7040#L436 assume !(0 != start_simulation_~tmp___0~1#1); 7039#L404-2 assume !false; 6639#L405 [2023-11-29 01:39:00,391 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,391 INFO L85 PathProgramCache]: Analyzing trace with hash 2020492972, now seen corresponding path program 1 times [2023-11-29 01:39:00,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,392 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [430757144] [2023-11-29 01:39:00,392 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,392 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,398 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:00,398 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:39:00,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:00,405 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:39:00,406 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,406 INFO L85 PathProgramCache]: Analyzing trace with hash -1382120805, now seen corresponding path program 1 times [2023-11-29 01:39:00,406 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,406 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1144579776] [2023-11-29 01:39:00,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,414 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:39:00,439 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2023-11-29 01:39:00,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:39:00,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1144579776] [2023-11-29 01:39:00,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1144579776] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:39:00,439 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:39:00,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:39:00,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1038124875] [2023-11-29 01:39:00,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:39:00,440 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:39:00,440 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:39:00,441 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:39:00,441 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:39:00,441 INFO L87 Difference]: Start difference. First operand 904 states and 1154 transitions. cyclomatic complexity: 256 Second operand has 3 states, 3 states have (on average 18.0) internal successors, (54), 3 states have internal predecessors, (54), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,482 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:39:00,482 INFO L93 Difference]: Finished difference Result 1379 states and 1723 transitions. [2023-11-29 01:39:00,482 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1379 states and 1723 transitions. [2023-11-29 01:39:00,493 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 838 [2023-11-29 01:39:00,503 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1379 states to 1309 states and 1639 transitions. [2023-11-29 01:39:00,504 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 893 [2023-11-29 01:39:00,505 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 893 [2023-11-29 01:39:00,505 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1309 states and 1639 transitions. [2023-11-29 01:39:00,505 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 01:39:00,506 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1309 states and 1639 transitions. [2023-11-29 01:39:00,507 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1309 states and 1639 transitions. [2023-11-29 01:39:00,527 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1309 to 1301. [2023-11-29 01:39:00,529 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1301 states, 1301 states have (on average 1.2536510376633359) internal successors, (1631), 1300 states have internal predecessors, (1631), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,535 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1301 states to 1301 states and 1631 transitions. [2023-11-29 01:39:00,535 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1301 states and 1631 transitions. [2023-11-29 01:39:00,535 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:39:00,536 INFO L428 stractBuchiCegarLoop]: Abstraction has 1301 states and 1631 transitions. [2023-11-29 01:39:00,536 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 01:39:00,536 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1301 states and 1631 transitions. [2023-11-29 01:39:00,543 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 832 [2023-11-29 01:39:00,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:39:00,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:39:00,544 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:00,544 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:00,544 INFO L748 eck$LassoCheckResult]: Stem: 8604#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 8605#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 8655#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8554#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 8526#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8527#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8713#L250 assume 0 == ~M_E~0;~M_E~0 := 1; 8738#L250-2 assume !(0 == ~T1_E~0); 8630#L255-1 assume !(0 == ~E_1~0); 8631#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8671#L115 assume !(1 == ~m_pc~0); 8672#L115-2 is_master_triggered_~__retres1~0#1 := 0; 8796#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8797#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8689#L300 assume !(0 != activate_threads_~tmp~1#1); 8690#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8793#L134 assume !(1 == ~t1_pc~0); 8792#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8791#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8790#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8544#L308 assume !(0 != activate_threads_~tmp___0~0#1); 8545#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8679#L273 assume 1 == ~M_E~0;~M_E~0 := 2; 8680#L273-2 assume !(1 == ~T1_E~0); 8751#L278-1 assume !(1 == ~E_1~0); 8695#L283-1 assume { :end_inline_reset_delta_events } true; 8696#L404-2 assume !false; 9034#L405 [2023-11-29 01:39:00,544 INFO L750 eck$LassoCheckResult]: Loop: 9034#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9506#L225-1 assume !false; 9518#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9516#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9306#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9514#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9512#L206 assume 0 != eval_~tmp~0#1; 9510#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 9406#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 8588#L41 assume !(0 == ~m_pc~0); 8589#L44 assume 1 == ~m_pc~0; 9703#$Ultimate##91 assume !false; 9702#L61 ~m_pc~0 := 1;~m_st~0 := 2; 9700#master_returnLabel#1 assume { :end_inline_master } true; 9405#L214-2 havoc eval_~tmp_ndt_1~0#1; 9314#L211-1 assume !(0 == ~t1_st~0); 9310#L225-1 assume !false; 9308#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9305#L179 assume !(0 == ~m_st~0); 9302#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 9287#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9280#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9274#L206 assume !(0 != eval_~tmp~0#1); 9269#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9263#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9258#L250-3 assume !(0 == ~M_E~0); 9255#L250-5 assume !(0 == ~T1_E~0); 9250#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9245#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8656#L115-6 assume !(1 == ~m_pc~0); 8657#L115-8 is_master_triggered_~__retres1~0#1 := 0; 8778#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8665#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 8666#L300-6 assume !(0 != activate_threads_~tmp~1#1); 8697#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8772#L134-6 assume !(1 == ~t1_pc~0); 8606#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 8607#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8663#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 8661#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 8532#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8533#L273-3 assume !(1 == ~M_E~0); 8783#L273-5 assume !(1 == ~T1_E~0); 9148#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9143#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9144#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9542#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9540#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 9538#L423 assume !(0 == start_simulation_~tmp~3#1); 9536#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 9533#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 9394#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 9530#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 9528#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9526#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9524#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 9522#L436 assume !(0 != start_simulation_~tmp___0~1#1); 9520#L404-2 assume !false; 9034#L405 [2023-11-29 01:39:00,545 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,545 INFO L85 PathProgramCache]: Analyzing trace with hash 1595944104, now seen corresponding path program 1 times [2023-11-29 01:39:00,545 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,545 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [136375004] [2023-11-29 01:39:00,545 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,545 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:39:00,570 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:39:00,570 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:39:00,571 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [136375004] [2023-11-29 01:39:00,571 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [136375004] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:39:00,571 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:39:00,571 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:39:00,571 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1247148733] [2023-11-29 01:39:00,571 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:39:00,571 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:39:00,572 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,572 INFO L85 PathProgramCache]: Analyzing trace with hash 2081720414, now seen corresponding path program 1 times [2023-11-29 01:39:00,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2019210629] [2023-11-29 01:39:00,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:39:00,602 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:39:00,602 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:39:00,602 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2019210629] [2023-11-29 01:39:00,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2019210629] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:39:00,602 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:39:00,602 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:39:00,603 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1195349232] [2023-11-29 01:39:00,603 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:39:00,603 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:39:00,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:39:00,603 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:39:00,604 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:39:00,604 INFO L87 Difference]: Start difference. First operand 1301 states and 1631 transitions. cyclomatic complexity: 338 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 2 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,627 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:39:00,628 INFO L93 Difference]: Finished difference Result 775 states and 956 transitions. [2023-11-29 01:39:00,628 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 775 states and 956 transitions. [2023-11-29 01:39:00,633 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 528 [2023-11-29 01:39:00,638 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 775 states to 557 states and 687 transitions. [2023-11-29 01:39:00,638 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 557 [2023-11-29 01:39:00,639 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 557 [2023-11-29 01:39:00,639 INFO L73 IsDeterministic]: Start isDeterministic. Operand 557 states and 687 transitions. [2023-11-29 01:39:00,640 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:39:00,640 INFO L218 hiAutomatonCegarLoop]: Abstraction has 557 states and 687 transitions. [2023-11-29 01:39:00,641 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 557 states and 687 transitions. [2023-11-29 01:39:00,646 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 557 to 338. [2023-11-29 01:39:00,647 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 338 states, 338 states have (on average 1.2248520710059172) internal successors, (414), 337 states have internal predecessors, (414), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,649 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 338 states to 338 states and 414 transitions. [2023-11-29 01:39:00,649 INFO L240 hiAutomatonCegarLoop]: Abstraction has 338 states and 414 transitions. [2023-11-29 01:39:00,649 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:39:00,650 INFO L428 stractBuchiCegarLoop]: Abstraction has 338 states and 414 transitions. [2023-11-29 01:39:00,650 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 01:39:00,650 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 338 states and 414 transitions. [2023-11-29 01:39:00,652 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 310 [2023-11-29 01:39:00,652 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:39:00,652 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:39:00,652 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:00,653 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:00,653 INFO L748 eck$LassoCheckResult]: Stem: 10654#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 10655#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 10681#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10676#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10624#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 10607#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10608#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10713#L250 assume !(0 == ~M_E~0); 10728#L250-2 assume !(0 == ~T1_E~0); 10668#L255-1 assume !(0 == ~E_1~0); 10669#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10689#L115 assume !(1 == ~m_pc~0); 10652#L115-2 is_master_triggered_~__retres1~0#1 := 0; 10692#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10613#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10614#L300 assume !(0 != activate_threads_~tmp~1#1); 10701#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10740#L134 assume !(1 == ~t1_pc~0); 10698#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10690#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10667#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10618#L308 assume !(0 != activate_threads_~tmp___0~0#1); 10619#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10693#L273 assume !(1 == ~M_E~0); 10694#L273-2 assume !(1 == ~T1_E~0); 10736#L278-1 assume !(1 == ~E_1~0); 10704#L283-1 assume { :end_inline_reset_delta_events } true; 10675#L404-2 [2023-11-29 01:39:00,653 INFO L750 eck$LassoCheckResult]: Loop: 10675#L404-2 assume !false; 10691#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10712#L225-1 assume !false; 10720#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10721#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10756#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10924#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10662#L206 assume 0 != eval_~tmp~0#1; 10663#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 10715#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 10645#L41 assume !(0 == ~m_pc~0); 10646#L44 assume 1 == ~m_pc~0; 10616#$Ultimate##91 assume !false; 10617#L61 ~m_pc~0 := 1;~m_st~0 := 2; 10703#master_returnLabel#1 assume { :end_inline_master } true; 10714#L214-2 havoc eval_~tmp_ndt_1~0#1; 10887#L211-1 assume !(0 == ~t1_st~0); 10884#L225-1 assume !false; 10883#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10882#L179 assume !(0 == ~m_st~0); 10648#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 10650#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10923#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10922#L206 assume !(0 != eval_~tmp~0#1); 10716#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10717#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10748#L250-3 assume !(0 == ~M_E~0); 10734#L250-5 assume !(0 == ~T1_E~0); 10735#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10609#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10610#L115-6 assume !(1 == ~m_pc~0); 10682#L115-8 is_master_triggered_~__retres1~0#1 := 0; 10753#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10686#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 10687#L300-6 assume !(0 != activate_threads_~tmp~1#1); 10705#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10749#L134-6 assume !(1 == ~t1_pc~0); 10761#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 10820#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10818#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 10815#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 10812#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10810#L273-3 assume !(1 == ~M_E~0); 10808#L273-5 assume !(1 == ~T1_E~0); 10805#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10803#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10800#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10801#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10794#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 10792#L423 assume !(0 == start_simulation_~tmp~3#1); 10631#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 10632#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 10638#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 10666#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 10625#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10626#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10630#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 10674#L436 assume !(0 != start_simulation_~tmp___0~1#1); 10675#L404-2 [2023-11-29 01:39:00,653 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,653 INFO L85 PathProgramCache]: Analyzing trace with hash -904654136, now seen corresponding path program 6 times [2023-11-29 01:39:00,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1400244085] [2023-11-29 01:39:00,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:00,659 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:39:00,662 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:00,666 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:39:00,667 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,667 INFO L85 PathProgramCache]: Analyzing trace with hash -136510844, now seen corresponding path program 2 times [2023-11-29 01:39:00,667 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,667 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [901457183] [2023-11-29 01:39:00,667 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,667 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,673 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:39:00,695 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:39:00,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:39:00,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [901457183] [2023-11-29 01:39:00,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [901457183] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:39:00,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:39:00,695 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:39:00,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [567965947] [2023-11-29 01:39:00,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:39:00,696 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:39:00,696 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:39:00,696 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:39:00,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:39:00,697 INFO L87 Difference]: Start difference. First operand 338 states and 414 transitions. cyclomatic complexity: 78 Second operand has 3 states, 3 states have (on average 19.333333333333332) internal successors, (58), 3 states have internal predecessors, (58), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,719 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:39:00,719 INFO L93 Difference]: Finished difference Result 404 states and 485 transitions. [2023-11-29 01:39:00,719 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 404 states and 485 transitions. [2023-11-29 01:39:00,723 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 287 [2023-11-29 01:39:00,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 404 states to 404 states and 485 transitions. [2023-11-29 01:39:00,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 404 [2023-11-29 01:39:00,726 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 404 [2023-11-29 01:39:00,726 INFO L73 IsDeterministic]: Start isDeterministic. Operand 404 states and 485 transitions. [2023-11-29 01:39:00,727 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:39:00,727 INFO L218 hiAutomatonCegarLoop]: Abstraction has 404 states and 485 transitions. [2023-11-29 01:39:00,728 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 404 states and 485 transitions. [2023-11-29 01:39:00,733 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 404 to 372. [2023-11-29 01:39:00,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 372 states, 372 states have (on average 1.2096774193548387) internal successors, (450), 371 states have internal predecessors, (450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,735 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 372 states to 372 states and 450 transitions. [2023-11-29 01:39:00,736 INFO L240 hiAutomatonCegarLoop]: Abstraction has 372 states and 450 transitions. [2023-11-29 01:39:00,736 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:39:00,736 INFO L428 stractBuchiCegarLoop]: Abstraction has 372 states and 450 transitions. [2023-11-29 01:39:00,737 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 01:39:00,737 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 372 states and 450 transitions. [2023-11-29 01:39:00,739 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 287 [2023-11-29 01:39:00,739 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:39:00,739 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:39:00,740 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:00,740 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:00,740 INFO L748 eck$LassoCheckResult]: Stem: 11403#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 11404#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 11432#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11426#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11370#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 11355#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11356#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11468#L250 assume !(0 == ~M_E~0); 11481#L250-2 assume !(0 == ~T1_E~0); 11418#L255-1 assume !(0 == ~E_1~0); 11419#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11439#L115 assume 1 == ~m_pc~0; 11397#L116 assume !(1 == ~M_E~0); 11398#L115-2 is_master_triggered_~__retres1~0#1 := 0; 11444#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11361#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11362#L300 assume !(0 != activate_threads_~tmp~1#1); 11452#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11492#L134 assume !(1 == ~t1_pc~0); 11501#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11646#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11644#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11364#L308 assume !(0 != activate_threads_~tmp___0~0#1); 11365#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11445#L273 assume !(1 == ~M_E~0); 11446#L273-2 assume !(1 == ~T1_E~0); 11489#L278-1 assume !(1 == ~E_1~0); 11458#L283-1 assume { :end_inline_reset_delta_events } true; 11425#L404-2 [2023-11-29 01:39:00,740 INFO L750 eck$LassoCheckResult]: Loop: 11425#L404-2 assume !false; 11443#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11467#L225-1 assume !false; 11475#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11476#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11682#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11675#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11676#L206 assume 0 != eval_~tmp~0#1; 11680#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 11506#L214 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 11508#L41 assume !(0 == ~m_pc~0); 11677#L44 assume 1 == ~m_pc~0; 11674#$Ultimate##91 assume !false; 11455#L61 ~m_pc~0 := 1;~m_st~0 := 2; 11456#master_returnLabel#1 assume { :end_inline_master } true; 11469#L214-2 havoc eval_~tmp_ndt_1~0#1; 11554#L211-1 assume !(0 == ~t1_st~0); 11555#L225-1 assume !false; 11716#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11715#L179 assume !(0 == ~m_st~0); 11399#L183 assume !(0 == ~t1_st~0);exists_runnable_thread_~__retres1~2#1 := 0; 11401#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11671#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11669#L206 assume !(0 != eval_~tmp~0#1); 11471#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11472#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11499#L250-3 assume !(0 == ~M_E~0); 11486#L250-5 assume !(0 == ~T1_E~0); 11487#L255-3 assume 0 == ~E_1~0;~E_1~0 := 1; 11357#L260-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11358#L115-6 assume 1 == ~m_pc~0; 11433#L116-2 assume !(1 == ~M_E~0); 11498#L115-8 is_master_triggered_~__retres1~0#1 := 0; 11502#L126-2 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11437#is_master_triggered_returnLabel#3 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 11438#L300-6 assume !(0 != activate_threads_~tmp~1#1); 11461#L300-8 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11500#L134-6 assume !(1 == ~t1_pc~0); 11405#L134-8 is_transmit1_triggered_~__retres1~1#1 := 0; 11406#L145-2 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11436#is_transmit1_triggered_returnLabel#3 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 11434#L308-6 assume !(0 != activate_threads_~tmp___0~0#1); 11359#L308-8 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11360#L273-3 assume !(1 == ~M_E~0); 11427#L273-5 assume !(1 == ~T1_E~0); 11407#L278-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11408#L283-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11462#L179-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11463#L191-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11488#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret10#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret10#1;havoc start_simulation_#t~ret10#1; 11382#L423 assume !(0 == start_simulation_~tmp~3#1); 11383#L423-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 11387#L179-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 11388#L191-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 11457#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret9#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret9#1;havoc stop_simulation_#t~ret9#1; 11373#L378 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11374#L385 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11509#stop_simulation_returnLabel#1 start_simulation_#t~ret11#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret9#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret11#1;havoc start_simulation_#t~ret11#1; 11424#L436 assume !(0 != start_simulation_~tmp___0~1#1); 11425#L404-2 [2023-11-29 01:39:00,740 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,740 INFO L85 PathProgramCache]: Analyzing trace with hash -831988783, now seen corresponding path program 1 times [2023-11-29 01:39:00,741 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,741 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194471900] [2023-11-29 01:39:00,741 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,741 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,745 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:39:00,760 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:39:00,760 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:39:00,760 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194471900] [2023-11-29 01:39:00,760 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [194471900] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:39:00,761 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:39:00,761 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:39:00,761 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1196730591] [2023-11-29 01:39:00,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:39:00,761 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:39:00,761 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,761 INFO L85 PathProgramCache]: Analyzing trace with hash 694585817, now seen corresponding path program 1 times [2023-11-29 01:39:00,762 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,762 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1866388583] [2023-11-29 01:39:00,762 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,762 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,802 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:39:00,823 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 3 proven. 0 refuted. 0 times theorem prover too weak. 3 trivial. 0 not checked. [2023-11-29 01:39:00,823 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:39:00,824 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1866388583] [2023-11-29 01:39:00,824 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1866388583] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:39:00,824 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:39:00,824 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:39:00,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [400295122] [2023-11-29 01:39:00,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:39:00,824 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:39:00,825 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:39:00,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:39:00,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:39:00,825 INFO L87 Difference]: Start difference. First operand 372 states and 450 transitions. cyclomatic complexity: 82 Second operand has 3 states, 3 states have (on average 9.333333333333334) internal successors, (28), 2 states have internal predecessors, (28), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,843 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:39:00,843 INFO L93 Difference]: Finished difference Result 358 states and 430 transitions. [2023-11-29 01:39:00,843 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 358 states and 430 transitions. [2023-11-29 01:39:00,846 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 287 [2023-11-29 01:39:00,848 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 358 states to 358 states and 430 transitions. [2023-11-29 01:39:00,849 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 358 [2023-11-29 01:39:00,849 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 358 [2023-11-29 01:39:00,849 INFO L73 IsDeterministic]: Start isDeterministic. Operand 358 states and 430 transitions. [2023-11-29 01:39:00,850 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:39:00,850 INFO L218 hiAutomatonCegarLoop]: Abstraction has 358 states and 430 transitions. [2023-11-29 01:39:00,851 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 358 states and 430 transitions. [2023-11-29 01:39:00,856 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 358 to 354. [2023-11-29 01:39:00,857 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 354 states, 354 states have (on average 1.2033898305084745) internal successors, (426), 353 states have internal predecessors, (426), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,858 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 354 states to 354 states and 426 transitions. [2023-11-29 01:39:00,858 INFO L240 hiAutomatonCegarLoop]: Abstraction has 354 states and 426 transitions. [2023-11-29 01:39:00,859 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:39:00,859 INFO L428 stractBuchiCegarLoop]: Abstraction has 354 states and 426 transitions. [2023-11-29 01:39:00,860 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 01:39:00,860 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 354 states and 426 transitions. [2023-11-29 01:39:00,862 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 287 [2023-11-29 01:39:00,862 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:39:00,862 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:39:00,862 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:00,862 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:00,863 INFO L748 eck$LassoCheckResult]: Stem: 12137#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 12138#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 12164#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12159#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12109#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 12092#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12093#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12202#L250 assume !(0 == ~M_E~0); 12217#L250-2 assume !(0 == ~T1_E~0); 12151#L255-1 assume !(0 == ~E_1~0); 12152#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12172#L115 assume !(1 == ~m_pc~0); 12173#L115-2 is_master_triggered_~__retres1~0#1 := 0; 12176#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12098#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 12099#L300 assume !(0 != activate_threads_~tmp~1#1); 12185#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12230#L134 assume !(1 == ~t1_pc~0); 12182#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12174#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12149#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 12103#L308 assume !(0 != activate_threads_~tmp___0~0#1); 12104#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12177#L273 assume !(1 == ~M_E~0); 12178#L273-2 assume !(1 == ~T1_E~0); 12223#L278-1 assume !(1 == ~E_1~0); 12189#L283-1 assume { :end_inline_reset_delta_events } true; 12190#L404-2 assume !false; 12328#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12327#L225-1 [2023-11-29 01:39:00,863 INFO L750 eck$LassoCheckResult]: Loop: 12327#L225-1 assume !false; 12326#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 12325#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 12324#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 12322#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12319#L206 assume 0 != eval_~tmp~0#1; 12316#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 12312#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 12313#L214-2 havoc eval_~tmp_ndt_1~0#1; 12330#L211-1 assume !(0 == ~t1_st~0); 12327#L225-1 [2023-11-29 01:39:00,863 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,863 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 1 times [2023-11-29 01:39:00,863 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,863 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779356758] [2023-11-29 01:39:00,864 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,864 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:00,869 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:39:00,873 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:00,876 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:39:00,877 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,877 INFO L85 PathProgramCache]: Analyzing trace with hash 722519487, now seen corresponding path program 1 times [2023-11-29 01:39:00,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371455031] [2023-11-29 01:39:00,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:00,881 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:39:00,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:00,883 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:39:00,884 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:00,884 INFO L85 PathProgramCache]: Analyzing trace with hash -1929671224, now seen corresponding path program 1 times [2023-11-29 01:39:00,884 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:00,884 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [225625191] [2023-11-29 01:39:00,884 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:00,884 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:00,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:39:00,907 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:39:00,907 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:39:00,907 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [225625191] [2023-11-29 01:39:00,907 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [225625191] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:39:00,908 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:39:00,908 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:39:00,908 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1488854971] [2023-11-29 01:39:00,908 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:39:00,944 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:39:00,945 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:39:00,945 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:39:00,945 INFO L87 Difference]: Start difference. First operand 354 states and 426 transitions. cyclomatic complexity: 76 Second operand has 3 states, 2 states have (on average 19.5) internal successors, (39), 3 states have internal predecessors, (39), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:00,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:39:00,977 INFO L93 Difference]: Finished difference Result 610 states and 721 transitions. [2023-11-29 01:39:00,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 610 states and 721 transitions. [2023-11-29 01:39:00,982 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 430 [2023-11-29 01:39:00,986 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 610 states to 610 states and 721 transitions. [2023-11-29 01:39:00,986 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 610 [2023-11-29 01:39:00,987 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 610 [2023-11-29 01:39:00,987 INFO L73 IsDeterministic]: Start isDeterministic. Operand 610 states and 721 transitions. [2023-11-29 01:39:00,988 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:39:00,988 INFO L218 hiAutomatonCegarLoop]: Abstraction has 610 states and 721 transitions. [2023-11-29 01:39:00,989 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 610 states and 721 transitions. [2023-11-29 01:39:00,998 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 610 to 536. [2023-11-29 01:39:00,999 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 536 states, 536 states have (on average 1.1884328358208955) internal successors, (637), 535 states have internal predecessors, (637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:01,001 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 536 states to 536 states and 637 transitions. [2023-11-29 01:39:01,001 INFO L240 hiAutomatonCegarLoop]: Abstraction has 536 states and 637 transitions. [2023-11-29 01:39:01,001 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:39:01,002 INFO L428 stractBuchiCegarLoop]: Abstraction has 536 states and 637 transitions. [2023-11-29 01:39:01,002 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 01:39:01,002 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 536 states and 637 transitions. [2023-11-29 01:39:01,005 INFO L131 ngComponentsAnalysis]: Automaton has 5 accepting balls. 401 [2023-11-29 01:39:01,005 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:39:01,005 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:39:01,006 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:01,006 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:01,006 INFO L748 eck$LassoCheckResult]: Stem: 13109#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 13110#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 13136#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13129#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13081#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 13064#L161-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 13065#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13175#L250 assume !(0 == ~M_E~0); 13188#L250-2 assume !(0 == ~T1_E~0); 13123#L255-1 assume !(0 == ~E_1~0); 13124#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13176#L115 assume !(1 == ~m_pc~0); 13432#L115-2 is_master_triggered_~__retres1~0#1 := 0; 13431#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13430#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 13429#L300 assume !(0 != activate_threads_~tmp~1#1); 13428#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13213#L134 assume !(1 == ~t1_pc~0); 13154#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13148#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13122#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13075#L308 assume !(0 != activate_threads_~tmp___0~0#1); 13076#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13423#L273 assume !(1 == ~M_E~0); 13422#L273-2 assume !(1 == ~T1_E~0); 13421#L278-1 assume !(1 == ~E_1~0); 13420#L283-1 assume { :end_inline_reset_delta_events } true; 13419#L404-2 assume !false; 13417#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13416#L225-1 [2023-11-29 01:39:01,006 INFO L750 eck$LassoCheckResult]: Loop: 13416#L225-1 assume !false; 13415#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 13414#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 13412#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 13411#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13117#L206 assume 0 != eval_~tmp~0#1; 13118#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 13372#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 13407#L214-2 havoc eval_~tmp_ndt_1~0#1; 13418#L211-1 assume !(0 == ~t1_st~0); 13416#L225-1 [2023-11-29 01:39:01,006 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:01,006 INFO L85 PathProgramCache]: Analyzing trace with hash -1923240696, now seen corresponding path program 1 times [2023-11-29 01:39:01,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:01,007 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [344567086] [2023-11-29 01:39:01,007 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:01,007 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:01,011 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:39:01,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:39:01,022 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:39:01,022 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [344567086] [2023-11-29 01:39:01,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [344567086] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:39:01,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:39:01,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:39:01,023 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [77633530] [2023-11-29 01:39:01,023 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:39:01,023 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:39:01,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:01,024 INFO L85 PathProgramCache]: Analyzing trace with hash 722519487, now seen corresponding path program 2 times [2023-11-29 01:39:01,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:01,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1013508903] [2023-11-29 01:39:01,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:01,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:01,027 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:01,027 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:39:01,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:01,030 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:39:01,064 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:39:01,065 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:39:01,065 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:39:01,065 INFO L87 Difference]: Start difference. First operand 536 states and 637 transitions. cyclomatic complexity: 106 Second operand has 3 states, 3 states have (on average 9.666666666666666) internal successors, (29), 3 states have internal predecessors, (29), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:01,071 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:39:01,071 INFO L93 Difference]: Finished difference Result 362 states and 434 transitions. [2023-11-29 01:39:01,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 362 states and 434 transitions. [2023-11-29 01:39:01,074 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 280 [2023-11-29 01:39:01,076 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 362 states to 362 states and 434 transitions. [2023-11-29 01:39:01,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 362 [2023-11-29 01:39:01,077 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 362 [2023-11-29 01:39:01,077 INFO L73 IsDeterministic]: Start isDeterministic. Operand 362 states and 434 transitions. [2023-11-29 01:39:01,077 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:39:01,077 INFO L218 hiAutomatonCegarLoop]: Abstraction has 362 states and 434 transitions. [2023-11-29 01:39:01,078 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 362 states and 434 transitions. [2023-11-29 01:39:01,082 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 362 to 362. [2023-11-29 01:39:01,083 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 362 states, 362 states have (on average 1.1988950276243093) internal successors, (434), 361 states have internal predecessors, (434), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:39:01,084 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 362 states to 362 states and 434 transitions. [2023-11-29 01:39:01,084 INFO L240 hiAutomatonCegarLoop]: Abstraction has 362 states and 434 transitions. [2023-11-29 01:39:01,085 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:39:01,086 INFO L428 stractBuchiCegarLoop]: Abstraction has 362 states and 434 transitions. [2023-11-29 01:39:01,086 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 01:39:01,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 362 states and 434 transitions. [2023-11-29 01:39:01,088 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 280 [2023-11-29 01:39:01,088 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:39:01,088 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:39:01,088 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:01,089 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:39:01,089 INFO L748 eck$LassoCheckResult]: Stem: 14011#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~E_1~0 := 2; 14012#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~3#1;havoc main_~__retres1~3#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1; 14036#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret10#1, start_simulation_#t~ret11#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14031#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 13983#L161 assume 1 == ~m_i~0;~m_st~0 := 0; 13968#L161-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13969#L166-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 14076#L250 assume !(0 == ~M_E~0); 14091#L250-2 assume !(0 == ~T1_E~0); 14023#L255-1 assume !(0 == ~E_1~0); 14024#L260-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14043#L115 assume !(1 == ~m_pc~0); 14044#L115-2 is_master_triggered_~__retres1~0#1 := 0; 14049#L126 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13974#is_master_triggered_returnLabel#1 activate_threads_#t~ret7#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret7#1;havoc activate_threads_#t~ret7#1; 13975#L300 assume !(0 != activate_threads_~tmp~1#1); 14058#L300-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14100#L134 assume !(1 == ~t1_pc~0); 14055#L134-2 is_transmit1_triggered_~__retres1~1#1 := 0; 14046#L145 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14022#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret8#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret8#1;havoc activate_threads_#t~ret8#1; 13977#L308 assume !(0 != activate_threads_~tmp___0~0#1); 13978#L308-2 havoc activate_threads_#t~ret7#1, activate_threads_#t~ret8#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14050#L273 assume !(1 == ~M_E~0); 14051#L273-2 assume !(1 == ~T1_E~0); 14097#L278-1 assume !(1 == ~E_1~0); 14064#L283-1 assume { :end_inline_reset_delta_events } true; 14047#L404-2 assume !false; 14048#L405 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14075#L225-1 [2023-11-29 01:39:01,089 INFO L750 eck$LassoCheckResult]: Loop: 14075#L225-1 assume !false; 14083#L202 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;havoc exists_runnable_thread_~__retres1~2#1; 14084#L179 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~2#1 := 1; 14072#L191 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~2#1; 14073#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~2#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 14305#L206 assume 0 != eval_~tmp~0#1; 14304#L206-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 14302#L214 assume !(0 != eval_~tmp_ndt_1~0#1); 14303#L214-2 havoc eval_~tmp_ndt_1~0#1; 14102#L211-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 14085#L228 assume !(0 != eval_~tmp_ndt_2~0#1); 14074#L228-2 havoc eval_~tmp_ndt_2~0#1; 14075#L225-1 [2023-11-29 01:39:01,089 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:01,089 INFO L85 PathProgramCache]: Analyzing trace with hash -1789227190, now seen corresponding path program 2 times [2023-11-29 01:39:01,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:01,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1241627803] [2023-11-29 01:39:01,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:01,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:01,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:01,095 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:39:01,098 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:01,101 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:39:01,101 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:01,101 INFO L85 PathProgramCache]: Analyzing trace with hash -1443506858, now seen corresponding path program 1 times [2023-11-29 01:39:01,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:01,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [150925767] [2023-11-29 01:39:01,102 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:01,102 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:01,104 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:01,105 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:39:01,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:01,108 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:39:01,108 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:39:01,108 INFO L85 PathProgramCache]: Analyzing trace with hash 1011793695, now seen corresponding path program 1 times [2023-11-29 01:39:01,108 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:39:01,108 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [537343189] [2023-11-29 01:39:01,109 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:39:01,109 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:39:01,115 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:01,115 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:39:01,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:01,122 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:39:01,504 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:01,504 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:39:01,514 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:39:01,577 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 29.11 01:39:01 BoogieIcfgContainer [2023-11-29 01:39:01,577 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-29 01:39:01,578 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-29 01:39:01,578 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-29 01:39:01,578 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-29 01:39:01,579 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:38:56" (3/4) ... [2023-11-29 01:39:01,580 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-29 01:39:01,634 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/witness.graphml [2023-11-29 01:39:01,634 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-29 01:39:01,635 INFO L158 Benchmark]: Toolchain (without parser) took 5831.29ms. Allocated memory was 184.5MB in the beginning and 224.4MB in the end (delta: 39.8MB). Free memory was 138.8MB in the beginning and 80.3MB in the end (delta: 58.6MB). Peak memory consumption was 98.9MB. Max. memory is 16.1GB. [2023-11-29 01:39:01,635 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 134.2MB. Free memory is still 80.4MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-29 01:39:01,636 INFO L158 Benchmark]: CACSL2BoogieTranslator took 258.20ms. Allocated memory is still 184.5MB. Free memory was 138.4MB in the beginning and 125.8MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2023-11-29 01:39:01,636 INFO L158 Benchmark]: Boogie Procedure Inliner took 47.96ms. Allocated memory is still 184.5MB. Free memory was 125.8MB in the beginning and 123.7MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-29 01:39:01,637 INFO L158 Benchmark]: Boogie Preprocessor took 50.14ms. Allocated memory is still 184.5MB. Free memory was 123.7MB in the beginning and 120.7MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-29 01:39:01,637 INFO L158 Benchmark]: RCFGBuilder took 471.04ms. Allocated memory is still 184.5MB. Free memory was 120.7MB in the beginning and 148.4MB in the end (delta: -27.7MB). Peak memory consumption was 22.4MB. Max. memory is 16.1GB. [2023-11-29 01:39:01,637 INFO L158 Benchmark]: BuchiAutomizer took 4942.38ms. Allocated memory was 184.5MB in the beginning and 224.4MB in the end (delta: 39.8MB). Free memory was 148.4MB in the beginning and 83.4MB in the end (delta: 65.0MB). Peak memory consumption was 105.9MB. Max. memory is 16.1GB. [2023-11-29 01:39:01,638 INFO L158 Benchmark]: Witness Printer took 56.68ms. Allocated memory is still 224.4MB. Free memory was 83.4MB in the beginning and 80.3MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. [2023-11-29 01:39:01,640 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 134.2MB. Free memory is still 80.4MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 258.20ms. Allocated memory is still 184.5MB. Free memory was 138.4MB in the beginning and 125.8MB in the end (delta: 12.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 47.96ms. Allocated memory is still 184.5MB. Free memory was 125.8MB in the beginning and 123.7MB in the end (delta: 2.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Boogie Preprocessor took 50.14ms. Allocated memory is still 184.5MB. Free memory was 123.7MB in the beginning and 120.7MB in the end (delta: 3.0MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * RCFGBuilder took 471.04ms. Allocated memory is still 184.5MB. Free memory was 120.7MB in the beginning and 148.4MB in the end (delta: -27.7MB). Peak memory consumption was 22.4MB. Max. memory is 16.1GB. * BuchiAutomizer took 4942.38ms. Allocated memory was 184.5MB in the beginning and 224.4MB in the end (delta: 39.8MB). Free memory was 148.4MB in the beginning and 83.4MB in the end (delta: 65.0MB). Peak memory consumption was 105.9MB. Max. memory is 16.1GB. * Witness Printer took 56.68ms. Allocated memory is still 224.4MB. Free memory was 83.4MB in the beginning and 80.3MB in the end (delta: 3.1MB). Peak memory consumption was 2.1MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 15 terminating modules (14 trivial, 1 deterministic, 0 nondeterministic) and one nonterminating remainder module.One deterministic module has affine ranking function ((-1 * M_E) + 1) and consists of 3 locations. 14 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 362 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 4.8s and 15 iterations. TraceHistogramMax:2. Analysis of lassos took 3.3s. Construction of modules took 0.3s. Büchi inclusion checks took 1.0s. Highest rank in rank-based complementation 3. Minimization of det autom 12. Minimization of nondet autom 3. Automata minimization 0.2s AutomataMinimizationTime, 15 MinimizatonAttempts, 878 StatesRemovedByMinimization, 11 NontrivialMinimizations. Non-live state removal took 0.1s Buchi closure took 0.0s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [1, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 1921 SdHoareTripleChecker+Valid, 0.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 1920 mSDsluCounter, 5290 SdHoareTripleChecker+Invalid, 0.3s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 2578 mSDsCounter, 102 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 303 IncrementalHoareTripleChecker+Invalid, 405 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 102 mSolverCounterUnsat, 2712 mSDtfsCounter, 303 mSolverCounterSat, 0.0s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc1 concLT1 SILN1 SILU0 SILI5 SILT0 lasso0 LassoPreprocessingBenchmarks: Lassos: inital61 mio100 ax100 hnf100 lsp16 ukn100 mio100 lsp100 div100 bol100 ite100 ukn100 eq179 hnf100 smp100 dnf166 smp73 tf109 neg100 sie116 LassoTerminationAnalysisBenchmarks: ConstraintsSatisfiability: unsat Degree: 0 Time: 28ms VariablesStem: 0 VariablesLoop: 1 DisjunctsStem: 1 DisjunctsLoop: 2 SupportingInvariants: 0 MotzkinApplications: 4 LassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 9 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 1 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.2s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 201]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, tmp=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, M_E=2, T1_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L211-L222] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L225-L236] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 201]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int m_st ; [L28] int t1_st ; [L29] int m_i ; [L30] int t1_i ; [L31] int M_E = 2; [L32] int T1_E = 2; [L33] int E_1 = 2; VAL [E_1=2, M_E=2, T1_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0] [L449] int __retres1 ; [L453] CALL init_model() [L364] m_i = 1 [L365] t1_i = 1 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L453] RET init_model() [L454] CALL start_simulation() [L390] int kernel_st ; [L391] int tmp ; [L392] int tmp___0 ; [L396] kernel_st = 0 [L397] FCALL update_channels() [L398] CALL init_threads() [L161] COND TRUE m_i == 1 [L162] m_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L166] COND TRUE t1_i == 1 [L167] t1_st = 0 VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L398] RET init_threads() [L399] CALL fire_delta_events() [L250] COND FALSE !(M_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L255] COND FALSE !(T1_E == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L260] COND FALSE !(E_1 == 0) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L399] RET fire_delta_events() [L400] CALL activate_threads() [L293] int tmp ; [L294] int tmp___0 ; [L298] CALL, EXPR is_master_triggered() [L112] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L115] COND FALSE !(m_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L125] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L127] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L298] RET, EXPR is_master_triggered() [L298] tmp = is_master_triggered() [L300] COND FALSE !(\read(tmp)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, tmp=0] [L306] CALL, EXPR is_transmit1_triggered() [L131] int __retres1 ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L134] COND FALSE !(t1_pc == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L144] __retres1 = 0 VAL [E_1=2, M_E=2, T1_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L146] return (__retres1); VAL [E_1=2, M_E=2, T1_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L306] RET, EXPR is_transmit1_triggered() [L306] tmp___0 = is_transmit1_triggered() [L308] COND FALSE !(\read(tmp___0)) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, tmp=0, tmp___0=0] [L400] RET activate_threads() [L401] CALL reset_delta_events() [L273] COND FALSE !(M_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L278] COND FALSE !(T1_E == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L283] COND FALSE !(E_1 == 1) VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L401] RET reset_delta_events() [L404] COND TRUE 1 VAL [E_1=2, M_E=2, T1_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] [L407] kernel_st = 1 [L408] CALL eval() [L197] int tmp ; VAL [E_1=2, M_E=2, T1_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0] Loop: [L201] COND TRUE 1 [L204] CALL, EXPR exists_runnable_thread() [L176] int __retres1 ; [L179] COND TRUE m_st == 0 [L180] __retres1 = 1 [L192] return (__retres1); [L204] RET, EXPR exists_runnable_thread() [L204] tmp = exists_runnable_thread() [L206] COND TRUE \read(tmp) [L211] COND TRUE m_st == 0 [L212] int tmp_ndt_1; [L213] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L214] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L211-L222] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L225] COND TRUE t1_st == 0 [L226] int tmp_ndt_2; [L227] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L228] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L225-L236] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-29 01:39:01,684 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_afc1e601-0f01-4a16-8ba4-15041620d5fe/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Ended with exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)