./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.05.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.05.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 01:06:59,114 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 01:06:59,189 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 01:06:59,195 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 01:06:59,196 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 01:06:59,225 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 01:06:59,226 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 01:06:59,226 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 01:06:59,227 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 01:06:59,228 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 01:06:59,229 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 01:06:59,229 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 01:06:59,230 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 01:06:59,231 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 01:06:59,231 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 01:06:59,232 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 01:06:59,232 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 01:06:59,233 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 01:06:59,233 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 01:06:59,234 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 01:06:59,235 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 01:06:59,235 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 01:06:59,236 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 01:06:59,236 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 01:06:59,237 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 01:06:59,237 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 01:06:59,238 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 01:06:59,238 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 01:06:59,239 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 01:06:59,239 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 01:06:59,239 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 01:06:59,240 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 01:06:59,240 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 01:06:59,241 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 01:06:59,241 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 01:06:59,242 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 01:06:59,242 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 01:06:59,243 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 01:06:59,243 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d8722862ca37b1ee13dec8b9e420cd40ba7901837b8f3b6258499da6e8a2ca6f [2023-11-29 01:06:59,498 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 01:06:59,530 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 01:06:59,533 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 01:06:59,534 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 01:06:59,535 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 01:06:59,536 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/transmitter.05.cil.c [2023-11-29 01:07:02,377 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 01:07:02,561 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 01:07:02,561 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/sv-benchmarks/c/systemc/transmitter.05.cil.c [2023-11-29 01:07:02,573 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/data/aff666326/434339afc5194a8dbbe1220a5e9703c2/FLAGeeab04bf8 [2023-11-29 01:07:02,585 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/data/aff666326/434339afc5194a8dbbe1220a5e9703c2 [2023-11-29 01:07:02,587 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 01:07:02,588 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 01:07:02,589 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 01:07:02,589 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 01:07:02,594 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 01:07:02,594 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:02,595 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@13da5762 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02, skipping insertion in model container [2023-11-29 01:07:02,596 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:02,641 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 01:07:02,837 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 01:07:02,853 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 01:07:02,908 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 01:07:02,929 INFO L206 MainTranslator]: Completed translation [2023-11-29 01:07:02,929 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02 WrapperNode [2023-11-29 01:07:02,930 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 01:07:02,931 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 01:07:02,931 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 01:07:02,931 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 01:07:02,940 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:02,951 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,005 INFO L138 Inliner]: procedures = 38, calls = 46, calls flagged for inlining = 41, calls inlined = 87, statements flattened = 1241 [2023-11-29 01:07:03,006 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 01:07:03,007 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 01:07:03,007 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 01:07:03,007 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 01:07:03,021 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,021 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,029 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,052 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 01:07:03,052 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,053 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,073 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,091 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,094 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,100 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,108 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 01:07:03,109 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 01:07:03,109 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 01:07:03,109 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 01:07:03,110 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (1/1) ... [2023-11-29 01:07:03,116 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:07:03,131 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:07:03,143 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:07:03,145 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 01:07:03,176 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 01:07:03,177 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 01:07:03,177 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 01:07:03,177 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 01:07:03,268 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 01:07:03,270 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 01:07:04,171 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 01:07:04,194 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 01:07:04,194 INFO L309 CfgBuilder]: Removed 9 assume(true) statements. [2023-11-29 01:07:04,196 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:07:04 BoogieIcfgContainer [2023-11-29 01:07:04,196 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 01:07:04,197 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 01:07:04,198 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 01:07:04,202 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 01:07:04,203 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:07:04,204 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 01:07:02" (1/3) ... [2023-11-29 01:07:04,205 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@74ed0526 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 01:07:04, skipping insertion in model container [2023-11-29 01:07:04,205 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:07:04,205 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:07:02" (2/3) ... [2023-11-29 01:07:04,206 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@74ed0526 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 01:07:04, skipping insertion in model container [2023-11-29 01:07:04,206 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:07:04,206 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:07:04" (3/3) ... [2023-11-29 01:07:04,207 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.05.cil.c [2023-11-29 01:07:04,288 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 01:07:04,288 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 01:07:04,288 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 01:07:04,288 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 01:07:04,289 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 01:07:04,289 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 01:07:04,289 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 01:07:04,289 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 01:07:04,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:04,340 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 431 [2023-11-29 01:07:04,341 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:04,341 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:04,354 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:04,354 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:04,354 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 01:07:04,356 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:04,368 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 431 [2023-11-29 01:07:04,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:04,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:04,373 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:04,374 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:04,382 INFO L748 eck$LassoCheckResult]: Stem: 151#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 412#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 243#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 409#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 257#L401true assume !(1 == ~m_i~0);~m_st~0 := 2; 348#L401-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 114#L406-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 402#L411-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 389#L416-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 467#L421-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 330#L426-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 93#L586true assume 0 == ~M_E~0;~M_E~0 := 1; 125#L586-2true assume !(0 == ~T1_E~0); 232#L591-1true assume !(0 == ~T2_E~0); 207#L596-1true assume !(0 == ~T3_E~0); 273#L601-1true assume !(0 == ~T4_E~0); 249#L606-1true assume !(0 == ~T5_E~0); 471#L611-1true assume !(0 == ~E_1~0); 347#L616-1true assume !(0 == ~E_2~0); 353#L621-1true assume 0 == ~E_3~0;~E_3~0 := 1; 49#L626-1true assume !(0 == ~E_4~0); 304#L631-1true assume !(0 == ~E_5~0); 147#L636-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47#L279true assume 1 == ~m_pc~0; 215#L280true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 371#L290true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 131#is_master_triggered_returnLabel#1true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 272#L720true assume !(0 != activate_threads_~tmp~1#1); 493#L720-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 152#L298true assume !(1 == ~t1_pc~0); 21#L298-2true is_transmit1_triggered_~__retres1~1#1 := 0; 457#L309true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 54#L728true assume !(0 != activate_threads_~tmp___0~0#1); 264#L728-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128#L317true assume 1 == ~t2_pc~0; 240#L318true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 475#L328true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 246#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 157#L736true assume !(0 != activate_threads_~tmp___1~0#1); 424#L736-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326#L336true assume 1 == ~t3_pc~0; 188#L337true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 494#L347true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 281#L744true assume !(0 != activate_threads_~tmp___2~0#1); 337#L744-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 403#L355true assume !(1 == ~t4_pc~0); 335#L355-2true is_transmit4_triggered_~__retres1~4#1 := 0; 106#L366true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 71#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 318#L752true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 61#L752-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 375#L374true assume 1 == ~t5_pc~0; 387#L375true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 390#L385true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 430#L760true assume !(0 != activate_threads_~tmp___4~0#1); 234#L760-2true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 438#L649true assume 1 == ~M_E~0;~M_E~0 := 2; 499#L649-2true assume !(1 == ~T1_E~0); 39#L654-1true assume !(1 == ~T2_E~0); 269#L659-1true assume !(1 == ~T3_E~0); 156#L664-1true assume !(1 == ~T4_E~0); 35#L669-1true assume !(1 == ~T5_E~0); 320#L674-1true assume !(1 == ~E_1~0); 333#L679-1true assume !(1 == ~E_2~0); 96#L684-1true assume 1 == ~E_3~0;~E_3~0 := 2; 202#L689-1true assume !(1 == ~E_4~0); 490#L694-1true assume !(1 == ~E_5~0); 201#L699-1true assume { :end_inline_reset_delta_events } true; 480#L900-2true [2023-11-29 01:07:04,385 INFO L750 eck$LassoCheckResult]: Loop: 480#L900-2true assume !false; 508#L901true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 212#L561-1true assume false; 75#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 363#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 425#L586-3true assume 0 == ~M_E~0;~M_E~0 := 1; 319#L586-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 218#L591-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 109#L596-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 229#L601-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 377#L606-3true assume !(0 == ~T5_E~0); 261#L611-3true assume 0 == ~E_1~0;~E_1~0 := 1; 265#L616-3true assume 0 == ~E_2~0;~E_2~0 := 1; 43#L621-3true assume 0 == ~E_3~0;~E_3~0 := 1; 20#L626-3true assume 0 == ~E_4~0;~E_4~0 := 1; 509#L631-3true assume 0 == ~E_5~0;~E_5~0 := 1; 23#L636-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 435#L279-18true assume !(1 == ~m_pc~0); 164#L279-20true is_master_triggered_~__retres1~0#1 := 0; 222#L290-6true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 161#is_master_triggered_returnLabel#7true activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 395#L720-18true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 349#L720-20true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 233#L298-18true assume !(1 == ~t1_pc~0); 8#L298-20true is_transmit1_triggered_~__retres1~1#1 := 0; 113#L309-6true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 422#is_transmit1_triggered_returnLabel#7true activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 123#L728-18true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 450#L728-20true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 208#L317-18true assume !(1 == ~t2_pc~0); 228#L317-20true is_transmit2_triggered_~__retres1~2#1 := 0; 242#L328-6true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 238#is_transmit2_triggered_returnLabel#7true activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 115#L736-18true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 356#L736-20true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 352#L336-18true assume 1 == ~t3_pc~0; 323#L337-6true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 398#L347-6true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 263#is_transmit3_triggered_returnLabel#7true activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 177#L744-18true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 78#L744-20true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 291#L355-18true assume 1 == ~t4_pc~0; 414#L356-6true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 421#L366-6true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180#is_transmit4_triggered_returnLabel#7true activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 213#L752-18true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 132#L752-20true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336#L374-18true assume !(1 == ~t5_pc~0); 294#L374-20true is_transmit5_triggered_~__retres1~5#1 := 0; 173#L385-6true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 133#is_transmit5_triggered_returnLabel#7true activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 452#L760-18true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 275#L760-20true havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 462#L649-3true assume 1 == ~M_E~0;~M_E~0 := 2; 187#L649-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 170#L654-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 83#L659-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 456#L664-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 24#L669-3true assume !(1 == ~T5_E~0); 484#L674-3true assume 1 == ~E_1~0;~E_1~0 := 2; 19#L679-3true assume 1 == ~E_2~0;~E_2~0 := 2; 183#L684-3true assume 1 == ~E_3~0;~E_3~0 := 2; 2#L689-3true assume 1 == ~E_4~0;~E_4~0 := 2; 137#L694-3true assume 1 == ~E_5~0;~E_5~0 := 2; 17#L699-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 419#L439-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 483#L471-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 217#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 200#L919true assume !(0 == start_simulation_~tmp~3#1); 492#L919-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 301#L439-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 380#L471-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 193#L874true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 355#L881true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 372#stop_simulation_returnLabel#1true start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 332#L932true assume !(0 != start_simulation_~tmp___0~1#1); 480#L900-2true [2023-11-29 01:07:04,392 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:04,392 INFO L85 PathProgramCache]: Analyzing trace with hash -777385748, now seen corresponding path program 1 times [2023-11-29 01:07:04,402 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:04,402 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [259101643] [2023-11-29 01:07:04,403 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:04,403 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:04,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:04,636 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:04,637 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:04,637 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [259101643] [2023-11-29 01:07:04,638 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [259101643] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:04,638 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:04,638 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:04,639 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967770896] [2023-11-29 01:07:04,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:04,644 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:04,645 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:04,645 INFO L85 PathProgramCache]: Analyzing trace with hash 1472852014, now seen corresponding path program 1 times [2023-11-29 01:07:04,645 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:04,646 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194195049] [2023-11-29 01:07:04,646 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:04,646 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:04,661 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:04,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:04,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:04,696 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194195049] [2023-11-29 01:07:04,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [194195049] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:04,697 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:04,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:07:04,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1899457251] [2023-11-29 01:07:04,697 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:04,699 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:04,700 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:04,727 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:04,728 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:04,730 INFO L87 Difference]: Start difference. First operand has 512 states, 511 states have (on average 1.5264187866927592) internal successors, (780), 511 states have internal predecessors, (780), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:04,783 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:04,784 INFO L93 Difference]: Finished difference Result 510 states and 758 transitions. [2023-11-29 01:07:04,785 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 510 states and 758 transitions. [2023-11-29 01:07:04,791 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-29 01:07:04,799 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 510 states to 504 states and 752 transitions. [2023-11-29 01:07:04,800 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2023-11-29 01:07:04,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2023-11-29 01:07:04,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 752 transitions. [2023-11-29 01:07:04,806 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:04,806 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 752 transitions. [2023-11-29 01:07:04,822 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 752 transitions. [2023-11-29 01:07:04,851 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2023-11-29 01:07:04,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.492063492063492) internal successors, (752), 503 states have internal predecessors, (752), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:04,855 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 752 transitions. [2023-11-29 01:07:04,855 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 752 transitions. [2023-11-29 01:07:04,857 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:04,860 INFO L428 stractBuchiCegarLoop]: Abstraction has 504 states and 752 transitions. [2023-11-29 01:07:04,861 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 01:07:04,861 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 752 transitions. [2023-11-29 01:07:04,865 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-29 01:07:04,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:04,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:04,868 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:04,868 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:04,869 INFO L748 eck$LassoCheckResult]: Stem: 1302#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 1303#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 1408#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1409#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1426#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 1427#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1237#L406-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1238#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1515#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1516#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1482#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1206#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 1207#L586-2 assume !(0 == ~T1_E~0); 1258#L591-1 assume !(0 == ~T2_E~0); 1372#L596-1 assume !(0 == ~T3_E~0); 1373#L601-1 assume !(0 == ~T4_E~0); 1414#L606-1 assume !(0 == ~T5_E~0); 1415#L611-1 assume !(0 == ~E_1~0); 1490#L616-1 assume !(0 == ~E_2~0); 1491#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 1133#L626-1 assume !(0 == ~E_4~0); 1134#L631-1 assume !(0 == ~E_5~0); 1297#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1128#L279 assume 1 == ~m_pc~0; 1129#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1378#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1272#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1273#L720 assume !(0 != activate_threads_~tmp~1#1); 1437#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1304#L298 assume !(1 == ~t1_pc~0); 1075#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1076#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1101#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1102#L728 assume !(0 != activate_threads_~tmp___0~0#1); 1142#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1264#L317 assume 1 == ~t2_pc~0; 1265#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1406#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1413#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1313#L736 assume !(0 != activate_threads_~tmp___1~0#1); 1314#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1479#L336 assume 1 == ~t3_pc~0; 1351#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1352#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1048#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1049#L744 assume !(0 != activate_threads_~tmp___2~0#1); 1445#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1486#L355 assume !(1 == ~t4_pc~0); 1369#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1224#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1172#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1173#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1152#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1153#L374 assume 1 == ~t5_pc~0; 1508#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1288#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1278#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1279#L760 assume !(0 != activate_threads_~tmp___4~0#1); 1397#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1398#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 1527#L649-2 assume !(1 == ~T1_E~0); 1114#L654-1 assume !(1 == ~T2_E~0); 1115#L659-1 assume !(1 == ~T3_E~0); 1312#L664-1 assume !(1 == ~T4_E~0); 1106#L669-1 assume !(1 == ~T5_E~0); 1107#L674-1 assume !(1 == ~E_1~0); 1471#L679-1 assume !(1 == ~E_2~0); 1211#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 1212#L689-1 assume !(1 == ~E_4~0); 1365#L694-1 assume !(1 == ~E_5~0); 1363#L699-1 assume { :end_inline_reset_delta_events } true; 1364#L900-2 [2023-11-29 01:07:04,869 INFO L750 eck$LassoCheckResult]: Loop: 1364#L900-2 assume !false; 1533#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1283#L561-1 assume !false; 1339#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1331#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1077#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1078#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1200#L486 assume !(0 != eval_~tmp~0#1); 1179#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1180#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1502#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1470#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1380#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1228#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1229#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1393#L606-3 assume !(0 == ~T5_E~0); 1429#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1430#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1122#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1073#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1074#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1079#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1080#L279-18 assume 1 == ~m_pc~0; 1187#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1188#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1317#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 1318#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1492#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1396#L298-18 assume !(1 == ~t1_pc~0); 1046#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 1047#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1236#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1254#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1255#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1374#L317-18 assume 1 == ~t2_pc~0; 1289#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1290#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1404#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1239#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1240#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1495#L336-18 assume 1 == ~t3_pc~0; 1475#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1476#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1431#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1340#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1181#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1182#L355-18 assume !(1 == ~t4_pc~0); 1443#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 1444#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1345#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1346#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1274#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1275#L374-18 assume !(1 == ~t5_pc~0); 1457#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 1336#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1276#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1277#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1438#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1439#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1350#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1330#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1191#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1192#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1083#L669-3 assume !(1 == ~T5_E~0); 1084#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1071#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1072#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1031#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1032#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1066#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1067#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1069#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1379#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 1362#L919 assume !(0 == start_simulation_~tmp~3#1); 1082#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 1461#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 1060#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 1098#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 1099#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1358#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1496#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 1484#L932 assume !(0 != start_simulation_~tmp___0~1#1); 1364#L900-2 [2023-11-29 01:07:04,870 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:04,870 INFO L85 PathProgramCache]: Analyzing trace with hash 438767978, now seen corresponding path program 1 times [2023-11-29 01:07:04,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:04,871 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [161301420] [2023-11-29 01:07:04,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:04,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:04,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:04,944 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:04,945 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:04,945 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [161301420] [2023-11-29 01:07:04,945 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [161301420] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:04,945 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:04,946 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:04,946 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [920329606] [2023-11-29 01:07:04,946 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:04,947 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:04,947 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:04,947 INFO L85 PathProgramCache]: Analyzing trace with hash 1177747720, now seen corresponding path program 1 times [2023-11-29 01:07:04,948 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:04,948 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [282651114] [2023-11-29 01:07:04,948 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:04,948 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:04,989 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:05,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:05,085 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:05,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [282651114] [2023-11-29 01:07:05,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [282651114] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:05,086 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:05,086 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:05,086 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [648208216] [2023-11-29 01:07:05,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:05,087 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:05,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:05,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:05,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:05,088 INFO L87 Difference]: Start difference. First operand 504 states and 752 transitions. cyclomatic complexity: 249 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:05,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:05,107 INFO L93 Difference]: Finished difference Result 504 states and 751 transitions. [2023-11-29 01:07:05,107 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 751 transitions. [2023-11-29 01:07:05,111 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-29 01:07:05,115 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 751 transitions. [2023-11-29 01:07:05,116 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2023-11-29 01:07:05,116 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2023-11-29 01:07:05,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 751 transitions. [2023-11-29 01:07:05,119 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:05,119 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 751 transitions. [2023-11-29 01:07:05,120 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 751 transitions. [2023-11-29 01:07:05,135 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2023-11-29 01:07:05,136 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4900793650793651) internal successors, (751), 503 states have internal predecessors, (751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:05,139 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 751 transitions. [2023-11-29 01:07:05,139 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 751 transitions. [2023-11-29 01:07:05,140 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:05,141 INFO L428 stractBuchiCegarLoop]: Abstraction has 504 states and 751 transitions. [2023-11-29 01:07:05,141 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 01:07:05,141 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 751 transitions. [2023-11-29 01:07:05,144 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-29 01:07:05,144 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:05,144 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:05,145 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:05,146 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:05,146 INFO L748 eck$LassoCheckResult]: Stem: 2319#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 2320#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 2425#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2426#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2443#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 2444#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2254#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2255#L411-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2532#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2533#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2499#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2223#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 2224#L586-2 assume !(0 == ~T1_E~0); 2275#L591-1 assume !(0 == ~T2_E~0); 2389#L596-1 assume !(0 == ~T3_E~0); 2390#L601-1 assume !(0 == ~T4_E~0); 2431#L606-1 assume !(0 == ~T5_E~0); 2432#L611-1 assume !(0 == ~E_1~0); 2507#L616-1 assume !(0 == ~E_2~0); 2508#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 2150#L626-1 assume !(0 == ~E_4~0); 2151#L631-1 assume !(0 == ~E_5~0); 2314#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2145#L279 assume 1 == ~m_pc~0; 2146#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2395#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2289#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2290#L720 assume !(0 != activate_threads_~tmp~1#1); 2454#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2321#L298 assume !(1 == ~t1_pc~0); 2092#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2093#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2118#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2119#L728 assume !(0 != activate_threads_~tmp___0~0#1); 2159#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2281#L317 assume 1 == ~t2_pc~0; 2282#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2423#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2430#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2330#L736 assume !(0 != activate_threads_~tmp___1~0#1); 2331#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2496#L336 assume 1 == ~t3_pc~0; 2368#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2369#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2065#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2066#L744 assume !(0 != activate_threads_~tmp___2~0#1); 2462#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2503#L355 assume !(1 == ~t4_pc~0); 2386#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2241#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2189#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2190#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2169#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2170#L374 assume 1 == ~t5_pc~0; 2525#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2305#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2295#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2296#L760 assume !(0 != activate_threads_~tmp___4~0#1); 2414#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2415#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 2544#L649-2 assume !(1 == ~T1_E~0); 2131#L654-1 assume !(1 == ~T2_E~0); 2132#L659-1 assume !(1 == ~T3_E~0); 2329#L664-1 assume !(1 == ~T4_E~0); 2123#L669-1 assume !(1 == ~T5_E~0); 2124#L674-1 assume !(1 == ~E_1~0); 2488#L679-1 assume !(1 == ~E_2~0); 2228#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 2229#L689-1 assume !(1 == ~E_4~0); 2382#L694-1 assume !(1 == ~E_5~0); 2380#L699-1 assume { :end_inline_reset_delta_events } true; 2381#L900-2 [2023-11-29 01:07:05,147 INFO L750 eck$LassoCheckResult]: Loop: 2381#L900-2 assume !false; 2550#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2300#L561-1 assume !false; 2356#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2348#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2094#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2095#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2217#L486 assume !(0 != eval_~tmp~0#1); 2196#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2197#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2519#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2487#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2397#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2245#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2246#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2410#L606-3 assume !(0 == ~T5_E~0); 2446#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2447#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2139#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2090#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2091#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2096#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2097#L279-18 assume 1 == ~m_pc~0; 2204#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2205#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2334#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 2335#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2509#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2413#L298-18 assume 1 == ~t1_pc~0; 2070#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2064#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2253#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2271#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2272#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2391#L317-18 assume 1 == ~t2_pc~0; 2306#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2307#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2421#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2256#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2257#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2512#L336-18 assume 1 == ~t3_pc~0; 2492#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2493#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2448#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2357#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2198#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2199#L355-18 assume 1 == ~t4_pc~0; 2472#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2461#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2362#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2363#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2291#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2292#L374-18 assume 1 == ~t5_pc~0; 2502#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2353#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2293#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2294#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2455#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2456#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2367#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2347#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2208#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2209#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2098#L669-3 assume !(1 == ~T5_E~0); 2099#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2088#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2089#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2048#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2049#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2083#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2084#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2086#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2396#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 2379#L919 assume !(0 == start_simulation_~tmp~3#1); 2101#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 2478#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 2077#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 2115#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 2116#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2375#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2513#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 2501#L932 assume !(0 != start_simulation_~tmp___0~1#1); 2381#L900-2 [2023-11-29 01:07:05,147 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:05,147 INFO L85 PathProgramCache]: Analyzing trace with hash 2124947816, now seen corresponding path program 1 times [2023-11-29 01:07:05,148 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:05,148 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1019771713] [2023-11-29 01:07:05,148 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:05,148 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:05,162 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:05,199 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:05,199 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:05,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1019771713] [2023-11-29 01:07:05,200 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1019771713] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:05,200 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:05,200 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:05,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1044271984] [2023-11-29 01:07:05,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:05,201 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:05,202 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:05,202 INFO L85 PathProgramCache]: Analyzing trace with hash -1398059989, now seen corresponding path program 1 times [2023-11-29 01:07:05,202 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:05,202 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [632169067] [2023-11-29 01:07:05,202 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:05,202 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:05,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:05,291 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:05,291 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:05,291 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [632169067] [2023-11-29 01:07:05,292 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [632169067] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:05,292 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:05,292 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:05,292 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027495673] [2023-11-29 01:07:05,292 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:05,293 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:05,293 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:05,294 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:05,294 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:05,294 INFO L87 Difference]: Start difference. First operand 504 states and 751 transitions. cyclomatic complexity: 248 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:05,308 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:05,308 INFO L93 Difference]: Finished difference Result 504 states and 750 transitions. [2023-11-29 01:07:05,308 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 750 transitions. [2023-11-29 01:07:05,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-29 01:07:05,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 750 transitions. [2023-11-29 01:07:05,315 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2023-11-29 01:07:05,315 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2023-11-29 01:07:05,315 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 750 transitions. [2023-11-29 01:07:05,316 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:05,316 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 750 transitions. [2023-11-29 01:07:05,317 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 750 transitions. [2023-11-29 01:07:05,322 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2023-11-29 01:07:05,323 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4880952380952381) internal successors, (750), 503 states have internal predecessors, (750), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:05,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 750 transitions. [2023-11-29 01:07:05,325 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 750 transitions. [2023-11-29 01:07:05,326 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:05,326 INFO L428 stractBuchiCegarLoop]: Abstraction has 504 states and 750 transitions. [2023-11-29 01:07:05,327 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 01:07:05,327 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 750 transitions. [2023-11-29 01:07:05,329 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-29 01:07:05,329 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:05,330 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:05,331 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:05,331 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:05,331 INFO L748 eck$LassoCheckResult]: Stem: 3336#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 3337#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 3442#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3443#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3460#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 3461#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3271#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3272#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3549#L416-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3550#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3516#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3240#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 3241#L586-2 assume !(0 == ~T1_E~0); 3292#L591-1 assume !(0 == ~T2_E~0); 3406#L596-1 assume !(0 == ~T3_E~0); 3407#L601-1 assume !(0 == ~T4_E~0); 3448#L606-1 assume !(0 == ~T5_E~0); 3449#L611-1 assume !(0 == ~E_1~0); 3524#L616-1 assume !(0 == ~E_2~0); 3525#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3167#L626-1 assume !(0 == ~E_4~0); 3168#L631-1 assume !(0 == ~E_5~0); 3331#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3162#L279 assume 1 == ~m_pc~0; 3163#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3412#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3306#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3307#L720 assume !(0 != activate_threads_~tmp~1#1); 3471#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3338#L298 assume !(1 == ~t1_pc~0); 3109#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3110#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3135#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3136#L728 assume !(0 != activate_threads_~tmp___0~0#1); 3176#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3298#L317 assume 1 == ~t2_pc~0; 3299#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3440#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3447#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3347#L736 assume !(0 != activate_threads_~tmp___1~0#1); 3348#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3513#L336 assume 1 == ~t3_pc~0; 3385#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3386#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3082#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3083#L744 assume !(0 != activate_threads_~tmp___2~0#1); 3479#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3520#L355 assume !(1 == ~t4_pc~0); 3403#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3258#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3206#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3207#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3186#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3187#L374 assume 1 == ~t5_pc~0; 3542#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3322#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3312#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3313#L760 assume !(0 != activate_threads_~tmp___4~0#1); 3431#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3432#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 3561#L649-2 assume !(1 == ~T1_E~0); 3148#L654-1 assume !(1 == ~T2_E~0); 3149#L659-1 assume !(1 == ~T3_E~0); 3346#L664-1 assume !(1 == ~T4_E~0); 3140#L669-1 assume !(1 == ~T5_E~0); 3141#L674-1 assume !(1 == ~E_1~0); 3505#L679-1 assume !(1 == ~E_2~0); 3245#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 3246#L689-1 assume !(1 == ~E_4~0); 3399#L694-1 assume !(1 == ~E_5~0); 3397#L699-1 assume { :end_inline_reset_delta_events } true; 3398#L900-2 [2023-11-29 01:07:05,331 INFO L750 eck$LassoCheckResult]: Loop: 3398#L900-2 assume !false; 3567#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3317#L561-1 assume !false; 3373#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3365#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3111#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3112#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3234#L486 assume !(0 != eval_~tmp~0#1); 3213#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3214#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3536#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3504#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3414#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3262#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3263#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3427#L606-3 assume !(0 == ~T5_E~0); 3463#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3464#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3156#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3107#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3108#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3113#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3114#L279-18 assume 1 == ~m_pc~0; 3221#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3222#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3351#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 3352#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3526#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3430#L298-18 assume !(1 == ~t1_pc~0); 3080#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 3081#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3270#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 3288#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3289#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3408#L317-18 assume 1 == ~t2_pc~0; 3323#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3324#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3438#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3273#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3274#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3529#L336-18 assume 1 == ~t3_pc~0; 3509#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3510#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3465#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3374#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3215#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3216#L355-18 assume 1 == ~t4_pc~0; 3489#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3478#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3379#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3380#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3308#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3309#L374-18 assume !(1 == ~t5_pc~0); 3491#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 3370#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3310#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3311#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3472#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3473#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3384#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3364#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3225#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3226#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3115#L669-3 assume !(1 == ~T5_E~0); 3116#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3105#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3106#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3065#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3066#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3100#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3101#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3103#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3413#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 3396#L919 assume !(0 == start_simulation_~tmp~3#1); 3118#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 3495#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 3094#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 3132#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 3133#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3392#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3530#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 3518#L932 assume !(0 != start_simulation_~tmp___0~1#1); 3398#L900-2 [2023-11-29 01:07:05,332 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:05,332 INFO L85 PathProgramCache]: Analyzing trace with hash -2115626582, now seen corresponding path program 1 times [2023-11-29 01:07:05,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:05,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [351238067] [2023-11-29 01:07:05,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:05,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:05,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:05,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:05,377 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:05,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [351238067] [2023-11-29 01:07:05,377 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [351238067] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:05,377 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:05,378 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:05,378 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2090667512] [2023-11-29 01:07:05,378 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:05,378 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:05,379 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:05,379 INFO L85 PathProgramCache]: Analyzing trace with hash -1352402967, now seen corresponding path program 1 times [2023-11-29 01:07:05,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:05,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [852980370] [2023-11-29 01:07:05,380 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:05,380 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:05,393 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:05,443 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:05,443 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:05,444 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [852980370] [2023-11-29 01:07:05,444 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [852980370] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:05,444 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:05,444 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:05,444 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1283382384] [2023-11-29 01:07:05,445 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:05,445 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:05,445 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:05,446 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:05,446 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:05,446 INFO L87 Difference]: Start difference. First operand 504 states and 750 transitions. cyclomatic complexity: 247 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:05,459 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:05,459 INFO L93 Difference]: Finished difference Result 504 states and 749 transitions. [2023-11-29 01:07:05,459 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 749 transitions. [2023-11-29 01:07:05,463 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-29 01:07:05,466 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 749 transitions. [2023-11-29 01:07:05,466 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2023-11-29 01:07:05,467 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2023-11-29 01:07:05,467 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 749 transitions. [2023-11-29 01:07:05,468 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:05,468 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 749 transitions. [2023-11-29 01:07:05,469 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 749 transitions. [2023-11-29 01:07:05,474 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2023-11-29 01:07:05,475 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4861111111111112) internal successors, (749), 503 states have internal predecessors, (749), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:05,476 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 749 transitions. [2023-11-29 01:07:05,477 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 749 transitions. [2023-11-29 01:07:05,477 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:05,478 INFO L428 stractBuchiCegarLoop]: Abstraction has 504 states and 749 transitions. [2023-11-29 01:07:05,478 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 01:07:05,479 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 749 transitions. [2023-11-29 01:07:05,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-29 01:07:05,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:05,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:05,484 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:05,484 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:05,484 INFO L748 eck$LassoCheckResult]: Stem: 4353#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 4354#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 4459#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4460#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4477#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 4478#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4288#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4289#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4566#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4567#L421-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4533#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4257#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 4258#L586-2 assume !(0 == ~T1_E~0); 4309#L591-1 assume !(0 == ~T2_E~0); 4423#L596-1 assume !(0 == ~T3_E~0); 4424#L601-1 assume !(0 == ~T4_E~0); 4465#L606-1 assume !(0 == ~T5_E~0); 4466#L611-1 assume !(0 == ~E_1~0); 4541#L616-1 assume !(0 == ~E_2~0); 4542#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 4184#L626-1 assume !(0 == ~E_4~0); 4185#L631-1 assume !(0 == ~E_5~0); 4348#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4179#L279 assume 1 == ~m_pc~0; 4180#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4429#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4323#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4324#L720 assume !(0 != activate_threads_~tmp~1#1); 4488#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4355#L298 assume !(1 == ~t1_pc~0); 4126#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4127#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4152#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4153#L728 assume !(0 != activate_threads_~tmp___0~0#1); 4193#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4315#L317 assume 1 == ~t2_pc~0; 4316#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4457#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4464#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4364#L736 assume !(0 != activate_threads_~tmp___1~0#1); 4365#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4530#L336 assume 1 == ~t3_pc~0; 4402#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4403#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4099#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4100#L744 assume !(0 != activate_threads_~tmp___2~0#1); 4496#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4537#L355 assume !(1 == ~t4_pc~0); 4420#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4275#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4223#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4224#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4203#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4204#L374 assume 1 == ~t5_pc~0; 4559#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4339#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4329#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4330#L760 assume !(0 != activate_threads_~tmp___4~0#1); 4448#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4449#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 4578#L649-2 assume !(1 == ~T1_E~0); 4165#L654-1 assume !(1 == ~T2_E~0); 4166#L659-1 assume !(1 == ~T3_E~0); 4363#L664-1 assume !(1 == ~T4_E~0); 4157#L669-1 assume !(1 == ~T5_E~0); 4158#L674-1 assume !(1 == ~E_1~0); 4522#L679-1 assume !(1 == ~E_2~0); 4262#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4263#L689-1 assume !(1 == ~E_4~0); 4416#L694-1 assume !(1 == ~E_5~0); 4414#L699-1 assume { :end_inline_reset_delta_events } true; 4415#L900-2 [2023-11-29 01:07:05,485 INFO L750 eck$LassoCheckResult]: Loop: 4415#L900-2 assume !false; 4584#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4334#L561-1 assume !false; 4390#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4382#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4128#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4129#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4251#L486 assume !(0 != eval_~tmp~0#1); 4230#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4231#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4553#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4521#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4431#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4279#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4280#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4444#L606-3 assume !(0 == ~T5_E~0); 4480#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4481#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4173#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4124#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4125#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4130#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4131#L279-18 assume !(1 == ~m_pc~0); 4240#L279-20 is_master_triggered_~__retres1~0#1 := 0; 4239#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4368#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 4369#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4543#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4447#L298-18 assume !(1 == ~t1_pc~0); 4097#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 4098#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4287#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4305#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4306#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4425#L317-18 assume 1 == ~t2_pc~0; 4340#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4341#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4455#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4290#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4291#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4546#L336-18 assume !(1 == ~t3_pc~0); 4528#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 4527#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4482#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4391#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4232#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4233#L355-18 assume 1 == ~t4_pc~0; 4506#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4495#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4396#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4397#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4325#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4326#L374-18 assume 1 == ~t5_pc~0; 4536#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4387#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4327#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4328#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4489#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4490#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4401#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4381#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4242#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4243#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4132#L669-3 assume !(1 == ~T5_E~0); 4133#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4122#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4123#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4082#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4083#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4117#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4118#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4120#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4430#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 4413#L919 assume !(0 == start_simulation_~tmp~3#1); 4135#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 4512#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 4111#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 4149#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 4150#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4409#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4547#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 4535#L932 assume !(0 != start_simulation_~tmp___0~1#1); 4415#L900-2 [2023-11-29 01:07:05,486 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:05,486 INFO L85 PathProgramCache]: Analyzing trace with hash -1698229976, now seen corresponding path program 1 times [2023-11-29 01:07:05,486 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:05,486 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [412947674] [2023-11-29 01:07:05,486 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:05,487 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:05,496 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:05,518 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:05,519 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:05,519 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [412947674] [2023-11-29 01:07:05,519 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [412947674] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:05,519 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:05,519 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:05,520 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1236888982] [2023-11-29 01:07:05,520 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:05,520 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:05,521 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:05,521 INFO L85 PathProgramCache]: Analyzing trace with hash -1062290040, now seen corresponding path program 1 times [2023-11-29 01:07:05,521 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:05,521 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749125713] [2023-11-29 01:07:05,521 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:05,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:05,532 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:05,574 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:05,574 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:05,575 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1749125713] [2023-11-29 01:07:05,575 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1749125713] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:05,575 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:05,575 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:05,575 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1268264464] [2023-11-29 01:07:05,575 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:05,576 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:05,576 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:05,576 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:05,577 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:05,577 INFO L87 Difference]: Start difference. First operand 504 states and 749 transitions. cyclomatic complexity: 246 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:05,590 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:05,590 INFO L93 Difference]: Finished difference Result 504 states and 748 transitions. [2023-11-29 01:07:05,590 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 504 states and 748 transitions. [2023-11-29 01:07:05,619 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-29 01:07:05,624 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 504 states to 504 states and 748 transitions. [2023-11-29 01:07:05,624 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 504 [2023-11-29 01:07:05,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 504 [2023-11-29 01:07:05,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 504 states and 748 transitions. [2023-11-29 01:07:05,626 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:05,626 INFO L218 hiAutomatonCegarLoop]: Abstraction has 504 states and 748 transitions. [2023-11-29 01:07:05,627 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 504 states and 748 transitions. [2023-11-29 01:07:05,634 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 504 to 504. [2023-11-29 01:07:05,636 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 504 states, 504 states have (on average 1.4841269841269842) internal successors, (748), 503 states have internal predecessors, (748), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:05,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 504 states to 504 states and 748 transitions. [2023-11-29 01:07:05,639 INFO L240 hiAutomatonCegarLoop]: Abstraction has 504 states and 748 transitions. [2023-11-29 01:07:05,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:05,640 INFO L428 stractBuchiCegarLoop]: Abstraction has 504 states and 748 transitions. [2023-11-29 01:07:05,640 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 01:07:05,640 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 504 states and 748 transitions. [2023-11-29 01:07:05,644 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 427 [2023-11-29 01:07:05,644 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:05,644 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:05,645 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:05,645 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:05,646 INFO L748 eck$LassoCheckResult]: Stem: 5370#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 5371#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 5476#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5477#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5494#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 5495#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5305#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5306#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5583#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5584#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5550#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5274#L586 assume 0 == ~M_E~0;~M_E~0 := 1; 5275#L586-2 assume !(0 == ~T1_E~0); 5326#L591-1 assume !(0 == ~T2_E~0); 5440#L596-1 assume !(0 == ~T3_E~0); 5441#L601-1 assume !(0 == ~T4_E~0); 5482#L606-1 assume !(0 == ~T5_E~0); 5483#L611-1 assume !(0 == ~E_1~0); 5558#L616-1 assume !(0 == ~E_2~0); 5559#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5201#L626-1 assume !(0 == ~E_4~0); 5202#L631-1 assume !(0 == ~E_5~0); 5365#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5196#L279 assume 1 == ~m_pc~0; 5197#L280 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5446#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5340#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5341#L720 assume !(0 != activate_threads_~tmp~1#1); 5505#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5372#L298 assume !(1 == ~t1_pc~0); 5143#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5144#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5169#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5170#L728 assume !(0 != activate_threads_~tmp___0~0#1); 5210#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5332#L317 assume 1 == ~t2_pc~0; 5333#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5474#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5381#L736 assume !(0 != activate_threads_~tmp___1~0#1); 5382#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5547#L336 assume 1 == ~t3_pc~0; 5419#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5420#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5117#L744 assume !(0 != activate_threads_~tmp___2~0#1); 5513#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5554#L355 assume !(1 == ~t4_pc~0); 5437#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5292#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5240#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5241#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5220#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5221#L374 assume 1 == ~t5_pc~0; 5576#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5356#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5346#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5347#L760 assume !(0 != activate_threads_~tmp___4~0#1); 5465#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5466#L649 assume 1 == ~M_E~0;~M_E~0 := 2; 5595#L649-2 assume !(1 == ~T1_E~0); 5182#L654-1 assume !(1 == ~T2_E~0); 5183#L659-1 assume !(1 == ~T3_E~0); 5380#L664-1 assume !(1 == ~T4_E~0); 5174#L669-1 assume !(1 == ~T5_E~0); 5175#L674-1 assume !(1 == ~E_1~0); 5539#L679-1 assume !(1 == ~E_2~0); 5279#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 5280#L689-1 assume !(1 == ~E_4~0); 5433#L694-1 assume !(1 == ~E_5~0); 5431#L699-1 assume { :end_inline_reset_delta_events } true; 5432#L900-2 [2023-11-29 01:07:05,646 INFO L750 eck$LassoCheckResult]: Loop: 5432#L900-2 assume !false; 5601#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5351#L561-1 assume !false; 5407#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5399#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5145#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5146#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5268#L486 assume !(0 != eval_~tmp~0#1); 5247#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5248#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5570#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5538#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5448#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5296#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5297#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5461#L606-3 assume !(0 == ~T5_E~0); 5497#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5498#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5190#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5141#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5142#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5147#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5148#L279-18 assume 1 == ~m_pc~0; 5255#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5256#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5385#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 5386#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5560#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5464#L298-18 assume 1 == ~t1_pc~0; 5121#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5115#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5304#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5322#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5323#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5442#L317-18 assume 1 == ~t2_pc~0; 5357#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5358#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5472#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5307#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5308#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5563#L336-18 assume 1 == ~t3_pc~0; 5543#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5544#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5499#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5408#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5249#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5250#L355-18 assume 1 == ~t4_pc~0; 5523#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5512#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5413#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5414#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5342#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5343#L374-18 assume 1 == ~t5_pc~0; 5553#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5404#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5344#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5345#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5506#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5507#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5418#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5398#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5259#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5260#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5149#L669-3 assume !(1 == ~T5_E~0); 5150#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5139#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5140#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5099#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5100#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5134#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5135#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5137#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5447#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 5430#L919 assume !(0 == start_simulation_~tmp~3#1); 5152#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 5529#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 5128#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 5166#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 5167#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5426#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5564#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 5552#L932 assume !(0 != start_simulation_~tmp___0~1#1); 5432#L900-2 [2023-11-29 01:07:05,647 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:05,647 INFO L85 PathProgramCache]: Analyzing trace with hash 1917465066, now seen corresponding path program 1 times [2023-11-29 01:07:05,647 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:05,648 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [133382889] [2023-11-29 01:07:05,648 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:05,648 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:05,659 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:05,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:05,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:05,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [133382889] [2023-11-29 01:07:05,696 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [133382889] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:05,697 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:05,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:07:05,698 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1051851812] [2023-11-29 01:07:05,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:05,698 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:05,698 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:05,699 INFO L85 PathProgramCache]: Analyzing trace with hash -1398059989, now seen corresponding path program 2 times [2023-11-29 01:07:05,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:05,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1083338163] [2023-11-29 01:07:05,699 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:05,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:05,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:05,763 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:05,764 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:05,764 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1083338163] [2023-11-29 01:07:05,764 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1083338163] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:05,764 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:05,764 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:05,765 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1752933372] [2023-11-29 01:07:05,765 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:05,765 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:05,765 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:05,766 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:05,766 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:05,766 INFO L87 Difference]: Start difference. First operand 504 states and 748 transitions. cyclomatic complexity: 245 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:05,860 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:05,860 INFO L93 Difference]: Finished difference Result 887 states and 1304 transitions. [2023-11-29 01:07:05,861 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 887 states and 1304 transitions. [2023-11-29 01:07:05,868 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 810 [2023-11-29 01:07:05,877 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 887 states to 887 states and 1304 transitions. [2023-11-29 01:07:05,877 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 887 [2023-11-29 01:07:05,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 887 [2023-11-29 01:07:05,878 INFO L73 IsDeterministic]: Start isDeterministic. Operand 887 states and 1304 transitions. [2023-11-29 01:07:05,880 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:05,880 INFO L218 hiAutomatonCegarLoop]: Abstraction has 887 states and 1304 transitions. [2023-11-29 01:07:05,882 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 887 states and 1304 transitions. [2023-11-29 01:07:05,898 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 887 to 887. [2023-11-29 01:07:05,900 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 887 states, 887 states have (on average 1.4701240135287486) internal successors, (1304), 886 states have internal predecessors, (1304), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:05,905 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 887 states to 887 states and 1304 transitions. [2023-11-29 01:07:05,905 INFO L240 hiAutomatonCegarLoop]: Abstraction has 887 states and 1304 transitions. [2023-11-29 01:07:05,905 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:05,906 INFO L428 stractBuchiCegarLoop]: Abstraction has 887 states and 1304 transitions. [2023-11-29 01:07:05,906 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 01:07:05,906 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 887 states and 1304 transitions. [2023-11-29 01:07:05,913 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 810 [2023-11-29 01:07:05,913 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:05,913 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:05,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:05,915 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:05,915 INFO L748 eck$LassoCheckResult]: Stem: 6769#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 6770#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 6878#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6879#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6896#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 6897#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6704#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6705#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6987#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6988#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6954#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6676#L586 assume !(0 == ~M_E~0); 6677#L586-2 assume !(0 == ~T1_E~0); 6725#L591-1 assume !(0 == ~T2_E~0); 6842#L596-1 assume !(0 == ~T3_E~0); 6843#L601-1 assume !(0 == ~T4_E~0); 6884#L606-1 assume !(0 == ~T5_E~0); 6885#L611-1 assume !(0 == ~E_1~0); 6961#L616-1 assume !(0 == ~E_2~0); 6962#L621-1 assume 0 == ~E_3~0;~E_3~0 := 1; 6601#L626-1 assume !(0 == ~E_4~0); 6602#L631-1 assume !(0 == ~E_5~0); 6764#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6596#L279 assume !(1 == ~m_pc~0); 6598#L279-2 is_master_triggered_~__retres1~0#1 := 0; 6908#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6739#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6740#L720 assume !(0 != activate_threads_~tmp~1#1); 6907#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6771#L298 assume !(1 == ~t1_pc~0); 6545#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6546#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6573#L728 assume !(0 != activate_threads_~tmp___0~0#1); 6610#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6731#L317 assume 1 == ~t2_pc~0; 6732#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6877#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6883#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6781#L736 assume !(0 != activate_threads_~tmp___1~0#1); 6782#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6951#L336 assume 1 == ~t3_pc~0; 6820#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6821#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6516#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6517#L744 assume !(0 != activate_threads_~tmp___2~0#1); 6916#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6958#L355 assume !(1 == ~t4_pc~0); 6841#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6693#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6640#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6641#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6623#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6624#L374 assume 1 == ~t5_pc~0; 6980#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6758#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6745#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6746#L760 assume !(0 != activate_threads_~tmp___4~0#1); 6866#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6867#L649 assume !(1 == ~M_E~0); 7000#L649-2 assume !(1 == ~T1_E~0); 6582#L654-1 assume !(1 == ~T2_E~0); 6583#L659-1 assume !(1 == ~T3_E~0); 6779#L664-1 assume !(1 == ~T4_E~0); 6574#L669-1 assume !(1 == ~T5_E~0); 6575#L674-1 assume !(1 == ~E_1~0); 6942#L679-1 assume !(1 == ~E_2~0); 6678#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 6679#L689-1 assume !(1 == ~E_4~0); 6836#L694-1 assume !(1 == ~E_5~0); 6833#L699-1 assume { :end_inline_reset_delta_events } true; 6834#L900-2 [2023-11-29 01:07:05,915 INFO L750 eck$LassoCheckResult]: Loop: 6834#L900-2 assume !false; 7007#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6750#L561-1 assume !false; 6808#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6799#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6543#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6544#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6667#L486 assume !(0 != eval_~tmp~0#1); 6647#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6648#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6974#L586-3 assume !(0 == ~M_E~0); 6941#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6849#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6695#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6696#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6862#L606-3 assume !(0 == ~T5_E~0); 6899#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6900#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6590#L621-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6541#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6542#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6547#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6548#L279-18 assume !(1 == ~m_pc~0); 6656#L279-20 is_master_triggered_~__retres1~0#1 := 0; 6791#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6784#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 6785#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6963#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6865#L298-18 assume !(1 == ~t1_pc~0); 6514#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 6515#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6703#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6721#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6722#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6844#L317-18 assume 1 == ~t2_pc~0; 6754#L318-6 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6755#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6873#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6706#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6707#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6966#L336-18 assume 1 == ~t3_pc~0; 6946#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6947#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6901#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6807#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6649#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6650#L355-18 assume !(1 == ~t4_pc~0); 6914#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 6915#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6812#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6813#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6741#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6742#L374-18 assume !(1 == ~t5_pc~0); 6928#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 6804#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6743#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6744#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6909#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6910#L649-3 assume !(1 == ~M_E~0); 6818#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6798#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6658#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6659#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6549#L669-3 assume !(1 == ~T5_E~0); 6550#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6539#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6540#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6499#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6500#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6534#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6535#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6537#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6848#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 6832#L919 assume !(0 == start_simulation_~tmp~3#1); 6552#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 6932#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 6528#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 6566#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 6567#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6826#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6967#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 6955#L932 assume !(0 != start_simulation_~tmp___0~1#1); 6834#L900-2 [2023-11-29 01:07:05,916 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:05,916 INFO L85 PathProgramCache]: Analyzing trace with hash -484678139, now seen corresponding path program 1 times [2023-11-29 01:07:05,916 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:05,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1264130300] [2023-11-29 01:07:05,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:05,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:05,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:05,985 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:05,986 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:05,986 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1264130300] [2023-11-29 01:07:05,986 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1264130300] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:05,986 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:05,986 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:05,986 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [286606130] [2023-11-29 01:07:05,987 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:05,987 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:05,987 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:05,987 INFO L85 PathProgramCache]: Analyzing trace with hash -785849181, now seen corresponding path program 1 times [2023-11-29 01:07:05,988 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:05,988 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [617448500] [2023-11-29 01:07:05,988 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:05,988 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:06,001 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:06,053 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:06,053 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:06,054 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [617448500] [2023-11-29 01:07:06,054 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [617448500] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:06,054 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:06,054 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:06,054 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [676001373] [2023-11-29 01:07:06,055 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:06,055 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:06,055 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:06,056 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:07:06,056 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:07:06,056 INFO L87 Difference]: Start difference. First operand 887 states and 1304 transitions. cyclomatic complexity: 418 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:06,211 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:06,211 INFO L93 Difference]: Finished difference Result 1620 states and 2381 transitions. [2023-11-29 01:07:06,211 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1620 states and 2381 transitions. [2023-11-29 01:07:06,225 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1532 [2023-11-29 01:07:06,238 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1620 states to 1620 states and 2381 transitions. [2023-11-29 01:07:06,238 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1620 [2023-11-29 01:07:06,240 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1620 [2023-11-29 01:07:06,240 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1620 states and 2381 transitions. [2023-11-29 01:07:06,243 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:06,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1620 states and 2381 transitions. [2023-11-29 01:07:06,246 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1620 states and 2381 transitions. [2023-11-29 01:07:06,277 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1620 to 1618. [2023-11-29 01:07:06,281 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1618 states, 1618 states have (on average 1.4703337453646477) internal successors, (2379), 1617 states have internal predecessors, (2379), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:06,288 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1618 states to 1618 states and 2379 transitions. [2023-11-29 01:07:06,288 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1618 states and 2379 transitions. [2023-11-29 01:07:06,288 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:07:06,289 INFO L428 stractBuchiCegarLoop]: Abstraction has 1618 states and 2379 transitions. [2023-11-29 01:07:06,289 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 01:07:06,289 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1618 states and 2379 transitions. [2023-11-29 01:07:06,299 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1532 [2023-11-29 01:07:06,299 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:06,299 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:06,300 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:06,300 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:06,301 INFO L748 eck$LassoCheckResult]: Stem: 9293#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 9294#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 9404#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9405#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9422#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 9423#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9227#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9228#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9529#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9530#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9491#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9197#L586 assume !(0 == ~M_E~0); 9198#L586-2 assume !(0 == ~T1_E~0); 9248#L591-1 assume !(0 == ~T2_E~0); 9367#L596-1 assume !(0 == ~T3_E~0); 9368#L601-1 assume !(0 == ~T4_E~0); 9409#L606-1 assume !(0 == ~T5_E~0); 9410#L611-1 assume !(0 == ~E_1~0); 9499#L616-1 assume !(0 == ~E_2~0); 9500#L621-1 assume !(0 == ~E_3~0); 9121#L626-1 assume !(0 == ~E_4~0); 9122#L631-1 assume !(0 == ~E_5~0); 9288#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9118#L279 assume !(1 == ~m_pc~0); 9120#L279-2 is_master_triggered_~__retres1~0#1 := 0; 9439#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9262#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 9263#L720 assume !(0 != activate_threads_~tmp~1#1); 9438#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9295#L298 assume !(1 == ~t1_pc~0); 9064#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9065#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9090#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9091#L728 assume !(0 != activate_threads_~tmp___0~0#1); 9130#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9254#L317 assume 1 == ~t2_pc~0; 9255#L318 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9402#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9408#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9305#L736 assume !(0 != activate_threads_~tmp___1~0#1); 9306#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9484#L336 assume 1 == ~t3_pc~0; 9346#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9347#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9035#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9036#L744 assume !(0 != activate_threads_~tmp___2~0#1); 9447#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9495#L355 assume !(1 == ~t4_pc~0); 9366#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9216#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9160#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9161#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9143#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9144#L374 assume 1 == ~t5_pc~0; 9520#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9282#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9268#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9269#L760 assume !(0 != activate_threads_~tmp___4~0#1); 9391#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9392#L649 assume !(1 == ~M_E~0); 9551#L649-2 assume !(1 == ~T1_E~0); 9100#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9101#L659-1 assume !(1 == ~T3_E~0); 9646#L664-1 assume !(1 == ~T4_E~0); 9645#L669-1 assume !(1 == ~T5_E~0); 9644#L674-1 assume !(1 == ~E_1~0); 9643#L679-1 assume !(1 == ~E_2~0); 9642#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 9201#L689-1 assume !(1 == ~E_4~0); 9361#L694-1 assume !(1 == ~E_5~0); 9629#L699-1 assume { :end_inline_reset_delta_events } true; 9621#L900-2 [2023-11-29 01:07:06,301 INFO L750 eck$LassoCheckResult]: Loop: 9621#L900-2 assume !false; 9615#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9611#L561-1 assume !false; 9610#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9608#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9603#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9602#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9600#L486 assume !(0 != eval_~tmp~0#1); 9599#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9598#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9597#L586-3 assume !(0 == ~M_E~0); 9596#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9593#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9594#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10599#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10598#L606-3 assume !(0 == ~T5_E~0); 10597#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10596#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10595#L621-3 assume !(0 == ~E_3~0); 10594#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10593#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10592#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10591#L279-18 assume !(1 == ~m_pc~0); 10589#L279-20 is_master_triggered_~__retres1~0#1 := 0; 10588#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10587#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 10586#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10585#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10584#L298-18 assume !(1 == ~t1_pc~0); 10582#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 10581#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10580#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10579#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10578#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10577#L317-18 assume !(1 == ~t2_pc~0); 10576#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 10574#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10573#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10572#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10571#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10570#L336-18 assume !(1 == ~t3_pc~0); 10568#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 10567#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10566#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10565#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10564#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10563#L355-18 assume 1 == ~t4_pc~0; 10561#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10560#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10354#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9828#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9829#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9492#L374-18 assume 1 == ~t5_pc~0; 9493#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9329#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9266#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9267#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9440#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9441#L649-3 assume !(1 == ~M_E~0); 9343#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9323#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9178#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9179#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9070#L669-3 assume !(1 == ~T5_E~0); 9071#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9058#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9059#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9018#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9019#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9053#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9054#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9056#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9373#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 9356#L919 assume !(0 == start_simulation_~tmp~3#1); 9069#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 9571#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 9677#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 9675#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 9668#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9656#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9640#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 9628#L932 assume !(0 != start_simulation_~tmp___0~1#1); 9621#L900-2 [2023-11-29 01:07:06,301 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:06,301 INFO L85 PathProgramCache]: Analyzing trace with hash 1446688901, now seen corresponding path program 1 times [2023-11-29 01:07:06,302 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:06,302 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748972443] [2023-11-29 01:07:06,302 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:06,302 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:06,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:06,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:06,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:06,398 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748972443] [2023-11-29 01:07:06,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [748972443] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:06,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:06,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:07:06,398 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [820274] [2023-11-29 01:07:06,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:06,399 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:06,399 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:06,400 INFO L85 PathProgramCache]: Analyzing trace with hash 259039073, now seen corresponding path program 1 times [2023-11-29 01:07:06,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:06,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1099515706] [2023-11-29 01:07:06,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:06,400 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:06,413 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:06,469 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:06,470 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:06,470 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1099515706] [2023-11-29 01:07:06,470 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1099515706] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:06,470 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:06,471 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:06,471 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1249666892] [2023-11-29 01:07:06,471 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:06,471 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:06,472 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:06,472 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:06,472 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:06,473 INFO L87 Difference]: Start difference. First operand 1618 states and 2379 transitions. cyclomatic complexity: 763 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:06,557 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:06,557 INFO L93 Difference]: Finished difference Result 3035 states and 4428 transitions. [2023-11-29 01:07:06,558 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3035 states and 4428 transitions. [2023-11-29 01:07:06,582 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2942 [2023-11-29 01:07:06,606 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3035 states to 3035 states and 4428 transitions. [2023-11-29 01:07:06,607 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3035 [2023-11-29 01:07:06,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3035 [2023-11-29 01:07:06,610 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3035 states and 4428 transitions. [2023-11-29 01:07:06,615 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:06,615 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3035 states and 4428 transitions. [2023-11-29 01:07:06,619 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3035 states and 4428 transitions. [2023-11-29 01:07:06,672 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3035 to 3027. [2023-11-29 01:07:06,679 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3027 states, 3027 states have (on average 1.4601916088536504) internal successors, (4420), 3026 states have internal predecessors, (4420), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:06,692 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3027 states to 3027 states and 4420 transitions. [2023-11-29 01:07:06,692 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3027 states and 4420 transitions. [2023-11-29 01:07:06,692 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:06,693 INFO L428 stractBuchiCegarLoop]: Abstraction has 3027 states and 4420 transitions. [2023-11-29 01:07:06,693 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 01:07:06,693 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3027 states and 4420 transitions. [2023-11-29 01:07:06,710 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2934 [2023-11-29 01:07:06,711 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:06,711 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:06,712 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:06,712 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:06,713 INFO L748 eck$LassoCheckResult]: Stem: 13959#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 13960#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 14077#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14078#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14099#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 14100#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13893#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13894#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14225#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 14226#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14177#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13863#L586 assume !(0 == ~M_E~0); 13864#L586-2 assume !(0 == ~T1_E~0); 13915#L591-1 assume !(0 == ~T2_E~0); 14038#L596-1 assume !(0 == ~T3_E~0); 14039#L601-1 assume !(0 == ~T4_E~0); 14087#L606-1 assume !(0 == ~T5_E~0); 14088#L611-1 assume !(0 == ~E_1~0); 14188#L616-1 assume !(0 == ~E_2~0); 14189#L621-1 assume !(0 == ~E_3~0); 13782#L626-1 assume !(0 == ~E_4~0); 13783#L631-1 assume !(0 == ~E_5~0); 13954#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13779#L279 assume !(1 == ~m_pc~0); 13781#L279-2 is_master_triggered_~__retres1~0#1 := 0; 14116#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13928#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13929#L720 assume !(0 != activate_threads_~tmp~1#1); 14115#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13961#L298 assume !(1 == ~t1_pc~0); 13726#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13727#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13752#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13753#L728 assume !(0 != activate_threads_~tmp___0~0#1); 13792#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13921#L317 assume !(1 == ~t2_pc~0); 13922#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 14135#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14083#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13973#L736 assume !(0 != activate_threads_~tmp___1~0#1); 13974#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14171#L336 assume 1 == ~t3_pc~0; 14014#L337 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14015#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13697#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13698#L744 assume !(0 != activate_threads_~tmp___2~0#1); 14124#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14183#L355 assume !(1 == ~t4_pc~0); 14037#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 13881#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13824#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13825#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13806#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13807#L374 assume 1 == ~t5_pc~0; 14216#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13947#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13935#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13936#L760 assume !(0 != activate_threads_~tmp___4~0#1); 14067#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14068#L649 assume !(1 == ~M_E~0); 14245#L649-2 assume !(1 == ~T1_E~0); 13762#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13763#L659-1 assume !(1 == ~T3_E~0); 13969#L664-1 assume !(1 == ~T4_E~0); 13970#L669-1 assume !(1 == ~T5_E~0); 14158#L674-1 assume !(1 == ~E_1~0); 14159#L679-1 assume !(1 == ~E_2~0); 13865#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 13866#L689-1 assume !(1 == ~E_4~0); 15787#L694-1 assume !(1 == ~E_5~0); 14028#L699-1 assume { :end_inline_reset_delta_events } true; 14029#L900-2 [2023-11-29 01:07:06,713 INFO L750 eck$LassoCheckResult]: Loop: 14029#L900-2 assume !false; 16400#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16396#L561-1 assume !false; 14001#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14002#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16390#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16389#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16388#L486 assume !(0 != eval_~tmp~0#1); 16387#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 14204#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 14205#L586-3 assume !(0 == ~M_E~0); 14157#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14047#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13884#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13885#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14063#L606-3 assume !(0 == ~T5_E~0); 14102#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14103#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13771#L621-3 assume !(0 == ~E_3~0); 13722#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13723#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13728#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13729#L279-18 assume !(1 == ~m_pc~0); 13840#L279-20 is_master_triggered_~__retres1~0#1 := 0; 13983#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13976#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 13977#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14190#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 14066#L298-18 assume 1 == ~t1_pc~0; 13702#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13696#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13892#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 13911#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13912#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14040#L317-18 assume !(1 == ~t2_pc~0); 14041#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 14062#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14074#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13895#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13896#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14193#L336-18 assume 1 == ~t3_pc~0; 14163#L337-6 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14164#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14105#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 14106#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16593#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14137#L355-18 assume 1 == ~t4_pc~0; 14138#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14123#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14007#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14008#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13930#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13931#L374-18 assume 1 == ~t5_pc~0; 14181#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13998#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13932#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13933#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 14117#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14118#L649-3 assume !(1 == ~M_E~0); 14251#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16568#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15939#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16567#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16566#L669-3 assume !(1 == ~T5_E~0); 16565#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16564#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16563#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15923#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16562#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16561#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 16545#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 16541#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 16539#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 16522#L919 assume !(0 == start_simulation_~tmp~3#1); 16506#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 14143#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 13709#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 13747#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 13748#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14018#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14194#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 14213#L932 assume !(0 != start_simulation_~tmp___0~1#1); 14029#L900-2 [2023-11-29 01:07:06,714 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:06,714 INFO L85 PathProgramCache]: Analyzing trace with hash -318127708, now seen corresponding path program 1 times [2023-11-29 01:07:06,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:06,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1299121438] [2023-11-29 01:07:06,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:06,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:06,726 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:06,766 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:06,766 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:06,767 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1299121438] [2023-11-29 01:07:06,767 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1299121438] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:06,767 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:06,767 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:07:06,767 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1646232658] [2023-11-29 01:07:06,768 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:06,768 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:06,768 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:06,768 INFO L85 PathProgramCache]: Analyzing trace with hash -1983215069, now seen corresponding path program 1 times [2023-11-29 01:07:06,768 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:06,769 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [834244671] [2023-11-29 01:07:06,769 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:06,769 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:06,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:06,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:06,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:06,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [834244671] [2023-11-29 01:07:06,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [834244671] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:06,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:06,829 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:06,829 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962616636] [2023-11-29 01:07:06,829 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:06,830 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:06,830 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:06,830 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:06,830 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:06,831 INFO L87 Difference]: Start difference. First operand 3027 states and 4420 transitions. cyclomatic complexity: 1397 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:06,920 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:06,920 INFO L93 Difference]: Finished difference Result 5566 states and 8084 transitions. [2023-11-29 01:07:06,920 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5566 states and 8084 transitions. [2023-11-29 01:07:06,958 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5458 [2023-11-29 01:07:07,032 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5566 states to 5566 states and 8084 transitions. [2023-11-29 01:07:07,032 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5566 [2023-11-29 01:07:07,038 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5566 [2023-11-29 01:07:07,039 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5566 states and 8084 transitions. [2023-11-29 01:07:07,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:07,049 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5566 states and 8084 transitions. [2023-11-29 01:07:07,056 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5566 states and 8084 transitions. [2023-11-29 01:07:07,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5566 to 5550. [2023-11-29 01:07:07,183 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5550 states, 5550 states have (on average 1.4536936936936937) internal successors, (8068), 5549 states have internal predecessors, (8068), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:07,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5550 states to 5550 states and 8068 transitions. [2023-11-29 01:07:07,208 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5550 states and 8068 transitions. [2023-11-29 01:07:07,209 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:07,210 INFO L428 stractBuchiCegarLoop]: Abstraction has 5550 states and 8068 transitions. [2023-11-29 01:07:07,210 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 01:07:07,210 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5550 states and 8068 transitions. [2023-11-29 01:07:07,237 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5442 [2023-11-29 01:07:07,237 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:07,237 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:07,238 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:07,238 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:07,239 INFO L748 eck$LassoCheckResult]: Stem: 22559#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 22560#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 22671#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22672#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 22689#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 22690#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 22494#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 22495#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 22808#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 22809#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 22769#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 22461#L586 assume !(0 == ~M_E~0); 22462#L586-2 assume !(0 == ~T1_E~0); 22516#L591-1 assume !(0 == ~T2_E~0); 22631#L596-1 assume !(0 == ~T3_E~0); 22632#L601-1 assume !(0 == ~T4_E~0); 22677#L606-1 assume !(0 == ~T5_E~0); 22678#L611-1 assume !(0 == ~E_1~0); 22778#L616-1 assume !(0 == ~E_2~0); 22779#L621-1 assume !(0 == ~E_3~0); 22386#L626-1 assume !(0 == ~E_4~0); 22387#L631-1 assume !(0 == ~E_5~0); 22554#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22381#L279 assume !(1 == ~m_pc~0); 22383#L279-2 is_master_triggered_~__retres1~0#1 := 0; 22706#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22529#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 22530#L720 assume !(0 != activate_threads_~tmp~1#1); 22705#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22561#L298 assume !(1 == ~t1_pc~0); 22326#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 22327#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22352#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 22353#L728 assume !(0 != activate_threads_~tmp___0~0#1); 22395#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22522#L317 assume !(1 == ~t2_pc~0); 22523#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 22729#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22676#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22570#L736 assume !(0 != activate_threads_~tmp___1~0#1); 22571#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22765#L336 assume !(1 == ~t3_pc~0); 22766#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 22841#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22299#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22300#L744 assume !(0 != activate_threads_~tmp___2~0#1); 22715#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22774#L355 assume !(1 == ~t4_pc~0); 22628#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 22481#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22426#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22427#L752 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22405#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22406#L374 assume 1 == ~t5_pc~0; 22801#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22544#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22535#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 22536#L760 assume !(0 != activate_threads_~tmp___4~0#1); 22659#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 22660#L649 assume !(1 == ~M_E~0); 22834#L649-2 assume !(1 == ~T1_E~0); 22365#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 22366#L659-1 assume !(1 == ~T3_E~0); 25084#L664-1 assume !(1 == ~T4_E~0); 25083#L669-1 assume !(1 == ~T5_E~0); 25082#L674-1 assume !(1 == ~E_1~0); 25081#L679-1 assume !(1 == ~E_2~0); 25080#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 22468#L689-1 assume !(1 == ~E_4~0); 25079#L694-1 assume !(1 == ~E_5~0); 25078#L699-1 assume { :end_inline_reset_delta_events } true; 25076#L900-2 [2023-11-29 01:07:07,239 INFO L750 eck$LassoCheckResult]: Loop: 25076#L900-2 assume !false; 25075#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 25071#L561-1 assume !false; 25070#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 25068#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25063#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25062#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 25060#L486 assume !(0 != eval_~tmp~0#1); 25061#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25515#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25513#L586-3 assume !(0 == ~M_E~0); 25511#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25509#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25507#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25504#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25501#L606-3 assume !(0 == ~T5_E~0); 25498#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 25495#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25492#L621-3 assume !(0 == ~E_3~0); 25489#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25486#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25483#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25480#L279-18 assume !(1 == ~m_pc~0); 25475#L279-20 is_master_triggered_~__retres1~0#1 := 0; 25472#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25469#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 25466#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25462#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25459#L298-18 assume 1 == ~t1_pc~0; 25456#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25451#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25448#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25445#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25442#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25438#L317-18 assume !(1 == ~t2_pc~0); 25435#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 25431#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25428#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25425#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25422#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25419#L336-18 assume !(1 == ~t3_pc~0); 25416#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 25413#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25410#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25407#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 25405#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25403#L355-18 assume 1 == ~t4_pc~0; 25400#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25398#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25394#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25389#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 25385#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25380#L374-18 assume 1 == ~t5_pc~0; 25376#L375-6 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25371#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25367#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25362#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 25359#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25355#L649-3 assume !(1 == ~M_E~0); 24846#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25347#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25329#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 25339#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25335#L669-3 assume !(1 == ~T5_E~0); 25332#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25327#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25322#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25311#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25317#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 25314#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 25302#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25292#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25286#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 24196#L919 assume !(0 == start_simulation_~tmp~3#1); 23376#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 23377#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 25089#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 25088#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 25087#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 25086#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 25085#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 25077#L932 assume !(0 != start_simulation_~tmp___0~1#1); 25076#L900-2 [2023-11-29 01:07:07,239 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:07,239 INFO L85 PathProgramCache]: Analyzing trace with hash -375271933, now seen corresponding path program 1 times [2023-11-29 01:07:07,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:07,240 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1889000194] [2023-11-29 01:07:07,240 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:07,240 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:07,250 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:07,297 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:07,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:07,298 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1889000194] [2023-11-29 01:07:07,298 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1889000194] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:07,298 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:07,298 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:07,298 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1099741079] [2023-11-29 01:07:07,299 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:07,299 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:07,299 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:07,300 INFO L85 PathProgramCache]: Analyzing trace with hash 156237826, now seen corresponding path program 1 times [2023-11-29 01:07:07,300 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:07,300 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738850065] [2023-11-29 01:07:07,300 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:07,300 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:07,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:07,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:07,358 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:07,358 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738850065] [2023-11-29 01:07:07,358 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [738850065] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:07,358 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:07,358 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:07,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1488849960] [2023-11-29 01:07:07,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:07,359 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:07,359 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:07,359 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:07:07,359 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:07:07,360 INFO L87 Difference]: Start difference. First operand 5550 states and 8068 transitions. cyclomatic complexity: 2526 Second operand has 5 states, 5 states have (on average 14.2) internal successors, (71), 5 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:07,622 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:07,622 INFO L93 Difference]: Finished difference Result 11476 states and 16496 transitions. [2023-11-29 01:07:07,622 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11476 states and 16496 transitions. [2023-11-29 01:07:07,718 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11304 [2023-11-29 01:07:07,783 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11476 states to 11476 states and 16496 transitions. [2023-11-29 01:07:07,783 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11476 [2023-11-29 01:07:07,794 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11476 [2023-11-29 01:07:07,794 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11476 states and 16496 transitions. [2023-11-29 01:07:07,813 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:07,813 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11476 states and 16496 transitions. [2023-11-29 01:07:07,828 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11476 states and 16496 transitions. [2023-11-29 01:07:07,965 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11476 to 5805. [2023-11-29 01:07:07,978 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5805 states, 5805 states have (on average 1.4337639965546942) internal successors, (8323), 5804 states have internal predecessors, (8323), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:07,997 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5805 states to 5805 states and 8323 transitions. [2023-11-29 01:07:07,997 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5805 states and 8323 transitions. [2023-11-29 01:07:07,997 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 01:07:07,998 INFO L428 stractBuchiCegarLoop]: Abstraction has 5805 states and 8323 transitions. [2023-11-29 01:07:07,998 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 01:07:07,998 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5805 states and 8323 transitions. [2023-11-29 01:07:08,023 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5694 [2023-11-29 01:07:08,024 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:08,024 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:08,025 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:08,025 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:08,026 INFO L748 eck$LassoCheckResult]: Stem: 39613#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 39614#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 39744#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39745#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39764#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 39765#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39539#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39540#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39912#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 39913#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 39857#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 39508#L586 assume !(0 == ~M_E~0); 39509#L586-2 assume !(0 == ~T1_E~0); 39564#L591-1 assume !(0 == ~T2_E~0); 39701#L596-1 assume !(0 == ~T3_E~0); 39702#L601-1 assume !(0 == ~T4_E~0); 39749#L606-1 assume !(0 == ~T5_E~0); 39750#L611-1 assume !(0 == ~E_1~0); 39874#L616-1 assume !(0 == ~E_2~0); 39875#L621-1 assume !(0 == ~E_3~0); 39426#L626-1 assume !(0 == ~E_4~0); 39427#L631-1 assume !(0 == ~E_5~0); 39606#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 39423#L279 assume !(1 == ~m_pc~0); 39425#L279-2 is_master_triggered_~__retres1~0#1 := 0; 39780#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39578#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 39579#L720 assume !(0 != activate_threads_~tmp~1#1); 39779#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 39615#L298 assume !(1 == ~t1_pc~0); 39369#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39370#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39395#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 39396#L728 assume !(0 != activate_threads_~tmp___0~0#1); 39436#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 39571#L317 assume !(1 == ~t2_pc~0); 39572#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 39803#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 39748#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 39626#L736 assume !(0 != activate_threads_~tmp___1~0#1); 39627#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39850#L336 assume !(1 == ~t3_pc~0); 39851#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 39970#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39340#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 39341#L744 assume !(0 != activate_threads_~tmp___2~0#1); 39789#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 39866#L355 assume !(1 == ~t4_pc~0); 39700#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 39527#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39528#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 39834#L752 assume !(0 != activate_threads_~tmp___3~0#1); 39450#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39451#L374 assume 1 == ~t5_pc~0; 39902#L375 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 39599#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 39584#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39585#L760 assume !(0 != activate_threads_~tmp___4~0#1); 39729#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39730#L649 assume !(1 == ~M_E~0); 39951#L649-2 assume !(1 == ~T1_E~0); 39406#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39407#L659-1 assume !(1 == ~T3_E~0); 42637#L664-1 assume !(1 == ~T4_E~0); 42636#L669-1 assume !(1 == ~T5_E~0); 39835#L674-1 assume !(1 == ~E_1~0); 39836#L679-1 assume !(1 == ~E_2~0); 39510#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 39511#L689-1 assume !(1 == ~E_4~0); 39994#L694-1 assume !(1 == ~E_5~0); 39995#L699-1 assume { :end_inline_reset_delta_events } true; 40767#L900-2 [2023-11-29 01:07:08,026 INFO L750 eck$LassoCheckResult]: Loop: 40767#L900-2 assume !false; 40768#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40621#L561-1 assume !false; 40622#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40605#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40601#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40595#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40596#L486 assume !(0 != eval_~tmp~0#1); 42600#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 43511#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 43510#L586-3 assume !(0 == ~M_E~0); 43509#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 43508#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 43507#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 43506#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 43505#L606-3 assume !(0 == ~T5_E~0); 43504#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 43503#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 43502#L621-3 assume !(0 == ~E_3~0); 43501#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 43500#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 43499#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 43498#L279-18 assume !(1 == ~m_pc~0); 43496#L279-20 is_master_triggered_~__retres1~0#1 := 0; 43495#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 43494#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 43493#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 43492#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 43491#L298-18 assume !(1 == ~t1_pc~0); 43489#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 43488#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 43487#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 43486#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 43485#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 43484#L317-18 assume !(1 == ~t2_pc~0); 43483#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 43482#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 43481#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 43480#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 43479#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 43478#L336-18 assume !(1 == ~t3_pc~0); 43477#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 43476#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 43475#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 43474#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 43473#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 43472#L355-18 assume 1 == ~t4_pc~0; 43470#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 43468#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 43466#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 43464#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 43463#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 43462#L374-18 assume !(1 == ~t5_pc~0); 43425#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 43423#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 43421#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 43370#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 40958#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40957#L649-3 assume !(1 == ~M_E~0); 40952#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 40950#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 40948#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 40946#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40944#L669-3 assume !(1 == ~T5_E~0); 40941#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 40907#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 40893#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 40880#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 40870#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40863#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40864#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40812#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40813#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 40808#L919 assume !(0 == start_simulation_~tmp~3#1); 40804#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 40805#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 40785#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 40786#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 40779#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40780#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40773#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 40774#L932 assume !(0 != start_simulation_~tmp___0~1#1); 40767#L900-2 [2023-11-29 01:07:08,026 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:08,026 INFO L85 PathProgramCache]: Analyzing trace with hash -1192920383, now seen corresponding path program 1 times [2023-11-29 01:07:08,026 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:08,027 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049914927] [2023-11-29 01:07:08,027 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:08,027 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:08,038 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:08,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:08,081 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:08,081 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049914927] [2023-11-29 01:07:08,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049914927] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:08,081 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:08,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:07:08,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [508548992] [2023-11-29 01:07:08,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:08,082 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:08,082 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:08,082 INFO L85 PathProgramCache]: Analyzing trace with hash 201894848, now seen corresponding path program 1 times [2023-11-29 01:07:08,082 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:08,082 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309523752] [2023-11-29 01:07:08,083 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:08,083 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:08,095 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:08,139 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:08,140 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:08,140 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309523752] [2023-11-29 01:07:08,140 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309523752] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:08,140 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:08,140 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:08,140 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [505783382] [2023-11-29 01:07:08,141 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:08,141 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:08,141 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:08,141 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:08,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:08,142 INFO L87 Difference]: Start difference. First operand 5805 states and 8323 transitions. cyclomatic complexity: 2526 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:08,262 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:08,262 INFO L93 Difference]: Finished difference Result 11422 states and 16248 transitions. [2023-11-29 01:07:08,262 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11422 states and 16248 transitions. [2023-11-29 01:07:08,306 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11256 [2023-11-29 01:07:08,345 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11422 states to 11422 states and 16248 transitions. [2023-11-29 01:07:08,345 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11422 [2023-11-29 01:07:08,354 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11422 [2023-11-29 01:07:08,354 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11422 states and 16248 transitions. [2023-11-29 01:07:08,365 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:08,366 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11422 states and 16248 transitions. [2023-11-29 01:07:08,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11422 states and 16248 transitions. [2023-11-29 01:07:08,473 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11422 to 11358. [2023-11-29 01:07:08,560 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11358 states, 11358 states have (on average 1.4234900510653283) internal successors, (16168), 11357 states have internal predecessors, (16168), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:08,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11358 states to 11358 states and 16168 transitions. [2023-11-29 01:07:08,584 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11358 states and 16168 transitions. [2023-11-29 01:07:08,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:08,585 INFO L428 stractBuchiCegarLoop]: Abstraction has 11358 states and 16168 transitions. [2023-11-29 01:07:08,585 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 01:07:08,585 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11358 states and 16168 transitions. [2023-11-29 01:07:08,614 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11224 [2023-11-29 01:07:08,614 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:08,614 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:08,615 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:08,615 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:08,615 INFO L748 eck$LassoCheckResult]: Stem: 56843#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 56844#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 56962#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 56963#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 56979#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 56980#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 56771#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 56772#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 57101#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 57102#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 57056#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 56743#L586 assume !(0 == ~M_E~0); 56744#L586-2 assume !(0 == ~T1_E~0); 56796#L591-1 assume !(0 == ~T2_E~0); 56921#L596-1 assume !(0 == ~T3_E~0); 56922#L601-1 assume !(0 == ~T4_E~0); 56967#L606-1 assume !(0 == ~T5_E~0); 56968#L611-1 assume !(0 == ~E_1~0); 57068#L616-1 assume !(0 == ~E_2~0); 57069#L621-1 assume !(0 == ~E_3~0); 56661#L626-1 assume !(0 == ~E_4~0); 56662#L631-1 assume !(0 == ~E_5~0); 56834#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 56658#L279 assume !(1 == ~m_pc~0); 56660#L279-2 is_master_triggered_~__retres1~0#1 := 0; 56995#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 56809#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 56810#L720 assume !(0 != activate_threads_~tmp~1#1); 56994#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 56845#L298 assume !(1 == ~t1_pc~0); 56605#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 56606#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 56631#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 56632#L728 assume !(0 != activate_threads_~tmp___0~0#1); 56670#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 56802#L317 assume !(1 == ~t2_pc~0); 56803#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 57014#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 56966#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 56855#L736 assume !(0 != activate_threads_~tmp___1~0#1); 56856#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57050#L336 assume !(1 == ~t3_pc~0); 57051#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 57141#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 56576#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 56577#L744 assume !(0 != activate_threads_~tmp___2~0#1); 57003#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57062#L355 assume !(1 == ~t4_pc~0); 56920#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 56760#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56702#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 56703#L752 assume !(0 != activate_threads_~tmp___3~0#1); 56684#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56685#L374 assume !(1 == ~t5_pc~0); 56827#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 56828#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56815#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 56816#L760 assume !(0 != activate_threads_~tmp___4~0#1); 56949#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56950#L649 assume !(1 == ~M_E~0); 57132#L649-2 assume !(1 == ~T1_E~0); 56641#L654-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 56642#L659-1 assume !(1 == ~T3_E~0); 56853#L664-1 assume !(1 == ~T4_E~0); 56633#L669-1 assume !(1 == ~T5_E~0); 56634#L674-1 assume !(1 == ~E_1~0); 57039#L679-1 assume !(1 == ~E_2~0); 56745#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 56746#L689-1 assume !(1 == ~E_4~0); 56914#L694-1 assume !(1 == ~E_5~0); 56911#L699-1 assume { :end_inline_reset_delta_events } true; 56912#L900-2 [2023-11-29 01:07:08,616 INFO L750 eck$LassoCheckResult]: Loop: 56912#L900-2 assume !false; 60540#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 60535#L561-1 assume !false; 60533#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 60527#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 60522#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 60521#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 60519#L486 assume !(0 != eval_~tmp~0#1); 60518#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 60516#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 60515#L586-3 assume !(0 == ~M_E~0); 60514#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 60513#L591-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60512#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 60510#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 60508#L606-3 assume !(0 == ~T5_E~0); 60507#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60506#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 60504#L621-3 assume !(0 == ~E_3~0); 60503#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 60502#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 60501#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60500#L279-18 assume !(1 == ~m_pc~0); 60498#L279-20 is_master_triggered_~__retres1~0#1 := 0; 60497#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60496#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 60494#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60491#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60489#L298-18 assume !(1 == ~t1_pc~0); 60486#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 60484#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60482#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 60480#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60477#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60475#L317-18 assume !(1 == ~t2_pc~0); 60473#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 60471#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60469#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 60467#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 60465#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60463#L336-18 assume !(1 == ~t3_pc~0); 60461#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 60459#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60457#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 60455#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60453#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60451#L355-18 assume 1 == ~t4_pc~0; 60449#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 60450#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60505#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60440#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60437#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60435#L374-18 assume !(1 == ~t5_pc~0); 60433#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 60430#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60428#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 60426#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 60424#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60422#L649-3 assume !(1 == ~M_E~0); 60273#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 60419#L654-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 59113#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60414#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60412#L669-3 assume !(1 == ~T5_E~0); 60410#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 60409#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 60406#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 59100#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 60405#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 60404#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 60399#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 60394#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 60390#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 60388#L919 assume !(0 == start_simulation_~tmp~3#1); 60389#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 60560#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 60553#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 60551#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 60549#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 60547#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 60545#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 60543#L932 assume !(0 != start_simulation_~tmp___0~1#1); 56912#L900-2 [2023-11-29 01:07:08,616 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:08,616 INFO L85 PathProgramCache]: Analyzing trace with hash -52568672, now seen corresponding path program 1 times [2023-11-29 01:07:08,616 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:08,616 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [543513105] [2023-11-29 01:07:08,617 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:08,617 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:08,626 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:08,660 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:08,660 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:08,660 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [543513105] [2023-11-29 01:07:08,660 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [543513105] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:08,660 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:08,661 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:07:08,661 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1599712349] [2023-11-29 01:07:08,661 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:08,661 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:08,662 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:08,662 INFO L85 PathProgramCache]: Analyzing trace with hash 201894848, now seen corresponding path program 2 times [2023-11-29 01:07:08,662 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:08,662 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1159493834] [2023-11-29 01:07:08,663 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:08,663 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:08,672 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:08,707 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:08,708 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:08,708 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1159493834] [2023-11-29 01:07:08,708 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1159493834] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:08,708 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:08,708 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:08,708 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1527740858] [2023-11-29 01:07:08,708 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:08,709 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:08,709 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:08,709 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:08,709 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:08,710 INFO L87 Difference]: Start difference. First operand 11358 states and 16168 transitions. cyclomatic complexity: 4826 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:08,797 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:08,797 INFO L93 Difference]: Finished difference Result 11352 states and 16075 transitions. [2023-11-29 01:07:08,798 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11352 states and 16075 transitions. [2023-11-29 01:07:08,840 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11224 [2023-11-29 01:07:08,873 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11352 states to 11352 states and 16075 transitions. [2023-11-29 01:07:08,873 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11352 [2023-11-29 01:07:08,881 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11352 [2023-11-29 01:07:08,882 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11352 states and 16075 transitions. [2023-11-29 01:07:08,893 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:08,893 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11352 states and 16075 transitions. [2023-11-29 01:07:08,905 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11352 states and 16075 transitions. [2023-11-29 01:07:08,986 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11352 to 5897. [2023-11-29 01:07:08,993 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5897 states, 5897 states have (on average 1.4132609801594032) internal successors, (8334), 5896 states have internal predecessors, (8334), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:09,010 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5897 states to 5897 states and 8334 transitions. [2023-11-29 01:07:09,010 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5897 states and 8334 transitions. [2023-11-29 01:07:09,010 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:09,011 INFO L428 stractBuchiCegarLoop]: Abstraction has 5897 states and 8334 transitions. [2023-11-29 01:07:09,011 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 01:07:09,011 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5897 states and 8334 transitions. [2023-11-29 01:07:09,030 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5796 [2023-11-29 01:07:09,030 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:09,030 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:09,031 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:09,031 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:09,032 INFO L748 eck$LassoCheckResult]: Stem: 79557#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 79558#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 79671#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 79672#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 79689#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 79690#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 79488#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 79489#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 79801#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 79802#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 79762#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 79455#L586 assume !(0 == ~M_E~0); 79456#L586-2 assume !(0 == ~T1_E~0); 79511#L591-1 assume !(0 == ~T2_E~0); 79633#L596-1 assume !(0 == ~T3_E~0); 79634#L601-1 assume !(0 == ~T4_E~0); 79677#L606-1 assume !(0 == ~T5_E~0); 79678#L611-1 assume !(0 == ~E_1~0); 79773#L616-1 assume !(0 == ~E_2~0); 79774#L621-1 assume !(0 == ~E_3~0); 79379#L626-1 assume !(0 == ~E_4~0); 79380#L631-1 assume !(0 == ~E_5~0); 79548#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 79374#L279 assume !(1 == ~m_pc~0); 79376#L279-2 is_master_triggered_~__retres1~0#1 := 0; 79704#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 79524#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 79525#L720 assume !(0 != activate_threads_~tmp~1#1); 79703#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 79559#L298 assume !(1 == ~t1_pc~0); 79322#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 79323#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 79348#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 79349#L728 assume !(0 != activate_threads_~tmp___0~0#1); 79388#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 79517#L317 assume !(1 == ~t2_pc~0); 79518#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 79723#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 79676#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 79568#L736 assume !(0 != activate_threads_~tmp___1~0#1); 79569#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 79758#L336 assume !(1 == ~t3_pc~0); 79759#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 79833#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 79295#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 79296#L744 assume !(0 != activate_threads_~tmp___2~0#1); 79713#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 79768#L355 assume !(1 == ~t4_pc~0); 79630#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 79766#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 79418#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 79419#L752 assume !(0 != activate_threads_~tmp___3~0#1); 79398#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 79399#L374 assume !(1 == ~t5_pc~0); 79538#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 79539#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 79530#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 79531#L760 assume !(0 != activate_threads_~tmp___4~0#1); 79660#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 79661#L649 assume !(1 == ~M_E~0); 79823#L649-2 assume !(1 == ~T1_E~0); 79360#L654-1 assume !(1 == ~T2_E~0); 79361#L659-1 assume !(1 == ~T3_E~0); 79567#L664-1 assume !(1 == ~T4_E~0); 79352#L669-1 assume !(1 == ~T5_E~0); 79353#L674-1 assume !(1 == ~E_1~0); 79748#L679-1 assume !(1 == ~E_2~0); 79461#L684-1 assume 1 == ~E_3~0;~E_3~0 := 2; 79462#L689-1 assume !(1 == ~E_4~0); 79626#L694-1 assume !(1 == ~E_5~0); 79624#L699-1 assume { :end_inline_reset_delta_events } true; 79625#L900-2 [2023-11-29 01:07:09,032 INFO L750 eck$LassoCheckResult]: Loop: 79625#L900-2 assume !false; 82556#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 82216#L561-1 assume !false; 82549#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 82362#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 82356#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 82353#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 82350#L486 assume !(0 != eval_~tmp~0#1); 82351#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 83442#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 83439#L586-3 assume !(0 == ~M_E~0); 83435#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 83432#L591-3 assume !(0 == ~T2_E~0); 83429#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 83425#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 83420#L606-3 assume !(0 == ~T5_E~0); 83414#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 83409#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 83403#L621-3 assume !(0 == ~E_3~0); 83398#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 83393#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 83389#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 82986#L279-18 assume !(1 == ~m_pc~0); 82983#L279-20 is_master_triggered_~__retres1~0#1 := 0; 82981#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 82979#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 82977#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 82975#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 82973#L298-18 assume 1 == ~t1_pc~0; 82971#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 82968#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 82966#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 82964#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 82962#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 82960#L317-18 assume !(1 == ~t2_pc~0); 82956#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 82954#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 82952#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 82950#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 82947#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 82945#L336-18 assume !(1 == ~t3_pc~0); 82943#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 82941#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 82939#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 82937#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 82935#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 82933#L355-18 assume 1 == ~t4_pc~0; 82931#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 82930#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 82928#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 82924#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 82922#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 82920#L374-18 assume !(1 == ~t5_pc~0); 82918#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 82916#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 82914#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 82912#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 82910#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 82909#L649-3 assume !(1 == ~M_E~0); 82900#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 82898#L654-3 assume !(1 == ~T2_E~0); 82896#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 82894#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 82892#L669-3 assume !(1 == ~T5_E~0); 82890#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 82888#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 82886#L684-3 assume 1 == ~E_3~0;~E_3~0 := 2; 82881#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 82879#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 82877#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 82764#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 82754#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 82746#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 82737#L919 assume !(0 == start_simulation_~tmp~3#1); 82731#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 82592#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 82585#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 82582#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 82580#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 82577#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 82575#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 82565#L932 assume !(0 != start_simulation_~tmp___0~1#1); 79625#L900-2 [2023-11-29 01:07:09,033 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:09,033 INFO L85 PathProgramCache]: Analyzing trace with hash -445595682, now seen corresponding path program 1 times [2023-11-29 01:07:09,033 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:09,033 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1482493835] [2023-11-29 01:07:09,033 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:09,034 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:09,046 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:09,090 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:09,090 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:09,090 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1482493835] [2023-11-29 01:07:09,090 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1482493835] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:09,090 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:09,091 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:09,091 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1908182512] [2023-11-29 01:07:09,091 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:09,091 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:09,092 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:09,092 INFO L85 PathProgramCache]: Analyzing trace with hash -2068561187, now seen corresponding path program 1 times [2023-11-29 01:07:09,092 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:09,092 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [145547673] [2023-11-29 01:07:09,092 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:09,093 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:09,146 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:09,190 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:09,190 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:09,190 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [145547673] [2023-11-29 01:07:09,190 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [145547673] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:09,190 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:09,190 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:09,191 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1412612947] [2023-11-29 01:07:09,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:09,191 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:09,191 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:09,192 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:07:09,192 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:07:09,192 INFO L87 Difference]: Start difference. First operand 5897 states and 8334 transitions. cyclomatic complexity: 2445 Second operand has 4 states, 4 states have (on average 17.75) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:09,311 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:09,311 INFO L93 Difference]: Finished difference Result 8753 states and 12285 transitions. [2023-11-29 01:07:09,311 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8753 states and 12285 transitions. [2023-11-29 01:07:09,353 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 8640 [2023-11-29 01:07:09,386 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8753 states to 8753 states and 12285 transitions. [2023-11-29 01:07:09,386 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8753 [2023-11-29 01:07:09,397 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8753 [2023-11-29 01:07:09,397 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8753 states and 12285 transitions. [2023-11-29 01:07:09,403 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:09,403 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8753 states and 12285 transitions. [2023-11-29 01:07:09,415 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8753 states and 12285 transitions. [2023-11-29 01:07:09,489 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8753 to 5897. [2023-11-29 01:07:09,499 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5897 states, 5897 states have (on average 1.400203493301679) internal successors, (8257), 5896 states have internal predecessors, (8257), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:09,515 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5897 states to 5897 states and 8257 transitions. [2023-11-29 01:07:09,516 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5897 states and 8257 transitions. [2023-11-29 01:07:09,524 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:07:09,525 INFO L428 stractBuchiCegarLoop]: Abstraction has 5897 states and 8257 transitions. [2023-11-29 01:07:09,526 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 01:07:09,526 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5897 states and 8257 transitions. [2023-11-29 01:07:09,545 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5796 [2023-11-29 01:07:09,545 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:09,545 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:09,547 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:09,547 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:09,547 INFO L748 eck$LassoCheckResult]: Stem: 94212#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 94213#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 94320#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 94321#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 94338#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 94339#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 94148#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 94149#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 94447#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 94448#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 94406#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 94116#L586 assume !(0 == ~M_E~0); 94117#L586-2 assume !(0 == ~T1_E~0); 94169#L591-1 assume !(0 == ~T2_E~0); 94285#L596-1 assume !(0 == ~T3_E~0); 94286#L601-1 assume !(0 == ~T4_E~0); 94326#L606-1 assume !(0 == ~T5_E~0); 94327#L611-1 assume !(0 == ~E_1~0); 94419#L616-1 assume !(0 == ~E_2~0); 94420#L621-1 assume !(0 == ~E_3~0); 94042#L626-1 assume !(0 == ~E_4~0); 94043#L631-1 assume !(0 == ~E_5~0); 94205#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 94037#L279 assume !(1 == ~m_pc~0); 94039#L279-2 is_master_triggered_~__retres1~0#1 := 0; 94351#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 94180#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 94181#L720 assume !(0 != activate_threads_~tmp~1#1); 94350#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94214#L298 assume !(1 == ~t1_pc~0); 93984#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 93985#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 94010#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 94011#L728 assume !(0 != activate_threads_~tmp___0~0#1); 94051#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 94174#L317 assume !(1 == ~t2_pc~0); 94175#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 94368#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 94325#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 94223#L736 assume !(0 != activate_threads_~tmp___1~0#1); 94224#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 94402#L336 assume !(1 == ~t3_pc~0); 94403#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 94473#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 93957#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 93958#L744 assume !(0 != activate_threads_~tmp___2~0#1); 94359#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 94412#L355 assume !(1 == ~t4_pc~0); 94282#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 94411#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 94081#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 94082#L752 assume !(0 != activate_threads_~tmp___3~0#1); 94062#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 94063#L374 assume !(1 == ~t5_pc~0); 94195#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 94196#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 94186#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 94187#L760 assume !(0 != activate_threads_~tmp___4~0#1); 94310#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 94311#L649 assume !(1 == ~M_E~0); 94467#L649-2 assume !(1 == ~T1_E~0); 94023#L654-1 assume !(1 == ~T2_E~0); 94024#L659-1 assume !(1 == ~T3_E~0); 94222#L664-1 assume !(1 == ~T4_E~0); 94015#L669-1 assume !(1 == ~T5_E~0); 94016#L674-1 assume !(1 == ~E_1~0); 94393#L679-1 assume !(1 == ~E_2~0); 94121#L684-1 assume !(1 == ~E_3~0); 94122#L689-1 assume !(1 == ~E_4~0); 94278#L694-1 assume !(1 == ~E_5~0); 94276#L699-1 assume { :end_inline_reset_delta_events } true; 94277#L900-2 [2023-11-29 01:07:09,548 INFO L750 eck$LassoCheckResult]: Loop: 94277#L900-2 assume !false; 95819#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95809#L561-1 assume !false; 95803#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 95790#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 95780#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 95775#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 95772#L486 assume !(0 != eval_~tmp~0#1); 95770#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 95763#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 95761#L586-3 assume !(0 == ~M_E~0); 95759#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 95756#L591-3 assume !(0 == ~T2_E~0); 95754#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 95752#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 95750#L606-3 assume !(0 == ~T5_E~0); 95748#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 95746#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 95744#L621-3 assume !(0 == ~E_3~0); 95742#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 95740#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 95738#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 95736#L279-18 assume !(1 == ~m_pc~0); 95733#L279-20 is_master_triggered_~__retres1~0#1 := 0; 95731#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 95729#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 95727#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 95723#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 95720#L298-18 assume 1 == ~t1_pc~0; 95717#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 95713#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 95710#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 95707#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 95704#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 95700#L317-18 assume !(1 == ~t2_pc~0); 95697#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 95694#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 95691#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 95688#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 95685#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 95682#L336-18 assume !(1 == ~t3_pc~0); 95678#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 95675#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 95672#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 95669#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 95665#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 95662#L355-18 assume 1 == ~t4_pc~0; 95657#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 95653#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95649#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 95645#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 95642#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 95638#L374-18 assume !(1 == ~t5_pc~0); 95634#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 95630#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 95626#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 95623#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 95620#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 95617#L649-3 assume !(1 == ~M_E~0); 95552#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 95612#L654-3 assume !(1 == ~T2_E~0); 95609#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 95606#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 95603#L669-3 assume !(1 == ~T5_E~0); 95600#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 95594#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 95589#L684-3 assume !(1 == ~E_3~0); 95584#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 95579#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 95575#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 95563#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 95559#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 95557#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 95554#L919 assume !(0 == start_simulation_~tmp~3#1); 95555#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 95853#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 95846#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 95844#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 95840#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 95838#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 95836#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 95835#L932 assume !(0 != start_simulation_~tmp___0~1#1); 94277#L900-2 [2023-11-29 01:07:09,548 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:09,549 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 1 times [2023-11-29 01:07:09,549 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:09,549 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1749244598] [2023-11-29 01:07:09,549 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:09,549 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:09,562 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:09,562 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:09,570 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:09,623 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:09,624 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:09,624 INFO L85 PathProgramCache]: Analyzing trace with hash 1205337755, now seen corresponding path program 1 times [2023-11-29 01:07:09,625 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:09,625 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1115536152] [2023-11-29 01:07:09,625 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:09,625 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:09,637 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:09,682 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:09,682 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:09,682 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1115536152] [2023-11-29 01:07:09,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1115536152] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:09,682 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:09,683 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:09,683 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1331573687] [2023-11-29 01:07:09,683 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:09,683 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:09,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:09,684 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:07:09,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:07:09,684 INFO L87 Difference]: Start difference. First operand 5897 states and 8257 transitions. cyclomatic complexity: 2368 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:09,819 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:09,819 INFO L93 Difference]: Finished difference Result 10509 states and 14497 transitions. [2023-11-29 01:07:09,819 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10509 states and 14497 transitions. [2023-11-29 01:07:09,862 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10384 [2023-11-29 01:07:09,897 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10509 states to 10509 states and 14497 transitions. [2023-11-29 01:07:09,898 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10509 [2023-11-29 01:07:09,905 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10509 [2023-11-29 01:07:09,905 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10509 states and 14497 transitions. [2023-11-29 01:07:09,911 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:09,911 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10509 states and 14497 transitions. [2023-11-29 01:07:09,923 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10509 states and 14497 transitions. [2023-11-29 01:07:09,996 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10509 to 5945. [2023-11-29 01:07:10,005 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5945 states, 5945 states have (on average 1.3969722455845248) internal successors, (8305), 5944 states have internal predecessors, (8305), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:10,022 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5945 states to 5945 states and 8305 transitions. [2023-11-29 01:07:10,022 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5945 states and 8305 transitions. [2023-11-29 01:07:10,051 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-29 01:07:10,051 INFO L428 stractBuchiCegarLoop]: Abstraction has 5945 states and 8305 transitions. [2023-11-29 01:07:10,051 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 01:07:10,051 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5945 states and 8305 transitions. [2023-11-29 01:07:10,065 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5844 [2023-11-29 01:07:10,066 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:10,066 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:10,067 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:10,067 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:10,067 INFO L748 eck$LassoCheckResult]: Stem: 110636#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 110637#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 110756#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 110757#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 110776#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 110777#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 110569#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 110570#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 110891#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 110892#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 110849#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 110538#L586 assume !(0 == ~M_E~0); 110539#L586-2 assume !(0 == ~T1_E~0); 110591#L591-1 assume !(0 == ~T2_E~0); 110715#L596-1 assume !(0 == ~T3_E~0); 110716#L601-1 assume !(0 == ~T4_E~0); 110764#L606-1 assume !(0 == ~T5_E~0); 110765#L611-1 assume !(0 == ~E_1~0); 110861#L616-1 assume !(0 == ~E_2~0); 110862#L621-1 assume !(0 == ~E_3~0); 110465#L626-1 assume !(0 == ~E_4~0); 110466#L631-1 assume !(0 == ~E_5~0); 110629#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 110460#L279 assume !(1 == ~m_pc~0); 110462#L279-2 is_master_triggered_~__retres1~0#1 := 0; 110794#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 110603#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 110604#L720 assume !(0 != activate_threads_~tmp~1#1); 110793#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 110638#L298 assume !(1 == ~t1_pc~0); 110407#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 110408#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 110433#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 110434#L728 assume !(0 != activate_threads_~tmp___0~0#1); 110474#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 110597#L317 assume !(1 == ~t2_pc~0); 110598#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 110813#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 110761#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 110647#L736 assume !(0 != activate_threads_~tmp___1~0#1); 110648#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 110845#L336 assume !(1 == ~t3_pc~0); 110846#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 110922#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 110380#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 110381#L744 assume !(0 != activate_threads_~tmp___2~0#1); 110802#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 110855#L355 assume !(1 == ~t4_pc~0); 110712#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 110853#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 110503#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 110504#L752 assume !(0 != activate_threads_~tmp___3~0#1); 110484#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 110485#L374 assume !(1 == ~t5_pc~0); 110618#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 110619#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 110610#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 110611#L760 assume !(0 != activate_threads_~tmp___4~0#1); 110743#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 110744#L649 assume !(1 == ~M_E~0); 110914#L649-2 assume !(1 == ~T1_E~0); 110446#L654-1 assume !(1 == ~T2_E~0); 110447#L659-1 assume !(1 == ~T3_E~0); 110646#L664-1 assume !(1 == ~T4_E~0); 110438#L669-1 assume !(1 == ~T5_E~0); 110439#L674-1 assume !(1 == ~E_1~0); 110838#L679-1 assume !(1 == ~E_2~0); 110542#L684-1 assume !(1 == ~E_3~0); 110543#L689-1 assume !(1 == ~E_4~0); 110708#L694-1 assume !(1 == ~E_5~0); 110706#L699-1 assume { :end_inline_reset_delta_events } true; 110707#L900-2 [2023-11-29 01:07:10,068 INFO L750 eck$LassoCheckResult]: Loop: 110707#L900-2 assume !false; 114840#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 114098#L561-1 assume !false; 114077#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 114073#L439 assume !(0 == ~m_st~0); 114074#L443 assume !(0 == ~t1_st~0); 114070#L447 assume !(0 == ~t2_st~0); 114071#L451 assume !(0 == ~t3_st~0); 114072#L455 assume !(0 == ~t4_st~0); 114068#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 114069#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 113636#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 113637#L486 assume !(0 != eval_~tmp~0#1); 114061#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 114060#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 114059#L586-3 assume !(0 == ~M_E~0); 114058#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 114057#L591-3 assume !(0 == ~T2_E~0); 114056#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 114055#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 114054#L606-3 assume !(0 == ~T5_E~0); 114053#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 114052#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 114051#L621-3 assume !(0 == ~E_3~0); 114050#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 114049#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 114048#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114047#L279-18 assume !(1 == ~m_pc~0); 114045#L279-20 is_master_triggered_~__retres1~0#1 := 0; 114044#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114043#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 114042#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 114041#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114040#L298-18 assume 1 == ~t1_pc~0; 114039#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 114037#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114036#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 114035#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 114034#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114033#L317-18 assume !(1 == ~t2_pc~0); 114032#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 114031#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114030#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 114029#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 114028#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114027#L336-18 assume !(1 == ~t3_pc~0); 114026#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 114025#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114024#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 114023#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 114022#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114021#L355-18 assume 1 == ~t4_pc~0; 114019#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 114017#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114015#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 114013#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 114012#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114011#L374-18 assume !(1 == ~t5_pc~0); 114010#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 114009#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114008#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 114007#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 114006#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114005#L649-3 assume !(1 == ~M_E~0); 113731#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 114004#L654-3 assume !(1 == ~T2_E~0); 114003#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 114002#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 114001#L669-3 assume !(1 == ~T5_E~0); 114000#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 113999#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 113998#L684-3 assume !(1 == ~E_3~0); 113997#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 113996#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 113995#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 113991#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 113985#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 113981#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 113977#L919 assume !(0 == start_simulation_~tmp~3#1); 113978#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 114869#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 114862#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 114860#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 114858#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 114854#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 114852#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 114849#L932 assume !(0 != start_simulation_~tmp___0~1#1); 110707#L900-2 [2023-11-29 01:07:10,068 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:10,068 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 2 times [2023-11-29 01:07:10,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:10,069 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1461805395] [2023-11-29 01:07:10,069 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:10,069 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:10,081 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:10,081 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:10,088 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:10,105 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:10,105 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:10,105 INFO L85 PathProgramCache]: Analyzing trace with hash -1684605094, now seen corresponding path program 1 times [2023-11-29 01:07:10,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:10,106 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1339013571] [2023-11-29 01:07:10,106 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:10,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:10,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:10,185 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:10,185 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:10,186 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1339013571] [2023-11-29 01:07:10,186 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1339013571] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:10,186 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:10,186 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:07:10,186 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81218283] [2023-11-29 01:07:10,186 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:10,187 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:10,187 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:10,187 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:07:10,187 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:07:10,187 INFO L87 Difference]: Start difference. First operand 5945 states and 8305 transitions. cyclomatic complexity: 2368 Second operand has 5 states, 5 states have (on average 17.4) internal successors, (87), 5 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:10,390 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:10,390 INFO L93 Difference]: Finished difference Result 11689 states and 16208 transitions. [2023-11-29 01:07:10,390 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11689 states and 16208 transitions. [2023-11-29 01:07:10,440 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 11564 [2023-11-29 01:07:10,481 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11689 states to 11689 states and 16208 transitions. [2023-11-29 01:07:10,481 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11689 [2023-11-29 01:07:10,489 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11689 [2023-11-29 01:07:10,489 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11689 states and 16208 transitions. [2023-11-29 01:07:10,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:10,497 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11689 states and 16208 transitions. [2023-11-29 01:07:10,509 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11689 states and 16208 transitions. [2023-11-29 01:07:10,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11689 to 6089. [2023-11-29 01:07:10,653 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6089 states, 6089 states have (on average 1.3808507144030218) internal successors, (8408), 6088 states have internal predecessors, (8408), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:10,667 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6089 states to 6089 states and 8408 transitions. [2023-11-29 01:07:10,667 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6089 states and 8408 transitions. [2023-11-29 01:07:10,668 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 01:07:10,668 INFO L428 stractBuchiCegarLoop]: Abstraction has 6089 states and 8408 transitions. [2023-11-29 01:07:10,668 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 01:07:10,669 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6089 states and 8408 transitions. [2023-11-29 01:07:10,695 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5988 [2023-11-29 01:07:10,695 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:10,695 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:10,696 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:10,697 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:10,697 INFO L748 eck$LassoCheckResult]: Stem: 128285#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 128286#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 128402#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 128403#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 128422#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 128423#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 128220#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 128221#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 128546#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 128547#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 128500#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 128189#L586 assume !(0 == ~M_E~0); 128190#L586-2 assume !(0 == ~T1_E~0); 128242#L591-1 assume !(0 == ~T2_E~0); 128364#L596-1 assume !(0 == ~T3_E~0); 128365#L601-1 assume !(0 == ~T4_E~0); 128408#L606-1 assume !(0 == ~T5_E~0); 128409#L611-1 assume !(0 == ~E_1~0); 128514#L616-1 assume !(0 == ~E_2~0); 128515#L621-1 assume !(0 == ~E_3~0); 128110#L626-1 assume !(0 == ~E_4~0); 128111#L631-1 assume !(0 == ~E_5~0); 128278#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 128105#L279 assume !(1 == ~m_pc~0); 128107#L279-2 is_master_triggered_~__retres1~0#1 := 0; 128439#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 128254#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 128255#L720 assume !(0 != activate_threads_~tmp~1#1); 128438#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 128287#L298 assume !(1 == ~t1_pc~0); 128053#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 128054#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 128079#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 128080#L728 assume !(0 != activate_threads_~tmp___0~0#1); 128120#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 128248#L317 assume !(1 == ~t2_pc~0); 128249#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 128462#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 128407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 128296#L736 assume !(0 != activate_threads_~tmp___1~0#1); 128297#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 128496#L336 assume !(1 == ~t3_pc~0); 128497#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 128582#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 128026#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 128027#L744 assume !(0 != activate_threads_~tmp___2~0#1); 128448#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 128507#L355 assume !(1 == ~t4_pc~0); 128361#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 128504#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 128152#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 128153#L752 assume !(0 != activate_threads_~tmp___3~0#1); 128133#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 128134#L374 assume !(1 == ~t5_pc~0); 128268#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 128269#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 128260#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 128261#L760 assume !(0 != activate_threads_~tmp___4~0#1); 128391#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 128392#L649 assume !(1 == ~M_E~0); 128572#L649-2 assume !(1 == ~T1_E~0); 128091#L654-1 assume !(1 == ~T2_E~0); 128092#L659-1 assume !(1 == ~T3_E~0); 128295#L664-1 assume !(1 == ~T4_E~0); 128083#L669-1 assume !(1 == ~T5_E~0); 128084#L674-1 assume !(1 == ~E_1~0); 128488#L679-1 assume !(1 == ~E_2~0); 128193#L684-1 assume !(1 == ~E_3~0); 128194#L689-1 assume !(1 == ~E_4~0); 128357#L694-1 assume !(1 == ~E_5~0); 128355#L699-1 assume { :end_inline_reset_delta_events } true; 128356#L900-2 [2023-11-29 01:07:10,697 INFO L750 eck$LassoCheckResult]: Loop: 128356#L900-2 assume !false; 132004#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 131999#L561-1 assume !false; 131998#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 131995#L439 assume !(0 == ~m_st~0); 131996#L443 assume !(0 == ~t1_st~0); 131992#L447 assume !(0 == ~t2_st~0); 131993#L451 assume !(0 == ~t3_st~0); 131994#L455 assume !(0 == ~t4_st~0); 131990#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 131991#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 131460#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 131461#L486 assume !(0 != eval_~tmp~0#1); 132615#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 132610#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 132606#L586-3 assume !(0 == ~M_E~0); 132602#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 132598#L591-3 assume !(0 == ~T2_E~0); 132594#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 132590#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 132586#L606-3 assume !(0 == ~T5_E~0); 132582#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 132580#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 132577#L621-3 assume !(0 == ~E_3~0); 132575#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 132573#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 132572#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 132571#L279-18 assume !(1 == ~m_pc~0); 132569#L279-20 is_master_triggered_~__retres1~0#1 := 0; 132568#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 132567#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 132566#L720-18 assume !(0 != activate_threads_~tmp~1#1); 132565#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 132564#L298-18 assume !(1 == ~t1_pc~0); 132562#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 132561#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 132560#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 132559#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 132558#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 132557#L317-18 assume !(1 == ~t2_pc~0); 132556#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 132555#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 132554#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 132553#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 132552#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 132551#L336-18 assume !(1 == ~t3_pc~0); 132550#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 132549#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 132548#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 132547#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 132546#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 132545#L355-18 assume !(1 == ~t4_pc~0); 132544#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 132542#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 132540#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 132538#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 132536#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 132535#L374-18 assume !(1 == ~t5_pc~0); 132534#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 132533#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 132532#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 132531#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 132530#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 132529#L649-3 assume !(1 == ~M_E~0); 132525#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 132523#L654-3 assume !(1 == ~T2_E~0); 132521#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 132519#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 132500#L669-3 assume !(1 == ~T5_E~0); 132495#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 132489#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 132483#L684-3 assume !(1 == ~E_3~0); 132479#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 132477#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 132461#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 132394#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 132385#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 132306#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 132304#L919 assume !(0 == start_simulation_~tmp~3#1); 132284#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 132027#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 132020#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 132018#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 132016#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 132014#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 132012#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 132010#L932 assume !(0 != start_simulation_~tmp___0~1#1); 128356#L900-2 [2023-11-29 01:07:10,698 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:10,698 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 3 times [2023-11-29 01:07:10,698 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:10,698 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1887184052] [2023-11-29 01:07:10,698 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:10,699 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:10,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:10,713 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:10,723 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:10,739 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:10,739 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:10,740 INFO L85 PathProgramCache]: Analyzing trace with hash 1263781204, now seen corresponding path program 1 times [2023-11-29 01:07:10,740 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:10,740 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [360525030] [2023-11-29 01:07:10,740 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:10,740 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:10,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:10,778 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:10,779 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:10,779 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [360525030] [2023-11-29 01:07:10,779 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [360525030] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:10,779 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:10,779 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:10,779 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [948742565] [2023-11-29 01:07:10,779 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:10,780 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:10,780 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:10,780 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:10,780 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:10,781 INFO L87 Difference]: Start difference. First operand 6089 states and 8408 transitions. cyclomatic complexity: 2327 Second operand has 3 states, 3 states have (on average 29.0) internal successors, (87), 3 states have internal predecessors, (87), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:10,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:10,855 INFO L93 Difference]: Finished difference Result 10621 states and 14480 transitions. [2023-11-29 01:07:10,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10621 states and 14480 transitions. [2023-11-29 01:07:10,897 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10496 [2023-11-29 01:07:10,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10621 states to 10621 states and 14480 transitions. [2023-11-29 01:07:10,930 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10621 [2023-11-29 01:07:10,936 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10621 [2023-11-29 01:07:10,936 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10621 states and 14480 transitions. [2023-11-29 01:07:10,943 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:10,943 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10621 states and 14480 transitions. [2023-11-29 01:07:10,949 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10621 states and 14480 transitions. [2023-11-29 01:07:11,041 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10621 to 10297. [2023-11-29 01:07:11,051 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10297 states, 10297 states have (on average 1.365834709138584) internal successors, (14064), 10296 states have internal predecessors, (14064), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:11,076 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10297 states to 10297 states and 14064 transitions. [2023-11-29 01:07:11,077 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10297 states and 14064 transitions. [2023-11-29 01:07:11,077 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:11,078 INFO L428 stractBuchiCegarLoop]: Abstraction has 10297 states and 14064 transitions. [2023-11-29 01:07:11,078 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 01:07:11,078 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10297 states and 14064 transitions. [2023-11-29 01:07:11,109 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 10172 [2023-11-29 01:07:11,109 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:11,109 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:11,111 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:11,111 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:11,112 INFO L748 eck$LassoCheckResult]: Stem: 145001#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 145002#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 145116#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 145117#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 145138#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 145139#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 144935#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 144936#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 145259#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 145260#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 145209#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 144903#L586 assume !(0 == ~M_E~0); 144904#L586-2 assume !(0 == ~T1_E~0); 144956#L591-1 assume !(0 == ~T2_E~0); 145075#L596-1 assume !(0 == ~T3_E~0); 145076#L601-1 assume !(0 == ~T4_E~0); 145123#L606-1 assume !(0 == ~T5_E~0); 145124#L611-1 assume !(0 == ~E_1~0); 145222#L616-1 assume !(0 == ~E_2~0); 145223#L621-1 assume !(0 == ~E_3~0); 144827#L626-1 assume !(0 == ~E_4~0); 144828#L631-1 assume !(0 == ~E_5~0); 144994#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144822#L279 assume !(1 == ~m_pc~0); 144824#L279-2 is_master_triggered_~__retres1~0#1 := 0; 145157#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 144968#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 144969#L720 assume !(0 != activate_threads_~tmp~1#1); 145156#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 145003#L298 assume !(1 == ~t1_pc~0); 144768#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 144769#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 144794#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 144795#L728 assume !(0 != activate_threads_~tmp___0~0#1); 144837#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 144962#L317 assume !(1 == ~t2_pc~0); 144963#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 145176#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 145122#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 145012#L736 assume !(0 != activate_threads_~tmp___1~0#1); 145013#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 145205#L336 assume !(1 == ~t3_pc~0); 145206#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 145294#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 144741#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144742#L744 assume !(0 != activate_threads_~tmp___2~0#1); 145165#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 145216#L355 assume !(1 == ~t4_pc~0); 145072#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 145214#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 144867#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 144868#L752 assume !(0 != activate_threads_~tmp___3~0#1); 144848#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 144849#L374 assume !(1 == ~t5_pc~0); 144984#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 144985#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 144974#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 144975#L760 assume !(0 != activate_threads_~tmp___4~0#1); 145104#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 145105#L649 assume !(1 == ~M_E~0); 145287#L649-2 assume !(1 == ~T1_E~0); 144806#L654-1 assume !(1 == ~T2_E~0); 144807#L659-1 assume !(1 == ~T3_E~0); 145011#L664-1 assume !(1 == ~T4_E~0); 144798#L669-1 assume !(1 == ~T5_E~0); 144799#L674-1 assume !(1 == ~E_1~0); 145197#L679-1 assume !(1 == ~E_2~0); 144907#L684-1 assume !(1 == ~E_3~0); 144908#L689-1 assume !(1 == ~E_4~0); 145068#L694-1 assume !(1 == ~E_5~0); 145066#L699-1 assume { :end_inline_reset_delta_events } true; 145067#L900-2 [2023-11-29 01:07:11,113 INFO L750 eck$LassoCheckResult]: Loop: 145067#L900-2 assume !false; 150565#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 150444#L561-1 assume !false; 150562#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 150560#L439 assume !(0 == ~m_st~0); 149054#L443 assume !(0 == ~t1_st~0); 149051#L447 assume !(0 == ~t2_st~0); 148960#L451 assume !(0 == ~t3_st~0); 148957#L455 assume !(0 == ~t4_st~0); 148955#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 148954#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 148952#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 148950#L486 assume !(0 != eval_~tmp~0#1); 148949#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 148947#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 148945#L586-3 assume !(0 == ~M_E~0); 148943#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 148940#L591-3 assume !(0 == ~T2_E~0); 148938#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 148936#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 148935#L606-3 assume !(0 == ~T5_E~0); 148934#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 148933#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 148932#L621-3 assume !(0 == ~E_3~0); 148930#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 148928#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 148924#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 148922#L279-18 assume !(1 == ~m_pc~0); 148919#L279-20 is_master_triggered_~__retres1~0#1 := 0; 148917#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148913#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 148911#L720-18 assume !(0 != activate_threads_~tmp~1#1); 148909#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148908#L298-18 assume !(1 == ~t1_pc~0); 148906#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 148905#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148903#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 148902#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 148901#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 148900#L317-18 assume !(1 == ~t2_pc~0); 148898#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 148897#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 148896#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 148895#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 148893#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148891#L336-18 assume !(1 == ~t3_pc~0); 148889#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 148887#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148885#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 148883#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 148881#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 148879#L355-18 assume !(1 == ~t4_pc~0); 148875#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 148873#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 148871#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 148869#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 148866#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 148862#L374-18 assume !(1 == ~t5_pc~0); 148860#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 148858#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 148856#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 148853#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 148851#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 148849#L649-3 assume !(1 == ~M_E~0); 148727#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 148846#L654-3 assume !(1 == ~T2_E~0); 148844#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 148842#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 148840#L669-3 assume !(1 == ~T5_E~0); 148837#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 148835#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 148833#L684-3 assume !(1 == ~E_3~0); 148831#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 148791#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 148785#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 148781#L439-1 assume !(0 == ~m_st~0); 148255#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 148682#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 148675#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 148271#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 148269#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 148267#L279-21 assume 1 == ~m_pc~0; 148264#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 148262#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 148260#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 148233#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 148232#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 148231#L298-21 assume !(1 == ~t1_pc~0); 148230#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 148228#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 148226#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 148224#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 148220#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 148218#L317-21 assume !(1 == ~t2_pc~0); 148216#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 148214#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 148210#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 148208#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 148206#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148203#L336-21 assume !(1 == ~t3_pc~0); 148198#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 148196#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 148194#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 148134#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 148126#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 148118#L355-21 assume 1 == ~t4_pc~0; 148116#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 148117#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 148484#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 148081#L752-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 148079#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 148077#L374-21 assume !(1 == ~t5_pc~0); 148075#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 148073#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 148071#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 148069#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 148067#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 148064#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 148065#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 150600#L798-1 assume !(1 == ~T2_E~0); 150598#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 150596#L808-1 assume !(1 == ~T4_E~0); 150594#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 150591#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 150589#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 150587#L828-1 assume !(1 == ~E_3~0); 150586#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 150585#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 150584#L843-1 assume { :end_inline_reset_time_events } true; 148250#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 150582#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 150579#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 150577#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 150575#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 150573#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 150571#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 150569#L932 assume !(0 != start_simulation_~tmp___0~1#1); 145067#L900-2 [2023-11-29 01:07:11,114 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:11,114 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 4 times [2023-11-29 01:07:11,114 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:11,114 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [542973221] [2023-11-29 01:07:11,115 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:11,115 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:11,189 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:11,189 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:11,197 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:11,210 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:11,211 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:11,211 INFO L85 PathProgramCache]: Analyzing trace with hash -300143274, now seen corresponding path program 1 times [2023-11-29 01:07:11,211 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:11,211 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [36152610] [2023-11-29 01:07:11,212 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:11,212 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:11,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:11,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:11,267 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:11,267 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [36152610] [2023-11-29 01:07:11,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [36152610] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:11,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:11,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:11,268 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [296202600] [2023-11-29 01:07:11,268 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:11,269 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:11,269 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:11,269 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:11,269 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:11,270 INFO L87 Difference]: Start difference. First operand 10297 states and 14064 transitions. cyclomatic complexity: 3775 Second operand has 3 states, 3 states have (on average 45.666666666666664) internal successors, (137), 3 states have internal predecessors, (137), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:11,370 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:11,371 INFO L93 Difference]: Finished difference Result 18768 states and 25478 transitions. [2023-11-29 01:07:11,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18768 states and 25478 transitions. [2023-11-29 01:07:11,453 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18596 [2023-11-29 01:07:11,521 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18768 states to 18768 states and 25478 transitions. [2023-11-29 01:07:11,521 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18768 [2023-11-29 01:07:11,534 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18768 [2023-11-29 01:07:11,535 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18768 states and 25478 transitions. [2023-11-29 01:07:11,548 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:11,548 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18768 states and 25478 transitions. [2023-11-29 01:07:11,562 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18768 states and 25478 transitions. [2023-11-29 01:07:11,739 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18768 to 18736. [2023-11-29 01:07:11,760 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18736 states, 18736 states have (on average 1.358134073441503) internal successors, (25446), 18735 states have internal predecessors, (25446), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:11,899 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18736 states to 18736 states and 25446 transitions. [2023-11-29 01:07:11,899 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18736 states and 25446 transitions. [2023-11-29 01:07:11,899 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:11,900 INFO L428 stractBuchiCegarLoop]: Abstraction has 18736 states and 25446 transitions. [2023-11-29 01:07:11,900 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 01:07:11,900 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18736 states and 25446 transitions. [2023-11-29 01:07:11,937 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 18564 [2023-11-29 01:07:11,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:11,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:11,940 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:11,940 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:11,940 INFO L748 eck$LassoCheckResult]: Stem: 174068#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 174069#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 174187#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 174188#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 174207#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 174208#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 174005#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 174006#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 174339#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 174340#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 174293#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 173975#L586 assume !(0 == ~M_E~0); 173976#L586-2 assume !(0 == ~T1_E~0); 174025#L591-1 assume !(0 == ~T2_E~0); 174148#L596-1 assume !(0 == ~T3_E~0); 174149#L601-1 assume !(0 == ~T4_E~0); 174193#L606-1 assume !(0 == ~T5_E~0); 174194#L611-1 assume !(0 == ~E_1~0); 174301#L616-1 assume !(0 == ~E_2~0); 174302#L621-1 assume !(0 == ~E_3~0); 173893#L626-1 assume !(0 == ~E_4~0); 173894#L631-1 assume !(0 == ~E_5~0); 174061#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 173891#L279 assume !(1 == ~m_pc~0); 173892#L279-2 is_master_triggered_~__retres1~0#1 := 0; 174225#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174036#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 174037#L720 assume !(0 != activate_threads_~tmp~1#1); 174224#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174070#L298 assume !(1 == ~t1_pc~0); 173840#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 173841#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 173865#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 173866#L728 assume !(0 != activate_threads_~tmp___0~0#1); 173903#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174030#L317 assume !(1 == ~t2_pc~0); 174031#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 174247#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174191#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 174081#L736 assume !(0 != activate_threads_~tmp___1~0#1); 174082#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174286#L336 assume !(1 == ~t3_pc~0); 174287#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 174375#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 173812#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 173813#L744 assume !(0 != activate_threads_~tmp___2~0#1); 174234#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 174297#L355 assume !(1 == ~t4_pc~0); 174147#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 174294#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 173933#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 173934#L752 assume !(0 != activate_threads_~tmp___3~0#1); 173916#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 173917#L374 assume !(1 == ~t5_pc~0); 174054#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 174055#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 174043#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 174044#L760 assume !(0 != activate_threads_~tmp___4~0#1); 174174#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 174175#L649 assume !(1 == ~M_E~0); 174365#L649-2 assume !(1 == ~T1_E~0); 173875#L654-1 assume !(1 == ~T2_E~0); 173876#L659-1 assume !(1 == ~T3_E~0); 174078#L664-1 assume !(1 == ~T4_E~0); 173867#L669-1 assume !(1 == ~T5_E~0); 173868#L674-1 assume !(1 == ~E_1~0); 174276#L679-1 assume !(1 == ~E_2~0); 173977#L684-1 assume !(1 == ~E_3~0); 173978#L689-1 assume !(1 == ~E_4~0); 174142#L694-1 assume !(1 == ~E_5~0); 174139#L699-1 assume { :end_inline_reset_delta_events } true; 174140#L900-2 [2023-11-29 01:07:11,941 INFO L750 eck$LassoCheckResult]: Loop: 174140#L900-2 assume !false; 174826#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 174611#L561-1 assume !false; 174612#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 174788#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 174775#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 174776#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 174768#L486 assume 0 != eval_~tmp~0#1; 174565#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 174566#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 174548#L65 assume 0 == ~m_pc~0; 174549#L92 assume !false; 174123#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 174124#L279-3 assume !(1 == ~m_pc~0); 173958#L279-5 is_master_triggered_~__retres1~0#1 := 0; 173959#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 174749#is_master_triggered_returnLabel#2 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 174745#L720-3 assume !(0 != activate_threads_~tmp~1#1); 174746#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 174740#L298-3 assume !(1 == ~t1_pc~0); 174742#L298-5 is_transmit1_triggered_~__retres1~1#1 := 0; 174735#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 174736#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 174386#L728-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 174387#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 174397#L317-3 assume !(1 == ~t2_pc~0); 174398#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 174643#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 174644#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 174641#L736-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 174167#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 174168#L336-3 assume !(1 == ~t3_pc~0); 174209#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 174633#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 174634#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 174606#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 174598#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 174599#L355-3 assume !(1 == ~t4_pc~0); 173850#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 181244#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 181243#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 181242#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 174034#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 174035#L374-3 assume !(1 == ~t5_pc~0); 181241#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 181239#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 181237#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 181235#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 181233#L760-5 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 181125#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 179601#$Ultimate##223 assume !false; 176919#L85 ~m_pc~0 := 1;~m_st~0 := 2; 176912#master_returnLabel#1 assume { :end_inline_master } true; 176906#L494-2 havoc eval_~tmp_ndt_1~0#1; 176859#L491-1 assume !(0 == ~t1_st~0); 176895#L505-1 assume !(0 == ~t2_st~0); 176809#L519-1 assume !(0 == ~t3_st~0); 176797#L533-1 assume !(0 == ~t4_st~0); 176786#L547-1 assume !(0 == ~t5_st~0); 176778#L561-1 assume !false; 176775#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 176772#L439 assume !(0 == ~m_st~0); 176768#L443 assume !(0 == ~t1_st~0); 176766#L447 assume !(0 == ~t2_st~0); 176763#L451 assume !(0 == ~t3_st~0); 176761#L455 assume !(0 == ~t4_st~0); 176758#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 176756#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 176754#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 176751#L486 assume !(0 != eval_~tmp~0#1); 176749#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176746#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176743#L586-3 assume !(0 == ~M_E~0); 176740#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 176737#L591-3 assume !(0 == ~T2_E~0); 176735#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176733#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 176731#L606-3 assume !(0 == ~T5_E~0); 176729#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 176727#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 176725#L621-3 assume !(0 == ~E_3~0); 176723#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 176720#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 176718#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176716#L279-18 assume 1 == ~m_pc~0; 176714#L280-6 assume !(1 == ~M_E~0); 176713#L279-20 is_master_triggered_~__retres1~0#1 := 0; 176712#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176710#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 176708#L720-18 assume !(0 != activate_threads_~tmp~1#1); 176706#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176705#L298-18 assume !(1 == ~t1_pc~0); 176702#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 176699#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176697#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 176695#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 176693#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176691#L317-18 assume !(1 == ~t2_pc~0); 176689#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 176687#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176685#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 176683#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 176681#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176679#L336-18 assume !(1 == ~t3_pc~0); 176677#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 176675#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 176673#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 176671#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 176669#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 176667#L355-18 assume 1 == ~t4_pc~0; 176664#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 176660#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 176656#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 176652#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 176649#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 176647#L374-18 assume !(1 == ~t5_pc~0); 176645#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 176643#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 176641#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 176639#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 176637#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 176635#L649-3 assume !(1 == ~M_E~0); 176632#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 176630#L654-3 assume !(1 == ~T2_E~0); 176627#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 176624#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 176621#L669-3 assume !(1 == ~T5_E~0); 176619#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 176616#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 176612#L684-3 assume !(1 == ~E_3~0); 176609#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 176606#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 176603#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 176600#L439-1 assume !(0 == ~m_st~0); 176425#L443-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 176523#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 176518#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 176408#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 176405#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176398#L279-21 assume 1 == ~m_pc~0; 176392#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 176387#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176381#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 176375#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 176372#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176370#L298-21 assume 1 == ~t1_pc~0; 176366#L299-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 176363#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176360#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 176355#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 176350#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176346#L317-21 assume !(1 == ~t2_pc~0); 176342#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 176339#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176335#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 176332#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 176326#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176320#L336-21 assume !(1 == ~t3_pc~0); 176315#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 176310#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 176303#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 176299#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 176295#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 176290#L355-21 assume 1 == ~t4_pc~0; 176286#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 176282#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 176278#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 176274#L752-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 176271#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 176268#L374-21 assume !(1 == ~t5_pc~0); 176265#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 176261#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 176258#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 176255#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 176252#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 176248#L793 assume !(1 == ~M_E~0); 176245#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 176242#L798-1 assume !(1 == ~T2_E~0); 176239#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 176236#L808-1 assume !(1 == ~T4_E~0); 176233#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 176229#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 176225#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 176220#L828-1 assume !(1 == ~E_3~0); 176216#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 176213#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 176209#L843-1 assume { :end_inline_reset_time_events } true; 176207#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 176204#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 176202#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 176200#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 176198#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 176194#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 176192#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 176190#L932 assume !(0 != start_simulation_~tmp___0~1#1); 176185#L900-2 assume !false; 176180#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 176174#L561-1 assume !false; 176171#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 176168#L439 assume !(0 == ~m_st~0); 176169#L443 assume !(0 == ~t1_st~0); 176480#L447 assume !(0 == ~t2_st~0); 176477#L451 assume !(0 == ~t3_st~0); 176475#L455 assume !(0 == ~t4_st~0); 176472#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 176470#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 176468#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 176466#L486 assume !(0 != eval_~tmp~0#1); 176464#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 176462#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 176460#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 176458#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 176455#L591-3 assume !(0 == ~T2_E~0); 176452#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 176449#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 176446#L606-3 assume !(0 == ~T5_E~0); 176443#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 176440#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 176437#L621-3 assume !(0 == ~E_3~0); 176434#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 176430#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 176426#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176420#L279-18 assume 1 == ~m_pc~0; 176415#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 176412#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 176406#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 176402#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 176396#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 176390#L298-18 assume !(1 == ~t1_pc~0); 176384#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 176379#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 176373#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 176371#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 176368#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 176364#L317-18 assume !(1 == ~t2_pc~0); 176361#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 176356#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 176351#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 176347#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 176343#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 176340#L336-18 assume !(1 == ~t3_pc~0); 176336#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 176333#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 176327#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 176321#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 176316#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 176311#L355-18 assume 1 == ~t4_pc~0; 176304#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 176300#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 176296#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 176291#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 176288#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 176284#L374-18 assume !(1 == ~t5_pc~0); 176280#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 176276#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 176272#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 176269#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 176266#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 176262#L649-3 assume !(1 == ~M_E~0); 176259#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 176256#L654-3 assume !(1 == ~T2_E~0); 176253#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 176250#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 176246#L669-3 assume !(1 == ~T5_E~0); 176243#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 176240#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 176237#L684-3 assume !(1 == ~E_3~0); 176234#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 176230#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 176226#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 176221#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 176217#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 176214#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 176210#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 176211#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 176400#L279-21 assume !(1 == ~m_pc~0); 176401#L279-23 is_master_triggered_~__retres1~0#1 := 0; 179912#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 179910#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 179908#L720-21 assume !(0 != activate_threads_~tmp~1#1); 179906#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 179904#L298-21 assume !(1 == ~t1_pc~0); 179902#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 179899#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 179897#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 179895#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 179893#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 179891#L317-21 assume !(1 == ~t2_pc~0); 179889#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 179887#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 179885#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 179883#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 179840#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 179837#L336-21 assume !(1 == ~t3_pc~0); 179835#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 179833#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 179831#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 179829#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 179827#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 179825#L355-21 assume 1 == ~t4_pc~0; 179823#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 179824#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 179843#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 179812#L752-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 179811#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 179808#L374-21 assume !(1 == ~t5_pc~0); 179807#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 179806#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 179803#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 179802#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 179801#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 179798#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 179797#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 179795#L798-1 assume !(1 == ~T2_E~0); 179793#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 179791#L808-1 assume !(1 == ~T4_E~0); 179789#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 179787#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 179784#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 179782#L828-1 assume !(1 == ~E_3~0); 179780#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 179778#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 179776#L843-1 assume { :end_inline_reset_time_events } true; 179774#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 179771#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 179769#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 179767#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 179765#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 179763#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 179760#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 179758#L932 assume !(0 != start_simulation_~tmp___0~1#1); 174140#L900-2 [2023-11-29 01:07:11,942 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:11,942 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 5 times [2023-11-29 01:07:11,943 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:11,943 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1655900838] [2023-11-29 01:07:11,943 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:11,943 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:11,952 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:11,952 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:11,957 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:11,966 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:11,966 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:11,966 INFO L85 PathProgramCache]: Analyzing trace with hash 1961595101, now seen corresponding path program 1 times [2023-11-29 01:07:11,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:11,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [836760739] [2023-11-29 01:07:11,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:11,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:11,984 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:12,036 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2023-11-29 01:07:12,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:12,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [836760739] [2023-11-29 01:07:12,036 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [836760739] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:12,036 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:12,036 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:12,036 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1980356587] [2023-11-29 01:07:12,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:12,037 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:12,037 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:12,038 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:12,038 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:12,038 INFO L87 Difference]: Start difference. First operand 18736 states and 25446 transitions. cyclomatic complexity: 6726 Second operand has 3 states, 3 states have (on average 69.0) internal successors, (207), 3 states have internal predecessors, (207), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:12,146 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:12,146 INFO L93 Difference]: Finished difference Result 34890 states and 46861 transitions. [2023-11-29 01:07:12,146 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 34890 states and 46861 transitions. [2023-11-29 01:07:12,342 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 34552 [2023-11-29 01:07:12,436 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 34890 states to 34890 states and 46861 transitions. [2023-11-29 01:07:12,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 34890 [2023-11-29 01:07:12,453 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 34890 [2023-11-29 01:07:12,453 INFO L73 IsDeterministic]: Start isDeterministic. Operand 34890 states and 46861 transitions. [2023-11-29 01:07:12,472 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:12,472 INFO L218 hiAutomatonCegarLoop]: Abstraction has 34890 states and 46861 transitions. [2023-11-29 01:07:12,491 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 34890 states and 46861 transitions. [2023-11-29 01:07:12,815 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 34890 to 32746. [2023-11-29 01:07:12,842 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32746 states, 32746 states have (on average 1.3489586514383436) internal successors, (44173), 32745 states have internal predecessors, (44173), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:12,910 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32746 states to 32746 states and 44173 transitions. [2023-11-29 01:07:12,910 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32746 states and 44173 transitions. [2023-11-29 01:07:12,911 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:12,912 INFO L428 stractBuchiCegarLoop]: Abstraction has 32746 states and 44173 transitions. [2023-11-29 01:07:12,912 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 01:07:12,912 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32746 states and 44173 transitions. [2023-11-29 01:07:13,013 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 32408 [2023-11-29 01:07:13,013 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:13,013 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:13,018 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:13,018 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:13,019 INFO L748 eck$LassoCheckResult]: Stem: 227706#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 227707#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 227828#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 227829#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 227846#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 227847#L401-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 227639#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 227640#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 227966#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 227967#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 227918#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 227605#L586 assume !(0 == ~M_E~0); 227606#L586-2 assume !(0 == ~T1_E~0); 227660#L591-1 assume !(0 == ~T2_E~0); 227784#L596-1 assume !(0 == ~T3_E~0); 227785#L601-1 assume !(0 == ~T4_E~0); 227833#L606-1 assume !(0 == ~T5_E~0); 227834#L611-1 assume !(0 == ~E_1~0); 227929#L616-1 assume !(0 == ~E_2~0); 227930#L621-1 assume !(0 == ~E_3~0); 227524#L626-1 assume !(0 == ~E_4~0); 227525#L631-1 assume !(0 == ~E_5~0); 227699#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 227522#L279 assume !(1 == ~m_pc~0); 227523#L279-2 is_master_triggered_~__retres1~0#1 := 0; 227861#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 227672#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 227673#L720 assume !(0 != activate_threads_~tmp~1#1); 227860#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 227708#L298 assume !(1 == ~t1_pc~0); 227472#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 227473#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 227496#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 227497#L728 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 227535#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 234775#L317 assume !(1 == ~t2_pc~0); 234774#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 234773#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 234772#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 234771#L736 assume !(0 != activate_threads_~tmp___1~0#1); 234770#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 234769#L336 assume !(1 == ~t3_pc~0); 234768#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 234767#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 234766#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 234765#L744 assume !(0 != activate_threads_~tmp___2~0#1); 234764#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 234763#L355 assume !(1 == ~t4_pc~0); 234762#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 234805#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 234804#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 234757#L752 assume !(0 != activate_threads_~tmp___3~0#1); 234756#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 234755#L374 assume !(1 == ~t5_pc~0); 234754#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 234753#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 234752#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 234751#L760 assume !(0 != activate_threads_~tmp___4~0#1); 234750#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 234749#L649 assume !(1 == ~M_E~0); 234748#L649-2 assume !(1 == ~T1_E~0); 234747#L654-1 assume !(1 == ~T2_E~0); 234746#L659-1 assume !(1 == ~T3_E~0); 234743#L664-1 assume !(1 == ~T4_E~0); 227498#L669-1 assume !(1 == ~T5_E~0); 227499#L674-1 assume !(1 == ~E_1~0); 227902#L679-1 assume !(1 == ~E_2~0); 227607#L684-1 assume !(1 == ~E_3~0); 227608#L689-1 assume !(1 == ~E_4~0); 234405#L694-1 assume !(1 == ~E_5~0); 227774#L699-1 assume { :end_inline_reset_delta_events } true; 227775#L900-2 [2023-11-29 01:07:13,019 INFO L750 eck$LassoCheckResult]: Loop: 227775#L900-2 assume !false; 234467#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 234458#L561-1 assume !false; 234453#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 234450#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 234448#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 234445#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 234443#L486 assume 0 != eval_~tmp~0#1; 234440#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 234437#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 234438#L65 assume 0 == ~m_pc~0; 237114#L92 assume !false; 237534#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 237484#L279-3 assume !(1 == ~m_pc~0); 237480#L279-5 is_master_triggered_~__retres1~0#1 := 0; 237475#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 237469#is_master_triggered_returnLabel#2 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 237463#L720-3 assume !(0 != activate_threads_~tmp~1#1); 237458#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 237453#L298-3 assume 1 == ~t1_pc~0; 237447#L299-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 237442#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 237436#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 237431#L728-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 235020#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 237424#L317-3 assume !(1 == ~t2_pc~0); 237419#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 237414#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 237409#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 237405#L736-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 237401#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 237397#L336-3 assume !(1 == ~t3_pc~0); 237392#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 237387#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 237380#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 237374#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 237363#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 237355#L355-3 assume !(1 == ~t4_pc~0); 237347#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 237338#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 237326#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 237315#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 237308#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 237303#L374-3 assume !(1 == ~t5_pc~0); 237297#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 237288#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 237281#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 237274#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 237268#L760-5 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 237112#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 237110#$Ultimate##223 assume !false; 237108#L85 ~m_pc~0 := 1;~m_st~0 := 2; 237106#master_returnLabel#1 assume { :end_inline_master } true; 237074#L494-2 havoc eval_~tmp_ndt_1~0#1; 234595#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 234387#L508 assume 0 != eval_~tmp_ndt_2~0#1;~t1_st~0 := 1;assume { :begin_inline_transmit1 } true; 237069#L106 assume 0 == ~t1_pc~0; 238203#L117-1 assume !false; 234522#L118 ~t1_pc~0 := 1;~t1_st~0 := 2; 234521#transmit1_returnLabel#1 assume { :end_inline_transmit1 } true; 234386#L508-2 havoc eval_~tmp_ndt_2~0#1; 234383#L505-1 assume !(0 == ~t2_st~0); 234375#L519-1 assume !(0 == ~t3_st~0); 234373#L533-1 assume !(0 == ~t4_st~0); 233948#L547-1 assume !(0 == ~t5_st~0); 233945#L561-1 assume !false; 233943#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 231749#L439 assume !(0 == ~m_st~0); 231747#L443 assume !(0 == ~t1_st~0); 231746#L447 assume !(0 == ~t2_st~0); 231745#L451 assume !(0 == ~t3_st~0); 231744#L455 assume !(0 == ~t4_st~0); 231742#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 231741#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 231740#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 231738#L486 assume !(0 != eval_~tmp~0#1); 231737#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 231736#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 231735#L586-3 assume !(0 == ~M_E~0); 231734#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 231733#L591-3 assume !(0 == ~T2_E~0); 231732#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 231731#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 231730#L606-3 assume !(0 == ~T5_E~0); 231729#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 231728#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 231727#L621-3 assume !(0 == ~E_3~0); 231726#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 231725#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 231724#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 231722#L279-18 assume 1 == ~m_pc~0; 231721#L280-6 assume !(1 == ~M_E~0); 231720#L279-20 is_master_triggered_~__retres1~0#1 := 0; 231719#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 231718#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 231717#L720-18 assume !(0 != activate_threads_~tmp~1#1); 231716#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 231715#L298-18 assume 1 == ~t1_pc~0; 231714#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 231712#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 231711#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 231709#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 231708#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 231707#L317-18 assume !(1 == ~t2_pc~0); 231706#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 231705#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 231704#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 231703#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 231702#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 231701#L336-18 assume !(1 == ~t3_pc~0); 231700#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 231699#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 231698#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 231696#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 231694#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 231692#L355-18 assume !(1 == ~t4_pc~0); 231689#L355-20 is_transmit4_triggered_~__retres1~4#1 := 0; 231685#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 231680#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 231676#L752-18 assume !(0 != activate_threads_~tmp___3~0#1); 231672#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 231668#L374-18 assume !(1 == ~t5_pc~0); 231665#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 231661#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 231657#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 231654#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 231651#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 231647#L649-3 assume !(1 == ~M_E~0); 231195#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 231640#L654-3 assume !(1 == ~T2_E~0); 231636#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 231632#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 231628#L669-3 assume !(1 == ~T5_E~0); 231624#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 231620#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 231616#L684-3 assume !(1 == ~E_3~0); 231607#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 231598#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 231590#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 231581#L439-1 assume !(0 == ~m_st~0); 231570#L443-1 assume !(0 == ~t1_st~0); 231568#L447-1 assume 0 == ~t2_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 231560#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 231554#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 231547#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 230343#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 231536#L279-21 assume 1 == ~m_pc~0; 231527#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 231521#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 231515#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 231509#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 231504#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 231498#L298-21 assume !(1 == ~t1_pc~0); 231483#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 231475#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 231468#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 231459#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 231454#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 231449#L317-21 assume !(1 == ~t2_pc~0); 231441#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 231433#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 231427#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 231421#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 231414#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 231408#L336-21 assume !(1 == ~t3_pc~0); 231402#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 231244#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 231239#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 231233#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 230355#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 230350#L355-21 assume !(1 == ~t4_pc~0); 230346#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 230344#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 230340#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 230338#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 230335#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 230333#L374-21 assume !(1 == ~t5_pc~0); 230332#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 230327#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 230325#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 230323#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 230321#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 230318#L793 assume !(1 == ~M_E~0); 230316#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 230314#L798-1 assume !(1 == ~T2_E~0); 230312#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 230307#L808-1 assume !(1 == ~T4_E~0); 230305#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 230303#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 230301#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 230299#L828-1 assume !(1 == ~E_3~0); 230297#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 230295#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 230129#L843-1 assume { :end_inline_reset_time_events } true; 230127#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 230124#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 230122#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 230119#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 230117#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 230115#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 230113#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 230111#L932 assume !(0 != start_simulation_~tmp___0~1#1); 230109#L900-2 assume !false; 230059#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 230054#L561-1 assume !false; 230052#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 230049#L439 assume !(0 == ~m_st~0); 230050#L443 assume !(0 == ~t1_st~0); 230298#L447 assume !(0 == ~t2_st~0); 230296#L451 assume !(0 == ~t3_st~0); 230294#L455 assume !(0 == ~t4_st~0); 230292#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 230291#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 230289#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 230287#L486 assume !(0 != eval_~tmp~0#1); 230286#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 230285#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 230283#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 230282#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 230281#L591-3 assume !(0 == ~T2_E~0); 230280#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 230279#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 230278#L606-3 assume !(0 == ~T5_E~0); 230277#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 230276#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 230274#L621-3 assume !(0 == ~E_3~0); 230272#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 230270#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 230268#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 230265#L279-18 assume 1 == ~m_pc~0; 230261#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 230259#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 230257#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 230253#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 230251#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 230249#L298-18 assume 1 == ~t1_pc~0; 230233#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 230230#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 230228#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 230225#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 230226#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 233534#L317-18 assume !(1 == ~t2_pc~0); 233532#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 233530#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 233528#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 233526#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 233524#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233522#L336-18 assume !(1 == ~t3_pc~0); 233518#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 233516#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 233514#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 233512#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 233509#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 233507#L355-18 assume 1 == ~t4_pc~0; 233505#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 233506#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 233542#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 233496#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 233494#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 233492#L374-18 assume !(1 == ~t5_pc~0); 233490#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 233489#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 233487#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 233485#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 233483#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 233480#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 233478#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 233476#L654-3 assume !(1 == ~T2_E~0); 233474#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 233472#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 233470#L669-3 assume !(1 == ~T5_E~0); 233468#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 233466#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 233465#L684-3 assume !(1 == ~E_3~0); 233464#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 233462#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 233459#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 233457#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 233454#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 233451#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 233448#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 232334#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 233445#L279-21 assume !(1 == ~m_pc~0); 233446#L279-23 is_master_triggered_~__retres1~0#1 := 0; 234729#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 234727#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 234725#L720-21 assume !(0 != activate_threads_~tmp~1#1); 234723#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 234721#L298-21 assume !(1 == ~t1_pc~0); 234719#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 234716#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 234714#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 234711#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 231671#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 234708#L317-21 assume !(1 == ~t2_pc~0); 234707#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 234706#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 234705#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 234704#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 234701#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 234699#L336-21 assume !(1 == ~t3_pc~0); 234697#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 234695#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 234693#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 234691#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 234689#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 234687#L355-21 assume !(1 == ~t4_pc~0); 234682#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 234680#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 234678#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 234674#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 234330#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 234329#L374-21 assume !(1 == ~t5_pc~0); 234328#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 234327#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 234325#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 234324#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 234322#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 234319#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 234320#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 235136#L798-1 assume !(1 == ~T2_E~0); 235134#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 235132#L808-1 assume !(1 == ~T4_E~0); 235129#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 235127#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 235125#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 235123#L828-1 assume !(1 == ~E_3~0); 235122#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 235120#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 235118#L843-1 assume { :end_inline_reset_time_events } true; 235116#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 235113#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 235111#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 235109#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 235106#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 235104#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 235102#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 235081#L932 assume !(0 != start_simulation_~tmp___0~1#1); 227775#L900-2 [2023-11-29 01:07:13,020 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:13,020 INFO L85 PathProgramCache]: Analyzing trace with hash -148144228, now seen corresponding path program 1 times [2023-11-29 01:07:13,020 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:13,020 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1941723353] [2023-11-29 01:07:13,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:13,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:13,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:13,049 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:13,049 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:13,049 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1941723353] [2023-11-29 01:07:13,049 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1941723353] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:13,049 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:13,049 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:13,050 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760222175] [2023-11-29 01:07:13,050 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:13,050 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:13,050 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:13,051 INFO L85 PathProgramCache]: Analyzing trace with hash 1285998487, now seen corresponding path program 1 times [2023-11-29 01:07:13,051 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:13,051 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [254367943] [2023-11-29 01:07:13,051 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:13,051 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:13,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:13,153 INFO L134 CoverageAnalysis]: Checked inductivity of 146 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 132 trivial. 0 not checked. [2023-11-29 01:07:13,153 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:13,153 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [254367943] [2023-11-29 01:07:13,153 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [254367943] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:13,154 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:13,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:13,154 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1421544998] [2023-11-29 01:07:13,154 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:13,155 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:13,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:13,155 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:13,155 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:13,156 INFO L87 Difference]: Start difference. First operand 32746 states and 44173 transitions. cyclomatic complexity: 11443 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 3 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:13,387 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:13,387 INFO L93 Difference]: Finished difference Result 32676 states and 44077 transitions. [2023-11-29 01:07:13,387 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32676 states and 44077 transitions. [2023-11-29 01:07:13,511 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 32408 [2023-11-29 01:07:13,649 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32676 states to 32676 states and 44077 transitions. [2023-11-29 01:07:13,649 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32676 [2023-11-29 01:07:13,667 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32676 [2023-11-29 01:07:13,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32676 states and 44077 transitions. [2023-11-29 01:07:13,696 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:13,696 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32676 states and 44077 transitions. [2023-11-29 01:07:13,717 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32676 states and 44077 transitions. [2023-11-29 01:07:13,976 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32676 to 32676. [2023-11-29 01:07:14,004 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 32676 states, 32676 states have (on average 1.3489105153629575) internal successors, (44077), 32675 states have internal predecessors, (44077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:14,072 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 32676 states to 32676 states and 44077 transitions. [2023-11-29 01:07:14,072 INFO L240 hiAutomatonCegarLoop]: Abstraction has 32676 states and 44077 transitions. [2023-11-29 01:07:14,072 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:14,073 INFO L428 stractBuchiCegarLoop]: Abstraction has 32676 states and 44077 transitions. [2023-11-29 01:07:14,073 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 01:07:14,073 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 32676 states and 44077 transitions. [2023-11-29 01:07:14,182 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 32408 [2023-11-29 01:07:14,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:14,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:14,187 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:14,187 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:14,188 INFO L748 eck$LassoCheckResult]: Stem: 293128#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 293129#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 293254#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 293255#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 293272#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 293273#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 293062#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 293063#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 293398#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 293399#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 293353#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 293030#L586 assume !(0 == ~M_E~0); 293031#L586-2 assume !(0 == ~T1_E~0); 293084#L591-1 assume !(0 == ~T2_E~0); 293209#L596-1 assume !(0 == ~T3_E~0); 293210#L601-1 assume !(0 == ~T4_E~0); 293259#L606-1 assume !(0 == ~T5_E~0); 293260#L611-1 assume !(0 == ~E_1~0); 293362#L616-1 assume !(0 == ~E_2~0); 293363#L621-1 assume !(0 == ~E_3~0); 292951#L626-1 assume !(0 == ~E_4~0); 292952#L631-1 assume !(0 == ~E_5~0); 293121#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 292949#L279 assume !(1 == ~m_pc~0); 292950#L279-2 is_master_triggered_~__retres1~0#1 := 0; 293289#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 293096#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 293097#L720 assume !(0 != activate_threads_~tmp~1#1); 293288#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 293130#L298 assume !(1 == ~t1_pc~0); 292900#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 292901#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 292924#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 292925#L728 assume !(0 != activate_threads_~tmp___0~0#1); 292962#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 293090#L317 assume !(1 == ~t2_pc~0); 293091#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 293311#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293258#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 293141#L736 assume !(0 != activate_threads_~tmp___1~0#1); 293142#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 293347#L336 assume !(1 == ~t3_pc~0); 293348#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 293434#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 292873#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 292874#L744 assume !(0 != activate_threads_~tmp___2~0#1); 293297#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 293359#L355 assume !(1 == ~t4_pc~0); 293208#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 293356#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 292991#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 292992#L752 assume !(0 != activate_threads_~tmp___3~0#1); 292974#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 292975#L374 assume !(1 == ~t5_pc~0); 293114#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 293115#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 293102#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 293103#L760 assume !(0 != activate_threads_~tmp___4~0#1); 293242#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 293243#L649 assume !(1 == ~M_E~0); 293424#L649-2 assume !(1 == ~T1_E~0); 292934#L654-1 assume !(1 == ~T2_E~0); 292935#L659-1 assume !(1 == ~T3_E~0); 293138#L664-1 assume !(1 == ~T4_E~0); 292926#L669-1 assume !(1 == ~T5_E~0); 292927#L674-1 assume !(1 == ~E_1~0); 293337#L679-1 assume !(1 == ~E_2~0); 293032#L684-1 assume !(1 == ~E_3~0); 293033#L689-1 assume !(1 == ~E_4~0); 293203#L694-1 assume !(1 == ~E_5~0); 293200#L699-1 assume { :end_inline_reset_delta_events } true; 293201#L900-2 [2023-11-29 01:07:14,188 INFO L750 eck$LassoCheckResult]: Loop: 293201#L900-2 assume !false; 301795#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 301790#L561-1 assume !false; 301788#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 301785#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 301783#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 301781#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 301779#L486 assume 0 != eval_~tmp~0#1; 301776#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 301774#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 301775#L65 assume 0 == ~m_pc~0; 303409#L92 assume !false; 303478#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 303477#L279-3 assume !(1 == ~m_pc~0); 303476#L279-5 is_master_triggered_~__retres1~0#1 := 0; 303475#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 303473#is_master_triggered_returnLabel#2 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 303472#L720-3 assume !(0 != activate_threads_~tmp~1#1); 303471#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 303470#L298-3 assume 1 == ~t1_pc~0; 303468#L299-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 303466#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 303465#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 303464#L728-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 302041#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 303463#L317-3 assume !(1 == ~t2_pc~0); 303461#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 303459#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 303457#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 303456#L736-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 303454#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 303451#L336-3 assume !(1 == ~t3_pc~0); 303449#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 303447#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 303445#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 303444#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 303442#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 303440#L355-3 assume !(1 == ~t4_pc~0); 303436#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 303434#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 303432#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 303430#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 303427#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 303425#L374-3 assume !(1 == ~t5_pc~0); 303423#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 303421#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 303419#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 303417#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 303413#L760-5 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 303407#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 303404#$Ultimate##223 assume !false; 303402#L85 ~m_pc~0 := 1;~m_st~0 := 2; 303400#master_returnLabel#1 assume { :end_inline_master } true; 303227#L494-2 havoc eval_~tmp_ndt_1~0#1; 301948#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 301945#L508 assume 0 != eval_~tmp_ndt_2~0#1;~t1_st~0 := 1;assume { :begin_inline_transmit1 } true; 301946#L106 assume 0 == ~t1_pc~0; 301981#L117-1 assume !false; 301980#L118 ~t1_pc~0 := 1;~t1_st~0 := 2; 301979#transmit1_returnLabel#1 assume { :end_inline_transmit1 } true; 301968#L508-2 havoc eval_~tmp_ndt_2~0#1; 301966#L505-1 assume !(0 == ~t2_st~0); 301955#L519-1 assume !(0 == ~t3_st~0); 301952#L533-1 assume !(0 == ~t4_st~0); 301940#L547-1 assume !(0 == ~t5_st~0); 301936#L561-1 assume !false; 301933#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 300230#L439 assume !(0 == ~m_st~0); 300227#L443 assume !(0 == ~t1_st~0); 300225#L447 assume !(0 == ~t2_st~0); 300222#L451 assume !(0 == ~t3_st~0); 300220#L455 assume !(0 == ~t4_st~0); 300217#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 300214#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 300212#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 300209#L486 assume !(0 != eval_~tmp~0#1); 300206#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 300204#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 300202#L586-3 assume !(0 == ~M_E~0); 300199#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 300197#L591-3 assume !(0 == ~T2_E~0); 300195#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 300193#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 300191#L606-3 assume !(0 == ~T5_E~0); 300190#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 300187#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 300185#L621-3 assume !(0 == ~E_3~0); 300183#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 300181#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 300179#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 300176#L279-18 assume 1 == ~m_pc~0; 300172#L280-6 assume !(1 == ~M_E~0); 300170#L279-20 is_master_triggered_~__retres1~0#1 := 0; 300168#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 300166#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 300163#L720-18 assume !(0 != activate_threads_~tmp~1#1); 300161#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 300159#L298-18 assume !(1 == ~t1_pc~0); 300156#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 300154#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 300152#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 300149#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 300147#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 300144#L317-18 assume !(1 == ~t2_pc~0); 300142#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 300140#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 300138#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 300136#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 300134#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 300132#L336-18 assume !(1 == ~t3_pc~0); 300130#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 300128#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 300126#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 300124#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 300122#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 300119#L355-18 assume 1 == ~t4_pc~0; 300117#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 300118#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 300712#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 300108#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 300105#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 300102#L374-18 assume !(1 == ~t5_pc~0); 300100#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 300098#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 300096#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 300091#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 300089#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 300087#L649-3 assume !(1 == ~M_E~0); 296891#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 300083#L654-3 assume !(1 == ~T2_E~0); 300081#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 300078#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 300076#L669-3 assume !(1 == ~T5_E~0); 300074#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 300071#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 300069#L684-3 assume !(1 == ~E_3~0); 300067#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 300065#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 300063#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 300060#L439-1 assume !(0 == ~m_st~0); 296326#L443-1 assume !(0 == ~t1_st~0); 300056#L447-1 assume 0 == ~t2_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 300051#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 300049#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 296316#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 296315#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 296311#L279-21 assume 1 == ~m_pc~0; 296307#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 296305#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 296303#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 296290#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 296288#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 296286#L298-21 assume !(1 == ~t1_pc~0); 296284#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 296280#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 296278#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 296266#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 296267#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 299918#L317-21 assume !(1 == ~t2_pc~0); 299917#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 299915#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 299914#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 299912#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 299910#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 299908#L336-21 assume !(1 == ~t3_pc~0); 299906#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 299904#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299902#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 299901#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 299876#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 299871#L355-21 assume 1 == ~t4_pc~0; 299869#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 299870#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 299879#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 299859#L752-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 299857#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 299855#L374-21 assume !(1 == ~t5_pc~0); 299853#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 299851#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 299849#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 299847#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 299846#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 299841#L793 assume !(1 == ~M_E~0); 296737#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 296735#L798-1 assume !(1 == ~T2_E~0); 295726#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 295724#L808-1 assume !(1 == ~T4_E~0); 295722#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 295720#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 295718#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 295715#L828-1 assume !(1 == ~E_3~0); 295713#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 295711#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 295348#L843-1 assume { :end_inline_reset_time_events } true; 295346#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 295343#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 295341#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 295339#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 295337#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 295335#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 295333#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 295330#L932 assume !(0 != start_simulation_~tmp___0~1#1); 295328#L900-2 assume !false; 295326#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 294676#L561-1 assume !false; 295320#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 295317#L439 assume !(0 == ~m_st~0); 295318#L443 assume !(0 == ~t1_st~0); 295527#L447 assume !(0 == ~t2_st~0); 295525#L451 assume !(0 == ~t3_st~0); 295523#L455 assume !(0 == ~t4_st~0); 295520#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 295518#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 295516#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 295513#L486 assume !(0 != eval_~tmp~0#1); 295511#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 295509#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 295507#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 295505#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 295503#L591-3 assume !(0 == ~T2_E~0); 295501#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 295499#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 295494#L606-3 assume !(0 == ~T5_E~0); 295492#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 295490#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 295489#L621-3 assume !(0 == ~E_3~0); 295488#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 295486#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 295485#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 295483#L279-18 assume 1 == ~m_pc~0; 295479#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 295477#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 295473#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 295471#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 295469#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 295465#L298-18 assume !(1 == ~t1_pc~0); 295461#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 295458#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 295456#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 295452#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 295453#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 296395#L317-18 assume !(1 == ~t2_pc~0); 296394#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 296392#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 296388#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 296385#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 296383#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 296379#L336-18 assume !(1 == ~t3_pc~0); 296378#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 296376#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 296372#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 296368#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 296367#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 296366#L355-18 assume 1 == ~t4_pc~0; 296365#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 296364#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 296362#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 296358#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 296356#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 295627#L374-18 assume !(1 == ~t5_pc~0); 295624#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 295622#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 295620#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 295618#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 295616#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 295613#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 295614#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 300487#L654-3 assume !(1 == ~T2_E~0); 300483#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 300482#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 300480#L669-3 assume !(1 == ~T5_E~0); 300476#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 300472#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 300469#L684-3 assume !(1 == ~E_3~0); 300466#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 300465#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 299947#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 299945#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 299944#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 299942#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 296930#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 295577#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 296926#L279-21 assume !(1 == ~m_pc~0); 296927#L279-23 is_master_triggered_~__retres1~0#1 := 0; 298147#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 298145#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 298143#L720-21 assume !(0 != activate_threads_~tmp~1#1); 298140#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 298138#L298-21 assume 1 == ~t1_pc~0; 298135#L299-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 298133#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 298131#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 298129#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 297971#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 298126#L317-21 assume !(1 == ~t2_pc~0); 298122#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 298120#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 298118#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 298117#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 298114#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 298113#L336-21 assume !(1 == ~t3_pc~0); 298112#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 298111#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 298110#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 298106#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 298105#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 298104#L355-21 assume !(1 == ~t4_pc~0); 298101#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 298099#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 298098#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 298096#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 298091#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 298087#L374-21 assume !(1 == ~t5_pc~0); 298086#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 298085#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 298084#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 298082#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 298081#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 298078#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 298079#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 301835#L798-1 assume !(1 == ~T2_E~0); 301834#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 301833#L808-1 assume !(1 == ~T4_E~0); 301831#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 301828#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 301826#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 301824#L828-1 assume !(1 == ~E_3~0); 301822#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 301820#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 301818#L843-1 assume { :end_inline_reset_time_events } true; 301816#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 301813#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 301811#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 301809#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 301807#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 301803#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 301801#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 301799#L932 assume !(0 != start_simulation_~tmp___0~1#1); 293201#L900-2 [2023-11-29 01:07:14,189 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:14,190 INFO L85 PathProgramCache]: Analyzing trace with hash -445536100, now seen corresponding path program 6 times [2023-11-29 01:07:14,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:14,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [733251729] [2023-11-29 01:07:14,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:14,190 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:14,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:14,285 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:14,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:14,303 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:14,304 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:14,304 INFO L85 PathProgramCache]: Analyzing trace with hash 961352986, now seen corresponding path program 1 times [2023-11-29 01:07:14,304 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:14,304 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [172410644] [2023-11-29 01:07:14,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:14,305 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:14,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:14,412 INFO L134 CoverageAnalysis]: Checked inductivity of 145 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 131 trivial. 0 not checked. [2023-11-29 01:07:14,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:14,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [172410644] [2023-11-29 01:07:14,412 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [172410644] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:14,412 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:14,413 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:14,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [782114448] [2023-11-29 01:07:14,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:14,414 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:14,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:14,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:14,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:14,415 INFO L87 Difference]: Start difference. First operand 32676 states and 44077 transitions. cyclomatic complexity: 11417 Second operand has 3 states, 3 states have (on average 73.33333333333333) internal successors, (220), 3 states have internal predecessors, (220), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:14,576 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:14,576 INFO L93 Difference]: Finished difference Result 36235 states and 48631 transitions. [2023-11-29 01:07:14,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36235 states and 48631 transitions. [2023-11-29 01:07:14,739 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 35384 [2023-11-29 01:07:14,960 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36235 states to 36235 states and 48631 transitions. [2023-11-29 01:07:14,961 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36235 [2023-11-29 01:07:14,974 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36235 [2023-11-29 01:07:14,974 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36235 states and 48631 transitions. [2023-11-29 01:07:15,000 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:15,000 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36235 states and 48631 transitions. [2023-11-29 01:07:15,021 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36235 states and 48631 transitions. [2023-11-29 01:07:15,349 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36235 to 36163. [2023-11-29 01:07:15,371 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36163 states, 36163 states have (on average 1.342117634045848) internal successors, (48535), 36162 states have internal predecessors, (48535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:15,447 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36163 states to 36163 states and 48535 transitions. [2023-11-29 01:07:15,447 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36163 states and 48535 transitions. [2023-11-29 01:07:15,447 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:15,448 INFO L428 stractBuchiCegarLoop]: Abstraction has 36163 states and 48535 transitions. [2023-11-29 01:07:15,448 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 01:07:15,448 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36163 states and 48535 transitions. [2023-11-29 01:07:15,633 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 35384 [2023-11-29 01:07:15,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:15,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:15,637 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:15,637 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:15,638 INFO L748 eck$LassoCheckResult]: Stem: 362052#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 362053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 362181#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 362182#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 362203#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 362204#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 361982#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 361983#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 362331#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 362332#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 362280#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 361948#L586 assume !(0 == ~M_E~0); 361949#L586-2 assume !(0 == ~T1_E~0); 362006#L591-1 assume !(0 == ~T2_E~0); 362135#L596-1 assume !(0 == ~T3_E~0); 362136#L601-1 assume !(0 == ~T4_E~0); 362188#L606-1 assume !(0 == ~T5_E~0); 362189#L611-1 assume !(0 == ~E_1~0); 362292#L616-1 assume !(0 == ~E_2~0); 362293#L621-1 assume !(0 == ~E_3~0); 361869#L626-1 assume !(0 == ~E_4~0); 361870#L631-1 assume !(0 == ~E_5~0); 362045#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 361867#L279 assume !(1 == ~m_pc~0); 361868#L279-2 is_master_triggered_~__retres1~0#1 := 0; 362219#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 362018#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 362019#L720 assume !(0 != activate_threads_~tmp~1#1); 362218#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 362054#L298 assume 1 == ~t1_pc~0; 362055#L299 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 362227#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 372009#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 372008#L728 assume !(0 != activate_threads_~tmp___0~0#1); 372007#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 372006#L317 assume !(1 == ~t2_pc~0); 372005#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 372004#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 372003#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 372002#L736 assume !(0 != activate_threads_~tmp___1~0#1); 372001#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 372000#L336 assume !(1 == ~t3_pc~0); 371999#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 371998#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 371997#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 371996#L744 assume !(0 != activate_threads_~tmp___2~0#1); 371995#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 371994#L355 assume !(1 == ~t4_pc~0); 371993#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 372011#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 372010#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 371988#L752 assume !(0 != activate_threads_~tmp___3~0#1); 371987#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 371986#L374 assume !(1 == ~t5_pc~0); 371985#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 371984#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 371983#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 371982#L760 assume !(0 != activate_threads_~tmp___4~0#1); 371981#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 371980#L649 assume !(1 == ~M_E~0); 371979#L649-2 assume !(1 == ~T1_E~0); 371978#L654-1 assume !(1 == ~T2_E~0); 371977#L659-1 assume !(1 == ~T3_E~0); 371976#L664-1 assume !(1 == ~T4_E~0); 371975#L669-1 assume !(1 == ~T5_E~0); 371974#L674-1 assume !(1 == ~E_1~0); 362282#L679-1 assume !(1 == ~E_2~0); 361950#L684-1 assume !(1 == ~E_3~0); 361951#L689-1 assume !(1 == ~E_4~0); 362390#L694-1 assume !(1 == ~E_5~0); 362125#L699-1 assume { :end_inline_reset_delta_events } true; 362126#L900-2 [2023-11-29 01:07:15,639 INFO L750 eck$LassoCheckResult]: Loop: 362126#L900-2 assume !false; 372365#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 372360#L561-1 assume !false; 372358#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 372355#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 372353#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 372351#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 372349#L486 assume 0 != eval_~tmp~0#1; 372346#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 372343#L494 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 372340#L65 assume 0 == ~m_pc~0; 372111#L92 assume !false; 372338#L77 ~E_1~0 := 1;assume { :begin_inline_immediate_notify } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 372336#L279-3 assume !(1 == ~m_pc~0); 372334#L279-5 is_master_triggered_~__retres1~0#1 := 0; 372332#L290-1 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 372330#is_master_triggered_returnLabel#2 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 372328#L720-3 assume !(0 != activate_threads_~tmp~1#1); 372326#L720-5 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 372324#L298-3 assume 1 == ~t1_pc~0; 371762#L299-1 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 372318#L309-1 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 372315#is_transmit1_triggered_returnLabel#2 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 372312#L728-3 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 371320#L728-5 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 372306#L317-3 assume !(1 == ~t2_pc~0); 372301#L317-5 is_transmit2_triggered_~__retres1~2#1 := 0; 372296#L328-1 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 372291#is_transmit2_triggered_returnLabel#2 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 372284#L736-3 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 372279#L736-5 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 372273#L336-3 assume !(1 == ~t3_pc~0); 372268#L336-5 is_transmit3_triggered_~__retres1~3#1 := 0; 372264#L347-1 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 372258#is_transmit3_triggered_returnLabel#2 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 372253#L744-3 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 372249#L744-5 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 372248#L355-3 assume !(1 == ~t4_pc~0); 372247#L355-5 is_transmit4_triggered_~__retres1~4#1 := 0; 372245#L366-1 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 372235#is_transmit4_triggered_returnLabel#2 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 372228#L752-3 assume !(0 != activate_threads_~tmp___3~0#1); 372223#L752-5 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 372203#L374-3 assume !(1 == ~t5_pc~0); 372150#L374-5 is_transmit5_triggered_~__retres1~5#1 := 0; 372140#L385-1 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 372132#is_transmit5_triggered_returnLabel#2 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 372125#L760-3 assume !(0 != activate_threads_~tmp___4~0#1); 372118#L760-5 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true; 372109#immediate_notify_returnLabel#1 assume { :end_inline_immediate_notify } true;~E_1~0 := 2; 372103#$Ultimate##223 assume !false; 372096#L85 ~m_pc~0 := 1;~m_st~0 := 2; 372088#master_returnLabel#1 assume { :end_inline_master } true; 372079#L494-2 havoc eval_~tmp_ndt_1~0#1; 369614#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 369440#L508 assume 0 != eval_~tmp_ndt_2~0#1;~t1_st~0 := 1;assume { :begin_inline_transmit1 } true; 372054#L106 assume !(0 == ~t1_pc~0); 371431#L109 assume !(1 == ~t1_pc~0); 371020#L117-1 assume !false; 369558#L118 ~t1_pc~0 := 1;~t1_st~0 := 2; 369556#transmit1_returnLabel#1 assume { :end_inline_transmit1 } true; 369438#L508-2 havoc eval_~tmp_ndt_2~0#1; 369435#L505-1 assume !(0 == ~t2_st~0); 369429#L519-1 assume !(0 == ~t3_st~0); 369426#L533-1 assume !(0 == ~t4_st~0); 369421#L547-1 assume !(0 == ~t5_st~0); 369422#L561-1 assume !false; 369482#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 369480#L439 assume !(0 == ~m_st~0); 369477#L443 assume !(0 == ~t1_st~0); 369475#L447 assume !(0 == ~t2_st~0); 369473#L451 assume !(0 == ~t3_st~0); 369471#L455 assume !(0 == ~t4_st~0); 369468#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 369466#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 369464#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 369461#L486 assume !(0 != eval_~tmp~0#1); 369462#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 369540#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 369538#L586-3 assume !(0 == ~M_E~0); 369536#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 369534#L591-3 assume !(0 == ~T2_E~0); 369533#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 369532#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 369530#L606-3 assume !(0 == ~T5_E~0); 369528#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 369526#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 369524#L621-3 assume !(0 == ~E_3~0); 369522#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 369520#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 369518#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 369515#L279-18 assume 1 == ~m_pc~0; 369513#L280-6 assume !(1 == ~M_E~0); 369511#L279-20 is_master_triggered_~__retres1~0#1 := 0; 369510#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 369502#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 369500#L720-18 assume !(0 != activate_threads_~tmp~1#1); 369498#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 369496#L298-18 assume !(1 == ~t1_pc~0); 369493#L298-20 is_transmit1_triggered_~__retres1~1#1 := 0; 369491#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 369489#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 369486#L728-18 assume !(0 != activate_threads_~tmp___0~0#1); 369484#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 369483#L317-18 assume !(1 == ~t2_pc~0); 369481#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 369479#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 369476#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 369474#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 369472#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 369470#L336-18 assume !(1 == ~t3_pc~0); 369467#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 369465#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 369463#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 369459#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 369454#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 369453#L355-18 assume 1 == ~t4_pc~0; 369452#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 369450#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 369448#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 369445#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 369441#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 369437#L374-18 assume !(1 == ~t5_pc~0); 369433#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 369432#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 369428#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 369409#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 369403#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 369345#L649-3 assume !(1 == ~M_E~0); 369340#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 369338#L654-3 assume !(1 == ~T2_E~0); 369336#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 369334#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 369332#L669-3 assume !(1 == ~T5_E~0); 369330#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 369327#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 369328#L684-3 assume !(1 == ~E_3~0); 369321#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 369319#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 369184#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 369185#L439-1 assume !(0 == ~m_st~0); 367595#L443-1 assume !(0 == ~t1_st~0); 370276#L447-1 assume 0 == ~t2_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 370265#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 368795#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 368796#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 367647#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 367644#L279-21 assume 1 == ~m_pc~0; 367641#L280-7 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 367639#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 367635#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 367566#L720-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 367564#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 367563#L298-21 assume 1 == ~t1_pc~0; 367559#L299-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 367558#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 367557#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 367555#L728-21 assume !(0 != activate_threads_~tmp___0~0#1); 367554#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 367550#L317-21 assume !(1 == ~t2_pc~0); 367549#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 367548#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 367546#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 367544#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 367543#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 367542#L336-21 assume !(1 == ~t3_pc~0); 367540#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 367539#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 367538#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 367537#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 367536#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 367534#L355-21 assume 1 == ~t4_pc~0; 367532#L356-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 367533#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 367541#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 367522#L752-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 367520#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 367518#L374-21 assume !(1 == ~t5_pc~0); 367516#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 367514#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 367512#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 367510#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 367508#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 367505#L793 assume !(1 == ~M_E~0); 367502#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 367500#L798-1 assume !(1 == ~T2_E~0); 367498#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 367495#L808-1 assume !(1 == ~T4_E~0); 367493#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 367491#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 367489#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 367487#L828-1 assume !(1 == ~E_3~0); 367485#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 367483#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 366335#L843-1 assume { :end_inline_reset_time_events } true; 366333#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 366330#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 366327#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 366325#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 366323#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 366321#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 366318#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 366315#L932 assume !(0 != start_simulation_~tmp___0~1#1); 366314#L900-2 assume !false; 366311#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 366307#L561-1 assume !false; 366305#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 366302#L439 assume !(0 == ~m_st~0); 366303#L443 assume !(0 == ~t1_st~0); 366505#L447 assume !(0 == ~t2_st~0); 366504#L451 assume !(0 == ~t3_st~0); 366502#L455 assume !(0 == ~t4_st~0); 366497#L459 assume !(0 == ~t5_st~0);exists_runnable_thread_~__retres1~6#1 := 0; 366493#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 366490#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 366487#L486 assume !(0 != eval_~tmp~0#1); 366486#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 366484#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 366482#L586-3 assume 0 == ~M_E~0;~M_E~0 := 1; 366480#L586-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 366479#L591-3 assume !(0 == ~T2_E~0); 366476#L596-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 366475#L601-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 366474#L606-3 assume !(0 == ~T5_E~0); 366473#L611-3 assume 0 == ~E_1~0;~E_1~0 := 1; 366470#L616-3 assume 0 == ~E_2~0;~E_2~0 := 1; 366467#L621-3 assume !(0 == ~E_3~0); 366465#L626-3 assume 0 == ~E_4~0;~E_4~0 := 1; 366463#L631-3 assume 0 == ~E_5~0;~E_5~0 := 1; 366462#L636-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 366460#L279-18 assume 1 == ~m_pc~0; 366457#L280-6 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 366455#L290-6 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 366454#is_master_triggered_returnLabel#7 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 366452#L720-18 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 366449#L720-20 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 366446#L298-18 assume 1 == ~t1_pc~0; 366443#L299-6 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 366437#L309-6 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 366435#is_transmit1_triggered_returnLabel#7 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 366432#L728-18 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 366433#L728-20 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 368478#L317-18 assume !(1 == ~t2_pc~0); 368473#L317-20 is_transmit2_triggered_~__retres1~2#1 := 0; 368467#L328-6 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 368464#is_transmit2_triggered_returnLabel#7 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 368459#L736-18 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 368454#L736-20 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 368449#L336-18 assume !(1 == ~t3_pc~0); 368443#L336-20 is_transmit3_triggered_~__retres1~3#1 := 0; 368437#L347-6 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 368432#is_transmit3_triggered_returnLabel#7 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 368428#L744-18 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 368421#L744-20 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 368415#L355-18 assume 1 == ~t4_pc~0; 368409#L356-6 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 368403#L366-6 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 368398#is_transmit4_triggered_returnLabel#7 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 368392#L752-18 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 368386#L752-20 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 368379#L374-18 assume !(1 == ~t5_pc~0); 368372#L374-20 is_transmit5_triggered_~__retres1~5#1 := 0; 368365#L385-6 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 368359#is_transmit5_triggered_returnLabel#7 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 368353#L760-18 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 368346#L760-20 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 368340#L649-3 assume 1 == ~M_E~0;~M_E~0 := 2; 368341#L649-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 368516#L654-3 assume !(1 == ~T2_E~0); 368514#L659-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 368512#L664-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 368510#L669-3 assume !(1 == ~T5_E~0); 368508#L674-3 assume 1 == ~E_1~0;~E_1~0 := 2; 368506#L679-3 assume 1 == ~E_2~0;~E_2~0 := 2; 368505#L684-3 assume !(1 == ~E_3~0); 368503#L689-3 assume 1 == ~E_4~0;~E_4~0 := 2; 368496#L694-3 assume 1 == ~E_5~0;~E_5~0 := 2; 368492#L699-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 368487#L439-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 368481#L471-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 368476#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret18#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret18#1;havoc start_simulation_#t~ret18#1; 368470#L919 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 368124#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 368462#L279-21 assume !(1 == ~m_pc~0); 368457#L279-23 is_master_triggered_~__retres1~0#1 := 0; 368452#L290-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 368446#is_master_triggered_returnLabel#8 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 368440#L720-21 assume !(0 != activate_threads_~tmp~1#1); 368434#L720-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 368430#L298-21 assume !(1 == ~t1_pc~0); 368425#L298-23 is_transmit1_triggered_~__retres1~1#1 := 0; 368417#L309-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 368412#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 368406#L728-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 368034#L728-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 368395#L317-21 assume !(1 == ~t2_pc~0); 368389#L317-23 is_transmit2_triggered_~__retres1~2#1 := 0; 368382#L328-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 368375#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 368368#L736-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 368361#L736-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 368355#L336-21 assume !(1 == ~t3_pc~0); 368349#L336-23 is_transmit3_triggered_~__retres1~3#1 := 0; 368343#L347-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 368337#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 368332#L744-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 368327#L744-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 368321#L355-21 assume !(1 == ~t4_pc~0); 368313#L355-23 is_transmit4_triggered_~__retres1~4#1 := 0; 368307#L366-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 368288#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 368278#L752-21 assume !(0 != activate_threads_~tmp___3~0#1); 368271#L752-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 368265#L374-21 assume !(1 == ~t5_pc~0); 368259#L374-23 is_transmit5_triggered_~__retres1~5#1 := 0; 368253#L385-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 368220#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 368211#L760-21 assume !(0 != activate_threads_~tmp___4~0#1); 368202#L760-23 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 368200#L793 assume 1 == ~M_E~0;~M_E~0 := 2; 368201#L793-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 372429#L798-1 assume !(1 == ~T2_E~0); 372427#L803-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 372425#L808-1 assume !(1 == ~T4_E~0); 372423#L813-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 372420#L818-1 assume 1 == ~E_1~0;~E_1~0 := 2; 372417#L823-1 assume 1 == ~E_2~0;~E_2~0 := 2; 372412#L828-1 assume !(1 == ~E_3~0); 372409#L833-1 assume 1 == ~E_4~0;~E_4~0 := 2; 372407#L838-1 assume 1 == ~E_5~0;~E_5~0 := 2; 372405#L843-1 assume { :end_inline_reset_time_events } true; 372403#L919-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 372400#L439-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 372398#L471-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 372396#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret17#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret17#1;havoc stop_simulation_#t~ret17#1; 372393#L874 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 372388#L881 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 372384#stop_simulation_returnLabel#1 start_simulation_#t~ret19#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret17#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret19#1;havoc start_simulation_#t~ret19#1; 372378#L932 assume !(0 != start_simulation_~tmp___0~1#1); 362126#L900-2 [2023-11-29 01:07:15,640 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:15,640 INFO L85 PathProgramCache]: Analyzing trace with hash 1709978301, now seen corresponding path program 1 times [2023-11-29 01:07:15,640 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:15,640 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [309812277] [2023-11-29 01:07:15,640 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:15,640 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:15,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:15,675 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:15,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:15,676 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [309812277] [2023-11-29 01:07:15,676 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [309812277] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:15,676 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:15,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:07:15,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1010662395] [2023-11-29 01:07:15,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:15,676 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:07:15,677 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:15,677 INFO L85 PathProgramCache]: Analyzing trace with hash -340683783, now seen corresponding path program 1 times [2023-11-29 01:07:15,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:15,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63453711] [2023-11-29 01:07:15,677 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:15,677 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:15,701 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:15,760 INFO L134 CoverageAnalysis]: Checked inductivity of 144 backedges. 14 proven. 0 refuted. 0 times theorem prover too weak. 130 trivial. 0 not checked. [2023-11-29 01:07:15,760 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:15,761 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [63453711] [2023-11-29 01:07:15,761 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [63453711] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:15,761 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:15,761 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:15,761 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1852664704] [2023-11-29 01:07:15,761 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:15,762 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:07:15,762 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:15,762 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:15,762 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:15,762 INFO L87 Difference]: Start difference. First operand 36163 states and 48535 transitions. cyclomatic complexity: 12412 Second operand has 3 states, 3 states have (on average 23.666666666666668) internal successors, (71), 2 states have internal predecessors, (71), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:15,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:15,909 INFO L93 Difference]: Finished difference Result 36189 states and 48488 transitions. [2023-11-29 01:07:15,909 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 36189 states and 48488 transitions. [2023-11-29 01:07:16,029 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 35384 [2023-11-29 01:07:16,103 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 36189 states to 36189 states and 48488 transitions. [2023-11-29 01:07:16,103 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 36189 [2023-11-29 01:07:16,122 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 36189 [2023-11-29 01:07:16,122 INFO L73 IsDeterministic]: Start isDeterministic. Operand 36189 states and 48488 transitions. [2023-11-29 01:07:16,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:16,140 INFO L218 hiAutomatonCegarLoop]: Abstraction has 36189 states and 48488 transitions. [2023-11-29 01:07:16,161 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 36189 states and 48488 transitions. [2023-11-29 01:07:16,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 36189 to 36141. [2023-11-29 01:07:16,527 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36141 states, 36141 states have (on average 1.3403060236296727) internal successors, (48440), 36140 states have internal predecessors, (48440), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:16,583 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36141 states to 36141 states and 48440 transitions. [2023-11-29 01:07:16,583 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36141 states and 48440 transitions. [2023-11-29 01:07:16,584 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:16,584 INFO L428 stractBuchiCegarLoop]: Abstraction has 36141 states and 48440 transitions. [2023-11-29 01:07:16,584 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 01:07:16,584 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36141 states and 48440 transitions. [2023-11-29 01:07:16,666 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 35384 [2023-11-29 01:07:16,666 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:16,666 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:16,667 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:16,667 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:16,667 INFO L748 eck$LassoCheckResult]: Stem: 434407#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 434408#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 434532#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 434533#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 434553#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 434554#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 434342#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 434343#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 434683#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 434684#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 434634#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 434307#L586 assume !(0 == ~M_E~0); 434308#L586-2 assume !(0 == ~T1_E~0); 434363#L591-1 assume !(0 == ~T2_E~0); 434489#L596-1 assume !(0 == ~T3_E~0); 434490#L601-1 assume !(0 == ~T4_E~0); 434539#L606-1 assume !(0 == ~T5_E~0); 434540#L611-1 assume !(0 == ~E_1~0); 434648#L616-1 assume !(0 == ~E_2~0); 434649#L621-1 assume !(0 == ~E_3~0); 434228#L626-1 assume !(0 == ~E_4~0); 434229#L631-1 assume !(0 == ~E_5~0); 434400#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 434224#L279 assume !(1 == ~m_pc~0); 434225#L279-2 is_master_triggered_~__retres1~0#1 := 0; 434571#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 434375#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 434376#L720 assume !(0 != activate_threads_~tmp~1#1); 434570#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 434409#L298 assume !(1 == ~t1_pc~0); 434174#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 434175#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 434200#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 434201#L728 assume !(0 != activate_threads_~tmp___0~0#1); 434238#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 434369#L317 assume !(1 == ~t2_pc~0); 434370#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 434594#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 434537#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 434417#L736 assume !(0 != activate_threads_~tmp___1~0#1); 434418#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 434630#L336 assume !(1 == ~t3_pc~0); 434631#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 434720#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 434149#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 434150#L744 assume !(0 != activate_threads_~tmp___2~0#1); 434582#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 434640#L355 assume !(1 == ~t4_pc~0); 434486#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 434639#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 434268#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 434269#L752 assume !(0 != activate_threads_~tmp___3~0#1); 434249#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 434250#L374 assume !(1 == ~t5_pc~0); 434390#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 434391#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 434382#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 434383#L760 assume !(0 != activate_threads_~tmp___4~0#1); 434521#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 434522#L649 assume !(1 == ~M_E~0); 434711#L649-2 assume !(1 == ~T1_E~0); 434210#L654-1 assume !(1 == ~T2_E~0); 434211#L659-1 assume !(1 == ~T3_E~0); 434416#L664-1 assume !(1 == ~T4_E~0); 434202#L669-1 assume !(1 == ~T5_E~0); 434203#L674-1 assume !(1 == ~E_1~0); 434621#L679-1 assume !(1 == ~E_2~0); 434311#L684-1 assume !(1 == ~E_3~0); 434312#L689-1 assume !(1 == ~E_4~0); 434482#L694-1 assume !(1 == ~E_5~0); 434480#L699-1 assume { :end_inline_reset_delta_events } true; 434481#L900-2 assume !false; 435442#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 435437#L561-1 [2023-11-29 01:07:16,667 INFO L750 eck$LassoCheckResult]: Loop: 435437#L561-1 assume !false; 435434#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 435431#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 435429#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 435427#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 435424#L486 assume 0 != eval_~tmp~0#1; 435420#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 435417#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 435415#L494-2 havoc eval_~tmp_ndt_1~0#1; 435412#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 435409#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 435406#L508-2 havoc eval_~tmp_ndt_2~0#1; 435396#L505-1 assume !(0 == ~t2_st~0); 435397#L519-1 assume !(0 == ~t3_st~0); 435559#L533-1 assume !(0 == ~t4_st~0); 435440#L547-1 assume !(0 == ~t5_st~0); 435437#L561-1 [2023-11-29 01:07:16,668 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:16,668 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 1 times [2023-11-29 01:07:16,668 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:16,668 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [152105828] [2023-11-29 01:07:16,668 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:16,669 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:16,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:16,681 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:16,688 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:16,703 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:16,703 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:16,703 INFO L85 PathProgramCache]: Analyzing trace with hash 1454566731, now seen corresponding path program 1 times [2023-11-29 01:07:16,704 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:16,704 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [931730120] [2023-11-29 01:07:16,704 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:16,704 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:16,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:16,708 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:16,710 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:16,711 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:16,712 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:16,712 INFO L85 PathProgramCache]: Analyzing trace with hash -887738904, now seen corresponding path program 1 times [2023-11-29 01:07:16,712 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:16,712 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [820333544] [2023-11-29 01:07:16,712 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:16,713 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:16,722 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:16,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:16,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:16,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [820333544] [2023-11-29 01:07:16,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [820333544] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:16,867 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:16,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:16,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1810103487] [2023-11-29 01:07:16,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:16,976 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:16,977 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:16,977 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:16,977 INFO L87 Difference]: Start difference. First operand 36141 states and 48440 transitions. cyclomatic complexity: 12339 Second operand has 3 states, 3 states have (on average 29.666666666666668) internal successors, (89), 3 states have internal predecessors, (89), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:17,107 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:17,107 INFO L93 Difference]: Finished difference Result 42162 states and 56037 transitions. [2023-11-29 01:07:17,108 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42162 states and 56037 transitions. [2023-11-29 01:07:17,250 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 40831 [2023-11-29 01:07:17,334 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42162 states to 42162 states and 56037 transitions. [2023-11-29 01:07:17,334 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42162 [2023-11-29 01:07:17,355 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42162 [2023-11-29 01:07:17,355 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42162 states and 56037 transitions. [2023-11-29 01:07:17,370 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:17,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42162 states and 56037 transitions. [2023-11-29 01:07:17,391 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42162 states and 56037 transitions. [2023-11-29 01:07:17,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42162 to 40110. [2023-11-29 01:07:17,787 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40110 states, 40110 states have (on average 1.3326601844926451) internal successors, (53453), 40109 states have internal predecessors, (53453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:17,864 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40110 states to 40110 states and 53453 transitions. [2023-11-29 01:07:17,864 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40110 states and 53453 transitions. [2023-11-29 01:07:17,864 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:17,865 INFO L428 stractBuchiCegarLoop]: Abstraction has 40110 states and 53453 transitions. [2023-11-29 01:07:17,865 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 01:07:17,865 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40110 states and 53453 transitions. [2023-11-29 01:07:17,978 INFO L131 ngComponentsAnalysis]: Automaton has 44 accepting balls. 38779 [2023-11-29 01:07:17,978 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:17,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:17,979 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:17,979 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:17,980 INFO L748 eck$LassoCheckResult]: Stem: 512724#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 512725#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 512849#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 512850#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 512870#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 512871#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 512655#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 512656#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 513001#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 513002#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 512949#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 512619#L586 assume !(0 == ~M_E~0); 512620#L586-2 assume !(0 == ~T1_E~0); 512678#L591-1 assume !(0 == ~T2_E~0); 512804#L596-1 assume !(0 == ~T3_E~0); 512805#L601-1 assume !(0 == ~T4_E~0); 512855#L606-1 assume !(0 == ~T5_E~0); 512856#L611-1 assume !(0 == ~E_1~0); 512962#L616-1 assume !(0 == ~E_2~0); 512963#L621-1 assume !(0 == ~E_3~0); 512540#L626-1 assume !(0 == ~E_4~0); 512541#L631-1 assume !(0 == ~E_5~0); 512717#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 512536#L279 assume !(1 == ~m_pc~0); 512537#L279-2 is_master_triggered_~__retres1~0#1 := 0; 512887#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 512690#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 512691#L720 assume !(0 != activate_threads_~tmp~1#1); 512886#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 512726#L298 assume !(1 == ~t1_pc~0); 512486#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 512487#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 512512#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 512513#L728 assume !(0 != activate_threads_~tmp___0~0#1); 512549#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 512684#L317 assume !(1 == ~t2_pc~0); 512685#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 512908#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 512854#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 512734#L736 assume !(0 != activate_threads_~tmp___1~0#1); 512735#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 512943#L336 assume !(1 == ~t3_pc~0); 512944#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 513047#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 512461#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 512462#L744 assume !(0 != activate_threads_~tmp___2~0#1); 512896#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 512956#L355 assume !(1 == ~t4_pc~0); 512801#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 512955#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 512583#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 512584#L752 assume !(0 != activate_threads_~tmp___3~0#1); 512561#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 512562#L374 assume !(1 == ~t5_pc~0); 512707#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 512708#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 512696#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 512697#L760 assume !(0 != activate_threads_~tmp___4~0#1); 512837#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 512838#L649 assume !(1 == ~M_E~0); 513038#L649-2 assume !(1 == ~T1_E~0); 512522#L654-1 assume !(1 == ~T2_E~0); 512523#L659-1 assume !(1 == ~T3_E~0); 512733#L664-1 assume !(1 == ~T4_E~0); 512514#L669-1 assume !(1 == ~T5_E~0); 512515#L674-1 assume !(1 == ~E_1~0); 512934#L679-1 assume !(1 == ~E_2~0); 512623#L684-1 assume !(1 == ~E_3~0); 512624#L689-1 assume !(1 == ~E_4~0); 512797#L694-1 assume !(1 == ~E_5~0); 512795#L699-1 assume { :end_inline_reset_delta_events } true; 512796#L900-2 assume !false; 530614#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 530609#L561-1 [2023-11-29 01:07:17,980 INFO L750 eck$LassoCheckResult]: Loop: 530609#L561-1 assume !false; 530607#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 530296#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 530295#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 530293#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 530291#L486 assume 0 != eval_~tmp~0#1; 530289#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 530287#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 530285#L494-2 havoc eval_~tmp_ndt_1~0#1; 530283#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 530281#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 530282#L508-2 havoc eval_~tmp_ndt_2~0#1; 530646#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 530637#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 530633#L522-2 havoc eval_~tmp_ndt_3~0#1; 530627#L519-1 assume !(0 == ~t3_st~0); 530620#L533-1 assume !(0 == ~t4_st~0); 530612#L547-1 assume !(0 == ~t5_st~0); 530609#L561-1 [2023-11-29 01:07:17,980 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:17,980 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 2 times [2023-11-29 01:07:17,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:17,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1280462444] [2023-11-29 01:07:17,981 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:17,981 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:17,995 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:17,996 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:18,004 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:18,020 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:18,020 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:18,020 INFO L85 PathProgramCache]: Analyzing trace with hash 990378971, now seen corresponding path program 1 times [2023-11-29 01:07:18,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:18,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1105447244] [2023-11-29 01:07:18,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:18,021 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:18,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:18,026 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:18,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:18,030 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:18,031 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:18,031 INFO L85 PathProgramCache]: Analyzing trace with hash 597526840, now seen corresponding path program 1 times [2023-11-29 01:07:18,031 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:18,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1246105432] [2023-11-29 01:07:18,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:18,032 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:18,045 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:18,080 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:18,080 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:18,080 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1246105432] [2023-11-29 01:07:18,081 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1246105432] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:18,081 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:18,081 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:18,081 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [21576578] [2023-11-29 01:07:18,081 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:18,184 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:18,184 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:18,184 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:18,184 INFO L87 Difference]: Start difference. First operand 40110 states and 53453 transitions. cyclomatic complexity: 13387 Second operand has 3 states, 3 states have (on average 30.333333333333332) internal successors, (91), 3 states have internal predecessors, (91), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:18,362 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:18,362 INFO L93 Difference]: Finished difference Result 48246 states and 63748 transitions. [2023-11-29 01:07:18,362 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48246 states and 63748 transitions. [2023-11-29 01:07:18,650 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 45958 [2023-11-29 01:07:18,715 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48246 states to 48246 states and 63748 transitions. [2023-11-29 01:07:18,715 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48246 [2023-11-29 01:07:18,728 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48246 [2023-11-29 01:07:18,728 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48246 states and 63748 transitions. [2023-11-29 01:07:18,740 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:18,740 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48246 states and 63748 transitions. [2023-11-29 01:07:18,755 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48246 states and 63748 transitions. [2023-11-29 01:07:19,133 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48246 to 46319. [2023-11-29 01:07:19,148 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 46319 states, 46319 states have (on average 1.3245320494829336) internal successors, (61351), 46318 states have internal predecessors, (61351), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:19,213 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 46319 states to 46319 states and 61351 transitions. [2023-11-29 01:07:19,214 INFO L240 hiAutomatonCegarLoop]: Abstraction has 46319 states and 61351 transitions. [2023-11-29 01:07:19,214 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:19,214 INFO L428 stractBuchiCegarLoop]: Abstraction has 46319 states and 61351 transitions. [2023-11-29 01:07:19,214 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 01:07:19,215 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 46319 states and 61351 transitions. [2023-11-29 01:07:19,313 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 44031 [2023-11-29 01:07:19,313 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:19,313 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:19,313 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:19,313 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:19,314 INFO L748 eck$LassoCheckResult]: Stem: 601083#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 601084#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 601211#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 601212#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 601232#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 601233#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 601016#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 601017#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 601367#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 601368#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 601314#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 600983#L586 assume !(0 == ~M_E~0); 600984#L586-2 assume !(0 == ~T1_E~0); 601040#L591-1 assume !(0 == ~T2_E~0); 601167#L596-1 assume !(0 == ~T3_E~0); 601168#L601-1 assume !(0 == ~T4_E~0); 601216#L606-1 assume !(0 == ~T5_E~0); 601217#L611-1 assume !(0 == ~E_1~0); 601327#L616-1 assume !(0 == ~E_2~0); 601328#L621-1 assume !(0 == ~E_3~0); 600904#L626-1 assume !(0 == ~E_4~0); 600905#L631-1 assume !(0 == ~E_5~0); 601078#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 600902#L279 assume !(1 == ~m_pc~0); 600903#L279-2 is_master_triggered_~__retres1~0#1 := 0; 601250#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 601051#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 601052#L720 assume !(0 != activate_threads_~tmp~1#1); 601249#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 601085#L298 assume !(1 == ~t1_pc~0); 600852#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 600853#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600876#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 600877#L728 assume !(0 != activate_threads_~tmp___0~0#1); 600914#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 601045#L317 assume !(1 == ~t2_pc~0); 601046#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 601271#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 601215#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 601095#L736 assume !(0 != activate_threads_~tmp___1~0#1); 601096#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 601307#L336 assume !(1 == ~t3_pc~0); 601308#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 601414#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 600825#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 600826#L744 assume !(0 != activate_threads_~tmp___2~0#1); 601258#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 601319#L355 assume !(1 == ~t4_pc~0); 601166#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 601317#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 600945#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 600946#L752 assume !(0 != activate_threads_~tmp___3~0#1); 600928#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 600929#L374 assume !(1 == ~t5_pc~0); 601071#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 601072#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 601057#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 601058#L760 assume !(0 != activate_threads_~tmp___4~0#1); 601200#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 601201#L649 assume !(1 == ~M_E~0); 601404#L649-2 assume !(1 == ~T1_E~0); 600886#L654-1 assume !(1 == ~T2_E~0); 600887#L659-1 assume !(1 == ~T3_E~0); 601092#L664-1 assume !(1 == ~T4_E~0); 600878#L669-1 assume !(1 == ~T5_E~0); 600879#L674-1 assume !(1 == ~E_1~0); 601297#L679-1 assume !(1 == ~E_2~0); 600985#L684-1 assume !(1 == ~E_3~0); 600986#L689-1 assume !(1 == ~E_4~0); 601161#L694-1 assume !(1 == ~E_5~0); 601157#L699-1 assume { :end_inline_reset_delta_events } true; 601158#L900-2 assume !false; 610401#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 610366#L561-1 [2023-11-29 01:07:19,314 INFO L750 eck$LassoCheckResult]: Loop: 610366#L561-1 assume !false; 610388#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 610386#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 610385#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 610383#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 610381#L486 assume 0 != eval_~tmp~0#1; 610368#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 610359#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 610360#L494-2 havoc eval_~tmp_ndt_1~0#1; 610428#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 610425#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 610422#L508-2 havoc eval_~tmp_ndt_2~0#1; 610420#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 610417#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 610416#L522-2 havoc eval_~tmp_ndt_3~0#1; 610406#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 610399#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 610394#L536-2 havoc eval_~tmp_ndt_4~0#1; 610378#L533-1 assume !(0 == ~t4_st~0); 610365#L547-1 assume !(0 == ~t5_st~0); 610366#L561-1 [2023-11-29 01:07:19,314 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:19,314 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 3 times [2023-11-29 01:07:19,314 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:19,315 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1231416996] [2023-11-29 01:07:19,315 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:19,315 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:19,324 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:19,324 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:19,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:19,337 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:19,338 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:19,338 INFO L85 PathProgramCache]: Analyzing trace with hash -1898656693, now seen corresponding path program 1 times [2023-11-29 01:07:19,338 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:19,338 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1404597787] [2023-11-29 01:07:19,338 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:19,338 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:19,341 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:19,341 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:19,343 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:19,344 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:19,345 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:19,345 INFO L85 PathProgramCache]: Analyzing trace with hash -1472432536, now seen corresponding path program 1 times [2023-11-29 01:07:19,345 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:19,345 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1188674638] [2023-11-29 01:07:19,345 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:19,345 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:19,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:19,371 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:19,371 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:19,371 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1188674638] [2023-11-29 01:07:19,371 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1188674638] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:19,371 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:19,371 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:07:19,371 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [413745995] [2023-11-29 01:07:19,371 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:19,464 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:19,465 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:19,465 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:19,465 INFO L87 Difference]: Start difference. First operand 46319 states and 61351 transitions. cyclomatic complexity: 15078 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:19,683 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:19,683 INFO L93 Difference]: Finished difference Result 81103 states and 107076 transitions. [2023-11-29 01:07:19,683 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 81103 states and 107076 transitions. [2023-11-29 01:07:20,128 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 76604 [2023-11-29 01:07:20,262 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 81103 states to 81103 states and 107076 transitions. [2023-11-29 01:07:20,262 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 81103 [2023-11-29 01:07:20,289 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 81103 [2023-11-29 01:07:20,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 81103 states and 107076 transitions. [2023-11-29 01:07:20,313 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:20,313 INFO L218 hiAutomatonCegarLoop]: Abstraction has 81103 states and 107076 transitions. [2023-11-29 01:07:20,344 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 81103 states and 107076 transitions. [2023-11-29 01:07:20,972 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 81103 to 78562. [2023-11-29 01:07:21,019 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78562 states, 78562 states have (on average 1.3244443878719991) internal successors, (104051), 78561 states have internal predecessors, (104051), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:21,174 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78562 states to 78562 states and 104051 transitions. [2023-11-29 01:07:21,175 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78562 states and 104051 transitions. [2023-11-29 01:07:21,175 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:21,176 INFO L428 stractBuchiCegarLoop]: Abstraction has 78562 states and 104051 transitions. [2023-11-29 01:07:21,176 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-29 01:07:21,176 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78562 states and 104051 transitions. [2023-11-29 01:07:21,420 INFO L131 ngComponentsAnalysis]: Automaton has 46 accepting balls. 74063 [2023-11-29 01:07:21,420 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:21,420 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:21,421 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:21,421 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:21,421 INFO L748 eck$LassoCheckResult]: Stem: 728515#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 728516#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 728654#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 728655#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 728677#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 728678#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 728445#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 728446#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 728814#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 728815#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 728757#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 728412#L586 assume !(0 == ~M_E~0); 728413#L586-2 assume !(0 == ~T1_E~0); 728469#L591-1 assume !(0 == ~T2_E~0); 728604#L596-1 assume !(0 == ~T3_E~0); 728605#L601-1 assume !(0 == ~T4_E~0); 728661#L606-1 assume !(0 == ~T5_E~0); 728662#L611-1 assume !(0 == ~E_1~0); 728771#L616-1 assume !(0 == ~E_2~0); 728772#L621-1 assume !(0 == ~E_3~0); 728332#L626-1 assume !(0 == ~E_4~0); 728333#L631-1 assume !(0 == ~E_5~0); 728508#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 728330#L279 assume !(1 == ~m_pc~0); 728331#L279-2 is_master_triggered_~__retres1~0#1 := 0; 728693#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 728480#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 728481#L720 assume !(0 != activate_threads_~tmp~1#1); 728692#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 728517#L298 assume !(1 == ~t1_pc~0); 728280#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 728281#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 728304#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 728305#L728 assume !(0 != activate_threads_~tmp___0~0#1); 728342#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 728474#L317 assume !(1 == ~t2_pc~0); 728475#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 728714#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 728660#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 728527#L736 assume !(0 != activate_threads_~tmp___1~0#1); 728528#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 728751#L336 assume !(1 == ~t3_pc~0); 728752#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 728872#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 728254#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 728255#L744 assume !(0 != activate_threads_~tmp___2~0#1); 728701#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 728764#L355 assume !(1 == ~t4_pc~0); 728603#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 728761#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 728372#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 728373#L752 assume !(0 != activate_threads_~tmp___3~0#1); 728355#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 728356#L374 assume !(1 == ~t5_pc~0); 728501#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 728502#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 728486#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 728487#L760 assume !(0 != activate_threads_~tmp___4~0#1); 728642#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 728643#L649 assume !(1 == ~M_E~0); 728860#L649-2 assume !(1 == ~T1_E~0); 728314#L654-1 assume !(1 == ~T2_E~0); 728315#L659-1 assume !(1 == ~T3_E~0); 728524#L664-1 assume !(1 == ~T4_E~0); 728306#L669-1 assume !(1 == ~T5_E~0); 728307#L674-1 assume !(1 == ~E_1~0); 728740#L679-1 assume !(1 == ~E_2~0); 728414#L684-1 assume !(1 == ~E_3~0); 728415#L689-1 assume !(1 == ~E_4~0); 728598#L694-1 assume !(1 == ~E_5~0); 728595#L699-1 assume { :end_inline_reset_delta_events } true; 728596#L900-2 assume !false; 737958#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 737945#L561-1 [2023-11-29 01:07:21,421 INFO L750 eck$LassoCheckResult]: Loop: 737945#L561-1 assume !false; 737936#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 737929#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 737921#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 737914#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 737908#L486 assume 0 != eval_~tmp~0#1; 737900#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 737891#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 737884#L494-2 havoc eval_~tmp_ndt_1~0#1; 737874#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 737863#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 737857#L508-2 havoc eval_~tmp_ndt_2~0#1; 737849#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 737842#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 737843#L522-2 havoc eval_~tmp_ndt_3~0#1; 737999#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 737992#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 737984#L536-2 havoc eval_~tmp_ndt_4~0#1; 737977#L533-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 736307#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 737967#L550-2 havoc eval_~tmp_ndt_5~0#1; 737956#L547-1 assume !(0 == ~t5_st~0); 737945#L561-1 [2023-11-29 01:07:21,422 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:21,422 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 4 times [2023-11-29 01:07:21,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:21,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [116933370] [2023-11-29 01:07:21,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:21,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:21,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:21,436 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:21,443 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:21,457 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:21,458 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:21,459 INFO L85 PathProgramCache]: Analyzing trace with hash 746708699, now seen corresponding path program 1 times [2023-11-29 01:07:21,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:21,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1315100422] [2023-11-29 01:07:21,459 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:21,459 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:21,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:21,463 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:21,465 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:21,467 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:21,468 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:21,468 INFO L85 PathProgramCache]: Analyzing trace with hash -1968736840, now seen corresponding path program 1 times [2023-11-29 01:07:21,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:21,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775471807] [2023-11-29 01:07:21,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:21,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:21,480 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:07:21,512 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:07:21,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:07:21,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1775471807] [2023-11-29 01:07:21,512 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1775471807] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:07:21,512 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:07:21,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:07:21,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1482239643] [2023-11-29 01:07:21,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:07:21,606 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:07:21,606 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:07:21,606 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:07:21,607 INFO L87 Difference]: Start difference. First operand 78562 states and 104051 transitions. cyclomatic complexity: 25535 Second operand has 3 states, 2 states have (on average 47.5) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:22,095 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:07:22,095 INFO L93 Difference]: Finished difference Result 96284 states and 126920 transitions. [2023-11-29 01:07:22,095 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 96284 states and 126920 transitions. [2023-11-29 01:07:22,458 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 88723 [2023-11-29 01:07:22,645 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 96284 states to 96284 states and 126920 transitions. [2023-11-29 01:07:22,645 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 96284 [2023-11-29 01:07:22,689 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 96284 [2023-11-29 01:07:22,689 INFO L73 IsDeterministic]: Start isDeterministic. Operand 96284 states and 126920 transitions. [2023-11-29 01:07:22,726 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:07:22,726 INFO L218 hiAutomatonCegarLoop]: Abstraction has 96284 states and 126920 transitions. [2023-11-29 01:07:22,772 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 96284 states and 126920 transitions. [2023-11-29 01:07:23,513 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 96284 to 96284. [2023-11-29 01:07:23,568 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 96284 states, 96284 states have (on average 1.3181837065348345) internal successors, (126920), 96283 states have internal predecessors, (126920), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:07:23,958 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 96284 states to 96284 states and 126920 transitions. [2023-11-29 01:07:23,958 INFO L240 hiAutomatonCegarLoop]: Abstraction has 96284 states and 126920 transitions. [2023-11-29 01:07:23,959 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:07:23,959 INFO L428 stractBuchiCegarLoop]: Abstraction has 96284 states and 126920 transitions. [2023-11-29 01:07:23,959 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-29 01:07:23,959 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 96284 states and 126920 transitions. [2023-11-29 01:07:24,154 INFO L131 ngComponentsAnalysis]: Automaton has 47 accepting balls. 88723 [2023-11-29 01:07:24,154 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:07:24,154 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:07:24,154 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:24,154 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:07:24,155 INFO L748 eck$LassoCheckResult]: Stem: 903368#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2; 903369#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~7#1;havoc main_~__retres1~7#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1; 903497#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret18#1, start_simulation_#t~ret19#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 903498#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 903519#L401 assume 1 == ~m_i~0;~m_st~0 := 0; 903520#L401-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 903301#L406-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 903302#L411-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 903654#L416-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 903655#L421-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 903599#L426-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 903266#L586 assume !(0 == ~M_E~0); 903267#L586-2 assume !(0 == ~T1_E~0); 903324#L591-1 assume !(0 == ~T2_E~0); 903452#L596-1 assume !(0 == ~T3_E~0); 903453#L601-1 assume !(0 == ~T4_E~0); 903505#L606-1 assume !(0 == ~T5_E~0); 903506#L611-1 assume !(0 == ~E_1~0); 903614#L616-1 assume !(0 == ~E_2~0); 903615#L621-1 assume !(0 == ~E_3~0); 903187#L626-1 assume !(0 == ~E_4~0); 903188#L631-1 assume !(0 == ~E_5~0); 903363#L636-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 903183#L279 assume !(1 == ~m_pc~0); 903184#L279-2 is_master_triggered_~__retres1~0#1 := 0; 903537#L290 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 903335#is_master_triggered_returnLabel#1 activate_threads_#t~ret11#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret11#1;havoc activate_threads_#t~ret11#1; 903336#L720 assume !(0 != activate_threads_~tmp~1#1); 903536#L720-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 903370#L298 assume !(1 == ~t1_pc~0); 903133#L298-2 is_transmit1_triggered_~__retres1~1#1 := 0; 903134#L309 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 903159#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 903160#L728 assume !(0 != activate_threads_~tmp___0~0#1); 903196#L728-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 903329#L317 assume !(1 == ~t2_pc~0); 903330#L317-2 is_transmit2_triggered_~__retres1~2#1 := 0; 903557#L328 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 903502#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 903378#L736 assume !(0 != activate_threads_~tmp___1~0#1); 903379#L736-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 903595#L336 assume !(1 == ~t3_pc~0); 903596#L336-2 is_transmit3_triggered_~__retres1~3#1 := 0; 903697#L347 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 903109#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 903110#L744 assume !(0 != activate_threads_~tmp___2~0#1); 903545#L744-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 903605#L355 assume !(1 == ~t4_pc~0); 903449#L355-2 is_transmit4_triggered_~__retres1~4#1 := 0; 903603#L366 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 903229#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 903230#L752 assume !(0 != activate_threads_~tmp___3~0#1); 903208#L752-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 903209#L374 assume !(1 == ~t5_pc~0); 903353#L374-2 is_transmit5_triggered_~__retres1~5#1 := 0; 903354#L385 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 903341#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 903342#L760 assume !(0 != activate_threads_~tmp___4~0#1); 903486#L760-2 havoc activate_threads_#t~ret11#1, activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 903487#L649 assume !(1 == ~M_E~0); 903690#L649-2 assume !(1 == ~T1_E~0); 903169#L654-1 assume !(1 == ~T2_E~0); 903170#L659-1 assume !(1 == ~T3_E~0); 903377#L664-1 assume !(1 == ~T4_E~0); 903161#L669-1 assume !(1 == ~T5_E~0); 903162#L674-1 assume !(1 == ~E_1~0); 903585#L679-1 assume !(1 == ~E_2~0); 903270#L684-1 assume !(1 == ~E_3~0); 903271#L689-1 assume !(1 == ~E_4~0); 903444#L694-1 assume !(1 == ~E_5~0); 903442#L699-1 assume { :end_inline_reset_delta_events } true; 903443#L900-2 assume !false; 912889#L901 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 912890#L561-1 [2023-11-29 01:07:24,155 INFO L750 eck$LassoCheckResult]: Loop: 912890#L561-1 assume !false; 914279#L482 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;havoc exists_runnable_thread_~__retres1~6#1; 914277#L439 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~6#1 := 1; 914276#L471 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~6#1; 914275#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~6#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 914274#L486 assume 0 != eval_~tmp~0#1; 914272#L486-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 914270#L494 assume !(0 != eval_~tmp_ndt_1~0#1); 914269#L494-2 havoc eval_~tmp_ndt_1~0#1; 914268#L491-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 914266#L508 assume !(0 != eval_~tmp_ndt_2~0#1); 912857#L508-2 havoc eval_~tmp_ndt_2~0#1; 912855#L505-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 912851#L522 assume !(0 != eval_~tmp_ndt_3~0#1); 912852#L522-2 havoc eval_~tmp_ndt_3~0#1; 914256#L519-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 912841#L536 assume !(0 != eval_~tmp_ndt_4~0#1); 912794#L536-2 havoc eval_~tmp_ndt_4~0#1; 912496#L533-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 912497#L550 assume !(0 != eval_~tmp_ndt_5~0#1); 914241#L550-2 havoc eval_~tmp_ndt_5~0#1; 914282#L547-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 914281#L564 assume !(0 != eval_~tmp_ndt_6~0#1); 914280#L564-2 havoc eval_~tmp_ndt_6~0#1; 912890#L561-1 [2023-11-29 01:07:24,155 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:24,155 INFO L85 PathProgramCache]: Analyzing trace with hash 1336547998, now seen corresponding path program 5 times [2023-11-29 01:07:24,156 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:24,156 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [917960361] [2023-11-29 01:07:24,156 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:24,156 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:24,166 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:24,166 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:24,172 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:24,186 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:24,187 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:24,187 INFO L85 PathProgramCache]: Analyzing trace with hash 327523058, now seen corresponding path program 1 times [2023-11-29 01:07:24,187 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:24,188 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151542515] [2023-11-29 01:07:24,188 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:24,188 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:24,191 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:24,192 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:24,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:24,195 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:24,196 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:07:24,196 INFO L85 PathProgramCache]: Analyzing trace with hash 2124476047, now seen corresponding path program 1 times [2023-11-29 01:07:24,196 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:07:24,196 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1207028797] [2023-11-29 01:07:24,196 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:07:24,196 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:07:24,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:24,206 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:24,211 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:24,229 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:07:25,565 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:25,565 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:07:25,587 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:07:25,731 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 29.11 01:07:25 BoogieIcfgContainer [2023-11-29 01:07:25,732 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-29 01:07:25,732 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-29 01:07:25,732 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-29 01:07:25,733 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-29 01:07:25,733 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:07:04" (3/4) ... [2023-11-29 01:07:25,735 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-29 01:07:25,823 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/witness.graphml [2023-11-29 01:07:25,823 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-29 01:07:25,824 INFO L158 Benchmark]: Toolchain (without parser) took 23235.76ms. Allocated memory was 167.8MB in the beginning and 9.2GB in the end (delta: 9.0GB). Free memory was 128.6MB in the beginning and 7.1GB in the end (delta: -7.0GB). Peak memory consumption was 2.0GB. Max. memory is 16.1GB. [2023-11-29 01:07:25,824 INFO L158 Benchmark]: CDTParser took 0.20ms. Allocated memory is still 167.8MB. Free memory is still 141.9MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-29 01:07:25,824 INFO L158 Benchmark]: CACSL2BoogieTranslator took 341.04ms. Allocated memory is still 167.8MB. Free memory was 128.2MB in the beginning and 112.2MB in the end (delta: 16.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-29 01:07:25,824 INFO L158 Benchmark]: Boogie Procedure Inliner took 75.46ms. Allocated memory is still 167.8MB. Free memory was 112.2MB in the beginning and 107.3MB in the end (delta: 4.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. [2023-11-29 01:07:25,825 INFO L158 Benchmark]: Boogie Preprocessor took 101.02ms. Allocated memory is still 167.8MB. Free memory was 107.3MB in the beginning and 101.4MB in the end (delta: 5.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-29 01:07:25,825 INFO L158 Benchmark]: RCFGBuilder took 1087.69ms. Allocated memory was 167.8MB in the beginning and 211.8MB in the end (delta: 44.0MB). Free memory was 101.4MB in the beginning and 150.9MB in the end (delta: -49.5MB). Peak memory consumption was 44.0MB. Max. memory is 16.1GB. [2023-11-29 01:07:25,825 INFO L158 Benchmark]: BuchiAutomizer took 21534.41ms. Allocated memory was 211.8MB in the beginning and 9.2GB in the end (delta: 8.9GB). Free memory was 150.9MB in the beginning and 7.1GB in the end (delta: -7.0GB). Peak memory consumption was 2.0GB. Max. memory is 16.1GB. [2023-11-29 01:07:25,826 INFO L158 Benchmark]: Witness Printer took 90.72ms. Allocated memory is still 9.2GB. Free memory was 7.1GB in the beginning and 7.1GB in the end (delta: 11.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. [2023-11-29 01:07:25,828 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.20ms. Allocated memory is still 167.8MB. Free memory is still 141.9MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 341.04ms. Allocated memory is still 167.8MB. Free memory was 128.2MB in the beginning and 112.2MB in the end (delta: 16.1MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 75.46ms. Allocated memory is still 167.8MB. Free memory was 112.2MB in the beginning and 107.3MB in the end (delta: 4.9MB). Peak memory consumption was 4.2MB. Max. memory is 16.1GB. * Boogie Preprocessor took 101.02ms. Allocated memory is still 167.8MB. Free memory was 107.3MB in the beginning and 101.4MB in the end (delta: 5.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 1087.69ms. Allocated memory was 167.8MB in the beginning and 211.8MB in the end (delta: 44.0MB). Free memory was 101.4MB in the beginning and 150.9MB in the end (delta: -49.5MB). Peak memory consumption was 44.0MB. Max. memory is 16.1GB. * BuchiAutomizer took 21534.41ms. Allocated memory was 211.8MB in the beginning and 9.2GB in the end (delta: 8.9GB). Free memory was 150.9MB in the beginning and 7.1GB in the end (delta: -7.0GB). Peak memory consumption was 2.0GB. Max. memory is 16.1GB. * Witness Printer took 90.72ms. Allocated memory is still 9.2GB. Free memory was 7.1GB in the beginning and 7.1GB in the end (delta: 11.5MB). Peak memory consumption was 10.5MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 25 terminating modules (25 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.25 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 96284 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 21.3s and 26 iterations. TraceHistogramMax:3. Analysis of lassos took 5.3s. Construction of modules took 0.7s. Büchi inclusion checks took 13.6s. Highest rank in rank-based complementation 0. Minimization of det autom 25. Minimization of nondet autom 0. Automata minimization 6.6s AutomataMinimizationTime, 25 MinimizatonAttempts, 33376 StatesRemovedByMinimization, 17 NontrivialMinimizations. Non-live state removal took 3.8s Buchi closure took 0.2s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 18585 SdHoareTripleChecker+Valid, 1.0s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 18585 mSDsluCounter, 35242 SdHoareTripleChecker+Invalid, 0.8s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 15916 mSDsCounter, 295 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 713 IncrementalHoareTripleChecker+Invalid, 1008 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 295 mSolverCounterUnsat, 19326 mSDtfsCounter, 713 mSolverCounterSat, 0.2s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI6 SFLT0 conc4 concLT0 SILN0 SILU0 SILI15 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 481]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L491-L502] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L505-L516] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L519-L530] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L533-L544] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L547-L558] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L561-L572] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 481]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int m_st ; [L32] int t1_st ; [L33] int t2_st ; [L34] int t3_st ; [L35] int t4_st ; [L36] int t5_st ; [L37] int m_i ; [L38] int t1_i ; [L39] int t2_i ; [L40] int t3_i ; [L41] int t4_i ; [L42] int t5_i ; [L43] int M_E = 2; [L44] int T1_E = 2; [L45] int T2_E = 2; [L46] int T3_E = 2; [L47] int T4_E = 2; [L48] int T5_E = 2; [L49] int E_1 = 2; [L50] int E_2 = 2; [L51] int E_3 = 2; [L52] int E_4 = 2; [L53] int E_5 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0] [L945] int __retres1 ; [L949] CALL init_model() [L856] m_i = 1 [L857] t1_i = 1 [L858] t2_i = 1 [L859] t3_i = 1 [L860] t4_i = 1 [L861] t5_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L949] RET init_model() [L950] CALL start_simulation() [L886] int kernel_st ; [L887] int tmp ; [L888] int tmp___0 ; [L892] kernel_st = 0 [L893] FCALL update_channels() [L894] CALL init_threads() [L401] COND TRUE m_i == 1 [L402] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L406] COND TRUE t1_i == 1 [L407] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L411] COND TRUE t2_i == 1 [L412] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L416] COND TRUE t3_i == 1 [L417] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L421] COND TRUE t4_i == 1 [L422] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L426] COND TRUE t5_i == 1 [L427] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L894] RET init_threads() [L895] CALL fire_delta_events() [L586] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L591] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L596] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L601] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L606] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L611] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L616] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L621] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L626] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L631] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L636] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L895] RET fire_delta_events() [L896] CALL activate_threads() [L709] int tmp ; [L710] int tmp___0 ; [L711] int tmp___1 ; [L712] int tmp___2 ; [L713] int tmp___3 ; [L714] int tmp___4 ; [L718] CALL, EXPR is_master_triggered() [L276] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L279] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L289] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L291] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L718] RET, EXPR is_master_triggered() [L718] tmp = is_master_triggered() [L720] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0] [L726] CALL, EXPR is_transmit1_triggered() [L295] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L298] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L308] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L310] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L726] RET, EXPR is_transmit1_triggered() [L726] tmp___0 = is_transmit1_triggered() [L728] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0] [L734] CALL, EXPR is_transmit2_triggered() [L314] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L317] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L327] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L329] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L734] RET, EXPR is_transmit2_triggered() [L734] tmp___1 = is_transmit2_triggered() [L736] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0] [L742] CALL, EXPR is_transmit3_triggered() [L333] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L336] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L346] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L348] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L742] RET, EXPR is_transmit3_triggered() [L742] tmp___2 = is_transmit3_triggered() [L744] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L750] CALL, EXPR is_transmit4_triggered() [L352] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L355] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L365] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L367] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L750] RET, EXPR is_transmit4_triggered() [L750] tmp___3 = is_transmit4_triggered() [L752] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L758] CALL, EXPR is_transmit5_triggered() [L371] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L374] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L384] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L386] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L758] RET, EXPR is_transmit5_triggered() [L758] tmp___4 = is_transmit5_triggered() [L760] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L896] RET activate_threads() [L897] CALL reset_delta_events() [L649] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L654] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L659] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L664] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L669] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L674] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L679] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L684] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L689] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L694] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L699] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L897] RET reset_delta_events() [L900] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] [L903] kernel_st = 1 [L904] CALL eval() [L477] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0] Loop: [L481] COND TRUE 1 [L484] CALL, EXPR exists_runnable_thread() [L436] int __retres1 ; [L439] COND TRUE m_st == 0 [L440] __retres1 = 1 [L472] return (__retres1); [L484] RET, EXPR exists_runnable_thread() [L484] tmp = exists_runnable_thread() [L486] COND TRUE \read(tmp) [L491] COND TRUE m_st == 0 [L492] int tmp_ndt_1; [L493] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L494] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L491-L502] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L505] COND TRUE t1_st == 0 [L506] int tmp_ndt_2; [L507] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L508] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L505-L516] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L519] COND TRUE t2_st == 0 [L520] int tmp_ndt_3; [L521] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L522] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L519-L530] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L533] COND TRUE t3_st == 0 [L534] int tmp_ndt_4; [L535] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L536] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L533-L544] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L547] COND TRUE t4_st == 0 [L548] int tmp_ndt_5; [L549] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L550] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L547-L558] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L561] COND TRUE t5_st == 0 [L562] int tmp_ndt_6; [L563] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L564] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L561-L572] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-29 01:07:26,117 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_89a0dcc6-78be-47e8-8275-9107ecd5d546/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)