./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.06.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.06.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 07:09:36,132 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 07:09:36,204 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 07:09:36,209 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 07:09:36,209 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 07:09:36,237 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 07:09:36,238 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 07:09:36,239 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 07:09:36,239 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 07:09:36,240 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 07:09:36,241 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 07:09:36,241 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 07:09:36,242 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 07:09:36,243 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 07:09:36,243 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 07:09:36,244 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 07:09:36,244 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 07:09:36,245 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 07:09:36,245 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 07:09:36,246 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 07:09:36,246 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 07:09:36,247 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 07:09:36,248 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 07:09:36,248 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 07:09:36,249 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 07:09:36,249 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 07:09:36,250 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 07:09:36,250 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 07:09:36,251 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 07:09:36,251 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 07:09:36,251 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 07:09:36,252 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 07:09:36,252 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 07:09:36,253 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 07:09:36,253 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 07:09:36,253 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 07:09:36,253 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 07:09:36,254 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 07:09:36,254 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> bbfdf3f22061e77485b28b33d06a9820d2c4b7aa22afc378a1743c2d746b69df [2023-11-29 07:09:36,500 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 07:09:36,524 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 07:09:36,527 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 07:09:36,528 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 07:09:36,529 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 07:09:36,530 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/transmitter.06.cil.c [2023-11-29 07:09:39,511 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 07:09:39,722 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 07:09:39,723 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/sv-benchmarks/c/systemc/transmitter.06.cil.c [2023-11-29 07:09:39,741 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/data/9e385f329/415e637df0f845a9954514551e1ca095/FLAG63a2df679 [2023-11-29 07:09:39,756 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/data/9e385f329/415e637df0f845a9954514551e1ca095 [2023-11-29 07:09:39,759 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 07:09:39,761 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 07:09:39,763 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 07:09:39,763 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 07:09:39,768 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 07:09:39,769 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 07:09:39" (1/1) ... [2023-11-29 07:09:39,771 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@90d5dab and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:39, skipping insertion in model container [2023-11-29 07:09:39,771 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 07:09:39" (1/1) ... [2023-11-29 07:09:39,829 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 07:09:40,089 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 07:09:40,108 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 07:09:40,166 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 07:09:40,191 INFO L206 MainTranslator]: Completed translation [2023-11-29 07:09:40,191 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40 WrapperNode [2023-11-29 07:09:40,192 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 07:09:40,193 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 07:09:40,193 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 07:09:40,193 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 07:09:40,202 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,215 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,268 INFO L138 Inliner]: procedures = 40, calls = 49, calls flagged for inlining = 44, calls inlined = 105, statements flattened = 1536 [2023-11-29 07:09:40,269 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 07:09:40,270 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 07:09:40,270 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 07:09:40,270 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 07:09:40,281 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,281 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,292 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,320 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 07:09:40,320 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,321 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,347 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,369 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,374 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,381 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,390 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 07:09:40,391 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 07:09:40,392 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 07:09:40,392 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 07:09:40,393 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (1/1) ... [2023-11-29 07:09:40,400 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 07:09:40,416 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 07:09:40,430 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 07:09:40,441 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 07:09:40,474 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 07:09:40,475 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 07:09:40,475 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 07:09:40,475 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 07:09:40,584 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 07:09:40,586 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 07:09:41,660 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 07:09:41,686 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 07:09:41,686 INFO L309 CfgBuilder]: Removed 10 assume(true) statements. [2023-11-29 07:09:41,688 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 07:09:41 BoogieIcfgContainer [2023-11-29 07:09:41,689 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 07:09:41,690 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 07:09:41,690 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 07:09:41,694 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 07:09:41,695 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 07:09:41,695 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 07:09:39" (1/3) ... [2023-11-29 07:09:41,697 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41deb80b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 07:09:41, skipping insertion in model container [2023-11-29 07:09:41,697 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 07:09:41,697 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 07:09:40" (2/3) ... [2023-11-29 07:09:41,697 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@41deb80b and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 07:09:41, skipping insertion in model container [2023-11-29 07:09:41,698 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 07:09:41,698 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 07:09:41" (3/3) ... [2023-11-29 07:09:41,699 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.06.cil.c [2023-11-29 07:09:41,775 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 07:09:41,775 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 07:09:41,776 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 07:09:41,776 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 07:09:41,776 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 07:09:41,776 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 07:09:41,776 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 07:09:41,776 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 07:09:41,785 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 641 states, 640 states have (on average 1.521875) internal successors, (974), 640 states have internal predecessors, (974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:41,833 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 548 [2023-11-29 07:09:41,834 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:41,834 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:41,845 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:41,846 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:41,846 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 07:09:41,848 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 641 states, 640 states have (on average 1.521875) internal successors, (974), 640 states have internal predecessors, (974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:41,861 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 548 [2023-11-29 07:09:41,861 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:41,861 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:41,866 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:41,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:41,876 INFO L748 eck$LassoCheckResult]: Stem: 183#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 525#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 291#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 521#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2#L461true assume !(1 == ~m_i~0);~m_st~0 := 2; 350#L461-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 565#L466-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 617#L471-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 43#L476-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 277#L481-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 136#L486-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 51#L491-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 536#L670true assume !(0 == ~M_E~0); 306#L670-2true assume !(0 == ~T1_E~0); 255#L675-1true assume !(0 == ~T2_E~0); 349#L680-1true assume !(0 == ~T3_E~0); 445#L685-1true assume !(0 == ~T4_E~0); 313#L690-1true assume !(0 == ~T5_E~0); 616#L695-1true assume !(0 == ~T6_E~0); 395#L700-1true assume 0 == ~E_1~0;~E_1~0 := 1; 382#L705-1true assume !(0 == ~E_2~0); 557#L710-1true assume !(0 == ~E_3~0); 253#L715-1true assume !(0 == ~E_4~0); 199#L720-1true assume !(0 == ~E_5~0); 240#L725-1true assume !(0 == ~E_6~0); 281#L730-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 415#L320true assume 1 == ~m_pc~0; 229#L321true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 162#L331true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 158#is_master_triggered_returnLabel#1true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 137#L825true assume !(0 != activate_threads_~tmp~1#1); 460#L825-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 140#L339true assume !(1 == ~t1_pc~0); 432#L339-2true is_transmit1_triggered_~__retres1~1#1 := 0; 122#L350true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 54#L833true assume !(0 != activate_threads_~tmp___0~0#1); 550#L833-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13#L358true assume 1 == ~t2_pc~0; 595#L359true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 519#L369true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 293#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 243#L841true assume !(0 != activate_threads_~tmp___1~0#1); 134#L841-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 465#L377true assume !(1 == ~t3_pc~0); 330#L377-2true is_transmit3_triggered_~__retres1~3#1 := 0; 341#L388true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 139#L849true assume !(0 != activate_threads_~tmp___2~0#1); 346#L849-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96#L396true assume 1 == ~t4_pc~0; 457#L397true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 14#L407true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 268#L857true assume !(0 != activate_threads_~tmp___3~0#1); 79#L857-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 125#L415true assume 1 == ~t5_pc~0; 334#L416true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 282#L426true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 164#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 435#L865true assume !(0 != activate_threads_~tmp___4~0#1); 32#L865-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 331#L434true assume !(1 == ~t6_pc~0); 220#L434-2true is_transmit6_triggered_~__retres1~6#1 := 0; 361#L445true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 286#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 362#L873true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 146#L873-2true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 548#L743true assume !(1 == ~M_E~0); 73#L743-2true assume !(1 == ~T1_E~0); 496#L748-1true assume !(1 == ~T2_E~0); 274#L753-1true assume !(1 == ~T3_E~0); 399#L758-1true assume 1 == ~T4_E~0;~T4_E~0 := 2; 472#L763-1true assume !(1 == ~T5_E~0); 561#L768-1true assume !(1 == ~T6_E~0); 143#L773-1true assume !(1 == ~E_1~0); 629#L778-1true assume !(1 == ~E_2~0); 131#L783-1true assume !(1 == ~E_3~0); 605#L788-1true assume !(1 == ~E_4~0); 347#L793-1true assume !(1 == ~E_5~0); 300#L798-1true assume 1 == ~E_6~0;~E_6~0 := 2; 63#L803-1true assume { :end_inline_reset_delta_events } true; 246#L1024-2true [2023-11-29 07:09:41,879 INFO L750 eck$LassoCheckResult]: Loop: 246#L1024-2true assume !false; 483#L1025true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 128#L645-1true assume !true; 91#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 447#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 58#L670-3true assume 0 == ~M_E~0;~M_E~0 := 1; 235#L670-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 159#L675-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 438#L680-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 344#L685-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 611#L690-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 567#L695-3true assume !(0 == ~T6_E~0); 355#L700-3true assume 0 == ~E_1~0;~E_1~0 := 1; 638#L705-3true assume 0 == ~E_2~0;~E_2~0 := 1; 86#L710-3true assume 0 == ~E_3~0;~E_3~0 := 1; 390#L715-3true assume 0 == ~E_4~0;~E_4~0 := 1; 244#L720-3true assume 0 == ~E_5~0;~E_5~0 := 1; 314#L725-3true assume 0 == ~E_6~0;~E_6~0 := 1; 506#L730-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 144#L320-21true assume 1 == ~m_pc~0; 470#L321-7true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 543#L331-7true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 112#is_master_triggered_returnLabel#8true activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 486#L825-21true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 454#L825-23true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 94#L339-21true assume 1 == ~t1_pc~0; 169#L340-7true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 626#L350-7true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77#is_transmit1_triggered_returnLabel#8true activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 24#L833-21true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 70#L833-23true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 587#L358-21true assume !(1 == ~t2_pc~0); 100#L358-23true is_transmit2_triggered_~__retres1~2#1 := 0; 64#L369-7true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198#is_transmit2_triggered_returnLabel#8true activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 405#L841-21true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80#L841-23true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 477#L377-21true assume 1 == ~t3_pc~0; 570#L378-7true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 267#L388-7true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 542#is_transmit3_triggered_returnLabel#8true activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 288#L849-21true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 178#L849-23true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 301#L396-21true assume !(1 == ~t4_pc~0); 190#L396-23true is_transmit4_triggered_~__retres1~4#1 := 0; 230#L407-7true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 499#is_transmit4_triggered_returnLabel#8true activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16#L857-21true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 303#L857-23true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 160#L415-21true assume 1 == ~t5_pc~0; 516#L416-7true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 437#L426-7true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 272#is_transmit5_triggered_returnLabel#8true activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 225#L865-21true assume !(0 != activate_threads_~tmp___4~0#1); 202#L865-23true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 383#L434-21true assume !(1 == ~t6_pc~0); 28#L434-23true is_transmit6_triggered_~__retres1~6#1 := 0; 431#L445-7true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 252#is_transmit6_triggered_returnLabel#8true activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 155#L873-21true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 260#L873-23true havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 151#L743-3true assume 1 == ~M_E~0;~M_E~0 := 2; 502#L743-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 564#L748-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 261#L753-3true assume !(1 == ~T3_E~0); 214#L758-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 172#L763-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 533#L768-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 478#L773-3true assume 1 == ~E_1~0;~E_1~0 := 2; 110#L778-3true assume 1 == ~E_2~0;~E_2~0 := 2; 265#L783-3true assume 1 == ~E_3~0;~E_3~0 := 2; 580#L788-3true assume 1 == ~E_4~0;~E_4~0 := 2; 528#L793-3true assume !(1 == ~E_5~0); 541#L798-3true assume 1 == ~E_6~0;~E_6~0 := 2; 304#L803-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 104#L504-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 401#L541-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 264#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 448#L1043true assume !(0 == start_simulation_~tmp~3#1); 443#L1043-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 262#L504-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 333#L541-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 41#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 234#L998true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57#L1005true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 466#stop_simulation_returnLabel#1true start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 224#L1056true assume !(0 != start_simulation_~tmp___0~1#1); 246#L1024-2true [2023-11-29 07:09:41,885 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:41,886 INFO L85 PathProgramCache]: Analyzing trace with hash -1010496615, now seen corresponding path program 1 times [2023-11-29 07:09:41,897 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:41,897 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [321375153] [2023-11-29 07:09:41,898 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:41,898 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:42,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:42,186 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:42,187 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:42,187 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [321375153] [2023-11-29 07:09:42,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [321375153] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:42,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:42,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:42,190 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1708720407] [2023-11-29 07:09:42,191 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:42,196 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:42,197 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:42,197 INFO L85 PathProgramCache]: Analyzing trace with hash -1655056166, now seen corresponding path program 1 times [2023-11-29 07:09:42,197 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:42,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1667934032] [2023-11-29 07:09:42,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:42,198 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:42,215 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:42,274 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:42,274 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:42,274 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1667934032] [2023-11-29 07:09:42,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1667934032] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:42,275 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:42,275 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 07:09:42,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1052183531] [2023-11-29 07:09:42,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:42,277 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:42,278 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:42,313 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:42,313 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:42,317 INFO L87 Difference]: Start difference. First operand has 641 states, 640 states have (on average 1.521875) internal successors, (974), 640 states have internal predecessors, (974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:42,384 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:42,385 INFO L93 Difference]: Finished difference Result 639 states and 950 transitions. [2023-11-29 07:09:42,386 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 639 states and 950 transitions. [2023-11-29 07:09:42,395 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:42,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 639 states to 633 states and 944 transitions. [2023-11-29 07:09:42,408 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-29 07:09:42,410 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-29 07:09:42,411 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 944 transitions. [2023-11-29 07:09:42,416 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:42,416 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 944 transitions. [2023-11-29 07:09:42,439 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 944 transitions. [2023-11-29 07:09:42,478 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-29 07:09:42,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4913112164296998) internal successors, (944), 632 states have internal predecessors, (944), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:42,484 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 944 transitions. [2023-11-29 07:09:42,486 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 944 transitions. [2023-11-29 07:09:42,487 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:42,491 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 944 transitions. [2023-11-29 07:09:42,492 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 07:09:42,492 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 944 transitions. [2023-11-29 07:09:42,498 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:42,498 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:42,498 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:42,501 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:42,502 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:42,502 INFO L748 eck$LassoCheckResult]: Stem: 1630#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1631#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1760#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1761#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1289#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1290#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1816#L466-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1914#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1387#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1388#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1552#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1401#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1402#L670 assume !(0 == ~M_E~0); 1772#L670-2 assume !(0 == ~T1_E~0); 1725#L675-1 assume !(0 == ~T2_E~0); 1726#L680-1 assume !(0 == ~T3_E~0); 1814#L685-1 assume !(0 == ~T4_E~0); 1779#L690-1 assume !(0 == ~T5_E~0); 1780#L695-1 assume !(0 == ~T6_E~0); 1851#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 1840#L705-1 assume !(0 == ~E_2~0); 1841#L710-1 assume !(0 == ~E_3~0); 1724#L715-1 assume !(0 == ~E_4~0); 1656#L720-1 assume !(0 == ~E_5~0); 1657#L725-1 assume !(0 == ~E_6~0); 1704#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1749#L320 assume 1 == ~m_pc~0; 1697#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1599#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1593#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1553#L825 assume !(0 != activate_threads_~tmp~1#1); 1554#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1558#L339 assume !(1 == ~t1_pc~0); 1559#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1528#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1383#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1384#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1406#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1315#L358 assume 1 == ~t2_pc~0; 1316#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1833#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1763#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1707#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1548#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1549#L377 assume !(1 == ~t3_pc~0); 1798#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1799#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1311#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1312#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1557#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1483#L396 assume 1 == ~t4_pc~0; 1484#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1318#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1319#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1465#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1450#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1451#L415 assume 1 == ~t5_pc~0; 1533#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1588#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1603#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1604#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1359#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1360#L434 assume !(1 == ~t6_pc~0); 1685#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1686#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1754#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1755#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1572#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1573#L743 assume !(1 == ~M_E~0); 1442#L743-2 assume !(1 == ~T1_E~0); 1443#L748-1 assume !(1 == ~T2_E~0); 1745#L753-1 assume !(1 == ~T3_E~0); 1746#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1854#L763-1 assume !(1 == ~T5_E~0); 1886#L768-1 assume !(1 == ~T6_E~0); 1567#L773-1 assume !(1 == ~E_1~0); 1568#L778-1 assume !(1 == ~E_2~0); 1543#L783-1 assume !(1 == ~E_3~0); 1544#L788-1 assume !(1 == ~E_4~0); 1812#L793-1 assume !(1 == ~E_5~0); 1768#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1423#L803-1 assume { :end_inline_reset_delta_events } true; 1424#L1024-2 [2023-11-29 07:09:42,503 INFO L750 eck$LassoCheckResult]: Loop: 1424#L1024-2 assume !false; 1712#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1297#L645-1 assume !false; 1538#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1653#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1367#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1786#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1787#L556 assume !(0 != eval_~tmp~0#1); 1474#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1475#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1417#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1418#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1596#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1597#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1809#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1810#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1915#L695-3 assume !(0 == ~T6_E~0); 1818#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1819#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1463#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1464#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1708#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1709#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1781#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1569#L320-21 assume !(1 == ~m_pc~0); 1570#L320-23 is_master_triggered_~__retres1~0#1 := 0; 1706#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1513#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1514#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1876#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1478#L339-21 assume 1 == ~t1_pc~0; 1479#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1609#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1447#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1343#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1344#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1440#L358-21 assume !(1 == ~t2_pc~0); 1492#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 1425#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1426#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1654#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1452#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1453#L377-21 assume 1 == ~t3_pc~0; 1888#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1737#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1738#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1756#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1620#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1621#L396-21 assume !(1 == ~t4_pc~0); 1640#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 1641#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1696#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1325#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1326#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1594#L415-21 assume 1 == ~t5_pc~0; 1595#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1566#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1744#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1690#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 1659#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1660#L434-21 assume !(1 == ~t6_pc~0); 1348#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 1349#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1723#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1589#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1590#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1582#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1583#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1898#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1731#L753-3 assume !(1 == ~T3_E~0); 1675#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1611#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1612#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1889#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 1507#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1508#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1736#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1906#L793-3 assume !(1 == ~E_5~0); 1907#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1771#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1498#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1395#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1734#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 1735#L1043 assume !(0 == start_simulation_~tmp~3#1); 1869#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1732#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1516#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1381#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 1382#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1411#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1412#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 1689#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 1424#L1024-2 [2023-11-29 07:09:42,504 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:42,504 INFO L85 PathProgramCache]: Analyzing trace with hash -1849530277, now seen corresponding path program 1 times [2023-11-29 07:09:42,504 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:42,505 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [685258728] [2023-11-29 07:09:42,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:42,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:42,526 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:42,589 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:42,590 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:42,590 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [685258728] [2023-11-29 07:09:42,590 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [685258728] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:42,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:42,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:42,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39160970] [2023-11-29 07:09:42,591 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:42,592 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:42,593 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:42,593 INFO L85 PathProgramCache]: Analyzing trace with hash -721591099, now seen corresponding path program 1 times [2023-11-29 07:09:42,593 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:42,593 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1619672109] [2023-11-29 07:09:42,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:42,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:42,623 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:42,696 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:42,696 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:42,697 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1619672109] [2023-11-29 07:09:42,697 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1619672109] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:42,697 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:42,697 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:42,697 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [447615442] [2023-11-29 07:09:42,698 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:42,698 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:42,698 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:42,699 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:42,699 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:42,699 INFO L87 Difference]: Start difference. First operand 633 states and 944 transitions. cyclomatic complexity: 312 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:42,725 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:42,725 INFO L93 Difference]: Finished difference Result 633 states and 943 transitions. [2023-11-29 07:09:42,725 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 943 transitions. [2023-11-29 07:09:42,733 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:42,739 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 943 transitions. [2023-11-29 07:09:42,739 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-29 07:09:42,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-29 07:09:42,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 943 transitions. [2023-11-29 07:09:42,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:42,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 943 transitions. [2023-11-29 07:09:42,744 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 943 transitions. [2023-11-29 07:09:42,755 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-29 07:09:42,757 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4897314375987363) internal successors, (943), 632 states have internal predecessors, (943), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:42,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 943 transitions. [2023-11-29 07:09:42,760 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 943 transitions. [2023-11-29 07:09:42,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:42,762 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 943 transitions. [2023-11-29 07:09:42,762 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 07:09:42,762 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 943 transitions. [2023-11-29 07:09:42,767 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:42,767 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:42,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:42,770 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:42,770 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:42,770 INFO L748 eck$LassoCheckResult]: Stem: 2905#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 2906#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 3033#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3034#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2562#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 2563#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3089#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3187#L471-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2660#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2661#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2825#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2675#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2676#L670 assume !(0 == ~M_E~0); 3047#L670-2 assume !(0 == ~T1_E~0); 2998#L675-1 assume !(0 == ~T2_E~0); 2999#L680-1 assume !(0 == ~T3_E~0); 3087#L685-1 assume !(0 == ~T4_E~0); 3053#L690-1 assume !(0 == ~T5_E~0); 3054#L695-1 assume !(0 == ~T6_E~0); 3124#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3113#L705-1 assume !(0 == ~E_2~0); 3114#L710-1 assume !(0 == ~E_3~0); 2997#L715-1 assume !(0 == ~E_4~0); 2929#L720-1 assume !(0 == ~E_5~0); 2930#L725-1 assume !(0 == ~E_6~0); 2977#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3022#L320 assume 1 == ~m_pc~0; 2970#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2872#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2866#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2826#L825 assume !(0 != activate_threads_~tmp~1#1); 2827#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2835#L339 assume !(1 == ~t1_pc~0); 2836#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2801#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2656#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2657#L833 assume !(0 != activate_threads_~tmp___0~0#1); 2679#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2588#L358 assume 1 == ~t2_pc~0; 2589#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3106#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3036#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2980#L841 assume !(0 != activate_threads_~tmp___1~0#1); 2821#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2822#L377 assume !(1 == ~t3_pc~0); 3071#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3072#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2586#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2587#L849 assume !(0 != activate_threads_~tmp___2~0#1); 2830#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2758#L396 assume 1 == ~t4_pc~0; 2759#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2591#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2592#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2738#L857 assume !(0 != activate_threads_~tmp___3~0#1); 2723#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2724#L415 assume 1 == ~t5_pc~0; 2808#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2861#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2879#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2880#L865 assume !(0 != activate_threads_~tmp___4~0#1); 2632#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2633#L434 assume !(1 == ~t6_pc~0); 2959#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2960#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3027#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3028#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2845#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2846#L743 assume !(1 == ~M_E~0); 2715#L743-2 assume !(1 == ~T1_E~0); 2716#L748-1 assume !(1 == ~T2_E~0); 3018#L753-1 assume !(1 == ~T3_E~0); 3019#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3127#L763-1 assume !(1 == ~T5_E~0); 3159#L768-1 assume !(1 == ~T6_E~0); 2843#L773-1 assume !(1 == ~E_1~0); 2844#L778-1 assume !(1 == ~E_2~0); 2816#L783-1 assume !(1 == ~E_3~0); 2817#L788-1 assume !(1 == ~E_4~0); 3085#L793-1 assume !(1 == ~E_5~0); 3041#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 2698#L803-1 assume { :end_inline_reset_delta_events } true; 2699#L1024-2 [2023-11-29 07:09:42,771 INFO L750 eck$LassoCheckResult]: Loop: 2699#L1024-2 assume !false; 2985#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2570#L645-1 assume !false; 2813#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2926#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2640#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3059#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3060#L556 assume !(0 != eval_~tmp~0#1); 2747#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2748#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2692#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2693#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2867#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2868#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3082#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3083#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3188#L695-3 assume !(0 == ~T6_E~0); 3090#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3091#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2736#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2737#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2981#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2982#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3052#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2838#L320-21 assume !(1 == ~m_pc~0); 2839#L320-23 is_master_triggered_~__retres1~0#1 := 0; 2979#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2786#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 2787#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3148#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2751#L339-21 assume 1 == ~t1_pc~0; 2752#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2881#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2720#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2616#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2617#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2713#L358-21 assume 1 == ~t2_pc~0; 2834#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2696#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2697#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2927#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2725#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2726#L377-21 assume 1 == ~t3_pc~0; 3161#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3012#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3013#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3029#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2893#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2894#L396-21 assume !(1 == ~t4_pc~0); 2913#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 2914#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2969#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2598#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2599#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2869#L415-21 assume 1 == ~t5_pc~0; 2870#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2842#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3017#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2963#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 2932#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2933#L434-21 assume 1 == ~t6_pc~0; 2942#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2624#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2996#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2862#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2863#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2855#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2856#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3171#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3004#L753-3 assume !(1 == ~T3_E~0); 2948#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2884#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2885#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3162#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2780#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2781#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3009#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3179#L793-3 assume !(1 == ~E_5~0); 3180#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3044#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 2771#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2668#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3007#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 3008#L1043 assume !(0 == start_simulation_~tmp~3#1); 3142#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 3005#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 2790#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 2654#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 2655#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2684#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2685#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 2962#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 2699#L1024-2 [2023-11-29 07:09:42,772 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:42,772 INFO L85 PathProgramCache]: Analyzing trace with hash 227806621, now seen corresponding path program 1 times [2023-11-29 07:09:42,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:42,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [106226986] [2023-11-29 07:09:42,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:42,773 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:42,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:42,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:42,829 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:42,829 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [106226986] [2023-11-29 07:09:42,829 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [106226986] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:42,829 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:42,830 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:42,830 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1597457659] [2023-11-29 07:09:42,830 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:42,830 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:42,831 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:42,831 INFO L85 PathProgramCache]: Analyzing trace with hash -1648316281, now seen corresponding path program 1 times [2023-11-29 07:09:42,831 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:42,832 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1446839253] [2023-11-29 07:09:42,832 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:42,832 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:42,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:42,902 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:42,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:42,902 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1446839253] [2023-11-29 07:09:42,902 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1446839253] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:42,903 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:42,903 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:42,903 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [879141634] [2023-11-29 07:09:42,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:42,904 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:42,904 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:42,904 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:42,904 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:42,905 INFO L87 Difference]: Start difference. First operand 633 states and 943 transitions. cyclomatic complexity: 311 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:42,929 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:42,929 INFO L93 Difference]: Finished difference Result 633 states and 942 transitions. [2023-11-29 07:09:42,929 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 942 transitions. [2023-11-29 07:09:42,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:42,942 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 942 transitions. [2023-11-29 07:09:42,942 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-29 07:09:42,943 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-29 07:09:42,943 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 942 transitions. [2023-11-29 07:09:42,945 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:42,945 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 942 transitions. [2023-11-29 07:09:42,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 942 transitions. [2023-11-29 07:09:42,955 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-29 07:09:42,957 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4881516587677726) internal successors, (942), 632 states have internal predecessors, (942), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:42,960 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 942 transitions. [2023-11-29 07:09:42,960 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 942 transitions. [2023-11-29 07:09:42,961 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:42,962 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 942 transitions. [2023-11-29 07:09:42,962 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 07:09:42,962 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 942 transitions. [2023-11-29 07:09:42,967 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:42,967 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:42,967 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:42,969 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:42,969 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:42,970 INFO L748 eck$LassoCheckResult]: Stem: 4173#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 4174#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 4306#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4307#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3835#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 3836#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4361#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4460#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3931#L476-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3932#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4098#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3947#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3948#L670 assume !(0 == ~M_E~0); 4318#L670-2 assume !(0 == ~T1_E~0); 4271#L675-1 assume !(0 == ~T2_E~0); 4272#L680-1 assume !(0 == ~T3_E~0); 4360#L685-1 assume !(0 == ~T4_E~0); 4325#L690-1 assume !(0 == ~T5_E~0); 4326#L695-1 assume !(0 == ~T6_E~0); 4397#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 4386#L705-1 assume !(0 == ~E_2~0); 4387#L710-1 assume !(0 == ~E_3~0); 4270#L715-1 assume !(0 == ~E_4~0); 4201#L720-1 assume !(0 == ~E_5~0); 4202#L725-1 assume !(0 == ~E_6~0); 4250#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4295#L320 assume 1 == ~m_pc~0; 4242#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4145#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4139#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4099#L825 assume !(0 != activate_threads_~tmp~1#1); 4100#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4104#L339 assume !(1 == ~t1_pc~0); 4105#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4074#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3929#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3930#L833 assume !(0 != activate_threads_~tmp___0~0#1); 3952#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3861#L358 assume 1 == ~t2_pc~0; 3862#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4379#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4309#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4253#L841 assume !(0 != activate_threads_~tmp___1~0#1); 4094#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4095#L377 assume !(1 == ~t3_pc~0); 4344#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4345#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3857#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3858#L849 assume !(0 != activate_threads_~tmp___2~0#1); 4103#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4029#L396 assume 1 == ~t4_pc~0; 4030#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3864#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3865#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4011#L857 assume !(0 != activate_threads_~tmp___3~0#1); 3996#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3997#L415 assume 1 == ~t5_pc~0; 4079#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4130#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4148#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4149#L865 assume !(0 != activate_threads_~tmp___4~0#1); 3905#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3906#L434 assume !(1 == ~t6_pc~0); 4231#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4232#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4300#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4301#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4118#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4119#L743 assume !(1 == ~M_E~0); 3988#L743-2 assume !(1 == ~T1_E~0); 3989#L748-1 assume !(1 == ~T2_E~0); 4291#L753-1 assume !(1 == ~T3_E~0); 4292#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4400#L763-1 assume !(1 == ~T5_E~0); 4432#L768-1 assume !(1 == ~T6_E~0); 4111#L773-1 assume !(1 == ~E_1~0); 4112#L778-1 assume !(1 == ~E_2~0); 4089#L783-1 assume !(1 == ~E_3~0); 4090#L788-1 assume !(1 == ~E_4~0); 4358#L793-1 assume !(1 == ~E_5~0); 4314#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3969#L803-1 assume { :end_inline_reset_delta_events } true; 3970#L1024-2 [2023-11-29 07:09:42,970 INFO L750 eck$LassoCheckResult]: Loop: 3970#L1024-2 assume !false; 4258#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3843#L645-1 assume !false; 4084#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4199#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3913#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4332#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4333#L556 assume !(0 != eval_~tmp~0#1); 4018#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4019#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3959#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3960#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4140#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4141#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4355#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4356#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4461#L695-3 assume !(0 == ~T6_E~0); 4363#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4364#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4009#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4010#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4254#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4255#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4327#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4113#L320-21 assume !(1 == ~m_pc~0); 4114#L320-23 is_master_triggered_~__retres1~0#1 := 0; 4252#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4059#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 4060#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4421#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4024#L339-21 assume 1 == ~t1_pc~0; 4025#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4155#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3993#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3889#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3890#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3986#L358-21 assume !(1 == ~t2_pc~0); 4038#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 3971#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3972#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4200#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3998#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3999#L377-21 assume 1 == ~t3_pc~0; 4434#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4285#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4286#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4302#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4166#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4167#L396-21 assume !(1 == ~t4_pc~0); 4186#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 4187#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4244#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3871#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3872#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4142#L415-21 assume !(1 == ~t5_pc~0); 4116#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 4117#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4290#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4236#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 4205#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4206#L434-21 assume 1 == ~t6_pc~0; 4215#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3897#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4269#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4135#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4136#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4128#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4129#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4444#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4277#L753-3 assume !(1 == ~T3_E~0); 4221#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4157#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4158#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4435#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4053#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4054#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4282#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4452#L793-3 assume !(1 == ~E_5~0); 4453#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4317#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4044#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 3941#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 4280#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 4281#L1043 assume !(0 == start_simulation_~tmp~3#1); 4415#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 4278#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 4063#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 3927#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 3928#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3957#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3958#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 4235#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 3970#L1024-2 [2023-11-29 07:09:42,971 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:42,971 INFO L85 PathProgramCache]: Analyzing trace with hash -1506297829, now seen corresponding path program 1 times [2023-11-29 07:09:42,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:42,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [440453101] [2023-11-29 07:09:42,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:42,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:42,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:43,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:43,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:43,020 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [440453101] [2023-11-29 07:09:43,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [440453101] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:43,021 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:43,021 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:43,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485946749] [2023-11-29 07:09:43,022 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:43,022 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:43,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:43,023 INFO L85 PathProgramCache]: Analyzing trace with hash -1117245051, now seen corresponding path program 1 times [2023-11-29 07:09:43,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:43,023 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079958686] [2023-11-29 07:09:43,023 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:43,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:43,040 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:43,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:43,085 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:43,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2079958686] [2023-11-29 07:09:43,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2079958686] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:43,086 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:43,086 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:43,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [185364539] [2023-11-29 07:09:43,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:43,087 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:43,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:43,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:43,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:43,089 INFO L87 Difference]: Start difference. First operand 633 states and 942 transitions. cyclomatic complexity: 310 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:43,125 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:43,125 INFO L93 Difference]: Finished difference Result 633 states and 941 transitions. [2023-11-29 07:09:43,125 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 941 transitions. [2023-11-29 07:09:43,131 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:43,137 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 941 transitions. [2023-11-29 07:09:43,138 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-29 07:09:43,139 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-29 07:09:43,139 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 941 transitions. [2023-11-29 07:09:43,140 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:43,140 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 941 transitions. [2023-11-29 07:09:43,141 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 941 transitions. [2023-11-29 07:09:43,150 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-29 07:09:43,152 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4865718799368088) internal successors, (941), 632 states have internal predecessors, (941), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:43,155 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 941 transitions. [2023-11-29 07:09:43,156 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 941 transitions. [2023-11-29 07:09:43,156 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:43,157 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 941 transitions. [2023-11-29 07:09:43,157 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 07:09:43,157 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 941 transitions. [2023-11-29 07:09:43,162 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:43,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:43,163 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:43,164 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:43,164 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:43,165 INFO L748 eck$LassoCheckResult]: Stem: 5446#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 5447#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 5579#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5580#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5108#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 5109#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5634#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5733#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5204#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5205#L481-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5371#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5220#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5221#L670 assume !(0 == ~M_E~0); 5591#L670-2 assume !(0 == ~T1_E~0); 5544#L675-1 assume !(0 == ~T2_E~0); 5545#L680-1 assume !(0 == ~T3_E~0); 5633#L685-1 assume !(0 == ~T4_E~0); 5598#L690-1 assume !(0 == ~T5_E~0); 5599#L695-1 assume !(0 == ~T6_E~0); 5670#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 5659#L705-1 assume !(0 == ~E_2~0); 5660#L710-1 assume !(0 == ~E_3~0); 5543#L715-1 assume !(0 == ~E_4~0); 5474#L720-1 assume !(0 == ~E_5~0); 5475#L725-1 assume !(0 == ~E_6~0); 5523#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5568#L320 assume 1 == ~m_pc~0; 5515#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5418#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5412#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5372#L825 assume !(0 != activate_threads_~tmp~1#1); 5373#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5377#L339 assume !(1 == ~t1_pc~0); 5378#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5347#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5202#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5203#L833 assume !(0 != activate_threads_~tmp___0~0#1); 5225#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5134#L358 assume 1 == ~t2_pc~0; 5135#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5652#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5582#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5526#L841 assume !(0 != activate_threads_~tmp___1~0#1); 5367#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5368#L377 assume !(1 == ~t3_pc~0); 5617#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5618#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5130#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5131#L849 assume !(0 != activate_threads_~tmp___2~0#1); 5376#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5302#L396 assume 1 == ~t4_pc~0; 5303#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5137#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5138#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5284#L857 assume !(0 != activate_threads_~tmp___3~0#1); 5269#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5270#L415 assume 1 == ~t5_pc~0; 5352#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5403#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5421#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5422#L865 assume !(0 != activate_threads_~tmp___4~0#1); 5178#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5179#L434 assume !(1 == ~t6_pc~0); 5504#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5505#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5573#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5574#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5391#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5392#L743 assume !(1 == ~M_E~0); 5261#L743-2 assume !(1 == ~T1_E~0); 5262#L748-1 assume !(1 == ~T2_E~0); 5564#L753-1 assume !(1 == ~T3_E~0); 5565#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5673#L763-1 assume !(1 == ~T5_E~0); 5705#L768-1 assume !(1 == ~T6_E~0); 5384#L773-1 assume !(1 == ~E_1~0); 5385#L778-1 assume !(1 == ~E_2~0); 5362#L783-1 assume !(1 == ~E_3~0); 5363#L788-1 assume !(1 == ~E_4~0); 5631#L793-1 assume !(1 == ~E_5~0); 5587#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5242#L803-1 assume { :end_inline_reset_delta_events } true; 5243#L1024-2 [2023-11-29 07:09:43,166 INFO L750 eck$LassoCheckResult]: Loop: 5243#L1024-2 assume !false; 5531#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5116#L645-1 assume !false; 5357#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5472#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5186#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5605#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5606#L556 assume !(0 != eval_~tmp~0#1); 5291#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5292#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5232#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5233#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5413#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 5414#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5628#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5629#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5734#L695-3 assume !(0 == ~T6_E~0); 5636#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5637#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5282#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5283#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5527#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5528#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 5600#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5386#L320-21 assume !(1 == ~m_pc~0); 5387#L320-23 is_master_triggered_~__retres1~0#1 := 0; 5525#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5332#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 5333#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5694#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5297#L339-21 assume 1 == ~t1_pc~0; 5298#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5428#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5266#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5162#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5163#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5259#L358-21 assume 1 == ~t2_pc~0; 5383#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5244#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5245#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5473#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5271#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5272#L377-21 assume 1 == ~t3_pc~0; 5707#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5558#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5559#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5575#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5439#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5440#L396-21 assume !(1 == ~t4_pc~0); 5459#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 5460#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5517#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5144#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5145#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5415#L415-21 assume 1 == ~t5_pc~0; 5416#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5390#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5563#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5509#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 5478#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5479#L434-21 assume 1 == ~t6_pc~0; 5488#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5170#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5542#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5408#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5409#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5401#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5402#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5717#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5550#L753-3 assume !(1 == ~T3_E~0); 5494#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5430#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5431#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5708#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5326#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5327#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5555#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5725#L793-3 assume !(1 == ~E_5~0); 5726#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5590#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5317#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5214#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5553#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 5554#L1043 assume !(0 == start_simulation_~tmp~3#1); 5688#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 5551#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 5336#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 5200#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 5201#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5230#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5231#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 5508#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 5243#L1024-2 [2023-11-29 07:09:43,166 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:43,166 INFO L85 PathProgramCache]: Analyzing trace with hash 1901446621, now seen corresponding path program 1 times [2023-11-29 07:09:43,167 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:43,167 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1093033899] [2023-11-29 07:09:43,167 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:43,167 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:43,181 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:43,211 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:43,211 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:43,212 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1093033899] [2023-11-29 07:09:43,212 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1093033899] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:43,212 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:43,212 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:43,212 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1781269804] [2023-11-29 07:09:43,213 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:43,213 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:43,213 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:43,214 INFO L85 PathProgramCache]: Analyzing trace with hash -1648316281, now seen corresponding path program 2 times [2023-11-29 07:09:43,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:43,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1004754708] [2023-11-29 07:09:43,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:43,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:43,230 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:43,270 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:43,270 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:43,271 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1004754708] [2023-11-29 07:09:43,271 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1004754708] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:43,271 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:43,271 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:43,271 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [747306478] [2023-11-29 07:09:43,272 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:43,272 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:43,272 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:43,273 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:43,273 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:43,273 INFO L87 Difference]: Start difference. First operand 633 states and 941 transitions. cyclomatic complexity: 309 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:43,296 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:43,296 INFO L93 Difference]: Finished difference Result 633 states and 940 transitions. [2023-11-29 07:09:43,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 940 transitions. [2023-11-29 07:09:43,302 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:43,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 940 transitions. [2023-11-29 07:09:43,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-29 07:09:43,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-29 07:09:43,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 940 transitions. [2023-11-29 07:09:43,310 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:43,310 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 940 transitions. [2023-11-29 07:09:43,311 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 940 transitions. [2023-11-29 07:09:43,320 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-29 07:09:43,321 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4849921011058451) internal successors, (940), 632 states have internal predecessors, (940), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:43,325 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 940 transitions. [2023-11-29 07:09:43,325 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 940 transitions. [2023-11-29 07:09:43,325 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:43,326 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 940 transitions. [2023-11-29 07:09:43,326 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 07:09:43,326 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 940 transitions. [2023-11-29 07:09:43,331 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:43,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:43,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:43,332 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:43,333 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:43,333 INFO L748 eck$LassoCheckResult]: Stem: 6722#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 6723#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 6852#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6853#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6381#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 6382#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6908#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7006#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6479#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6480#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6644#L486-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6493#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6494#L670 assume !(0 == ~M_E~0); 6864#L670-2 assume !(0 == ~T1_E~0); 6817#L675-1 assume !(0 == ~T2_E~0); 6818#L680-1 assume !(0 == ~T3_E~0); 6906#L685-1 assume !(0 == ~T4_E~0); 6871#L690-1 assume !(0 == ~T5_E~0); 6872#L695-1 assume !(0 == ~T6_E~0); 6943#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6932#L705-1 assume !(0 == ~E_2~0); 6933#L710-1 assume !(0 == ~E_3~0); 6816#L715-1 assume !(0 == ~E_4~0); 6747#L720-1 assume !(0 == ~E_5~0); 6748#L725-1 assume !(0 == ~E_6~0); 6796#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6841#L320 assume 1 == ~m_pc~0; 6789#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6691#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6685#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6645#L825 assume !(0 != activate_threads_~tmp~1#1); 6646#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6650#L339 assume !(1 == ~t1_pc~0); 6651#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6620#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6475#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6476#L833 assume !(0 != activate_threads_~tmp___0~0#1); 6498#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6407#L358 assume 1 == ~t2_pc~0; 6408#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6925#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6855#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6799#L841 assume !(0 != activate_threads_~tmp___1~0#1); 6640#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6641#L377 assume !(1 == ~t3_pc~0); 6890#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6891#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6403#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6404#L849 assume !(0 != activate_threads_~tmp___2~0#1); 6649#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6575#L396 assume 1 == ~t4_pc~0; 6576#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6410#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6411#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6557#L857 assume !(0 != activate_threads_~tmp___3~0#1); 6542#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6543#L415 assume 1 == ~t5_pc~0; 6625#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6680#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6695#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6696#L865 assume !(0 != activate_threads_~tmp___4~0#1); 6451#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6452#L434 assume !(1 == ~t6_pc~0); 6777#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6778#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6846#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6847#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6664#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6665#L743 assume !(1 == ~M_E~0); 6534#L743-2 assume !(1 == ~T1_E~0); 6535#L748-1 assume !(1 == ~T2_E~0); 6837#L753-1 assume !(1 == ~T3_E~0); 6838#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6946#L763-1 assume !(1 == ~T5_E~0); 6978#L768-1 assume !(1 == ~T6_E~0); 6659#L773-1 assume !(1 == ~E_1~0); 6660#L778-1 assume !(1 == ~E_2~0); 6635#L783-1 assume !(1 == ~E_3~0); 6636#L788-1 assume !(1 == ~E_4~0); 6904#L793-1 assume !(1 == ~E_5~0); 6860#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6515#L803-1 assume { :end_inline_reset_delta_events } true; 6516#L1024-2 [2023-11-29 07:09:43,333 INFO L750 eck$LassoCheckResult]: Loop: 6516#L1024-2 assume !false; 6804#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6389#L645-1 assume !false; 6630#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6745#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6459#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6878#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6879#L556 assume !(0 != eval_~tmp~0#1); 6566#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6567#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6509#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6510#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6688#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6689#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6901#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6902#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7007#L695-3 assume !(0 == ~T6_E~0); 6910#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6911#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6555#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6556#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6800#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6801#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6873#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6661#L320-21 assume !(1 == ~m_pc~0); 6662#L320-23 is_master_triggered_~__retres1~0#1 := 0; 6798#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6605#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 6606#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6968#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6570#L339-21 assume 1 == ~t1_pc~0; 6571#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6701#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6539#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6435#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6436#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6532#L358-21 assume 1 == ~t2_pc~0; 6656#L359-7 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6517#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6518#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6746#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6544#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6545#L377-21 assume 1 == ~t3_pc~0; 6980#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6829#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6830#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6848#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6712#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6713#L396-21 assume !(1 == ~t4_pc~0); 6732#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 6733#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6788#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6417#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6418#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6686#L415-21 assume !(1 == ~t5_pc~0); 6657#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 6658#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6836#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6782#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 6751#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6752#L434-21 assume !(1 == ~t6_pc~0); 6440#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 6441#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6815#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6681#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6682#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6674#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6675#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6990#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6823#L753-3 assume !(1 == ~T3_E~0); 6767#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6703#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6704#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6981#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6599#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6600#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6828#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6998#L793-3 assume !(1 == ~E_5~0); 6999#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6863#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6590#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6487#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6826#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 6827#L1043 assume !(0 == start_simulation_~tmp~3#1); 6961#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 6824#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 6608#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 6473#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 6474#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6503#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6504#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 6781#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 6516#L1024-2 [2023-11-29 07:09:43,334 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:43,334 INFO L85 PathProgramCache]: Analyzing trace with hash -482478117, now seen corresponding path program 1 times [2023-11-29 07:09:43,334 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:43,334 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1378951200] [2023-11-29 07:09:43,334 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:43,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:43,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:43,372 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:43,373 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:43,373 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1378951200] [2023-11-29 07:09:43,373 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1378951200] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:43,373 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:43,373 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:43,373 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1719831228] [2023-11-29 07:09:43,374 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:43,374 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:43,374 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:43,374 INFO L85 PathProgramCache]: Analyzing trace with hash -206020987, now seen corresponding path program 1 times [2023-11-29 07:09:43,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:43,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1402951217] [2023-11-29 07:09:43,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:43,375 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:43,389 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:43,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:43,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:43,423 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1402951217] [2023-11-29 07:09:43,423 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1402951217] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:43,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:43,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:43,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1228577125] [2023-11-29 07:09:43,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:43,425 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:43,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:43,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:43,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:43,425 INFO L87 Difference]: Start difference. First operand 633 states and 940 transitions. cyclomatic complexity: 308 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:43,447 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:43,447 INFO L93 Difference]: Finished difference Result 633 states and 939 transitions. [2023-11-29 07:09:43,447 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 633 states and 939 transitions. [2023-11-29 07:09:43,453 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:43,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 633 states to 633 states and 939 transitions. [2023-11-29 07:09:43,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 633 [2023-11-29 07:09:43,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 633 [2023-11-29 07:09:43,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 633 states and 939 transitions. [2023-11-29 07:09:43,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:43,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 633 states and 939 transitions. [2023-11-29 07:09:43,462 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 633 states and 939 transitions. [2023-11-29 07:09:43,470 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 633 to 633. [2023-11-29 07:09:43,472 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 633 states, 633 states have (on average 1.4834123222748816) internal successors, (939), 632 states have internal predecessors, (939), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:43,475 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 633 states to 633 states and 939 transitions. [2023-11-29 07:09:43,476 INFO L240 hiAutomatonCegarLoop]: Abstraction has 633 states and 939 transitions. [2023-11-29 07:09:43,476 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:43,477 INFO L428 stractBuchiCegarLoop]: Abstraction has 633 states and 939 transitions. [2023-11-29 07:09:43,477 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 07:09:43,477 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 633 states and 939 transitions. [2023-11-29 07:09:43,482 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 544 [2023-11-29 07:09:43,482 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:43,482 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:43,483 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:43,484 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:43,484 INFO L748 eck$LassoCheckResult]: Stem: 7997#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 7998#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 8125#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8126#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7654#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 7655#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8181#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8279#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7752#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7753#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7917#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7767#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7768#L670 assume !(0 == ~M_E~0); 8139#L670-2 assume !(0 == ~T1_E~0); 8090#L675-1 assume !(0 == ~T2_E~0); 8091#L680-1 assume !(0 == ~T3_E~0); 8179#L685-1 assume !(0 == ~T4_E~0); 8145#L690-1 assume !(0 == ~T5_E~0); 8146#L695-1 assume !(0 == ~T6_E~0); 8216#L700-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8205#L705-1 assume !(0 == ~E_2~0); 8206#L710-1 assume !(0 == ~E_3~0); 8089#L715-1 assume !(0 == ~E_4~0); 8021#L720-1 assume !(0 == ~E_5~0); 8022#L725-1 assume !(0 == ~E_6~0); 8069#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8114#L320 assume 1 == ~m_pc~0; 8062#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7964#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7958#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7918#L825 assume !(0 != activate_threads_~tmp~1#1); 7919#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7924#L339 assume !(1 == ~t1_pc~0); 7925#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7893#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7748#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7749#L833 assume !(0 != activate_threads_~tmp___0~0#1); 7771#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7680#L358 assume 1 == ~t2_pc~0; 7681#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8198#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8128#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8072#L841 assume !(0 != activate_threads_~tmp___1~0#1); 7913#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7914#L377 assume !(1 == ~t3_pc~0); 8163#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8164#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7678#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7679#L849 assume !(0 != activate_threads_~tmp___2~0#1); 7922#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7850#L396 assume 1 == ~t4_pc~0; 7851#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7683#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7684#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7830#L857 assume !(0 != activate_threads_~tmp___3~0#1); 7815#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7816#L415 assume 1 == ~t5_pc~0; 7900#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7953#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7971#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7972#L865 assume !(0 != activate_threads_~tmp___4~0#1); 7724#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7725#L434 assume !(1 == ~t6_pc~0); 8051#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8052#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8119#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8120#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7937#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7938#L743 assume !(1 == ~M_E~0); 7807#L743-2 assume !(1 == ~T1_E~0); 7808#L748-1 assume !(1 == ~T2_E~0); 8110#L753-1 assume !(1 == ~T3_E~0); 8111#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8219#L763-1 assume !(1 == ~T5_E~0); 8251#L768-1 assume !(1 == ~T6_E~0); 7935#L773-1 assume !(1 == ~E_1~0); 7936#L778-1 assume !(1 == ~E_2~0); 7908#L783-1 assume !(1 == ~E_3~0); 7909#L788-1 assume !(1 == ~E_4~0); 8177#L793-1 assume !(1 == ~E_5~0); 8133#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 7790#L803-1 assume { :end_inline_reset_delta_events } true; 7791#L1024-2 [2023-11-29 07:09:43,484 INFO L750 eck$LassoCheckResult]: Loop: 7791#L1024-2 assume !false; 8077#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7662#L645-1 assume !false; 7905#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8018#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7732#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8151#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8152#L556 assume !(0 != eval_~tmp~0#1); 7839#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7784#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7785#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7961#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7962#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8174#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8175#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8280#L695-3 assume !(0 == ~T6_E~0); 8182#L700-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8183#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7828#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7829#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8073#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8074#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8144#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7930#L320-21 assume !(1 == ~m_pc~0); 7931#L320-23 is_master_triggered_~__retres1~0#1 := 0; 8071#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7878#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 7879#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8240#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7843#L339-21 assume 1 == ~t1_pc~0; 7844#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7973#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7812#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7708#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7709#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7805#L358-21 assume !(1 == ~t2_pc~0); 7857#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 7788#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7789#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8019#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7817#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7818#L377-21 assume !(1 == ~t3_pc~0); 8192#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 8102#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8103#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8121#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7985#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7986#L396-21 assume !(1 == ~t4_pc~0); 8005#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 8006#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8061#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7690#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7691#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7959#L415-21 assume 1 == ~t5_pc~0; 7960#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7934#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8109#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8055#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 8024#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8025#L434-21 assume 1 == ~t6_pc~0; 8034#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7716#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8088#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7954#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7955#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7947#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7948#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8263#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8096#L753-3 assume !(1 == ~T3_E~0); 8040#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7976#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7977#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8254#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7872#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7873#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8101#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8271#L793-3 assume !(1 == ~E_5~0); 8272#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8136#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 7863#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7760#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 8099#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 8100#L1043 assume !(0 == start_simulation_~tmp~3#1); 8234#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 8097#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 7881#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 7746#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 7747#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7776#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7777#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 8054#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 7791#L1024-2 [2023-11-29 07:09:43,485 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:43,485 INFO L85 PathProgramCache]: Analyzing trace with hash -559378915, now seen corresponding path program 1 times [2023-11-29 07:09:43,485 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:43,485 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [424859434] [2023-11-29 07:09:43,485 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:43,486 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:43,500 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:43,560 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:43,560 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:43,560 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [424859434] [2023-11-29 07:09:43,561 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [424859434] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:43,561 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:43,561 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:43,561 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [961797791] [2023-11-29 07:09:43,561 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:43,562 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:43,562 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:43,562 INFO L85 PathProgramCache]: Analyzing trace with hash 924064517, now seen corresponding path program 1 times [2023-11-29 07:09:43,563 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:43,563 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1756167440] [2023-11-29 07:09:43,563 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:43,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:43,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:43,611 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:43,611 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:43,611 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1756167440] [2023-11-29 07:09:43,611 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1756167440] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:43,611 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:43,612 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:43,612 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [738891967] [2023-11-29 07:09:43,612 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:43,612 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:43,612 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:43,613 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 07:09:43,613 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 07:09:43,613 INFO L87 Difference]: Start difference. First operand 633 states and 939 transitions. cyclomatic complexity: 307 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:43,827 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:43,827 INFO L93 Difference]: Finished difference Result 1138 states and 1686 transitions. [2023-11-29 07:09:43,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1138 states and 1686 transitions. [2023-11-29 07:09:43,839 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1036 [2023-11-29 07:09:43,850 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1138 states to 1138 states and 1686 transitions. [2023-11-29 07:09:43,850 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1138 [2023-11-29 07:09:43,851 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1138 [2023-11-29 07:09:43,852 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1138 states and 1686 transitions. [2023-11-29 07:09:43,853 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:43,853 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1138 states and 1686 transitions. [2023-11-29 07:09:43,856 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1138 states and 1686 transitions. [2023-11-29 07:09:43,875 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1138 to 1136. [2023-11-29 07:09:43,878 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1136 states, 1136 states have (on average 1.482394366197183) internal successors, (1684), 1135 states have internal predecessors, (1684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:43,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1136 states to 1136 states and 1684 transitions. [2023-11-29 07:09:43,885 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1136 states and 1684 transitions. [2023-11-29 07:09:43,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 07:09:43,886 INFO L428 stractBuchiCegarLoop]: Abstraction has 1136 states and 1684 transitions. [2023-11-29 07:09:43,886 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 07:09:43,886 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1136 states and 1684 transitions. [2023-11-29 07:09:43,895 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1036 [2023-11-29 07:09:43,895 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:43,895 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:43,897 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:43,897 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:43,897 INFO L748 eck$LassoCheckResult]: Stem: 9774#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 9775#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 9907#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9908#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9435#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 9436#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9964#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10076#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9531#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9532#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9699#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9547#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9548#L670 assume !(0 == ~M_E~0); 9919#L670-2 assume !(0 == ~T1_E~0); 9872#L675-1 assume !(0 == ~T2_E~0); 9873#L680-1 assume !(0 == ~T3_E~0); 9963#L685-1 assume !(0 == ~T4_E~0); 9926#L690-1 assume !(0 == ~T5_E~0); 9927#L695-1 assume !(0 == ~T6_E~0); 10000#L700-1 assume !(0 == ~E_1~0); 9989#L705-1 assume !(0 == ~E_2~0); 9990#L710-1 assume !(0 == ~E_3~0); 9871#L715-1 assume !(0 == ~E_4~0); 9802#L720-1 assume !(0 == ~E_5~0); 9803#L725-1 assume !(0 == ~E_6~0); 9851#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9896#L320 assume 1 == ~m_pc~0; 9843#L321 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9746#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9740#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 9700#L825 assume !(0 != activate_threads_~tmp~1#1); 9701#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9705#L339 assume !(1 == ~t1_pc~0); 9706#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9674#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9529#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9530#L833 assume !(0 != activate_threads_~tmp___0~0#1); 9552#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9461#L358 assume 1 == ~t2_pc~0; 9462#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9982#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9910#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9854#L841 assume !(0 != activate_threads_~tmp___1~0#1); 9695#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9696#L377 assume !(1 == ~t3_pc~0); 9946#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9947#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9457#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9458#L849 assume !(0 != activate_threads_~tmp___2~0#1); 9704#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9629#L396 assume 1 == ~t4_pc~0; 9630#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9464#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9465#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9611#L857 assume !(0 != activate_threads_~tmp___3~0#1); 9596#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9597#L415 assume 1 == ~t5_pc~0; 9679#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9731#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9749#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9750#L865 assume !(0 != activate_threads_~tmp___4~0#1); 9505#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9506#L434 assume !(1 == ~t6_pc~0); 9832#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9833#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9901#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9902#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9719#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9720#L743 assume !(1 == ~M_E~0); 9588#L743-2 assume !(1 == ~T1_E~0); 9589#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9892#L753-1 assume !(1 == ~T3_E~0); 9893#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10003#L763-1 assume !(1 == ~T5_E~0); 10038#L768-1 assume !(1 == ~T6_E~0); 9712#L773-1 assume !(1 == ~E_1~0); 9713#L778-1 assume !(1 == ~E_2~0); 9690#L783-1 assume !(1 == ~E_3~0); 9691#L788-1 assume !(1 == ~E_4~0); 9961#L793-1 assume !(1 == ~E_5~0); 9915#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9569#L803-1 assume { :end_inline_reset_delta_events } true; 9570#L1024-2 [2023-11-29 07:09:43,898 INFO L750 eck$LassoCheckResult]: Loop: 9570#L1024-2 assume !false; 9859#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9684#L645-1 assume !false; 9685#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9800#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9513#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9933#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9934#L556 assume !(0 != eval_~tmp~0#1); 9618#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9619#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10092#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10091#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10089#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 10090#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 10570#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10569#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10568#L695-3 assume !(0 == ~T6_E~0); 10567#L700-3 assume !(0 == ~E_1~0); 10566#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10565#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10564#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 10563#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10562#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10561#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10560#L320-21 assume !(1 == ~m_pc~0); 10558#L320-23 is_master_triggered_~__retres1~0#1 := 0; 10557#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10556#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 10555#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10554#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10553#L339-21 assume 1 == ~t1_pc~0; 10551#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10550#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9593#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9489#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9490#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9586#L358-21 assume !(1 == ~t2_pc~0); 10458#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 10455#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10453#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10451#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 10449#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10447#L377-21 assume 1 == ~t3_pc~0; 10444#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10441#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10439#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10437#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10435#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10433#L396-21 assume !(1 == ~t4_pc~0); 10430#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 10427#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10425#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10423#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10421#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10419#L415-21 assume 1 == ~t5_pc~0; 10416#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10413#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10411#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10385#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 10384#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10382#L434-21 assume 1 == ~t6_pc~0; 10379#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10377#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10375#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10373#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10370#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10368#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10053#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10054#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9878#L753-3 assume !(1 == ~T3_E~0); 9822#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9758#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9759#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10041#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9653#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9654#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9883#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10067#L793-3 assume !(1 == ~E_5~0); 10068#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9918#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9644#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9541#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9881#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 9882#L1043 assume !(0 == start_simulation_~tmp~3#1); 10019#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 9879#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 9663#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 9527#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 9528#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9557#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9558#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 9836#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 9570#L1024-2 [2023-11-29 07:09:43,898 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:43,898 INFO L85 PathProgramCache]: Analyzing trace with hash -1234940959, now seen corresponding path program 1 times [2023-11-29 07:09:43,898 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:43,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [46024997] [2023-11-29 07:09:43,899 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:43,899 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:43,912 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:43,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:43,953 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:43,953 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [46024997] [2023-11-29 07:09:43,953 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [46024997] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:43,953 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:43,953 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 07:09:43,954 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2070166520] [2023-11-29 07:09:43,954 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:43,954 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:43,955 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:43,955 INFO L85 PathProgramCache]: Analyzing trace with hash 93538728, now seen corresponding path program 1 times [2023-11-29 07:09:43,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:43,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1542226626] [2023-11-29 07:09:43,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:43,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:43,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:44,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:44,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:44,018 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1542226626] [2023-11-29 07:09:44,018 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1542226626] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:44,018 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:44,018 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:44,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [81129790] [2023-11-29 07:09:44,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:44,019 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:44,019 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:44,019 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:44,019 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:44,019 INFO L87 Difference]: Start difference. First operand 1136 states and 1684 transitions. cyclomatic complexity: 550 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:44,116 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:44,116 INFO L93 Difference]: Finished difference Result 1660 states and 2431 transitions. [2023-11-29 07:09:44,117 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1660 states and 2431 transitions. [2023-11-29 07:09:44,133 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1557 [2023-11-29 07:09:44,149 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1660 states to 1660 states and 2431 transitions. [2023-11-29 07:09:44,149 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1660 [2023-11-29 07:09:44,151 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1660 [2023-11-29 07:09:44,151 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1660 states and 2431 transitions. [2023-11-29 07:09:44,154 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:44,154 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1660 states and 2431 transitions. [2023-11-29 07:09:44,157 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1660 states and 2431 transitions. [2023-11-29 07:09:44,183 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1660 to 1608. [2023-11-29 07:09:44,187 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1608 states, 1608 states have (on average 1.467039800995025) internal successors, (2359), 1607 states have internal predecessors, (2359), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:44,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1608 states to 1608 states and 2359 transitions. [2023-11-29 07:09:44,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1608 states and 2359 transitions. [2023-11-29 07:09:44,196 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:44,197 INFO L428 stractBuchiCegarLoop]: Abstraction has 1608 states and 2359 transitions. [2023-11-29 07:09:44,197 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 07:09:44,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1608 states and 2359 transitions. [2023-11-29 07:09:44,210 INFO L131 ngComponentsAnalysis]: Automaton has 3 accepting balls. 1507 [2023-11-29 07:09:44,210 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:44,211 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:44,212 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:44,212 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:44,213 INFO L748 eck$LassoCheckResult]: Stem: 12574#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 12575#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 12708#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12709#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12238#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 12239#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12772#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12901#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12333#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12334#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12499#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12349#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12350#L670 assume !(0 == ~M_E~0); 12721#L670-2 assume !(0 == ~T1_E~0); 12673#L675-1 assume !(0 == ~T2_E~0); 12674#L680-1 assume !(0 == ~T3_E~0); 12771#L685-1 assume !(0 == ~T4_E~0); 12729#L690-1 assume !(0 == ~T5_E~0); 12730#L695-1 assume !(0 == ~T6_E~0); 12807#L700-1 assume !(0 == ~E_1~0); 12796#L705-1 assume !(0 == ~E_2~0); 12797#L710-1 assume !(0 == ~E_3~0); 12672#L715-1 assume !(0 == ~E_4~0); 12605#L720-1 assume !(0 == ~E_5~0); 12606#L725-1 assume !(0 == ~E_6~0); 12652#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12697#L320 assume !(1 == ~m_pc~0); 12826#L320-2 is_master_triggered_~__retres1~0#1 := 0; 12546#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12540#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12500#L825 assume !(0 != activate_threads_~tmp~1#1); 12501#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12505#L339 assume !(1 == ~t1_pc~0); 12506#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12475#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12331#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12332#L833 assume !(0 != activate_threads_~tmp___0~0#1); 12354#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12264#L358 assume 1 == ~t2_pc~0; 12265#L359 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12789#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12711#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12655#L841 assume !(0 != activate_threads_~tmp___1~0#1); 12495#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12496#L377 assume !(1 == ~t3_pc~0); 12752#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12753#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12260#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12261#L849 assume !(0 != activate_threads_~tmp___2~0#1); 12504#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12432#L396 assume 1 == ~t4_pc~0; 12433#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12267#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12268#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12414#L857 assume !(0 != activate_threads_~tmp___3~0#1); 12399#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12400#L415 assume 1 == ~t5_pc~0; 12480#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12530#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12549#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12550#L865 assume !(0 != activate_threads_~tmp___4~0#1); 12308#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12309#L434 assume !(1 == ~t6_pc~0); 12635#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12636#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12702#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12703#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12518#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12519#L743 assume !(1 == ~M_E~0); 12390#L743-2 assume !(1 == ~T1_E~0); 12391#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12692#L753-1 assume !(1 == ~T3_E~0); 12693#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12811#L763-1 assume !(1 == ~T5_E~0); 12861#L768-1 assume !(1 == ~T6_E~0); 12512#L773-1 assume !(1 == ~E_1~0); 12513#L778-1 assume !(1 == ~E_2~0); 12490#L783-1 assume !(1 == ~E_3~0); 12491#L788-1 assume !(1 == ~E_4~0); 12769#L793-1 assume !(1 == ~E_5~0); 12716#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 12371#L803-1 assume { :end_inline_reset_delta_events } true; 12372#L1024-2 [2023-11-29 07:09:44,213 INFO L750 eck$LassoCheckResult]: Loop: 12372#L1024-2 assume !false; 12660#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13405#L645-1 assume !false; 12602#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12603#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12315#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12736#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12737#L556 assume !(0 != eval_~tmp~0#1); 12421#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12422#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13393#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13392#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13390#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13391#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13597#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13596#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13595#L695-3 assume !(0 == ~T6_E~0); 13594#L700-3 assume !(0 == ~E_1~0); 13593#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13592#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13591#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13590#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13589#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13588#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13587#L320-21 assume !(1 == ~m_pc~0); 13586#L320-23 is_master_triggered_~__retres1~0#1 := 0; 13585#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13584#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 12871#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12847#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12427#L339-21 assume 1 == ~t1_pc~0; 12428#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12556#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12396#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 12292#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12293#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12388#L358-21 assume !(1 == ~t2_pc~0); 12441#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 12373#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12374#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 12604#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12401#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12402#L377-21 assume !(1 == ~t3_pc~0); 12784#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 12686#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12687#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 12704#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 12567#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12568#L396-21 assume 1 == ~t4_pc~0; 12717#L397-7 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 12590#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12646#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12274#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12275#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12543#L415-21 assume 1 == ~t5_pc~0; 12544#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12517#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12691#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12640#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 12609#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12610#L434-21 assume 1 == ~t6_pc~0; 12619#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 12300#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12671#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12535#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 12536#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12528#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12529#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12878#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 12678#L753-3 assume !(1 == ~T3_E~0); 12625#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12558#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12559#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12864#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 12456#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12457#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12683#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12890#L793-3 assume !(1 == ~E_5~0); 12891#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12719#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12720#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 13472#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 13470#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 13467#L1043 assume !(0 == start_simulation_~tmp~3#1); 13464#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 12679#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 12464#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 12329#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 12330#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12359#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12360#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 12639#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 12372#L1024-2 [2023-11-29 07:09:44,214 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:44,214 INFO L85 PathProgramCache]: Analyzing trace with hash -1227190400, now seen corresponding path program 1 times [2023-11-29 07:09:44,214 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:44,214 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816420902] [2023-11-29 07:09:44,214 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:44,214 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:44,228 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:44,272 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:44,272 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:44,272 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816420902] [2023-11-29 07:09:44,273 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816420902] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:44,273 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:44,273 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 07:09:44,273 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [311620417] [2023-11-29 07:09:44,273 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:44,274 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:44,274 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:44,274 INFO L85 PathProgramCache]: Analyzing trace with hash -361695640, now seen corresponding path program 1 times [2023-11-29 07:09:44,274 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:44,275 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2075011877] [2023-11-29 07:09:44,275 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:44,275 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:44,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:44,324 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:44,324 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:44,324 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2075011877] [2023-11-29 07:09:44,325 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2075011877] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:44,325 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:44,325 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:44,325 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [951247295] [2023-11-29 07:09:44,325 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:44,326 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:44,326 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:44,326 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:44,326 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:44,326 INFO L87 Difference]: Start difference. First operand 1608 states and 2359 transitions. cyclomatic complexity: 754 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:44,454 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:44,455 INFO L93 Difference]: Finished difference Result 2943 states and 4289 transitions. [2023-11-29 07:09:44,455 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2943 states and 4289 transitions. [2023-11-29 07:09:44,487 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2835 [2023-11-29 07:09:44,516 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2943 states to 2943 states and 4289 transitions. [2023-11-29 07:09:44,517 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2943 [2023-11-29 07:09:44,521 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2943 [2023-11-29 07:09:44,521 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2943 states and 4289 transitions. [2023-11-29 07:09:44,526 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:44,526 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2943 states and 4289 transitions. [2023-11-29 07:09:44,531 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2943 states and 4289 transitions. [2023-11-29 07:09:44,591 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2943 to 2937. [2023-11-29 07:09:44,598 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2937 states, 2937 states have (on average 1.4582907728975145) internal successors, (4283), 2936 states have internal predecessors, (4283), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:44,613 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2937 states to 2937 states and 4283 transitions. [2023-11-29 07:09:44,614 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2937 states and 4283 transitions. [2023-11-29 07:09:44,614 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:44,615 INFO L428 stractBuchiCegarLoop]: Abstraction has 2937 states and 4283 transitions. [2023-11-29 07:09:44,615 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 07:09:44,615 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2937 states and 4283 transitions. [2023-11-29 07:09:44,634 INFO L131 ngComponentsAnalysis]: Automaton has 6 accepting balls. 2829 [2023-11-29 07:09:44,634 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:44,634 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:44,636 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:44,636 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:44,637 INFO L748 eck$LassoCheckResult]: Stem: 17139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 17140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 17284#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17285#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16796#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 16797#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17357#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17514#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16889#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16890#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17058#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16905#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16906#L670 assume !(0 == ~M_E~0); 17299#L670-2 assume !(0 == ~T1_E~0); 17245#L675-1 assume !(0 == ~T2_E~0); 17246#L680-1 assume !(0 == ~T3_E~0); 17356#L685-1 assume !(0 == ~T4_E~0); 17307#L690-1 assume !(0 == ~T5_E~0); 17308#L695-1 assume !(0 == ~T6_E~0); 17399#L700-1 assume !(0 == ~E_1~0); 17387#L705-1 assume !(0 == ~E_2~0); 17388#L710-1 assume !(0 == ~E_3~0); 17244#L715-1 assume !(0 == ~E_4~0); 17168#L720-1 assume !(0 == ~E_5~0); 17169#L725-1 assume !(0 == ~E_6~0); 17223#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17273#L320 assume !(1 == ~m_pc~0); 17419#L320-2 is_master_triggered_~__retres1~0#1 := 0; 17105#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17099#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 17059#L825 assume !(0 != activate_threads_~tmp~1#1); 17060#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17064#L339 assume !(1 == ~t1_pc~0); 17065#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 17033#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16887#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16888#L833 assume !(0 != activate_threads_~tmp___0~0#1); 16910#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16822#L358 assume !(1 == ~t2_pc~0); 16823#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 17379#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17287#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17226#L841 assume !(0 != activate_threads_~tmp___1~0#1); 17054#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17055#L377 assume !(1 == ~t3_pc~0); 17334#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17335#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16818#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16819#L849 assume !(0 != activate_threads_~tmp___2~0#1); 17063#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16991#L396 assume 1 == ~t4_pc~0; 16992#L397 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16824#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16825#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16974#L857 assume !(0 != activate_threads_~tmp___3~0#1); 16958#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16959#L415 assume 1 == ~t5_pc~0; 17038#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17094#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17109#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17110#L865 assume !(0 != activate_threads_~tmp___4~0#1); 16864#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16865#L434 assume !(1 == ~t6_pc~0); 17203#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 17204#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17278#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17279#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17078#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17079#L743 assume !(1 == ~M_E~0); 16947#L743-2 assume !(1 == ~T1_E~0); 16948#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17480#L753-1 assume !(1 == ~T3_E~0); 19732#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19731#L763-1 assume !(1 == ~T5_E~0); 19730#L768-1 assume !(1 == ~T6_E~0); 19729#L773-1 assume !(1 == ~E_1~0); 17074#L778-1 assume !(1 == ~E_2~0); 19728#L783-1 assume !(1 == ~E_3~0); 19727#L788-1 assume !(1 == ~E_4~0); 19726#L793-1 assume !(1 == ~E_5~0); 19725#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 19303#L803-1 assume { :end_inline_reset_delta_events } true; 19301#L1024-2 [2023-11-29 07:09:44,637 INFO L750 eck$LassoCheckResult]: Loop: 19301#L1024-2 assume !false; 19300#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 19296#L645-1 assume !false; 19295#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 17520#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 16871#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17314#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17315#L556 assume !(0 != eval_~tmp~0#1); 17545#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 19621#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 19620#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 19619#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19618#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19617#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19616#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 19615#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 19614#L695-3 assume !(0 == ~T6_E~0); 19613#L700-3 assume !(0 == ~E_1~0); 19612#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19611#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19610#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19609#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 19608#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 19607#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19606#L320-21 assume !(1 == ~m_pc~0); 19605#L320-23 is_master_triggered_~__retres1~0#1 := 0; 19604#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19603#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 19602#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 19601#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19600#L339-21 assume 1 == ~t1_pc~0; 19598#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19597#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19596#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 19595#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 19594#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 19593#L358-21 assume !(1 == ~t2_pc~0); 19592#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 19591#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19590#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19589#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19588#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19587#L377-21 assume 1 == ~t3_pc~0; 19585#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19584#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19583#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19582#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19581#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19580#L396-21 assume !(1 == ~t4_pc~0); 19578#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 19577#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19576#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19575#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19574#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19573#L415-21 assume 1 == ~t5_pc~0; 19571#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19570#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19569#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19568#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 19567#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19566#L434-21 assume 1 == ~t6_pc~0; 19564#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 19563#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19562#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19561#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 19560#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19559#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19558#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19557#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18863#L753-3 assume !(1 == ~T3_E~0); 19556#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19555#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 19554#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 19553#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18857#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19552#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19551#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19550#L793-3 assume !(1 == ~E_5~0); 19549#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 19548#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 19547#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 19540#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 19539#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 19537#L1043 assume !(0 == start_simulation_~tmp~3#1); 19535#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 19534#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 17339#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 17340#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 17217#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17218#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17452#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 17453#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 19301#L1024-2 [2023-11-29 07:09:44,638 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:44,638 INFO L85 PathProgramCache]: Analyzing trace with hash 1792674207, now seen corresponding path program 1 times [2023-11-29 07:09:44,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:44,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998715019] [2023-11-29 07:09:44,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:44,639 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:44,653 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:44,692 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:44,692 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:44,693 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998715019] [2023-11-29 07:09:44,693 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1998715019] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:44,693 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:44,693 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 07:09:44,693 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [13707996] [2023-11-29 07:09:44,693 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:44,694 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:44,694 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:44,694 INFO L85 PathProgramCache]: Analyzing trace with hash 93538728, now seen corresponding path program 2 times [2023-11-29 07:09:44,694 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:44,694 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1317526243] [2023-11-29 07:09:44,695 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:44,695 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:44,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:44,738 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:44,738 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:44,738 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1317526243] [2023-11-29 07:09:44,738 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1317526243] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:44,738 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:44,738 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:44,739 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1654355114] [2023-11-29 07:09:44,739 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:44,739 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:44,739 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:44,740 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:44,740 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:44,740 INFO L87 Difference]: Start difference. First operand 2937 states and 4283 transitions. cyclomatic complexity: 1352 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:44,839 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:44,840 INFO L93 Difference]: Finished difference Result 5435 states and 7885 transitions. [2023-11-29 07:09:44,840 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5435 states and 7885 transitions. [2023-11-29 07:09:44,878 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5306 [2023-11-29 07:09:44,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5435 states to 5435 states and 7885 transitions. [2023-11-29 07:09:44,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5435 [2023-11-29 07:09:44,930 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5435 [2023-11-29 07:09:44,930 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5435 states and 7885 transitions. [2023-11-29 07:09:44,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:44,939 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5435 states and 7885 transitions. [2023-11-29 07:09:44,946 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5435 states and 7885 transitions. [2023-11-29 07:09:45,038 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5435 to 5423. [2023-11-29 07:09:45,050 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5423 states, 5423 states have (on average 1.4517794578646506) internal successors, (7873), 5422 states have internal predecessors, (7873), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:45,116 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5423 states to 5423 states and 7873 transitions. [2023-11-29 07:09:45,117 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5423 states and 7873 transitions. [2023-11-29 07:09:45,117 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:45,118 INFO L428 stractBuchiCegarLoop]: Abstraction has 5423 states and 7873 transitions. [2023-11-29 07:09:45,118 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 07:09:45,118 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5423 states and 7873 transitions. [2023-11-29 07:09:45,141 INFO L131 ngComponentsAnalysis]: Automaton has 12 accepting balls. 5294 [2023-11-29 07:09:45,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:45,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:45,143 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:45,143 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:45,144 INFO L748 eck$LassoCheckResult]: Stem: 25516#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 25517#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 25649#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25650#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25175#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 25176#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 25714#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25864#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25270#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 25271#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 25436#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25286#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 25287#L670 assume !(0 == ~M_E~0); 25663#L670-2 assume !(0 == ~T1_E~0); 25614#L675-1 assume !(0 == ~T2_E~0); 25615#L680-1 assume !(0 == ~T3_E~0); 25713#L685-1 assume !(0 == ~T4_E~0); 25670#L690-1 assume !(0 == ~T5_E~0); 25671#L695-1 assume !(0 == ~T6_E~0); 25756#L700-1 assume !(0 == ~E_1~0); 25744#L705-1 assume !(0 == ~E_2~0); 25745#L710-1 assume !(0 == ~E_3~0); 25613#L715-1 assume !(0 == ~E_4~0); 25541#L720-1 assume !(0 == ~E_5~0); 25542#L725-1 assume !(0 == ~E_6~0); 25592#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25638#L320 assume !(1 == ~m_pc~0); 25777#L320-2 is_master_triggered_~__retres1~0#1 := 0; 25484#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25478#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25437#L825 assume !(0 != activate_threads_~tmp~1#1); 25438#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25442#L339 assume !(1 == ~t1_pc~0); 25443#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25412#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25268#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25269#L833 assume !(0 != activate_threads_~tmp___0~0#1); 25291#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25201#L358 assume !(1 == ~t2_pc~0); 25202#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 25736#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25652#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25595#L841 assume !(0 != activate_threads_~tmp___1~0#1); 25432#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 25433#L377 assume !(1 == ~t3_pc~0); 25693#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25694#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 25197#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 25198#L849 assume !(0 != activate_threads_~tmp___2~0#1); 25441#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 25371#L396 assume !(1 == ~t4_pc~0); 25372#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 25203#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 25204#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 25353#L857 assume !(0 != activate_threads_~tmp___3~0#1); 25337#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 25338#L415 assume 1 == ~t5_pc~0; 25417#L416 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 25473#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25488#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 25489#L865 assume !(0 != activate_threads_~tmp___4~0#1); 25245#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25246#L434 assume !(1 == ~t6_pc~0); 25573#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 25574#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25643#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25644#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25457#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25458#L743 assume !(1 == ~M_E~0); 25328#L743-2 assume !(1 == ~T1_E~0); 25329#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25633#L753-1 assume !(1 == ~T3_E~0); 25634#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25821#L763-1 assume !(1 == ~T5_E~0); 25822#L768-1 assume !(1 == ~T6_E~0); 25451#L773-1 assume !(1 == ~E_1~0); 25452#L778-1 assume !(1 == ~E_2~0); 25427#L783-1 assume !(1 == ~E_3~0); 25428#L788-1 assume !(1 == ~E_4~0); 29738#L793-1 assume !(1 == ~E_5~0); 29736#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 25308#L803-1 assume { :end_inline_reset_delta_events } true; 25309#L1024-2 [2023-11-29 07:09:45,144 INFO L750 eck$LassoCheckResult]: Loop: 25309#L1024-2 assume !false; 27863#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 27860#L645-1 assume !false; 27853#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 27854#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 27840#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 27835#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 27705#L556 assume !(0 != eval_~tmp~0#1); 25360#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 25361#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 25298#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 25299#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 25479#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 25480#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 25706#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 25707#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 25865#L695-3 assume !(0 == ~T6_E~0); 25717#L700-3 assume !(0 == ~E_1~0); 25718#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 25351#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 25352#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 25596#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 25597#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 25672#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 25453#L320-21 assume !(1 == ~m_pc~0); 25454#L320-23 is_master_triggered_~__retres1~0#1 := 0; 25594#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 25398#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 25399#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 25802#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 25366#L339-21 assume 1 == ~t1_pc~0; 25367#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 25495#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25334#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 25229#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 25230#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25325#L358-21 assume !(1 == ~t2_pc~0); 25379#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 25310#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 25311#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 25540#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 25765#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 30146#L377-21 assume 1 == ~t3_pc~0; 30144#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 30143#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 30142#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30141#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 30140#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30139#L396-21 assume !(1 == ~t4_pc~0); 30138#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 30137#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 30136#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 30135#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 30134#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30133#L415-21 assume 1 == ~t5_pc~0; 30131#L416-7 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 30130#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30129#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 30128#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 30127#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 30126#L434-21 assume 1 == ~t6_pc~0; 30124#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 30123#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 25612#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 25474#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 25475#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 25467#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 25468#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25838#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25619#L753-3 assume !(1 == ~T3_E~0); 25559#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 25497#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 25498#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 25824#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 25393#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 25394#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 25624#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 25851#L793-3 assume !(1 == ~E_5~0); 25852#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 25661#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 25662#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29560#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29847#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 29843#L1043 assume !(0 == start_simulation_~tmp~3#1); 28520#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 28521#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 29794#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 29793#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 29792#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 29791#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 29790#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 27871#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 25309#L1024-2 [2023-11-29 07:09:45,145 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:45,145 INFO L85 PathProgramCache]: Analyzing trace with hash -1583318466, now seen corresponding path program 1 times [2023-11-29 07:09:45,145 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:45,145 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [177140629] [2023-11-29 07:09:45,145 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:45,145 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:45,157 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:45,196 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:45,196 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:45,196 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [177140629] [2023-11-29 07:09:45,197 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [177140629] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:45,197 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:45,197 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 07:09:45,197 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [287035331] [2023-11-29 07:09:45,197 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:45,197 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:45,198 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:45,198 INFO L85 PathProgramCache]: Analyzing trace with hash 93538728, now seen corresponding path program 3 times [2023-11-29 07:09:45,198 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:45,198 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [775269660] [2023-11-29 07:09:45,198 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:45,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:45,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:45,245 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:45,246 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:45,246 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [775269660] [2023-11-29 07:09:45,246 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [775269660] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:45,246 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:45,246 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:45,246 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1906670930] [2023-11-29 07:09:45,246 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:45,247 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:45,247 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:45,247 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:45,248 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:45,248 INFO L87 Difference]: Start difference. First operand 5423 states and 7873 transitions. cyclomatic complexity: 2462 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:45,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:45,371 INFO L93 Difference]: Finished difference Result 10080 states and 14576 transitions. [2023-11-29 07:09:45,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10080 states and 14576 transitions. [2023-11-29 07:09:45,425 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 9896 [2023-11-29 07:09:45,495 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10080 states to 10080 states and 14576 transitions. [2023-11-29 07:09:45,495 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10080 [2023-11-29 07:09:45,508 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10080 [2023-11-29 07:09:45,509 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10080 states and 14576 transitions. [2023-11-29 07:09:45,524 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:45,524 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10080 states and 14576 transitions. [2023-11-29 07:09:45,538 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10080 states and 14576 transitions. [2023-11-29 07:09:45,732 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10080 to 10056. [2023-11-29 07:09:45,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10056 states, 10056 states have (on average 1.447096260938743) internal successors, (14552), 10055 states have internal predecessors, (14552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:45,782 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10056 states to 10056 states and 14552 transitions. [2023-11-29 07:09:45,783 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10056 states and 14552 transitions. [2023-11-29 07:09:45,783 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:45,784 INFO L428 stractBuchiCegarLoop]: Abstraction has 10056 states and 14552 transitions. [2023-11-29 07:09:45,784 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 07:09:45,784 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10056 states and 14552 transitions. [2023-11-29 07:09:45,819 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 9872 [2023-11-29 07:09:45,819 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:45,819 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:45,821 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:45,821 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:45,821 INFO L748 eck$LassoCheckResult]: Stem: 41027#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 41028#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 41166#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 41167#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 40685#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 40686#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 41239#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 41421#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 40779#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 40780#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 40945#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 40794#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 40795#L670 assume !(0 == ~M_E~0); 41183#L670-2 assume !(0 == ~T1_E~0); 41130#L675-1 assume !(0 == ~T2_E~0); 41131#L680-1 assume !(0 == ~T3_E~0); 41237#L685-1 assume !(0 == ~T4_E~0); 41191#L690-1 assume !(0 == ~T5_E~0); 41192#L695-1 assume !(0 == ~T6_E~0); 41287#L700-1 assume !(0 == ~E_1~0); 41272#L705-1 assume !(0 == ~E_2~0); 41273#L710-1 assume !(0 == ~E_3~0); 41129#L715-1 assume !(0 == ~E_4~0); 41053#L720-1 assume !(0 == ~E_5~0); 41054#L725-1 assume !(0 == ~E_6~0); 41107#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 41153#L320 assume !(1 == ~m_pc~0); 41308#L320-2 is_master_triggered_~__retres1~0#1 := 0; 40992#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 40986#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 40946#L825 assume !(0 != activate_threads_~tmp~1#1); 40947#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 40955#L339 assume !(1 == ~t1_pc~0); 40956#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 40921#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 40775#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 40776#L833 assume !(0 != activate_threads_~tmp___0~0#1); 40798#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 40711#L358 assume !(1 == ~t2_pc~0); 40712#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 41264#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 41169#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 41111#L841 assume !(0 != activate_threads_~tmp___1~0#1); 40941#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 40942#L377 assume !(1 == ~t3_pc~0); 41215#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 41216#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 40709#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 40710#L849 assume !(0 != activate_threads_~tmp___2~0#1); 40950#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 40878#L396 assume !(1 == ~t4_pc~0); 40879#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 40713#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 40714#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 40858#L857 assume !(0 != activate_threads_~tmp___3~0#1); 40843#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 40844#L415 assume !(1 == ~t5_pc~0); 40928#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 40981#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 40999#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 41000#L865 assume !(0 != activate_threads_~tmp___4~0#1); 40752#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 40753#L434 assume !(1 == ~t6_pc~0); 41085#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 41086#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 41159#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 41160#L873 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 40965#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 40966#L743 assume !(1 == ~M_E~0); 40834#L743-2 assume !(1 == ~T1_E~0); 40835#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41378#L753-1 assume !(1 == ~T3_E~0); 41290#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 41291#L763-1 assume !(1 == ~T5_E~0); 41419#L768-1 assume !(1 == ~T6_E~0); 41420#L773-1 assume !(1 == ~E_1~0); 40963#L778-1 assume !(1 == ~E_2~0); 41451#L783-1 assume !(1 == ~E_3~0); 41441#L788-1 assume !(1 == ~E_4~0); 41442#L793-1 assume !(1 == ~E_5~0); 41175#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 41176#L803-1 assume { :end_inline_reset_delta_events } true; 46683#L1024-2 [2023-11-29 07:09:45,821 INFO L750 eck$LassoCheckResult]: Loop: 46683#L1024-2 assume !false; 46674#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 46668#L645-1 assume !false; 46664#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 46661#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 46652#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 46647#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 46643#L556 assume !(0 != eval_~tmp~0#1); 46644#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 47159#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 47156#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 47153#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 47150#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 47147#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 47144#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 47141#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 47137#L695-3 assume !(0 == ~T6_E~0); 47134#L700-3 assume !(0 == ~E_1~0); 47131#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 47128#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 47125#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 47122#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 47119#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 47116#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 47113#L320-21 assume !(1 == ~m_pc~0); 47110#L320-23 is_master_triggered_~__retres1~0#1 := 0; 47107#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 47104#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 47100#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 47097#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 47093#L339-21 assume 1 == ~t1_pc~0; 47088#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 47083#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47079#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 47075#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 47071#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47066#L358-21 assume !(1 == ~t2_pc~0); 47060#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 47055#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47051#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 47046#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 47041#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 47036#L377-21 assume 1 == ~t3_pc~0; 47030#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 47024#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47019#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 47013#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 47007#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 47002#L396-21 assume !(1 == ~t4_pc~0); 46996#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 46991#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 46986#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 46981#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 46977#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 46972#L415-21 assume !(1 == ~t5_pc~0); 46967#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 46962#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 46958#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 46953#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 46947#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 46942#L434-21 assume 1 == ~t6_pc~0; 46936#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 46929#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 46923#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 46917#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 46910#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 46904#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 46897#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 46891#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 46883#L753-3 assume !(1 == ~T3_E~0); 46878#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 46873#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 46868#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 46863#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 46854#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 46849#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 46844#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 46837#L793-3 assume !(1 == ~E_5~0); 46832#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 46788#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 46787#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 46777#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 46773#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 46768#L1043 assume !(0 == start_simulation_~tmp~3#1); 46765#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 46728#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 46716#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 46710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 46709#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 46708#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 46699#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 46691#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 46683#L1024-2 [2023-11-29 07:09:45,822 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:45,822 INFO L85 PathProgramCache]: Analyzing trace with hash -944533987, now seen corresponding path program 1 times [2023-11-29 07:09:45,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:45,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294651890] [2023-11-29 07:09:45,822 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:45,822 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:45,833 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:45,880 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:45,880 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:45,880 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294651890] [2023-11-29 07:09:45,880 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294651890] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:45,880 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:45,881 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 07:09:45,881 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223598200] [2023-11-29 07:09:45,881 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:45,881 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:45,881 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:45,882 INFO L85 PathProgramCache]: Analyzing trace with hash 616859399, now seen corresponding path program 1 times [2023-11-29 07:09:45,882 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:45,882 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1139202712] [2023-11-29 07:09:45,882 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:45,882 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:45,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:45,924 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:45,924 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:45,924 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1139202712] [2023-11-29 07:09:45,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1139202712] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:45,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:45,925 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:45,925 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1671533784] [2023-11-29 07:09:45,925 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:45,925 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:45,926 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:45,926 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 07:09:45,926 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 07:09:45,926 INFO L87 Difference]: Start difference. First operand 10056 states and 14552 transitions. cyclomatic complexity: 4520 Second operand has 5 states, 5 states have (on average 16.4) internal successors, (82), 5 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:46,314 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:46,314 INFO L93 Difference]: Finished difference Result 19766 states and 28313 transitions. [2023-11-29 07:09:46,314 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19766 states and 28313 transitions. [2023-11-29 07:09:46,471 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 19464 [2023-11-29 07:09:46,568 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19766 states to 19766 states and 28313 transitions. [2023-11-29 07:09:46,568 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19766 [2023-11-29 07:09:46,595 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19766 [2023-11-29 07:09:46,595 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19766 states and 28313 transitions. [2023-11-29 07:09:46,624 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:46,624 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19766 states and 28313 transitions. [2023-11-29 07:09:46,654 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19766 states and 28313 transitions. [2023-11-29 07:09:46,962 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19766 to 10479. [2023-11-29 07:09:46,975 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10479 states, 10479 states have (on average 1.4290485733371505) internal successors, (14975), 10478 states have internal predecessors, (14975), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:47,007 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10479 states to 10479 states and 14975 transitions. [2023-11-29 07:09:47,007 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10479 states and 14975 transitions. [2023-11-29 07:09:47,008 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 07:09:47,008 INFO L428 stractBuchiCegarLoop]: Abstraction has 10479 states and 14975 transitions. [2023-11-29 07:09:47,008 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 07:09:47,009 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10479 states and 14975 transitions. [2023-11-29 07:09:47,045 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 10292 [2023-11-29 07:09:47,046 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:47,046 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:47,047 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:47,048 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:47,048 INFO L748 eck$LassoCheckResult]: Stem: 70874#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 70875#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 71018#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71019#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 70520#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 70521#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 71098#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 71323#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 70615#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 70616#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 70790#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 70633#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 70634#L670 assume !(0 == ~M_E~0); 71033#L670-2 assume !(0 == ~T1_E~0); 70978#L675-1 assume !(0 == ~T2_E~0); 70979#L680-1 assume !(0 == ~T3_E~0); 71095#L685-1 assume !(0 == ~T4_E~0); 71047#L690-1 assume !(0 == ~T5_E~0); 71048#L695-1 assume !(0 == ~T6_E~0); 71162#L700-1 assume !(0 == ~E_1~0); 71146#L705-1 assume !(0 == ~E_2~0); 71147#L710-1 assume !(0 == ~E_3~0); 70977#L715-1 assume !(0 == ~E_4~0); 70904#L720-1 assume !(0 == ~E_5~0); 70905#L725-1 assume !(0 == ~E_6~0); 70955#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 71006#L320 assume !(1 == ~m_pc~0); 71187#L320-2 is_master_triggered_~__retres1~0#1 := 0; 70839#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70833#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 70791#L825 assume !(0 != activate_threads_~tmp~1#1); 70792#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 70797#L339 assume !(1 == ~t1_pc~0); 70798#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 70765#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70611#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 70612#L833 assume !(0 != activate_threads_~tmp___0~0#1); 70637#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 70546#L358 assume !(1 == ~t2_pc~0); 70547#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 71134#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 71021#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 70959#L841 assume !(0 != activate_threads_~tmp___1~0#1); 70786#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 70787#L377 assume !(1 == ~t3_pc~0); 71072#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 71073#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70542#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 70543#L849 assume !(0 != activate_threads_~tmp___2~0#1); 70795#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70719#L396 assume !(1 == ~t4_pc~0); 70720#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 70548#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70549#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 70701#L857 assume !(0 != activate_threads_~tmp___3~0#1); 70685#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70686#L415 assume !(1 == ~t5_pc~0); 70770#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 70826#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 70844#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70845#L865 assume !(0 != activate_threads_~tmp___4~0#1); 70588#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 70589#L434 assume !(1 == ~t6_pc~0); 70934#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 70935#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 71109#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 71110#L873 assume !(0 != activate_threads_~tmp___5~0#1); 70810#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70811#L743 assume !(1 == ~M_E~0); 70676#L743-2 assume !(1 == ~T1_E~0); 70677#L748-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71263#L753-1 assume !(1 == ~T3_E~0); 77438#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77437#L763-1 assume !(1 == ~T5_E~0); 77436#L768-1 assume !(1 == ~T6_E~0); 77435#L773-1 assume !(1 == ~E_1~0); 70806#L778-1 assume !(1 == ~E_2~0); 77434#L783-1 assume !(1 == ~E_3~0); 77433#L788-1 assume !(1 == ~E_4~0); 77432#L793-1 assume !(1 == ~E_5~0); 77431#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 77430#L803-1 assume { :end_inline_reset_delta_events } true; 77428#L1024-2 [2023-11-29 07:09:47,048 INFO L750 eck$LassoCheckResult]: Loop: 77428#L1024-2 assume !false; 75761#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75758#L645-1 assume !false; 75741#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 75742#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 77411#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 77410#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 73239#L556 assume !(0 != eval_~tmp~0#1); 73241#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 77876#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 77875#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 77874#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 77873#L675-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 77872#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 77871#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 77870#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 77869#L695-3 assume !(0 == ~T6_E~0); 77868#L700-3 assume !(0 == ~E_1~0); 77867#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 77866#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 77865#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 77864#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 77863#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 77862#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 77861#L320-21 assume !(1 == ~m_pc~0); 77860#L320-23 is_master_triggered_~__retres1~0#1 := 0; 77859#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 77858#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 77857#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 77856#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 77855#L339-21 assume 1 == ~t1_pc~0; 77853#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 77852#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 77851#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 77850#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 77849#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 77848#L358-21 assume !(1 == ~t2_pc~0); 77847#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 77846#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 77845#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 77844#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 77843#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 77842#L377-21 assume !(1 == ~t3_pc~0); 77841#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 77839#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 77838#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 77837#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 77836#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 77835#L396-21 assume !(1 == ~t4_pc~0); 77834#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 77833#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 77832#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 77831#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 77830#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 77829#L415-21 assume !(1 == ~t5_pc~0); 77828#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 77827#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 77826#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 77825#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 77824#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 77823#L434-21 assume 1 == ~t6_pc~0; 77821#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 77819#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 77817#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 77815#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 77558#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 77557#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 77556#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 77555#L748-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 76233#L753-3 assume !(1 == ~T3_E~0); 77554#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 77553#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 77552#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 77551#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 76217#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 77550#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 77549#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 77547#L793-3 assume !(1 == ~E_5~0); 76191#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 76177#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 75953#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 75947#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 75936#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 75937#L1043 assume !(0 == start_simulation_~tmp~3#1); 75852#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 75853#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 77443#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 77442#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 77441#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 77440#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 77439#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 77429#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 77428#L1024-2 [2023-11-29 07:09:47,049 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:47,049 INFO L85 PathProgramCache]: Analyzing trace with hash -1965602341, now seen corresponding path program 1 times [2023-11-29 07:09:47,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:47,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [329329211] [2023-11-29 07:09:47,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:47,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:47,062 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:47,110 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:47,111 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:47,111 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [329329211] [2023-11-29 07:09:47,111 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [329329211] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:47,111 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:47,111 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 07:09:47,111 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1681982746] [2023-11-29 07:09:47,111 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:47,112 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:47,112 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:47,112 INFO L85 PathProgramCache]: Analyzing trace with hash -1113477658, now seen corresponding path program 1 times [2023-11-29 07:09:47,112 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:47,113 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [364174147] [2023-11-29 07:09:47,113 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:47,113 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:47,127 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:47,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:47,156 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:47,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [364174147] [2023-11-29 07:09:47,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [364174147] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:47,157 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:47,157 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:47,157 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [554597234] [2023-11-29 07:09:47,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:47,157 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:47,158 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:47,158 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:47,158 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:47,158 INFO L87 Difference]: Start difference. First operand 10479 states and 14975 transitions. cyclomatic complexity: 4520 Second operand has 3 states, 3 states have (on average 27.333333333333332) internal successors, (82), 2 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:47,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:47,245 INFO L93 Difference]: Finished difference Result 10474 states and 14900 transitions. [2023-11-29 07:09:47,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10474 states and 14900 transitions. [2023-11-29 07:09:47,335 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 10292 [2023-11-29 07:09:47,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10474 states to 10474 states and 14900 transitions. [2023-11-29 07:09:47,374 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10474 [2023-11-29 07:09:47,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10474 [2023-11-29 07:09:47,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10474 states and 14900 transitions. [2023-11-29 07:09:47,394 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:47,395 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10474 states and 14900 transitions. [2023-11-29 07:09:47,408 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10474 states and 14900 transitions. [2023-11-29 07:09:47,499 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10474 to 7192. [2023-11-29 07:09:47,509 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7192 states, 7192 states have (on average 1.4233870967741935) internal successors, (10237), 7191 states have internal predecessors, (10237), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:47,530 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7192 states to 7192 states and 10237 transitions. [2023-11-29 07:09:47,530 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7192 states and 10237 transitions. [2023-11-29 07:09:47,531 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:47,531 INFO L428 stractBuchiCegarLoop]: Abstraction has 7192 states and 10237 transitions. [2023-11-29 07:09:47,532 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 07:09:47,532 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7192 states and 10237 transitions. [2023-11-29 07:09:47,588 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7040 [2023-11-29 07:09:47,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:47,589 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:47,590 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:47,590 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:47,591 INFO L748 eck$LassoCheckResult]: Stem: 91818#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 91819#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 91951#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 91952#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 91480#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 91481#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 92011#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 92160#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 91573#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 91574#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 91735#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 91588#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 91589#L670 assume !(0 == ~M_E~0); 91965#L670-2 assume !(0 == ~T1_E~0); 91917#L675-1 assume !(0 == ~T2_E~0); 91918#L680-1 assume !(0 == ~T3_E~0); 92009#L685-1 assume !(0 == ~T4_E~0); 91971#L690-1 assume !(0 == ~T5_E~0); 91972#L695-1 assume !(0 == ~T6_E~0); 92051#L700-1 assume !(0 == ~E_1~0); 92037#L705-1 assume !(0 == ~E_2~0); 92038#L710-1 assume !(0 == ~E_3~0); 91916#L715-1 assume !(0 == ~E_4~0); 91842#L720-1 assume !(0 == ~E_5~0); 91843#L725-1 assume !(0 == ~E_6~0); 91896#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 91940#L320 assume !(1 == ~m_pc~0); 92070#L320-2 is_master_triggered_~__retres1~0#1 := 0; 91782#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 91775#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 91736#L825 assume !(0 != activate_threads_~tmp~1#1); 91737#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 91744#L339 assume !(1 == ~t1_pc~0); 91745#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 91712#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 91569#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 91570#L833 assume !(0 != activate_threads_~tmp___0~0#1); 91592#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 91506#L358 assume !(1 == ~t2_pc~0); 91507#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 92028#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 91955#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 91899#L841 assume !(0 != activate_threads_~tmp___1~0#1); 91731#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 91732#L377 assume !(1 == ~t3_pc~0); 91992#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 91993#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 91504#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 91505#L849 assume !(0 != activate_threads_~tmp___2~0#1); 91739#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 91671#L396 assume !(1 == ~t4_pc~0); 91672#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 91508#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 91509#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 91651#L857 assume !(0 != activate_threads_~tmp___3~0#1); 91636#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 91637#L415 assume !(1 == ~t5_pc~0); 91719#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 91769#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 91789#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 91790#L865 assume !(0 != activate_threads_~tmp___4~0#1); 91546#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 91547#L434 assume !(1 == ~t6_pc~0); 91876#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 91877#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 91945#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 91946#L873 assume !(0 != activate_threads_~tmp___5~0#1); 91753#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 91754#L743 assume !(1 == ~M_E~0); 91628#L743-2 assume !(1 == ~T1_E~0); 91629#L748-1 assume !(1 == ~T2_E~0); 91936#L753-1 assume !(1 == ~T3_E~0); 91937#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 92053#L763-1 assume !(1 == ~T5_E~0); 92111#L768-1 assume !(1 == ~T6_E~0); 91751#L773-1 assume !(1 == ~E_1~0); 91752#L778-1 assume !(1 == ~E_2~0); 91726#L783-1 assume !(1 == ~E_3~0); 91727#L788-1 assume !(1 == ~E_4~0); 92007#L793-1 assume !(1 == ~E_5~0); 91960#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 91611#L803-1 assume { :end_inline_reset_delta_events } true; 91612#L1024-2 [2023-11-29 07:09:47,591 INFO L750 eck$LassoCheckResult]: Loop: 91612#L1024-2 assume !false; 95988#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 95975#L645-1 assume !false; 95970#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 95892#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 95703#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 95539#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 95534#L556 assume !(0 != eval_~tmp~0#1); 95535#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 96457#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 96455#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 96452#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 96450#L675-3 assume !(0 == ~T2_E~0); 96448#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 96446#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 96444#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 96442#L695-3 assume !(0 == ~T6_E~0); 96440#L700-3 assume !(0 == ~E_1~0); 96438#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 96436#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 96434#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 96432#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 96430#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 96427#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 96425#L320-21 assume !(1 == ~m_pc~0); 96423#L320-23 is_master_triggered_~__retres1~0#1 := 0; 96421#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 96419#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 96417#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 96415#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 96413#L339-21 assume !(1 == ~t1_pc~0); 96411#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 96408#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 96406#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 96404#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 96402#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 96400#L358-21 assume !(1 == ~t2_pc~0); 96398#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 96396#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 96394#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 96390#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 96388#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 96386#L377-21 assume !(1 == ~t3_pc~0); 96384#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 96380#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 96378#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 96376#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 96374#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 96372#L396-21 assume !(1 == ~t4_pc~0); 96370#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 96368#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 96366#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96364#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 96362#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 96360#L415-21 assume !(1 == ~t5_pc~0); 96358#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 96356#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 96354#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 96352#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 96351#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 96350#L434-21 assume 1 == ~t6_pc~0; 96349#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 96347#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 96345#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 96342#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 96341#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 96340#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 96339#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 96338#L748-3 assume !(1 == ~T2_E~0); 96337#L753-3 assume !(1 == ~T3_E~0); 96336#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 96335#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 96333#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 96331#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 96329#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 96327#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 96325#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 96323#L793-3 assume !(1 == ~E_5~0); 96321#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 96318#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 96316#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 96308#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 96306#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 96303#L1043 assume !(0 == start_simulation_~tmp~3#1); 96300#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 96047#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 96040#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 96037#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 96036#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 96035#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 96019#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 96009#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 91612#L1024-2 [2023-11-29 07:09:47,591 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:47,591 INFO L85 PathProgramCache]: Analyzing trace with hash -1707436903, now seen corresponding path program 1 times [2023-11-29 07:09:47,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:47,592 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [355892415] [2023-11-29 07:09:47,592 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:47,592 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:47,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:47,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:47,652 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:47,652 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [355892415] [2023-11-29 07:09:47,652 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [355892415] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:47,652 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:47,652 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:47,652 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [169148528] [2023-11-29 07:09:47,652 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:47,653 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:47,653 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:47,653 INFO L85 PathProgramCache]: Analyzing trace with hash -570267711, now seen corresponding path program 1 times [2023-11-29 07:09:47,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:47,654 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1722405993] [2023-11-29 07:09:47,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:47,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:47,665 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:47,690 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:47,690 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:47,690 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1722405993] [2023-11-29 07:09:47,690 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1722405993] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:47,691 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:47,691 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:47,691 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1162424844] [2023-11-29 07:09:47,691 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:47,691 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:47,691 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:47,692 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 07:09:47,692 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 07:09:47,693 INFO L87 Difference]: Start difference. First operand 7192 states and 10237 transitions. cyclomatic complexity: 3061 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:47,845 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:47,845 INFO L93 Difference]: Finished difference Result 15391 states and 21859 transitions. [2023-11-29 07:09:47,845 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 15391 states and 21859 transitions. [2023-11-29 07:09:47,939 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 15104 [2023-11-29 07:09:47,989 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 15391 states to 15391 states and 21859 transitions. [2023-11-29 07:09:47,989 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 15391 [2023-11-29 07:09:48,003 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 15391 [2023-11-29 07:09:48,003 INFO L73 IsDeterministic]: Start isDeterministic. Operand 15391 states and 21859 transitions. [2023-11-29 07:09:48,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:48,015 INFO L218 hiAutomatonCegarLoop]: Abstraction has 15391 states and 21859 transitions. [2023-11-29 07:09:48,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 15391 states and 21859 transitions. [2023-11-29 07:09:48,142 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 15391 to 8278. [2023-11-29 07:09:48,151 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8278 states, 8278 states have (on average 1.42087460739309) internal successors, (11762), 8277 states have internal predecessors, (11762), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:48,171 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8278 states to 8278 states and 11762 transitions. [2023-11-29 07:09:48,171 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8278 states and 11762 transitions. [2023-11-29 07:09:48,171 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 07:09:48,172 INFO L428 stractBuchiCegarLoop]: Abstraction has 8278 states and 11762 transitions. [2023-11-29 07:09:48,172 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 07:09:48,172 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8278 states and 11762 transitions. [2023-11-29 07:09:48,198 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8064 [2023-11-29 07:09:48,198 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:48,198 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:48,199 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:48,199 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:48,200 INFO L748 eck$LassoCheckResult]: Stem: 114415#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 114416#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 114563#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 114564#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 114073#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 114074#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 114638#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 114811#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 114165#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 114166#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 114334#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 114181#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 114182#L670 assume !(0 == ~M_E~0); 114579#L670-2 assume !(0 == ~T1_E~0); 114520#L675-1 assume !(0 == ~T2_E~0); 114521#L680-1 assume !(0 == ~T3_E~0); 114637#L685-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 114728#L690-1 assume !(0 == ~T5_E~0); 114834#L695-1 assume !(0 == ~T6_E~0); 114835#L700-1 assume !(0 == ~E_1~0); 114671#L705-1 assume !(0 == ~E_2~0); 114672#L710-1 assume !(0 == ~E_3~0); 114851#L715-1 assume !(0 == ~E_4~0); 114443#L720-1 assume !(0 == ~E_5~0); 114444#L725-1 assume !(0 == ~E_6~0); 114549#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 114550#L320 assume !(1 == ~m_pc~0); 114817#L320-2 is_master_triggered_~__retres1~0#1 := 0; 114818#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 114377#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 114378#L825 assume !(0 != activate_threads_~tmp~1#1); 114738#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 114739#L339 assume !(1 == ~t1_pc~0); 114543#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 114309#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 114310#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 114186#L833 assume !(0 != activate_threads_~tmp___0~0#1); 114187#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 114099#L358 assume !(1 == ~t2_pc~0); 114100#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 114849#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 114566#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 114567#L841 assume !(0 != activate_threads_~tmp___1~0#1); 114330#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 114331#L377 assume !(1 == ~t3_pc~0); 114612#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 114613#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 114095#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 114096#L849 assume !(0 != activate_threads_~tmp___2~0#1); 114633#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 114634#L396 assume !(1 == ~t4_pc~0); 114848#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 114101#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 114102#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 114535#L857 assume !(0 != activate_threads_~tmp___3~0#1); 114536#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 114847#L415 assume !(1 == ~t5_pc~0); 114367#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 114368#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 114388#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 114389#L865 assume !(0 != activate_threads_~tmp___4~0#1); 114846#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 114614#L434 assume !(1 == ~t6_pc~0); 114615#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 114843#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 114844#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 114651#L873 assume !(0 != activate_threads_~tmp___5~0#1); 114652#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 114795#L743 assume !(1 == ~M_E~0); 114796#L743-2 assume !(1 == ~T1_E~0); 114845#L748-1 assume !(1 == ~T2_E~0); 114544#L753-1 assume !(1 == ~T3_E~0); 114545#L758-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 114690#L763-1 assume !(1 == ~T5_E~0); 114752#L768-1 assume !(1 == ~T6_E~0); 114349#L773-1 assume !(1 == ~E_1~0); 114350#L778-1 assume !(1 == ~E_2~0); 114325#L783-1 assume !(1 == ~E_3~0); 114326#L788-1 assume !(1 == ~E_4~0); 114635#L793-1 assume !(1 == ~E_5~0); 114572#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 114204#L803-1 assume { :end_inline_reset_delta_events } true; 114205#L1024-2 [2023-11-29 07:09:48,200 INFO L750 eck$LassoCheckResult]: Loop: 114205#L1024-2 assume !false; 119531#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 119527#L645-1 assume !false; 119525#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 119523#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 119509#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 119501#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 119480#L556 assume !(0 != eval_~tmp~0#1); 119481#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 119668#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 119666#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 119664#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 119661#L675-3 assume !(0 == ~T2_E~0); 119659#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 119656#L685-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 119655#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 119654#L695-3 assume !(0 == ~T6_E~0); 119653#L700-3 assume !(0 == ~E_1~0); 119652#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 119651#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 119650#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 119649#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 119648#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 119647#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119646#L320-21 assume !(1 == ~m_pc~0); 119645#L320-23 is_master_triggered_~__retres1~0#1 := 0; 119644#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119643#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 119642#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 119641#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119640#L339-21 assume !(1 == ~t1_pc~0); 119639#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 119637#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119636#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 119635#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 119634#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119633#L358-21 assume !(1 == ~t2_pc~0); 119632#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 119631#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119630#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119629#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 119628#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119627#L377-21 assume 1 == ~t3_pc~0; 119625#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 119624#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119623#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119622#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 119621#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119620#L396-21 assume !(1 == ~t4_pc~0); 119619#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 119618#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119617#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119616#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119615#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119614#L415-21 assume !(1 == ~t5_pc~0); 119613#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 119612#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119611#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119610#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 119609#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 119608#L434-21 assume !(1 == ~t6_pc~0); 119607#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 119605#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119603#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 119601#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 119599#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119598#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 119597#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 119596#L748-3 assume !(1 == ~T2_E~0); 119595#L753-3 assume !(1 == ~T3_E~0); 119593#L758-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119590#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 119588#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 119586#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 119584#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 119582#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 119580#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 119577#L793-3 assume !(1 == ~E_5~0); 119575#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 119573#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 119571#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 119563#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 119561#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 119558#L1043 assume !(0 == start_simulation_~tmp~3#1); 119555#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 119553#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 119545#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 119543#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 119541#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 119538#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 119536#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 119534#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 114205#L1024-2 [2023-11-29 07:09:48,201 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:48,201 INFO L85 PathProgramCache]: Analyzing trace with hash -975469477, now seen corresponding path program 1 times [2023-11-29 07:09:48,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:48,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1881486437] [2023-11-29 07:09:48,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:48,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:48,212 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:48,255 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:48,255 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:48,255 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1881486437] [2023-11-29 07:09:48,255 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1881486437] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:48,256 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:48,256 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:48,256 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [569734925] [2023-11-29 07:09:48,256 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:48,256 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:48,257 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:48,257 INFO L85 PathProgramCache]: Analyzing trace with hash 1569570879, now seen corresponding path program 1 times [2023-11-29 07:09:48,257 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:48,257 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2091030274] [2023-11-29 07:09:48,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:48,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:48,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:48,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:48,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:48,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2091030274] [2023-11-29 07:09:48,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2091030274] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:48,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:48,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:48,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [978261454] [2023-11-29 07:09:48,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:48,297 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:48,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:48,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 07:09:48,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 07:09:48,298 INFO L87 Difference]: Start difference. First operand 8278 states and 11762 transitions. cyclomatic complexity: 3500 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:48,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:48,369 INFO L93 Difference]: Finished difference Result 7192 states and 10187 transitions. [2023-11-29 07:09:48,369 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7192 states and 10187 transitions. [2023-11-29 07:09:48,435 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7040 [2023-11-29 07:09:48,459 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7192 states to 7192 states and 10187 transitions. [2023-11-29 07:09:48,459 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7192 [2023-11-29 07:09:48,463 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7192 [2023-11-29 07:09:48,463 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7192 states and 10187 transitions. [2023-11-29 07:09:48,469 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:48,469 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7192 states and 10187 transitions. [2023-11-29 07:09:48,475 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7192 states and 10187 transitions. [2023-11-29 07:09:48,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7192 to 7192. [2023-11-29 07:09:48,556 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7192 states, 7192 states have (on average 1.4164349276974415) internal successors, (10187), 7191 states have internal predecessors, (10187), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:48,572 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7192 states to 7192 states and 10187 transitions. [2023-11-29 07:09:48,572 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7192 states and 10187 transitions. [2023-11-29 07:09:48,572 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:48,573 INFO L428 stractBuchiCegarLoop]: Abstraction has 7192 states and 10187 transitions. [2023-11-29 07:09:48,573 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 07:09:48,573 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7192 states and 10187 transitions. [2023-11-29 07:09:48,594 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7040 [2023-11-29 07:09:48,594 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:48,595 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:48,596 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:48,596 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:48,596 INFO L748 eck$LassoCheckResult]: Stem: 129889#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 129890#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 130029#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 130030#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 129553#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 129554#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 130091#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 130244#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 129645#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 129646#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 129811#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 129661#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 129662#L670 assume !(0 == ~M_E~0); 130044#L670-2 assume !(0 == ~T1_E~0); 129993#L675-1 assume !(0 == ~T2_E~0); 129994#L680-1 assume !(0 == ~T3_E~0); 130090#L685-1 assume !(0 == ~T4_E~0); 130051#L690-1 assume !(0 == ~T5_E~0); 130052#L695-1 assume !(0 == ~T6_E~0); 130134#L700-1 assume !(0 == ~E_1~0); 130120#L705-1 assume !(0 == ~E_2~0); 130121#L710-1 assume !(0 == ~E_3~0); 129991#L715-1 assume !(0 == ~E_4~0); 129917#L720-1 assume !(0 == ~E_5~0); 129918#L725-1 assume !(0 == ~E_6~0); 129971#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 130018#L320 assume !(1 == ~m_pc~0); 130158#L320-2 is_master_triggered_~__retres1~0#1 := 0; 129859#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 129853#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 129812#L825 assume !(0 != activate_threads_~tmp~1#1); 129813#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 129816#L339 assume !(1 == ~t1_pc~0); 129817#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 129788#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 129643#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 129644#L833 assume !(0 != activate_threads_~tmp___0~0#1); 129666#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 129579#L358 assume !(1 == ~t2_pc~0); 129580#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 130110#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 130032#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 129974#L841 assume !(0 != activate_threads_~tmp___1~0#1); 129807#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 129808#L377 assume !(1 == ~t3_pc~0); 130072#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 130073#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 129575#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 129576#L849 assume !(0 != activate_threads_~tmp___2~0#1); 129815#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 129745#L396 assume !(1 == ~t4_pc~0); 129746#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 129581#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 129582#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 129728#L857 assume !(0 != activate_threads_~tmp___3~0#1); 129712#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 129713#L415 assume !(1 == ~t5_pc~0); 129793#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 129844#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 129862#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 129863#L865 assume !(0 != activate_threads_~tmp___4~0#1); 129619#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 129620#L434 assume !(1 == ~t6_pc~0); 129950#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 129951#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 130023#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 130024#L873 assume !(0 != activate_threads_~tmp___5~0#1); 129832#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 129833#L743 assume !(1 == ~M_E~0); 129702#L743-2 assume !(1 == ~T1_E~0); 129703#L748-1 assume !(1 == ~T2_E~0); 130012#L753-1 assume !(1 == ~T3_E~0); 130013#L758-1 assume !(1 == ~T4_E~0); 130137#L763-1 assume !(1 == ~T5_E~0); 130201#L768-1 assume !(1 == ~T6_E~0); 129825#L773-1 assume !(1 == ~E_1~0); 129826#L778-1 assume !(1 == ~E_2~0); 129802#L783-1 assume !(1 == ~E_3~0); 129803#L788-1 assume !(1 == ~E_4~0); 130088#L793-1 assume !(1 == ~E_5~0); 130039#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 129683#L803-1 assume { :end_inline_reset_delta_events } true; 129684#L1024-2 [2023-11-29 07:09:48,597 INFO L750 eck$LassoCheckResult]: Loop: 129684#L1024-2 assume !false; 133311#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 133306#L645-1 assume !false; 133304#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 133302#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 133294#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 133292#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 133289#L556 assume !(0 != eval_~tmp~0#1); 133290#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 136414#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 136413#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 136412#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 136411#L675-3 assume !(0 == ~T2_E~0); 136410#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 136409#L685-3 assume !(0 == ~T4_E~0); 136408#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 136407#L695-3 assume !(0 == ~T6_E~0); 136406#L700-3 assume !(0 == ~E_1~0); 136405#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 136404#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 136403#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 136402#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 136401#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 136400#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 136399#L320-21 assume !(1 == ~m_pc~0); 136398#L320-23 is_master_triggered_~__retres1~0#1 := 0; 136397#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 136396#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 136395#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 136394#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 136393#L339-21 assume 1 == ~t1_pc~0; 136391#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 136390#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 136389#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 136388#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 136387#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 136386#L358-21 assume !(1 == ~t2_pc~0); 136385#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 136384#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 136383#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 136382#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 136381#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 136380#L377-21 assume 1 == ~t3_pc~0; 136378#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 136377#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 136376#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 136375#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 136374#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 136373#L396-21 assume !(1 == ~t4_pc~0); 136372#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 136371#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 136370#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 136369#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 136368#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 136367#L415-21 assume !(1 == ~t5_pc~0); 136366#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 136365#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 136364#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 136363#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 136362#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 136361#L434-21 assume 1 == ~t6_pc~0; 136359#L435-7 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 136357#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 136355#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 136353#L873-21 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 136352#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 136351#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 136350#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 135843#L748-3 assume !(1 == ~T2_E~0); 135842#L753-3 assume !(1 == ~T3_E~0); 135841#L758-3 assume !(1 == ~T4_E~0); 135840#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 135839#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 135838#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 135837#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 135835#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 135833#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 135832#L793-3 assume !(1 == ~E_5~0); 135831#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 135830#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 133351#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 133343#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 133341#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 133338#L1043 assume !(0 == start_simulation_~tmp~3#1); 133334#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 133332#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 133324#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 133322#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 133320#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 133318#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 133316#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 133314#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 129684#L1024-2 [2023-11-29 07:09:48,597 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:48,597 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463913, now seen corresponding path program 1 times [2023-11-29 07:09:48,597 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:48,598 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [895182365] [2023-11-29 07:09:48,598 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:48,598 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:48,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:48,657 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:48,658 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:48,658 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [895182365] [2023-11-29 07:09:48,658 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [895182365] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:48,658 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:48,658 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:48,658 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [964390060] [2023-11-29 07:09:48,658 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:48,658 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:48,659 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:48,659 INFO L85 PathProgramCache]: Analyzing trace with hash 398231807, now seen corresponding path program 1 times [2023-11-29 07:09:48,659 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:48,659 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [404486058] [2023-11-29 07:09:48,659 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:48,659 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:48,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:48,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:48,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:48,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [404486058] [2023-11-29 07:09:48,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [404486058] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:48,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:48,695 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:48,695 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [373964030] [2023-11-29 07:09:48,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:48,696 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:48,697 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:48,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 07:09:48,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 07:09:48,697 INFO L87 Difference]: Start difference. First operand 7192 states and 10187 transitions. cyclomatic complexity: 3011 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:48,886 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:48,886 INFO L93 Difference]: Finished difference Result 14506 states and 20380 transitions. [2023-11-29 07:09:48,886 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 14506 states and 20380 transitions. [2023-11-29 07:09:48,954 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 14204 [2023-11-29 07:09:49,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 14506 states to 14506 states and 20380 transitions. [2023-11-29 07:09:49,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 14506 [2023-11-29 07:09:49,027 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 14506 [2023-11-29 07:09:49,027 INFO L73 IsDeterministic]: Start isDeterministic. Operand 14506 states and 20380 transitions. [2023-11-29 07:09:49,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:49,044 INFO L218 hiAutomatonCegarLoop]: Abstraction has 14506 states and 20380 transitions. [2023-11-29 07:09:49,058 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 14506 states and 20380 transitions. [2023-11-29 07:09:49,269 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 14506 to 8011. [2023-11-29 07:09:49,278 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8011 states, 8011 states have (on average 1.4064411434277868) internal successors, (11267), 8010 states have internal predecessors, (11267), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:49,296 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8011 states to 8011 states and 11267 transitions. [2023-11-29 07:09:49,296 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8011 states and 11267 transitions. [2023-11-29 07:09:49,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 07:09:49,297 INFO L428 stractBuchiCegarLoop]: Abstraction has 8011 states and 11267 transitions. [2023-11-29 07:09:49,297 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 07:09:49,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8011 states and 11267 transitions. [2023-11-29 07:09:49,323 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7800 [2023-11-29 07:09:49,323 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:49,323 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:49,325 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:49,325 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:49,325 INFO L748 eck$LassoCheckResult]: Stem: 151603#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 151604#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 151749#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 151750#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 151261#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 151262#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 151822#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 151984#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 151353#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 151354#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 151524#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 151369#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 151370#L670 assume !(0 == ~M_E~0); 151762#L670-2 assume !(0 == ~T1_E~0); 151708#L675-1 assume !(0 == ~T2_E~0); 151709#L680-1 assume !(0 == ~T3_E~0); 151821#L685-1 assume !(0 == ~T4_E~0); 151769#L690-1 assume !(0 == ~T5_E~0); 151770#L695-1 assume !(0 == ~T6_E~0); 151868#L700-1 assume !(0 == ~E_1~0); 151853#L705-1 assume !(0 == ~E_2~0); 151854#L710-1 assume !(0 == ~E_3~0); 151707#L715-1 assume !(0 == ~E_4~0); 151633#L720-1 assume !(0 == ~E_5~0); 151634#L725-1 assume 0 == ~E_6~0;~E_6~0 := 1; 151685#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 151737#L320 assume !(1 == ~m_pc~0); 151992#L320-2 is_master_triggered_~__retres1~0#1 := 0; 151993#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 151565#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 151566#L825 assume !(0 != activate_threads_~tmp~1#1); 151917#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 151918#L339 assume !(1 == ~t1_pc~0); 151731#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 151732#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 151351#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 151352#L833 assume !(0 != activate_threads_~tmp___0~0#1); 151975#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 151976#L358 assume !(1 == ~t2_pc~0); 151843#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 151844#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 151961#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 151689#L841 assume !(0 != activate_threads_~tmp___1~0#1); 151690#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 151922#L377 assume !(1 == ~t3_pc~0); 151923#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 151810#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 151811#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 151528#L849 assume !(0 != activate_threads_~tmp___2~0#1); 151529#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 151455#L396 assume !(1 == ~t4_pc~0); 151456#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 151289#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 151290#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 151724#L857 assume !(0 != activate_threads_~tmp___3~0#1); 151725#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 151503#L415 assume !(1 == ~t5_pc~0); 151504#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 151738#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 151739#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 152032#L865 assume !(0 != activate_threads_~tmp___4~0#1); 152031#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 151799#L434 assume !(1 == ~t6_pc~0); 151800#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 152034#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 152033#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 152027#L873 assume !(0 != activate_threads_~tmp___5~0#1); 152026#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 152025#L743 assume !(1 == ~M_E~0); 152024#L743-2 assume !(1 == ~T1_E~0); 152023#L748-1 assume !(1 == ~T2_E~0); 152022#L753-1 assume !(1 == ~T3_E~0); 152021#L758-1 assume !(1 == ~T4_E~0); 152020#L763-1 assume !(1 == ~T5_E~0); 152019#L768-1 assume !(1 == ~T6_E~0); 152018#L773-1 assume !(1 == ~E_1~0); 152017#L778-1 assume !(1 == ~E_2~0); 152016#L783-1 assume !(1 == ~E_3~0); 152015#L788-1 assume !(1 == ~E_4~0); 152014#L793-1 assume !(1 == ~E_5~0); 152013#L798-1 assume 1 == ~E_6~0;~E_6~0 := 2; 151392#L803-1 assume { :end_inline_reset_delta_events } true; 151393#L1024-2 [2023-11-29 07:09:49,325 INFO L750 eck$LassoCheckResult]: Loop: 151393#L1024-2 assume !false; 154887#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 154882#L645-1 assume !false; 154880#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 154878#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 154871#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 154867#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 154864#L556 assume !(0 != eval_~tmp~0#1); 154865#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 155024#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 155022#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 155020#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 155018#L675-3 assume !(0 == ~T2_E~0); 155015#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 155013#L685-3 assume !(0 == ~T4_E~0); 155011#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 155009#L695-3 assume !(0 == ~T6_E~0); 155007#L700-3 assume !(0 == ~E_1~0); 155005#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 155002#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 155000#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 154998#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 154995#L725-3 assume 0 == ~E_6~0;~E_6~0 := 1; 154994#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 154993#L320-21 assume !(1 == ~m_pc~0); 154992#L320-23 is_master_triggered_~__retres1~0#1 := 0; 154991#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 154990#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 154989#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 154988#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 154987#L339-21 assume !(1 == ~t1_pc~0); 154986#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 154984#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 154983#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 154982#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 154981#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 154980#L358-21 assume !(1 == ~t2_pc~0); 154979#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 154978#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 154977#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 154976#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 154975#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 154974#L377-21 assume 1 == ~t3_pc~0; 154972#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 154971#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 154970#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 154969#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 154968#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 154967#L396-21 assume !(1 == ~t4_pc~0); 154966#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 154965#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 154964#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 154963#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 154962#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 154961#L415-21 assume !(1 == ~t5_pc~0); 154960#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 154959#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 154958#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 154957#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 154956#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 154955#L434-21 assume !(1 == ~t6_pc~0); 154954#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 154951#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 154949#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 154947#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 154945#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 154944#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 154943#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 154942#L748-3 assume !(1 == ~T2_E~0); 154941#L753-3 assume !(1 == ~T3_E~0); 154940#L758-3 assume !(1 == ~T4_E~0); 154939#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 154938#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 154937#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 154936#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 154935#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 154934#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 154933#L793-3 assume !(1 == ~E_5~0); 154931#L798-3 assume 1 == ~E_6~0;~E_6~0 := 2; 154929#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 154927#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 154919#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 154917#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 154914#L1043 assume !(0 == start_simulation_~tmp~3#1); 154911#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 154909#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 154901#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 154899#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 154897#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 154895#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 154893#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 154890#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 151393#L1024-2 [2023-11-29 07:09:49,326 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:49,326 INFO L85 PathProgramCache]: Analyzing trace with hash 1760774297, now seen corresponding path program 1 times [2023-11-29 07:09:49,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:49,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [445660238] [2023-11-29 07:09:49,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:49,327 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:49,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:49,379 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:49,379 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:49,379 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [445660238] [2023-11-29 07:09:49,380 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [445660238] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:49,380 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:49,380 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:49,380 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [440927352] [2023-11-29 07:09:49,380 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:49,380 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:49,381 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:49,381 INFO L85 PathProgramCache]: Analyzing trace with hash -1667508037, now seen corresponding path program 1 times [2023-11-29 07:09:49,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:49,381 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607476709] [2023-11-29 07:09:49,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:49,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:49,394 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:49,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:49,421 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:49,421 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1607476709] [2023-11-29 07:09:49,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1607476709] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:49,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:49,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:49,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112160665] [2023-11-29 07:09:49,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:49,422 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:49,423 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:49,423 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 07:09:49,423 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 07:09:49,423 INFO L87 Difference]: Start difference. First operand 8011 states and 11267 transitions. cyclomatic complexity: 3272 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:49,526 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:49,526 INFO L93 Difference]: Finished difference Result 10177 states and 14288 transitions. [2023-11-29 07:09:49,526 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10177 states and 14288 transitions. [2023-11-29 07:09:49,567 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 9996 [2023-11-29 07:09:49,599 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10177 states to 10177 states and 14288 transitions. [2023-11-29 07:09:49,599 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10177 [2023-11-29 07:09:49,606 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10177 [2023-11-29 07:09:49,606 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10177 states and 14288 transitions. [2023-11-29 07:09:49,615 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:49,615 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10177 states and 14288 transitions. [2023-11-29 07:09:49,624 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10177 states and 14288 transitions. [2023-11-29 07:09:49,704 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10177 to 6925. [2023-11-29 07:09:49,712 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6925 states, 6925 states have (on average 1.3995667870036101) internal successors, (9692), 6924 states have internal predecessors, (9692), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:49,726 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6925 states to 6925 states and 9692 transitions. [2023-11-29 07:09:49,727 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6925 states and 9692 transitions. [2023-11-29 07:09:49,727 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 07:09:49,728 INFO L428 stractBuchiCegarLoop]: Abstraction has 6925 states and 9692 transitions. [2023-11-29 07:09:49,728 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 07:09:49,728 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6925 states and 9692 transitions. [2023-11-29 07:09:49,749 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6776 [2023-11-29 07:09:49,750 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:49,750 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:49,751 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:49,751 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:49,752 INFO L748 eck$LassoCheckResult]: Stem: 169800#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 169801#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 169927#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 169928#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169459#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 169460#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 169994#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 170134#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 169553#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 169554#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 169717#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 169568#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 169569#L670 assume !(0 == ~M_E~0); 169941#L670-2 assume !(0 == ~T1_E~0); 169894#L675-1 assume !(0 == ~T2_E~0); 169895#L680-1 assume !(0 == ~T3_E~0); 169992#L685-1 assume !(0 == ~T4_E~0); 169949#L690-1 assume !(0 == ~T5_E~0); 169950#L695-1 assume !(0 == ~T6_E~0); 170038#L700-1 assume !(0 == ~E_1~0); 170023#L705-1 assume !(0 == ~E_2~0); 170024#L710-1 assume !(0 == ~E_3~0); 169893#L715-1 assume !(0 == ~E_4~0); 169825#L720-1 assume !(0 == ~E_5~0); 169826#L725-1 assume !(0 == ~E_6~0); 169873#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 169917#L320 assume !(1 == ~m_pc~0); 170054#L320-2 is_master_triggered_~__retres1~0#1 := 0; 169764#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 169757#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 169718#L825 assume !(0 != activate_threads_~tmp~1#1); 169719#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 169727#L339 assume !(1 == ~t1_pc~0); 169728#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 169694#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169549#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 169550#L833 assume !(0 != activate_threads_~tmp___0~0#1); 169572#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169485#L358 assume !(1 == ~t2_pc~0); 169486#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 170014#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 169930#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 169876#L841 assume !(0 != activate_threads_~tmp___1~0#1); 169713#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169714#L377 assume !(1 == ~t3_pc~0); 169976#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 169977#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169483#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 169484#L849 assume !(0 != activate_threads_~tmp___2~0#1); 169722#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169652#L396 assume !(1 == ~t4_pc~0); 169653#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 169487#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 169488#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 169633#L857 assume !(0 != activate_threads_~tmp___3~0#1); 169617#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169618#L415 assume !(1 == ~t5_pc~0); 169701#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 169752#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169771#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 169772#L865 assume !(0 != activate_threads_~tmp___4~0#1); 169526#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 169527#L434 assume !(1 == ~t6_pc~0); 169855#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 169856#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169921#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 169922#L873 assume !(0 != activate_threads_~tmp___5~0#1); 169736#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169737#L743 assume !(1 == ~M_E~0); 169608#L743-2 assume !(1 == ~T1_E~0); 169609#L748-1 assume !(1 == ~T2_E~0); 169913#L753-1 assume !(1 == ~T3_E~0); 169914#L758-1 assume !(1 == ~T4_E~0); 170040#L763-1 assume !(1 == ~T5_E~0); 170092#L768-1 assume !(1 == ~T6_E~0); 169734#L773-1 assume !(1 == ~E_1~0); 169735#L778-1 assume !(1 == ~E_2~0); 169708#L783-1 assume !(1 == ~E_3~0); 169709#L788-1 assume !(1 == ~E_4~0); 169990#L793-1 assume !(1 == ~E_5~0); 169935#L798-1 assume !(1 == ~E_6~0); 169591#L803-1 assume { :end_inline_reset_delta_events } true; 169592#L1024-2 [2023-11-29 07:09:49,752 INFO L750 eck$LassoCheckResult]: Loop: 169592#L1024-2 assume !false; 171019#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 171013#L645-1 assume !false; 171010#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 171007#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 170998#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 170993#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 170988#L556 assume !(0 != eval_~tmp~0#1); 170989#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 171261#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 171260#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 171259#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 171258#L675-3 assume !(0 == ~T2_E~0); 171257#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 171256#L685-3 assume !(0 == ~T4_E~0); 171255#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 171254#L695-3 assume !(0 == ~T6_E~0); 171253#L700-3 assume !(0 == ~E_1~0); 171252#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 171251#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 171250#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 171249#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 171248#L725-3 assume !(0 == ~E_6~0); 171247#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 171246#L320-21 assume !(1 == ~m_pc~0); 171245#L320-23 is_master_triggered_~__retres1~0#1 := 0; 171244#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 171243#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 171242#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 171240#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 171238#L339-21 assume 1 == ~t1_pc~0; 171235#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 171233#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 171231#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 171229#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 171227#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 171224#L358-21 assume !(1 == ~t2_pc~0); 171222#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 171220#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 171218#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 171216#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 171214#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 171212#L377-21 assume !(1 == ~t3_pc~0); 171210#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 171207#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 171205#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 171203#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 171201#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 171198#L396-21 assume !(1 == ~t4_pc~0); 171196#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 171194#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 171192#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 171190#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 171188#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 171186#L415-21 assume !(1 == ~t5_pc~0); 171184#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 171182#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 171180#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 171178#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 171176#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 171174#L434-21 assume !(1 == ~t6_pc~0); 171170#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 171167#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 171164#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 171160#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 171155#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 171151#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 171147#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 171142#L748-3 assume !(1 == ~T2_E~0); 171138#L753-3 assume !(1 == ~T3_E~0); 171134#L758-3 assume !(1 == ~T4_E~0); 171129#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 171125#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 171121#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 171117#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 171113#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 171109#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 171105#L793-3 assume !(1 == ~E_5~0); 171101#L798-3 assume !(1 == ~E_6~0); 171097#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 171080#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 171070#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 171066#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 171061#L1043 assume !(0 == start_simulation_~tmp~3#1); 171057#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 171054#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 171045#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 171042#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 171039#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 171036#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 171032#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 171028#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 169592#L1024-2 [2023-11-29 07:09:49,752 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:49,753 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 1 times [2023-11-29 07:09:49,753 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:49,753 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1607532659] [2023-11-29 07:09:49,753 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:49,753 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:49,836 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:49,836 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:49,844 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:49,888 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:49,889 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:49,889 INFO L85 PathProgramCache]: Analyzing trace with hash -25263177, now seen corresponding path program 1 times [2023-11-29 07:09:49,889 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:49,889 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [894853558] [2023-11-29 07:09:49,890 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:49,890 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:49,901 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:49,925 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:49,925 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:49,925 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [894853558] [2023-11-29 07:09:49,925 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [894853558] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:49,925 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:49,926 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:49,926 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [357387459] [2023-11-29 07:09:49,926 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:49,926 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:49,926 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:49,927 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:49,927 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:49,927 INFO L87 Difference]: Start difference. First operand 6925 states and 9692 transitions. cyclomatic complexity: 2783 Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:49,971 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:49,971 INFO L93 Difference]: Finished difference Result 7960 states and 11114 transitions. [2023-11-29 07:09:49,971 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7960 states and 11114 transitions. [2023-11-29 07:09:50,002 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7752 [2023-11-29 07:09:50,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7960 states to 7960 states and 11114 transitions. [2023-11-29 07:09:50,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7960 [2023-11-29 07:09:50,039 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7960 [2023-11-29 07:09:50,040 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7960 states and 11114 transitions. [2023-11-29 07:09:50,048 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:50,048 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7960 states and 11114 transitions. [2023-11-29 07:09:50,055 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7960 states and 11114 transitions. [2023-11-29 07:09:50,136 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7960 to 7960. [2023-11-29 07:09:50,144 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7960 states, 7960 states have (on average 1.3962311557788945) internal successors, (11114), 7959 states have internal predecessors, (11114), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:50,160 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7960 states to 7960 states and 11114 transitions. [2023-11-29 07:09:50,161 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7960 states and 11114 transitions. [2023-11-29 07:09:50,161 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:50,162 INFO L428 stractBuchiCegarLoop]: Abstraction has 7960 states and 11114 transitions. [2023-11-29 07:09:50,162 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 07:09:50,162 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7960 states and 11114 transitions. [2023-11-29 07:09:50,187 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 7752 [2023-11-29 07:09:50,187 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:50,187 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:50,189 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:50,189 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:50,189 INFO L748 eck$LassoCheckResult]: Stem: 184694#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 184695#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 184829#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 184830#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 184350#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 184351#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 184896#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 185051#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 184444#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 184445#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 184607#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 184459#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 184460#L670 assume !(0 == ~M_E~0); 184844#L670-2 assume !(0 == ~T1_E~0); 184793#L675-1 assume !(0 == ~T2_E~0); 184794#L680-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 184893#L685-1 assume !(0 == ~T4_E~0); 184977#L690-1 assume !(0 == ~T5_E~0); 185073#L695-1 assume !(0 == ~T6_E~0); 184940#L700-1 assume !(0 == ~E_1~0); 184941#L705-1 assume !(0 == ~E_2~0); 185049#L710-1 assume !(0 == ~E_3~0); 184792#L715-1 assume !(0 == ~E_4~0); 184720#L720-1 assume !(0 == ~E_5~0); 184721#L725-1 assume !(0 == ~E_6~0); 184770#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 185114#L320 assume !(1 == ~m_pc~0); 185057#L320-2 is_master_triggered_~__retres1~0#1 := 0; 185058#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 184651#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 184652#L825 assume !(0 != activate_threads_~tmp~1#1); 185113#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 184619#L339 assume !(1 == ~t1_pc~0); 184620#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 184584#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 184440#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 184441#L833 assume !(0 != activate_threads_~tmp___0~0#1); 184463#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 185107#L358 assume !(1 == ~t2_pc~0); 185106#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 185105#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 184833#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 184774#L841 assume !(0 != activate_threads_~tmp___1~0#1); 184775#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 185103#L377 assume !(1 == ~t3_pc~0); 185101#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 185100#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 185099#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 184611#L849 assume !(0 != activate_threads_~tmp___2~0#1); 184612#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 184543#L396 assume !(1 == ~t4_pc~0); 184544#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 184378#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 184379#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 184523#L857 assume !(0 != activate_threads_~tmp___3~0#1); 184508#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 184509#L415 assume !(1 == ~t5_pc~0); 184591#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 184819#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 184664#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 184665#L865 assume !(0 != activate_threads_~tmp___4~0#1); 184417#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 184418#L434 assume !(1 == ~t6_pc~0); 184752#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 184753#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 184904#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 185085#L873 assume !(0 != activate_threads_~tmp___5~0#1); 184629#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 184630#L743 assume !(1 == ~M_E~0); 184499#L743-2 assume !(1 == ~T1_E~0); 184500#L748-1 assume !(1 == ~T2_E~0); 184813#L753-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 184814#L758-1 assume !(1 == ~T4_E~0); 184943#L763-1 assume !(1 == ~T5_E~0); 184999#L768-1 assume !(1 == ~T6_E~0); 184627#L773-1 assume !(1 == ~E_1~0); 184628#L778-1 assume !(1 == ~E_2~0); 184598#L783-1 assume !(1 == ~E_3~0); 184599#L788-1 assume !(1 == ~E_4~0); 184891#L793-1 assume !(1 == ~E_5~0); 184839#L798-1 assume !(1 == ~E_6~0); 184482#L803-1 assume { :end_inline_reset_delta_events } true; 184483#L1024-2 [2023-11-29 07:09:50,189 INFO L750 eck$LassoCheckResult]: Loop: 184483#L1024-2 assume !false; 188021#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 188016#L645-1 assume !false; 188014#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 188012#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 188003#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 188001#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 187999#L556 assume !(0 != eval_~tmp~0#1); 184530#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 184531#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 184470#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 184471#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 184653#L675-3 assume !(0 == ~T2_E~0); 184654#L680-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 184971#L685-3 assume !(0 == ~T4_E~0); 192308#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 192307#L695-3 assume !(0 == ~T6_E~0); 192306#L700-3 assume !(0 == ~E_1~0); 192305#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 192304#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 192303#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 192302#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 192301#L725-3 assume !(0 == ~E_6~0); 192300#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 192299#L320-21 assume !(1 == ~m_pc~0); 192298#L320-23 is_master_triggered_~__retres1~0#1 := 0; 192297#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 192296#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 192295#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 192294#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 192293#L339-21 assume 1 == ~t1_pc~0; 192291#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 192290#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 192289#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 192288#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 192287#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 192286#L358-21 assume !(1 == ~t2_pc~0); 192285#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 192284#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 192283#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 192282#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 192281#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 192280#L377-21 assume 1 == ~t3_pc~0; 192278#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 192277#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 192276#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 192275#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 192274#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 192273#L396-21 assume !(1 == ~t4_pc~0); 192272#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 192271#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 192270#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 192269#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 192268#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 192267#L415-21 assume !(1 == ~t5_pc~0); 192266#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 192265#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 192264#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 192263#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 192262#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 184923#L434-21 assume !(1 == ~t6_pc~0); 184734#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 192239#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 192238#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 192237#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 192236#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 192235#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 192234#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 192233#L748-3 assume !(1 == ~T2_E~0); 184798#L753-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 184738#L758-3 assume !(1 == ~T4_E~0); 184673#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 184674#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 185002#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 184564#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 184565#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 184803#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 185031#L793-3 assume !(1 == ~E_5~0); 185032#L798-3 assume !(1 == ~E_6~0); 184841#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 184555#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 184452#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 184801#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 184802#L1043 assume !(0 == start_simulation_~tmp~3#1); 184975#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 184799#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 184572#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 191613#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 191607#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 191602#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 191597#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 191589#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 184483#L1024-2 [2023-11-29 07:09:50,190 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:50,190 INFO L85 PathProgramCache]: Analyzing trace with hash -1585374703, now seen corresponding path program 1 times [2023-11-29 07:09:50,190 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:50,190 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1077256402] [2023-11-29 07:09:50,190 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:50,191 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:50,201 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:50,239 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:50,239 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:50,240 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1077256402] [2023-11-29 07:09:50,240 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1077256402] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:50,240 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:50,240 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:50,240 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [830380873] [2023-11-29 07:09:50,240 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:50,240 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:50,241 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:50,241 INFO L85 PathProgramCache]: Analyzing trace with hash -784455082, now seen corresponding path program 1 times [2023-11-29 07:09:50,241 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:50,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [372284340] [2023-11-29 07:09:50,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:50,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:50,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:50,275 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:50,275 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:50,275 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [372284340] [2023-11-29 07:09:50,275 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [372284340] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:50,275 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:50,275 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:50,275 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1454948879] [2023-11-29 07:09:50,275 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:50,276 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:50,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:50,276 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 07:09:50,276 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 07:09:50,277 INFO L87 Difference]: Start difference. First operand 7960 states and 11114 transitions. cyclomatic complexity: 3170 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:50,376 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:50,377 INFO L93 Difference]: Finished difference Result 13775 states and 19252 transitions. [2023-11-29 07:09:50,377 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13775 states and 19252 transitions. [2023-11-29 07:09:50,489 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 13552 [2023-11-29 07:09:50,544 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13775 states to 13775 states and 19252 transitions. [2023-11-29 07:09:50,544 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13775 [2023-11-29 07:09:50,553 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13775 [2023-11-29 07:09:50,553 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13775 states and 19252 transitions. [2023-11-29 07:09:50,571 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:50,571 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13775 states and 19252 transitions. [2023-11-29 07:09:50,582 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13775 states and 19252 transitions. [2023-11-29 07:09:50,692 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13775 to 6925. [2023-11-29 07:09:50,700 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6925 states, 6925 states have (on average 1.3971119133574008) internal successors, (9675), 6924 states have internal predecessors, (9675), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:50,721 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6925 states to 6925 states and 9675 transitions. [2023-11-29 07:09:50,721 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6925 states and 9675 transitions. [2023-11-29 07:09:50,722 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 07:09:50,722 INFO L428 stractBuchiCegarLoop]: Abstraction has 6925 states and 9675 transitions. [2023-11-29 07:09:50,723 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 07:09:50,723 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6925 states and 9675 transitions. [2023-11-29 07:09:50,751 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 6776 [2023-11-29 07:09:50,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:50,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:50,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:50,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:50,754 INFO L748 eck$LassoCheckResult]: Stem: 206432#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 206433#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 206557#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 206558#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 206095#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 206096#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 206618#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 206760#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 206188#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 206189#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 206350#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 206203#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 206204#L670 assume !(0 == ~M_E~0); 206572#L670-2 assume !(0 == ~T1_E~0); 206525#L675-1 assume !(0 == ~T2_E~0); 206526#L680-1 assume !(0 == ~T3_E~0); 206616#L685-1 assume !(0 == ~T4_E~0); 206578#L690-1 assume !(0 == ~T5_E~0); 206579#L695-1 assume !(0 == ~T6_E~0); 206657#L700-1 assume !(0 == ~E_1~0); 206644#L705-1 assume !(0 == ~E_2~0); 206645#L710-1 assume !(0 == ~E_3~0); 206524#L715-1 assume !(0 == ~E_4~0); 206456#L720-1 assume !(0 == ~E_5~0); 206457#L725-1 assume !(0 == ~E_6~0); 206503#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 206547#L320 assume !(1 == ~m_pc~0); 206680#L320-2 is_master_triggered_~__retres1~0#1 := 0; 206397#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 206392#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 206351#L825 assume !(0 != activate_threads_~tmp~1#1); 206352#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 206361#L339 assume !(1 == ~t1_pc~0); 206362#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 206327#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 206184#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 206185#L833 assume !(0 != activate_threads_~tmp___0~0#1); 206207#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 206121#L358 assume !(1 == ~t2_pc~0); 206122#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 206635#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 206560#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 206506#L841 assume !(0 != activate_threads_~tmp___1~0#1); 206346#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 206347#L377 assume !(1 == ~t3_pc~0); 206600#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 206601#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 206119#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 206120#L849 assume !(0 != activate_threads_~tmp___2~0#1); 206354#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 206286#L396 assume !(1 == ~t4_pc~0); 206287#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 206123#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 206124#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 206267#L857 assume !(0 != activate_threads_~tmp___3~0#1); 206252#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 206253#L415 assume !(1 == ~t5_pc~0); 206334#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 206387#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 206401#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 206402#L865 assume !(0 != activate_threads_~tmp___4~0#1); 206161#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 206162#L434 assume !(1 == ~t6_pc~0); 206485#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 206486#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 206551#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 206552#L873 assume !(0 != activate_threads_~tmp___5~0#1); 206371#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 206372#L743 assume !(1 == ~M_E~0); 206244#L743-2 assume !(1 == ~T1_E~0); 206245#L748-1 assume !(1 == ~T2_E~0); 206543#L753-1 assume !(1 == ~T3_E~0); 206544#L758-1 assume !(1 == ~T4_E~0); 206660#L763-1 assume !(1 == ~T5_E~0); 206710#L768-1 assume !(1 == ~T6_E~0); 206369#L773-1 assume !(1 == ~E_1~0); 206370#L778-1 assume !(1 == ~E_2~0); 206341#L783-1 assume !(1 == ~E_3~0); 206342#L788-1 assume !(1 == ~E_4~0); 206614#L793-1 assume !(1 == ~E_5~0); 206566#L798-1 assume !(1 == ~E_6~0); 206226#L803-1 assume { :end_inline_reset_delta_events } true; 206227#L1024-2 [2023-11-29 07:09:50,754 INFO L750 eck$LassoCheckResult]: Loop: 206227#L1024-2 assume !false; 210377#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 210373#L645-1 assume !false; 210372#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 210370#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 210362#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 210360#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 210357#L556 assume !(0 != eval_~tmp~0#1); 210358#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 210630#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 210628#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 210626#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 210624#L675-3 assume !(0 == ~T2_E~0); 210622#L680-3 assume !(0 == ~T3_E~0); 210620#L685-3 assume !(0 == ~T4_E~0); 210618#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 210617#L695-3 assume !(0 == ~T6_E~0); 210616#L700-3 assume !(0 == ~E_1~0); 210615#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 210614#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 210613#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 210612#L720-3 assume 0 == ~E_5~0;~E_5~0 := 1; 210610#L725-3 assume !(0 == ~E_6~0); 210608#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 210606#L320-21 assume !(1 == ~m_pc~0); 210604#L320-23 is_master_triggered_~__retres1~0#1 := 0; 210602#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 210600#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 210598#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 210595#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 210593#L339-21 assume !(1 == ~t1_pc~0); 210591#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 210588#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 210586#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 210584#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 210582#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210580#L358-21 assume !(1 == ~t2_pc~0); 210578#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 210576#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 210574#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 210572#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 210569#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 210567#L377-21 assume !(1 == ~t3_pc~0); 210493#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 210490#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 210488#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 210485#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 210482#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 210480#L396-21 assume !(1 == ~t4_pc~0); 210478#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 210476#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 210474#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 210472#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 210470#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 210468#L415-21 assume !(1 == ~t5_pc~0); 210466#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 210464#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 210462#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 210460#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 210458#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 210456#L434-21 assume !(1 == ~t6_pc~0); 210453#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 210451#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 210449#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 210446#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 210444#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 210442#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 210440#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 210438#L748-3 assume !(1 == ~T2_E~0); 210436#L753-3 assume !(1 == ~T3_E~0); 210434#L758-3 assume !(1 == ~T4_E~0); 210432#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 210430#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 210428#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 210426#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 210424#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 210422#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 210420#L793-3 assume !(1 == ~E_5~0); 210418#L798-3 assume !(1 == ~E_6~0); 210416#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 210414#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 210406#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 210404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 210402#L1043 assume !(0 == start_simulation_~tmp~3#1); 210399#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 210395#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 210388#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 210387#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 210385#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 210383#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 210381#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 210380#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 206227#L1024-2 [2023-11-29 07:09:50,755 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:50,755 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 2 times [2023-11-29 07:09:50,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:50,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1071211010] [2023-11-29 07:09:50,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:50,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:50,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:50,772 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:50,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:50,810 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:50,811 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:50,811 INFO L85 PathProgramCache]: Analyzing trace with hash 2034702488, now seen corresponding path program 1 times [2023-11-29 07:09:50,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:50,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1287437725] [2023-11-29 07:09:50,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:50,812 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:50,826 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:50,859 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:50,860 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:50,860 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1287437725] [2023-11-29 07:09:50,860 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1287437725] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:50,860 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:50,860 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:50,860 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1803463218] [2023-11-29 07:09:50,861 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:50,861 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:50,861 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:50,861 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:50,862 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:50,862 INFO L87 Difference]: Start difference. First operand 6925 states and 9675 transitions. cyclomatic complexity: 2766 Second operand has 3 states, 3 states have (on average 30.666666666666668) internal successors, (92), 3 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:50,977 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:50,977 INFO L93 Difference]: Finished difference Result 10396 states and 14454 transitions. [2023-11-29 07:09:50,978 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10396 states and 14454 transitions. [2023-11-29 07:09:51,034 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10164 [2023-11-29 07:09:51,072 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10396 states to 10396 states and 14454 transitions. [2023-11-29 07:09:51,072 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10396 [2023-11-29 07:09:51,080 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10396 [2023-11-29 07:09:51,080 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10396 states and 14454 transitions. [2023-11-29 07:09:51,096 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:51,096 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10396 states and 14454 transitions. [2023-11-29 07:09:51,107 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10396 states and 14454 transitions. [2023-11-29 07:09:51,255 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10396 to 10392. [2023-11-29 07:09:51,267 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10392 states, 10392 states have (on average 1.390492686682063) internal successors, (14450), 10391 states have internal predecessors, (14450), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:51,295 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10392 states to 10392 states and 14450 transitions. [2023-11-29 07:09:51,296 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10392 states and 14450 transitions. [2023-11-29 07:09:51,296 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:51,297 INFO L428 stractBuchiCegarLoop]: Abstraction has 10392 states and 14450 transitions. [2023-11-29 07:09:51,297 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 07:09:51,297 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10392 states and 14450 transitions. [2023-11-29 07:09:51,339 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10160 [2023-11-29 07:09:51,339 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:51,339 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:51,341 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:51,342 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:51,342 INFO L748 eck$LassoCheckResult]: Stem: 223766#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 223767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 223905#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 223906#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 223422#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 223423#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 223973#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 224148#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 223515#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 223516#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 223681#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 223531#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 223532#L670 assume !(0 == ~M_E~0); 223917#L670-2 assume !(0 == ~T1_E~0); 223869#L675-1 assume !(0 == ~T2_E~0); 223870#L680-1 assume !(0 == ~T3_E~0); 223972#L685-1 assume !(0 == ~T4_E~0); 223924#L690-1 assume !(0 == ~T5_E~0); 223925#L695-1 assume !(0 == ~T6_E~0); 224025#L700-1 assume !(0 == ~E_1~0); 224011#L705-1 assume !(0 == ~E_2~0); 224012#L710-1 assume !(0 == ~E_3~0); 223868#L715-1 assume !(0 == ~E_4~0); 223796#L720-1 assume 0 == ~E_5~0;~E_5~0 := 1; 223797#L725-1 assume !(0 == ~E_6~0); 223893#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 223894#L320 assume !(1 == ~m_pc~0); 224048#L320-2 is_master_triggered_~__retres1~0#1 := 0; 223733#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223734#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 223682#L825 assume !(0 != activate_threads_~tmp~1#1); 223683#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 224077#L339 assume !(1 == ~t1_pc~0); 224218#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 224217#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 224216#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 224215#L833 assume !(0 != activate_threads_~tmp___0~0#1); 224138#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223447#L358 assume !(1 == ~t2_pc~0); 223448#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 224003#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 224120#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 224211#L841 assume !(0 != activate_threads_~tmp___1~0#1); 223677#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 223678#L377 assume !(1 == ~t3_pc~0); 223951#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 223952#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 223443#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 223444#L849 assume !(0 != activate_threads_~tmp___2~0#1); 224205#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 224204#L396 assume !(1 == ~t4_pc~0); 224203#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 224202#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 224201#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 223883#L857 assume !(0 != activate_threads_~tmp___3~0#1); 223884#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 224200#L415 assume !(1 == ~t5_pc~0); 223714#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 223715#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 224199#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 224198#L865 assume !(0 != activate_threads_~tmp___4~0#1); 224197#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 224196#L434 assume !(1 == ~t6_pc~0); 224194#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 224193#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 223899#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 223900#L873 assume !(0 != activate_threads_~tmp___5~0#1); 223987#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 224136#L743 assume !(1 == ~M_E~0); 223573#L743-2 assume !(1 == ~T1_E~0); 223574#L748-1 assume !(1 == ~T2_E~0); 224111#L753-1 assume !(1 == ~T3_E~0); 224189#L758-1 assume !(1 == ~T4_E~0); 224188#L763-1 assume !(1 == ~T5_E~0); 224187#L768-1 assume !(1 == ~T6_E~0); 224186#L773-1 assume !(1 == ~E_1~0); 224185#L778-1 assume !(1 == ~E_2~0); 223672#L783-1 assume !(1 == ~E_3~0); 223673#L788-1 assume !(1 == ~E_4~0); 223969#L793-1 assume 1 == ~E_5~0;~E_5~0 := 2; 223913#L798-1 assume !(1 == ~E_6~0); 223554#L803-1 assume { :end_inline_reset_delta_events } true; 223555#L1024-2 [2023-11-29 07:09:51,342 INFO L750 eck$LassoCheckResult]: Loop: 223555#L1024-2 assume !false; 233763#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 223666#L645-1 assume !false; 223667#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 223794#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 229714#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 229712#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 229709#L556 assume !(0 != eval_~tmp~0#1); 229710#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 233758#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 233757#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 233756#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 233755#L675-3 assume !(0 == ~T2_E~0); 233754#L680-3 assume !(0 == ~T3_E~0); 233753#L685-3 assume !(0 == ~T4_E~0); 233752#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 233751#L695-3 assume !(0 == ~T6_E~0); 233750#L700-3 assume !(0 == ~E_1~0); 233749#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 233748#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 233747#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 233745#L720-3 assume !(0 == ~E_5~0); 233746#L725-3 assume !(0 == ~E_6~0); 233760#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 233759#L320-21 assume !(1 == ~m_pc~0); 233625#L320-23 is_master_triggered_~__retres1~0#1 := 0; 224133#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 223643#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 223644#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 224072#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 223610#L339-21 assume 1 == ~t1_pc~0; 223611#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 223745#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 223579#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 223474#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 223475#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 223571#L358-21 assume !(1 == ~t2_pc~0); 223623#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 223556#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 223557#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 223795#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 233624#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 233623#L377-21 assume !(1 == ~t3_pc~0); 233622#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 223881#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 223882#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 223901#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 223757#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 223758#L396-21 assume !(1 == ~t4_pc~0); 223914#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 233729#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 233727#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 223456#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 223457#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 223729#L415-21 assume !(1 == ~t5_pc~0); 223730#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 233708#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 233707#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 233706#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 233705#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 233704#L434-21 assume !(1 == ~t6_pc~0); 233702#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 233701#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 233700#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 233699#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 233697#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 233695#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 233693#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 233691#L748-3 assume !(1 == ~T2_E~0); 233689#L753-3 assume !(1 == ~T3_E~0); 233687#L758-3 assume !(1 == ~T4_E~0); 233685#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 233682#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 233680#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 233678#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 233676#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 224157#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 224158#L793-3 assume !(1 == ~E_5~0); 224127#L798-3 assume !(1 == ~E_6~0); 224132#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 233346#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 233336#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 233332#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 233327#L1043 assume !(0 == start_simulation_~tmp~3#1); 233328#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 233777#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 233770#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 233769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 233768#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 233767#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 233765#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 233764#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 223555#L1024-2 [2023-11-29 07:09:51,343 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:51,343 INFO L85 PathProgramCache]: Analyzing trace with hash 1633801745, now seen corresponding path program 1 times [2023-11-29 07:09:51,343 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:51,344 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [921003821] [2023-11-29 07:09:51,344 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:51,344 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:51,358 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:51,409 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:51,409 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:51,409 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [921003821] [2023-11-29 07:09:51,409 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [921003821] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:51,410 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:51,410 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:51,410 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1026609622] [2023-11-29 07:09:51,410 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:51,410 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:51,411 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:51,411 INFO L85 PathProgramCache]: Analyzing trace with hash -752374085, now seen corresponding path program 1 times [2023-11-29 07:09:51,411 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:51,411 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1075846029] [2023-11-29 07:09:51,412 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:51,412 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:51,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:51,483 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:51,483 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:51,483 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1075846029] [2023-11-29 07:09:51,484 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1075846029] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:51,484 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:51,484 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 07:09:51,484 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1706318061] [2023-11-29 07:09:51,484 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:51,484 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:51,485 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:51,485 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 07:09:51,485 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 07:09:51,485 INFO L87 Difference]: Start difference. First operand 10392 states and 14450 transitions. cyclomatic complexity: 4074 Second operand has 4 states, 4 states have (on average 20.5) internal successors, (82), 3 states have internal predecessors, (82), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:51,661 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:51,661 INFO L93 Difference]: Finished difference Result 19227 states and 26748 transitions. [2023-11-29 07:09:51,661 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 19227 states and 26748 transitions. [2023-11-29 07:09:51,789 INFO L131 ngComponentsAnalysis]: Automaton has 40 accepting balls. 18168 [2023-11-29 07:09:51,824 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 19227 states to 19227 states and 26748 transitions. [2023-11-29 07:09:51,825 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 19227 [2023-11-29 07:09:51,831 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 19227 [2023-11-29 07:09:51,832 INFO L73 IsDeterministic]: Start isDeterministic. Operand 19227 states and 26748 transitions. [2023-11-29 07:09:51,844 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:51,844 INFO L218 hiAutomatonCegarLoop]: Abstraction has 19227 states and 26748 transitions. [2023-11-29 07:09:51,858 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 19227 states and 26748 transitions. [2023-11-29 07:09:51,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 19227 to 9849. [2023-11-29 07:09:51,974 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9849 states, 9849 states have (on average 1.3895826987511422) internal successors, (13686), 9848 states have internal predecessors, (13686), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:51,993 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9849 states to 9849 states and 13686 transitions. [2023-11-29 07:09:51,994 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9849 states and 13686 transitions. [2023-11-29 07:09:51,994 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 07:09:51,995 INFO L428 stractBuchiCegarLoop]: Abstraction has 9849 states and 13686 transitions. [2023-11-29 07:09:51,995 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 07:09:51,995 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9849 states and 13686 transitions. [2023-11-29 07:09:52,021 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9676 [2023-11-29 07:09:52,021 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:52,021 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:52,022 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:52,023 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:52,023 INFO L748 eck$LassoCheckResult]: Stem: 253393#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 253394#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 253522#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 253523#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 253053#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 253054#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 253592#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 253748#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 253145#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 253146#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 253312#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 253161#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 253162#L670 assume !(0 == ~M_E~0); 253535#L670-2 assume !(0 == ~T1_E~0); 253488#L675-1 assume !(0 == ~T2_E~0); 253489#L680-1 assume !(0 == ~T3_E~0); 253591#L685-1 assume !(0 == ~T4_E~0); 253543#L690-1 assume !(0 == ~T5_E~0); 253544#L695-1 assume !(0 == ~T6_E~0); 253635#L700-1 assume !(0 == ~E_1~0); 253621#L705-1 assume !(0 == ~E_2~0); 253622#L710-1 assume !(0 == ~E_3~0); 253487#L715-1 assume !(0 == ~E_4~0); 253421#L720-1 assume !(0 == ~E_5~0); 253422#L725-1 assume !(0 == ~E_6~0); 253467#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 253511#L320 assume !(1 == ~m_pc~0); 253653#L320-2 is_master_triggered_~__retres1~0#1 := 0; 253363#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 253354#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 253313#L825 assume !(0 != activate_threads_~tmp~1#1); 253314#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 253318#L339 assume !(1 == ~t1_pc~0); 253319#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 253289#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 253143#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 253144#L833 assume !(0 != activate_threads_~tmp___0~0#1); 253167#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 253078#L358 assume !(1 == ~t2_pc~0); 253079#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 253613#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 253525#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 253470#L841 assume !(0 != activate_threads_~tmp___1~0#1); 253308#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 253309#L377 assume !(1 == ~t3_pc~0); 253569#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 253570#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 253074#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 253075#L849 assume !(0 != activate_threads_~tmp___2~0#1); 253317#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 253245#L396 assume !(1 == ~t4_pc~0); 253246#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 253080#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 253081#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 253228#L857 assume !(0 != activate_threads_~tmp___3~0#1); 253212#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 253213#L415 assume !(1 == ~t5_pc~0); 253294#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 253345#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 253366#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 253367#L865 assume !(0 != activate_threads_~tmp___4~0#1); 253120#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 253121#L434 assume !(1 == ~t6_pc~0); 253451#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 253452#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 253515#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 253516#L873 assume !(0 != activate_threads_~tmp___5~0#1); 253333#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 253334#L743 assume !(1 == ~M_E~0); 253203#L743-2 assume !(1 == ~T1_E~0); 253204#L748-1 assume !(1 == ~T2_E~0); 253506#L753-1 assume !(1 == ~T3_E~0); 253507#L758-1 assume !(1 == ~T4_E~0); 253638#L763-1 assume !(1 == ~T5_E~0); 253693#L768-1 assume !(1 == ~T6_E~0); 253327#L773-1 assume !(1 == ~E_1~0); 253328#L778-1 assume !(1 == ~E_2~0); 253303#L783-1 assume !(1 == ~E_3~0); 253304#L788-1 assume !(1 == ~E_4~0); 253588#L793-1 assume !(1 == ~E_5~0); 253532#L798-1 assume !(1 == ~E_6~0); 253184#L803-1 assume { :end_inline_reset_delta_events } true; 253185#L1024-2 [2023-11-29 07:09:52,023 INFO L750 eck$LassoCheckResult]: Loop: 253185#L1024-2 assume !false; 255166#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 255161#L645-1 assume !false; 255159#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 255156#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 255018#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 255010#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 254999#L556 assume !(0 != eval_~tmp~0#1); 255000#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 256768#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 256765#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 256760#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 256755#L675-3 assume !(0 == ~T2_E~0); 256750#L680-3 assume !(0 == ~T3_E~0); 256746#L685-3 assume !(0 == ~T4_E~0); 256741#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 256737#L695-3 assume !(0 == ~T6_E~0); 256734#L700-3 assume !(0 == ~E_1~0); 256730#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 256726#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 256722#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 256718#L720-3 assume !(0 == ~E_5~0); 256714#L725-3 assume !(0 == ~E_6~0); 256710#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 256705#L320-21 assume !(1 == ~m_pc~0); 256701#L320-23 is_master_triggered_~__retres1~0#1 := 0; 256697#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 256692#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 256688#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 256684#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 256680#L339-21 assume !(1 == ~t1_pc~0); 256675#L339-23 is_transmit1_triggered_~__retres1~1#1 := 0; 256670#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 256666#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 256662#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 256657#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 256653#L358-21 assume !(1 == ~t2_pc~0); 256648#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 256645#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 256641#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 256638#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 256634#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 256630#L377-21 assume !(1 == ~t3_pc~0); 256626#L377-23 is_transmit3_triggered_~__retres1~3#1 := 0; 256621#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 256616#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 256612#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 256608#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 256605#L396-21 assume !(1 == ~t4_pc~0); 256602#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 256598#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 256594#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 256590#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 256586#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 256582#L415-21 assume !(1 == ~t5_pc~0); 256579#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 256576#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 256572#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 256569#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 256565#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 256562#L434-21 assume !(1 == ~t6_pc~0); 256557#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 256552#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 256547#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 256543#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 256538#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 256534#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 256530#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 256525#L748-3 assume !(1 == ~T2_E~0); 256520#L753-3 assume !(1 == ~T3_E~0); 256516#L758-3 assume !(1 == ~T4_E~0); 256511#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 256508#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 256505#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 256500#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 256495#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 256491#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 256487#L793-3 assume !(1 == ~E_5~0); 256483#L798-3 assume !(1 == ~E_6~0); 256479#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 255205#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 255197#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 255195#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 255192#L1043 assume !(0 == start_simulation_~tmp~3#1); 255189#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 255187#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 255179#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 255177#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 255175#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 255173#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 255171#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 255169#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 253185#L1024-2 [2023-11-29 07:09:52,024 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:52,024 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 3 times [2023-11-29 07:09:52,024 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:52,025 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608191763] [2023-11-29 07:09:52,025 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:52,025 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:52,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:52,034 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:52,041 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:52,057 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:52,057 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:52,057 INFO L85 PathProgramCache]: Analyzing trace with hash 1067351834, now seen corresponding path program 1 times [2023-11-29 07:09:52,057 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:52,058 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2049839684] [2023-11-29 07:09:52,058 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:52,058 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:52,068 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:52,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:52,101 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:52,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2049839684] [2023-11-29 07:09:52,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2049839684] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:52,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:52,101 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 07:09:52,101 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1122357680] [2023-11-29 07:09:52,101 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:52,102 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:52,102 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:52,102 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 07:09:52,102 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 07:09:52,102 INFO L87 Difference]: Start difference. First operand 9849 states and 13686 transitions. cyclomatic complexity: 3853 Second operand has 5 states, 5 states have (on average 18.4) internal successors, (92), 5 states have internal predecessors, (92), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:52,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:52,245 INFO L93 Difference]: Finished difference Result 17681 states and 24318 transitions. [2023-11-29 07:09:52,246 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17681 states and 24318 transitions. [2023-11-29 07:09:52,302 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17420 [2023-11-29 07:09:52,339 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17681 states to 17681 states and 24318 transitions. [2023-11-29 07:09:52,339 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17681 [2023-11-29 07:09:52,348 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17681 [2023-11-29 07:09:52,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17681 states and 24318 transitions. [2023-11-29 07:09:52,356 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:52,356 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17681 states and 24318 transitions. [2023-11-29 07:09:52,366 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17681 states and 24318 transitions. [2023-11-29 07:09:52,454 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17681 to 9921. [2023-11-29 07:09:52,461 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9921 states, 9921 states have (on average 1.3867553674024795) internal successors, (13758), 9920 states have internal predecessors, (13758), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:52,477 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9921 states to 9921 states and 13758 transitions. [2023-11-29 07:09:52,477 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9921 states and 13758 transitions. [2023-11-29 07:09:52,478 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-29 07:09:52,478 INFO L428 stractBuchiCegarLoop]: Abstraction has 9921 states and 13758 transitions. [2023-11-29 07:09:52,478 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 07:09:52,478 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9921 states and 13758 transitions. [2023-11-29 07:09:52,503 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9748 [2023-11-29 07:09:52,503 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:52,503 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:52,504 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:52,505 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:52,505 INFO L748 eck$LassoCheckResult]: Stem: 280942#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 280943#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 281077#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 281078#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 280600#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 280601#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 281140#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 281301#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 280693#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 280694#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 280861#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 280709#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 280710#L670 assume !(0 == ~M_E~0); 281090#L670-2 assume !(0 == ~T1_E~0); 281043#L675-1 assume !(0 == ~T2_E~0); 281044#L680-1 assume !(0 == ~T3_E~0); 281139#L685-1 assume !(0 == ~T4_E~0); 281097#L690-1 assume !(0 == ~T5_E~0); 281098#L695-1 assume !(0 == ~T6_E~0); 281186#L700-1 assume !(0 == ~E_1~0); 281172#L705-1 assume !(0 == ~E_2~0); 281173#L710-1 assume !(0 == ~E_3~0); 281042#L715-1 assume !(0 == ~E_4~0); 280970#L720-1 assume !(0 == ~E_5~0); 280971#L725-1 assume !(0 == ~E_6~0); 281021#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281067#L320 assume !(1 == ~m_pc~0); 281204#L320-2 is_master_triggered_~__retres1~0#1 := 0; 280911#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 280903#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 280862#L825 assume !(0 != activate_threads_~tmp~1#1); 280863#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 280866#L339 assume !(1 == ~t1_pc~0); 280867#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 280838#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 280691#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 280692#L833 assume !(0 != activate_threads_~tmp___0~0#1); 280715#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 280625#L358 assume !(1 == ~t2_pc~0); 280626#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 281163#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281080#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 281025#L841 assume !(0 != activate_threads_~tmp___1~0#1); 280857#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 280858#L377 assume !(1 == ~t3_pc~0); 281120#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 281121#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 280621#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 280622#L849 assume !(0 != activate_threads_~tmp___2~0#1); 280865#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 280794#L396 assume !(1 == ~t4_pc~0); 280795#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 280627#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 280628#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 280778#L857 assume !(0 != activate_threads_~tmp___3~0#1); 280762#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 280763#L415 assume !(1 == ~t5_pc~0); 280843#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 280894#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 280914#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 280915#L865 assume !(0 != activate_threads_~tmp___4~0#1); 280667#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 280668#L434 assume !(1 == ~t6_pc~0); 281000#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 281001#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 281071#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 281072#L873 assume !(0 != activate_threads_~tmp___5~0#1); 280882#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 280883#L743 assume !(1 == ~M_E~0); 280753#L743-2 assume !(1 == ~T1_E~0); 280754#L748-1 assume !(1 == ~T2_E~0); 281062#L753-1 assume !(1 == ~T3_E~0); 281063#L758-1 assume !(1 == ~T4_E~0); 281188#L763-1 assume !(1 == ~T5_E~0); 281247#L768-1 assume !(1 == ~T6_E~0); 280875#L773-1 assume !(1 == ~E_1~0); 280876#L778-1 assume !(1 == ~E_2~0); 280852#L783-1 assume !(1 == ~E_3~0); 280853#L788-1 assume !(1 == ~E_4~0); 281137#L793-1 assume !(1 == ~E_5~0); 281086#L798-1 assume !(1 == ~E_6~0); 280733#L803-1 assume { :end_inline_reset_delta_events } true; 280734#L1024-2 [2023-11-29 07:09:52,505 INFO L750 eck$LassoCheckResult]: Loop: 280734#L1024-2 assume !false; 282729#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 282725#L645-1 assume !false; 282724#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 282723#L504 assume !(0 == ~m_st~0); 282718#L508 assume !(0 == ~t1_st~0); 282719#L512 assume !(0 == ~t2_st~0); 282721#L516 assume !(0 == ~t3_st~0); 282716#L520 assume !(0 == ~t4_st~0); 282717#L524 assume !(0 == ~t5_st~0); 282720#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 282722#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 282317#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 282318#L556 assume !(0 != eval_~tmp~0#1); 282841#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 282840#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282839#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 282838#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 282837#L675-3 assume !(0 == ~T2_E~0); 282836#L680-3 assume !(0 == ~T3_E~0); 282835#L685-3 assume !(0 == ~T4_E~0); 282834#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 282833#L695-3 assume !(0 == ~T6_E~0); 282832#L700-3 assume !(0 == ~E_1~0); 282831#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 282830#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 282829#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 282828#L720-3 assume !(0 == ~E_5~0); 282827#L725-3 assume !(0 == ~E_6~0); 282826#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 282825#L320-21 assume !(1 == ~m_pc~0); 282824#L320-23 is_master_triggered_~__retres1~0#1 := 0; 282823#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 282822#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 282821#L825-21 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 282820#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282819#L339-21 assume 1 == ~t1_pc~0; 282817#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 282816#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 282815#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 282814#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 282813#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282812#L358-21 assume !(1 == ~t2_pc~0); 282811#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 282810#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 282809#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 282808#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 282807#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 282806#L377-21 assume 1 == ~t3_pc~0; 282804#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 282803#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 282802#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 282801#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 282800#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 282799#L396-21 assume !(1 == ~t4_pc~0); 282798#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 282797#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 282796#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 282795#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 282794#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 282793#L415-21 assume !(1 == ~t5_pc~0); 282792#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 282791#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 282790#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 282789#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 282788#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 282787#L434-21 assume !(1 == ~t6_pc~0); 282785#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 282784#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 282783#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 282782#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 282781#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 282780#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 282779#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 282778#L748-3 assume !(1 == ~T2_E~0); 282777#L753-3 assume !(1 == ~T3_E~0); 282776#L758-3 assume !(1 == ~T4_E~0); 282775#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 282774#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 282773#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 282772#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 282771#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 282770#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 282769#L793-3 assume !(1 == ~E_5~0); 282768#L798-3 assume !(1 == ~E_6~0); 282767#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 282766#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 282758#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 282756#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 282753#L1043 assume !(0 == start_simulation_~tmp~3#1); 282751#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 282750#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 282743#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 282742#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 282741#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 282740#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 282738#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 282736#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 280734#L1024-2 [2023-11-29 07:09:52,506 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:52,506 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 4 times [2023-11-29 07:09:52,506 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:52,506 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [746791706] [2023-11-29 07:09:52,507 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:52,507 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:52,519 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:52,519 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:52,525 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:52,542 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:52,543 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:52,543 INFO L85 PathProgramCache]: Analyzing trace with hash -1313003349, now seen corresponding path program 1 times [2023-11-29 07:09:52,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:52,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [163851677] [2023-11-29 07:09:52,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:52,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:52,557 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:52,613 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:52,614 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:52,614 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [163851677] [2023-11-29 07:09:52,614 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [163851677] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:52,614 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:52,614 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 07:09:52,615 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2086795236] [2023-11-29 07:09:52,615 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:52,615 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:52,615 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:52,615 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 07:09:52,616 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 07:09:52,616 INFO L87 Difference]: Start difference. First operand 9921 states and 13758 transitions. cyclomatic complexity: 3853 Second operand has 5 states, 5 states have (on average 19.6) internal successors, (98), 5 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:52,870 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:52,870 INFO L93 Difference]: Finished difference Result 18133 states and 24751 transitions. [2023-11-29 07:09:52,870 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18133 states and 24751 transitions. [2023-11-29 07:09:52,985 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17928 [2023-11-29 07:09:53,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18133 states to 18133 states and 24751 transitions. [2023-11-29 07:09:53,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18133 [2023-11-29 07:09:53,024 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18133 [2023-11-29 07:09:53,024 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18133 states and 24751 transitions. [2023-11-29 07:09:53,031 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:53,031 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18133 states and 24751 transitions. [2023-11-29 07:09:53,039 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18133 states and 24751 transitions. [2023-11-29 07:09:53,115 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18133 to 10143. [2023-11-29 07:09:53,121 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10143 states, 10143 states have (on average 1.3720792664892043) internal successors, (13917), 10142 states have internal predecessors, (13917), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:53,138 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10143 states to 10143 states and 13917 transitions. [2023-11-29 07:09:53,138 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10143 states and 13917 transitions. [2023-11-29 07:09:53,139 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 07:09:53,139 INFO L428 stractBuchiCegarLoop]: Abstraction has 10143 states and 13917 transitions. [2023-11-29 07:09:53,139 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 07:09:53,140 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10143 states and 13917 transitions. [2023-11-29 07:09:53,162 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9970 [2023-11-29 07:09:53,162 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:53,162 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:53,164 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:53,164 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:53,164 INFO L748 eck$LassoCheckResult]: Stem: 309005#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 309006#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 309140#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 309141#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 308666#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 308667#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 309209#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 309362#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 308758#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 308759#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 308922#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 308773#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 308774#L670 assume !(0 == ~M_E~0); 309156#L670-2 assume !(0 == ~T1_E~0); 309105#L675-1 assume !(0 == ~T2_E~0); 309106#L680-1 assume !(0 == ~T3_E~0); 309207#L685-1 assume !(0 == ~T4_E~0); 309162#L690-1 assume !(0 == ~T5_E~0); 309163#L695-1 assume !(0 == ~T6_E~0); 309253#L700-1 assume !(0 == ~E_1~0); 309238#L705-1 assume !(0 == ~E_2~0); 309239#L710-1 assume !(0 == ~E_3~0); 309104#L715-1 assume !(0 == ~E_4~0); 309030#L720-1 assume !(0 == ~E_5~0); 309031#L725-1 assume !(0 == ~E_6~0); 309083#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 309130#L320 assume !(1 == ~m_pc~0); 309273#L320-2 is_master_triggered_~__retres1~0#1 := 0; 308970#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 308963#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 308923#L825 assume !(0 != activate_threads_~tmp~1#1); 308924#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 308932#L339 assume !(1 == ~t1_pc~0); 308933#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 308899#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 308754#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 308755#L833 assume !(0 != activate_threads_~tmp___0~0#1); 308777#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 308691#L358 assume !(1 == ~t2_pc~0); 308692#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 309229#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 309143#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 309087#L841 assume !(0 != activate_threads_~tmp___1~0#1); 308918#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 308919#L377 assume !(1 == ~t3_pc~0); 309186#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 309187#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 308689#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 308690#L849 assume !(0 != activate_threads_~tmp___2~0#1); 308927#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 308856#L396 assume !(1 == ~t4_pc~0); 308857#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 308693#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 308694#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 308838#L857 assume !(0 != activate_threads_~tmp___3~0#1); 308823#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 308824#L415 assume !(1 == ~t5_pc~0); 308906#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 308958#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 308977#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 308978#L865 assume !(0 != activate_threads_~tmp___4~0#1); 308731#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 308732#L434 assume !(1 == ~t6_pc~0); 309064#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 309065#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 309134#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 309135#L873 assume !(0 != activate_threads_~tmp___5~0#1); 308942#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 308943#L743 assume !(1 == ~M_E~0); 308814#L743-2 assume !(1 == ~T1_E~0); 308815#L748-1 assume !(1 == ~T2_E~0); 309125#L753-1 assume !(1 == ~T3_E~0); 309126#L758-1 assume !(1 == ~T4_E~0); 309256#L763-1 assume !(1 == ~T5_E~0); 309308#L768-1 assume !(1 == ~T6_E~0); 308940#L773-1 assume !(1 == ~E_1~0); 308941#L778-1 assume !(1 == ~E_2~0); 308913#L783-1 assume !(1 == ~E_3~0); 308914#L788-1 assume !(1 == ~E_4~0); 309205#L793-1 assume !(1 == ~E_5~0); 309149#L798-1 assume !(1 == ~E_6~0); 308796#L803-1 assume { :end_inline_reset_delta_events } true; 308797#L1024-2 [2023-11-29 07:09:53,164 INFO L750 eck$LassoCheckResult]: Loop: 308797#L1024-2 assume !false; 311708#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 311703#L645-1 assume !false; 311354#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 311209#L504 assume !(0 == ~m_st~0); 311204#L508 assume !(0 == ~t1_st~0); 311205#L512 assume !(0 == ~t2_st~0); 311207#L516 assume !(0 == ~t3_st~0); 311202#L520 assume !(0 == ~t4_st~0); 311203#L524 assume !(0 == ~t5_st~0); 311206#L528 assume !(0 == ~t6_st~0);exists_runnable_thread_~__retres1~7#1 := 0; 311208#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 312870#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 312869#L556 assume !(0 != eval_~tmp~0#1); 312868#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 312867#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 312866#L670-3 assume 0 == ~M_E~0;~M_E~0 := 1; 312865#L670-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 312864#L675-3 assume !(0 == ~T2_E~0); 312862#L680-3 assume !(0 == ~T3_E~0); 312861#L685-3 assume !(0 == ~T4_E~0); 312860#L690-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 312859#L695-3 assume !(0 == ~T6_E~0); 312858#L700-3 assume !(0 == ~E_1~0); 312857#L705-3 assume 0 == ~E_2~0;~E_2~0 := 1; 312855#L710-3 assume 0 == ~E_3~0;~E_3~0 := 1; 312853#L715-3 assume 0 == ~E_4~0;~E_4~0 := 1; 312851#L720-3 assume !(0 == ~E_5~0); 312820#L725-3 assume !(0 == ~E_6~0); 312769#L730-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 312263#L320-21 assume !(1 == ~m_pc~0); 312260#L320-23 is_master_triggered_~__retres1~0#1 := 0; 312259#L331-7 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 312140#is_master_triggered_returnLabel#8 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 312134#L825-21 assume !(0 != activate_threads_~tmp~1#1); 312116#L825-23 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 312110#L339-21 assume 1 == ~t1_pc~0; 312104#L340-7 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 312098#L350-7 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 312093#is_transmit1_triggered_returnLabel#8 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 312088#L833-21 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 312081#L833-23 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 312076#L358-21 assume !(1 == ~t2_pc~0); 312071#L358-23 is_transmit2_triggered_~__retres1~2#1 := 0; 312066#L369-7 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 312060#is_transmit2_triggered_returnLabel#8 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 312055#L841-21 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 312049#L841-23 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 312043#L377-21 assume 1 == ~t3_pc~0; 312036#L378-7 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 312029#L388-7 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312023#is_transmit3_triggered_returnLabel#8 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 312017#L849-21 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 312011#L849-23 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 312004#L396-21 assume !(1 == ~t4_pc~0); 311998#L396-23 is_transmit4_triggered_~__retres1~4#1 := 0; 311992#L407-7 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 311985#is_transmit4_triggered_returnLabel#8 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 311979#L857-21 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 311975#L857-23 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 311971#L415-21 assume !(1 == ~t5_pc~0); 311966#L415-23 is_transmit5_triggered_~__retres1~5#1 := 0; 311961#L426-7 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 311957#is_transmit5_triggered_returnLabel#8 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 311953#L865-21 assume !(0 != activate_threads_~tmp___4~0#1); 311948#L865-23 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 311785#L434-21 assume !(1 == ~t6_pc~0); 311782#L434-23 is_transmit6_triggered_~__retres1~6#1 := 0; 311779#L445-7 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 311777#is_transmit6_triggered_returnLabel#8 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 311775#L873-21 assume !(0 != activate_threads_~tmp___5~0#1); 311773#L873-23 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 311771#L743-3 assume 1 == ~M_E~0;~M_E~0 := 2; 311769#L743-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 311767#L748-3 assume !(1 == ~T2_E~0); 311765#L753-3 assume !(1 == ~T3_E~0); 311763#L758-3 assume !(1 == ~T4_E~0); 311761#L763-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 311759#L768-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 311757#L773-3 assume 1 == ~E_1~0;~E_1~0 := 2; 311755#L778-3 assume 1 == ~E_2~0;~E_2~0 := 2; 311753#L783-3 assume 1 == ~E_3~0;~E_3~0 := 2; 311751#L788-3 assume 1 == ~E_4~0;~E_4~0 := 2; 311749#L793-3 assume !(1 == ~E_5~0); 311747#L798-3 assume !(1 == ~E_6~0); 311745#L803-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 311743#L504-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 311736#L541-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 311735#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret20#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret20#1;havoc start_simulation_#t~ret20#1; 311732#L1043 assume !(0 == start_simulation_~tmp~3#1); 311729#L1043-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 311727#L504-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 311720#L541-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 311717#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret19#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret19#1;havoc stop_simulation_#t~ret19#1; 311716#L998 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 311715#L1005 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 311713#stop_simulation_returnLabel#1 start_simulation_#t~ret21#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret19#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret21#1;havoc start_simulation_#t~ret21#1; 311711#L1056 assume !(0 != start_simulation_~tmp___0~1#1); 308797#L1024-2 [2023-11-29 07:09:53,165 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:53,165 INFO L85 PathProgramCache]: Analyzing trace with hash -2100463851, now seen corresponding path program 5 times [2023-11-29 07:09:53,165 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:53,165 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1180335202] [2023-11-29 07:09:53,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:53,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:53,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:53,179 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:53,187 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:53,203 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:53,203 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:53,204 INFO L85 PathProgramCache]: Analyzing trace with hash -1367396247, now seen corresponding path program 1 times [2023-11-29 07:09:53,204 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:53,204 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1751378776] [2023-11-29 07:09:53,204 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:53,204 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:53,213 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:53,236 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:53,236 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:53,236 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1751378776] [2023-11-29 07:09:53,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1751378776] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:53,236 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:53,236 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:53,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710048069] [2023-11-29 07:09:53,237 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:53,237 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 07:09:53,237 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:53,238 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:53,238 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:53,238 INFO L87 Difference]: Start difference. First operand 10143 states and 13917 transitions. cyclomatic complexity: 3790 Second operand has 3 states, 3 states have (on average 32.666666666666664) internal successors, (98), 3 states have internal predecessors, (98), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:53,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:53,326 INFO L93 Difference]: Finished difference Result 17623 states and 23871 transitions. [2023-11-29 07:09:53,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17623 states and 23871 transitions. [2023-11-29 07:09:53,384 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 17384 [2023-11-29 07:09:53,421 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17623 states to 17623 states and 23871 transitions. [2023-11-29 07:09:53,421 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17623 [2023-11-29 07:09:53,431 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17623 [2023-11-29 07:09:53,431 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17623 states and 23871 transitions. [2023-11-29 07:09:53,439 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:53,439 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17623 states and 23871 transitions. [2023-11-29 07:09:53,448 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17623 states and 23871 transitions. [2023-11-29 07:09:53,553 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17623 to 17087. [2023-11-29 07:09:53,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 17087 states, 17087 states have (on average 1.3565283548896823) internal successors, (23179), 17086 states have internal predecessors, (23179), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:53,592 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 17087 states to 17087 states and 23179 transitions. [2023-11-29 07:09:53,593 INFO L240 hiAutomatonCegarLoop]: Abstraction has 17087 states and 23179 transitions. [2023-11-29 07:09:53,593 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:53,593 INFO L428 stractBuchiCegarLoop]: Abstraction has 17087 states and 23179 transitions. [2023-11-29 07:09:53,593 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-29 07:09:53,593 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 17087 states and 23179 transitions. [2023-11-29 07:09:53,633 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 16848 [2023-11-29 07:09:53,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:53,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:53,634 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:53,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:53,634 INFO L748 eck$LassoCheckResult]: Stem: 336783#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 336784#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 336914#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 336915#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 336438#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 336439#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 336985#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 337131#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 336533#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 336534#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 336701#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 336549#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 336550#L670 assume !(0 == ~M_E~0); 336929#L670-2 assume !(0 == ~T1_E~0); 336877#L675-1 assume !(0 == ~T2_E~0); 336878#L680-1 assume !(0 == ~T3_E~0); 336983#L685-1 assume !(0 == ~T4_E~0); 336935#L690-1 assume !(0 == ~T5_E~0); 336936#L695-1 assume !(0 == ~T6_E~0); 337026#L700-1 assume !(0 == ~E_1~0); 337013#L705-1 assume !(0 == ~E_2~0); 337014#L710-1 assume !(0 == ~E_3~0); 336876#L715-1 assume !(0 == ~E_4~0); 336810#L720-1 assume !(0 == ~E_5~0); 336811#L725-1 assume !(0 == ~E_6~0); 336856#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 336904#L320 assume !(1 == ~m_pc~0); 337044#L320-2 is_master_triggered_~__retres1~0#1 := 0; 336750#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 336743#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 336702#L825 assume !(0 != activate_threads_~tmp~1#1); 336703#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 336712#L339 assume !(1 == ~t1_pc~0); 336713#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 336677#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 336529#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 336530#L833 assume !(0 != activate_threads_~tmp___0~0#1); 336553#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 336463#L358 assume !(1 == ~t2_pc~0); 336464#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 337004#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 336917#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 336859#L841 assume !(0 != activate_threads_~tmp___1~0#1); 336697#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 336698#L377 assume !(1 == ~t3_pc~0); 336957#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 336958#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 336459#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 336460#L849 assume !(0 != activate_threads_~tmp___2~0#1); 336707#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 336633#L396 assume !(1 == ~t4_pc~0); 336634#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 336465#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 336466#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 336613#L857 assume !(0 != activate_threads_~tmp___3~0#1); 336598#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 336599#L415 assume !(1 == ~t5_pc~0); 336684#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 336737#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 336759#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 336760#L865 assume !(0 != activate_threads_~tmp___4~0#1); 336506#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 336507#L434 assume !(1 == ~t6_pc~0); 336841#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 336842#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 336908#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 336909#L873 assume !(0 != activate_threads_~tmp___5~0#1); 336721#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 336722#L743 assume !(1 == ~M_E~0); 336589#L743-2 assume !(1 == ~T1_E~0); 336590#L748-1 assume !(1 == ~T2_E~0); 336897#L753-1 assume !(1 == ~T3_E~0); 336898#L758-1 assume !(1 == ~T4_E~0); 337028#L763-1 assume !(1 == ~T5_E~0); 337085#L768-1 assume !(1 == ~T6_E~0); 336719#L773-1 assume !(1 == ~E_1~0); 336720#L778-1 assume !(1 == ~E_2~0); 336691#L783-1 assume !(1 == ~E_3~0); 336692#L788-1 assume !(1 == ~E_4~0); 336980#L793-1 assume !(1 == ~E_5~0); 336924#L798-1 assume !(1 == ~E_6~0); 336572#L803-1 assume { :end_inline_reset_delta_events } true; 336573#L1024-2 assume !false; 341078#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 341073#L645-1 [2023-11-29 07:09:53,635 INFO L750 eck$LassoCheckResult]: Loop: 341073#L645-1 assume !false; 341071#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 341068#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 341066#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 341064#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 341062#L556 assume 0 != eval_~tmp~0#1; 341059#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 341056#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 341057#L564-2 havoc eval_~tmp_ndt_1~0#1; 341761#L561-1 assume !(0 == ~t1_st~0); 341754#L575-1 assume !(0 == ~t2_st~0); 341108#L589-1 assume !(0 == ~t3_st~0); 341104#L603-1 assume !(0 == ~t4_st~0); 341094#L617-1 assume !(0 == ~t5_st~0); 341075#L631-1 assume !(0 == ~t6_st~0); 341073#L645-1 [2023-11-29 07:09:53,635 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:53,635 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 1 times [2023-11-29 07:09:53,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:53,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [439315624] [2023-11-29 07:09:53,636 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:53,636 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:53,649 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:53,649 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:53,657 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:53,676 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:53,677 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:53,677 INFO L85 PathProgramCache]: Analyzing trace with hash -2144970051, now seen corresponding path program 1 times [2023-11-29 07:09:53,677 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:53,677 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1161956924] [2023-11-29 07:09:53,678 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:53,678 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:53,681 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:53,682 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:53,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:53,686 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:53,686 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:53,686 INFO L85 PathProgramCache]: Analyzing trace with hash -444216697, now seen corresponding path program 1 times [2023-11-29 07:09:53,687 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:53,687 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1119446811] [2023-11-29 07:09:53,687 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:53,687 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:53,700 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:53,733 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:53,733 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:53,733 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1119446811] [2023-11-29 07:09:53,733 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1119446811] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:53,733 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:53,733 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:53,734 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [599361819] [2023-11-29 07:09:53,734 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:53,852 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:53,852 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:53,852 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:53,853 INFO L87 Difference]: Start difference. First operand 17087 states and 23179 transitions. cyclomatic complexity: 6118 Second operand has 3 states, 3 states have (on average 33.0) internal successors, (99), 3 states have internal predecessors, (99), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:53,986 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:53,986 INFO L93 Difference]: Finished difference Result 32100 states and 43203 transitions. [2023-11-29 07:09:53,986 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 32100 states and 43203 transitions. [2023-11-29 07:09:54,092 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 31628 [2023-11-29 07:09:54,177 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 32100 states to 32100 states and 43203 transitions. [2023-11-29 07:09:54,177 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 32100 [2023-11-29 07:09:54,195 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 32100 [2023-11-29 07:09:54,195 INFO L73 IsDeterministic]: Start isDeterministic. Operand 32100 states and 43203 transitions. [2023-11-29 07:09:54,213 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:54,214 INFO L218 hiAutomatonCegarLoop]: Abstraction has 32100 states and 43203 transitions. [2023-11-29 07:09:54,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 32100 states and 43203 transitions. [2023-11-29 07:09:54,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 32100 to 30292. [2023-11-29 07:09:54,505 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30292 states, 30292 states have (on average 1.3506866499405783) internal successors, (40915), 30291 states have internal predecessors, (40915), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:54,558 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30292 states to 30292 states and 40915 transitions. [2023-11-29 07:09:54,558 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30292 states and 40915 transitions. [2023-11-29 07:09:54,559 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:54,559 INFO L428 stractBuchiCegarLoop]: Abstraction has 30292 states and 40915 transitions. [2023-11-29 07:09:54,559 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-29 07:09:54,560 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30292 states and 40915 transitions. [2023-11-29 07:09:54,632 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 29820 [2023-11-29 07:09:54,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:54,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:54,633 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:54,634 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:54,634 INFO L748 eck$LassoCheckResult]: Stem: 385978#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 385979#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 386114#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 386115#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 385633#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 385634#L461-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 386188#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 386356#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 385723#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 385724#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 385894#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 385739#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 385740#L670 assume !(0 == ~M_E~0); 386131#L670-2 assume !(0 == ~T1_E~0); 386079#L675-1 assume !(0 == ~T2_E~0); 386080#L680-1 assume !(0 == ~T3_E~0); 386187#L685-1 assume !(0 == ~T4_E~0); 386140#L690-1 assume !(0 == ~T5_E~0); 386141#L695-1 assume !(0 == ~T6_E~0); 386237#L700-1 assume !(0 == ~E_1~0); 386223#L705-1 assume !(0 == ~E_2~0); 386224#L710-1 assume !(0 == ~E_3~0); 386078#L715-1 assume !(0 == ~E_4~0); 386007#L720-1 assume !(0 == ~E_5~0); 386008#L725-1 assume !(0 == ~E_6~0); 386057#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 386102#L320 assume !(1 == ~m_pc~0); 386259#L320-2 is_master_triggered_~__retres1~0#1 := 0; 385944#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 385937#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 385895#L825 assume !(0 != activate_threads_~tmp~1#1); 385896#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 385900#L339 assume !(1 == ~t1_pc~0); 385901#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 385869#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 385721#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 385722#L833 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 385745#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 390803#L358 assume !(1 == ~t2_pc~0); 390802#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 390801#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 390800#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 390799#L841 assume !(0 != activate_threads_~tmp___1~0#1); 390798#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 390797#L377 assume !(1 == ~t3_pc~0); 390795#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 390794#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 390793#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 390792#L849 assume !(0 != activate_threads_~tmp___2~0#1); 390791#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 390790#L396 assume !(1 == ~t4_pc~0); 390789#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 390788#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 390787#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 390786#L857 assume !(0 != activate_threads_~tmp___3~0#1); 390785#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 390784#L415 assume !(1 == ~t5_pc~0); 390783#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 390782#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 390781#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 390780#L865 assume !(0 != activate_threads_~tmp___4~0#1); 390779#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 390778#L434 assume !(1 == ~t6_pc~0); 390776#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 390775#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 390774#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 390773#L873 assume !(0 != activate_threads_~tmp___5~0#1); 390772#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 390771#L743 assume !(1 == ~M_E~0); 390770#L743-2 assume !(1 == ~T1_E~0); 390769#L748-1 assume !(1 == ~T2_E~0); 390768#L753-1 assume !(1 == ~T3_E~0); 390767#L758-1 assume !(1 == ~T4_E~0); 390766#L763-1 assume !(1 == ~T5_E~0); 390765#L768-1 assume !(1 == ~T6_E~0); 390764#L773-1 assume !(1 == ~E_1~0); 390763#L778-1 assume !(1 == ~E_2~0); 390762#L783-1 assume !(1 == ~E_3~0); 390761#L788-1 assume !(1 == ~E_4~0); 390760#L793-1 assume !(1 == ~E_5~0); 386123#L798-1 assume !(1 == ~E_6~0); 385764#L803-1 assume { :end_inline_reset_delta_events } true; 385765#L1024-2 assume !false; 391716#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 391708#L645-1 [2023-11-29 07:09:54,634 INFO L750 eck$LassoCheckResult]: Loop: 391708#L645-1 assume !false; 391703#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 391653#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 391646#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 391621#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 391615#L556 assume 0 != eval_~tmp~0#1; 391607#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 391599#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 391600#L564-2 havoc eval_~tmp_ndt_1~0#1; 391756#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 390725#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 391752#L578-2 havoc eval_~tmp_ndt_2~0#1; 391749#L575-1 assume !(0 == ~t2_st~0); 391739#L589-1 assume !(0 == ~t3_st~0); 391735#L603-1 assume !(0 == ~t4_st~0); 391723#L617-1 assume !(0 == ~t5_st~0); 391713#L631-1 assume !(0 == ~t6_st~0); 391708#L645-1 [2023-11-29 07:09:54,634 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:54,634 INFO L85 PathProgramCache]: Analyzing trace with hash -1610041797, now seen corresponding path program 1 times [2023-11-29 07:09:54,635 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:54,635 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [233297300] [2023-11-29 07:09:54,635 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:54,635 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:54,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:54,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:54,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:54,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [233297300] [2023-11-29 07:09:54,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [233297300] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:54,674 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:54,674 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:54,674 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [553371284] [2023-11-29 07:09:54,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:54,675 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 07:09:54,675 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:54,675 INFO L85 PathProgramCache]: Analyzing trace with hash 2044493828, now seen corresponding path program 1 times [2023-11-29 07:09:54,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:54,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [846048075] [2023-11-29 07:09:54,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:54,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:54,680 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:54,680 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:54,682 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:54,684 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:54,775 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:54,775 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:54,775 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:54,775 INFO L87 Difference]: Start difference. First operand 30292 states and 40915 transitions. cyclomatic complexity: 10649 Second operand has 3 states, 3 states have (on average 28.0) internal successors, (84), 3 states have internal predecessors, (84), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:54,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:54,946 INFO L93 Difference]: Finished difference Result 30211 states and 40806 transitions. [2023-11-29 07:09:54,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30211 states and 40806 transitions. [2023-11-29 07:09:55,050 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 29820 [2023-11-29 07:09:55,111 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30211 states to 30211 states and 40806 transitions. [2023-11-29 07:09:55,112 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30211 [2023-11-29 07:09:55,125 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30211 [2023-11-29 07:09:55,125 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30211 states and 40806 transitions. [2023-11-29 07:09:55,137 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:55,137 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30211 states and 40806 transitions. [2023-11-29 07:09:55,151 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30211 states and 40806 transitions. [2023-11-29 07:09:55,333 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30211 to 30211. [2023-11-29 07:09:55,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 30211 states, 30211 states have (on average 1.3507000761312105) internal successors, (40806), 30210 states have internal predecessors, (40806), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:55,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 30211 states to 30211 states and 40806 transitions. [2023-11-29 07:09:55,404 INFO L240 hiAutomatonCegarLoop]: Abstraction has 30211 states and 40806 transitions. [2023-11-29 07:09:55,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:55,405 INFO L428 stractBuchiCegarLoop]: Abstraction has 30211 states and 40806 transitions. [2023-11-29 07:09:55,405 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-29 07:09:55,405 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 30211 states and 40806 transitions. [2023-11-29 07:09:55,477 INFO L131 ngComponentsAnalysis]: Automaton has 26 accepting balls. 29820 [2023-11-29 07:09:55,477 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:55,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:55,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:55,478 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:55,479 INFO L748 eck$LassoCheckResult]: Stem: 446497#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 446498#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 446632#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 446633#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 446142#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 446143#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 446702#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 446863#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 446235#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 446236#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 446409#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 446251#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 446252#L670 assume !(0 == ~M_E~0); 446644#L670-2 assume !(0 == ~T1_E~0); 446596#L675-1 assume !(0 == ~T2_E~0); 446597#L680-1 assume !(0 == ~T3_E~0); 446701#L685-1 assume !(0 == ~T4_E~0); 446652#L690-1 assume !(0 == ~T5_E~0); 446653#L695-1 assume !(0 == ~T6_E~0); 446747#L700-1 assume !(0 == ~E_1~0); 446732#L705-1 assume !(0 == ~E_2~0); 446733#L710-1 assume !(0 == ~E_3~0); 446595#L715-1 assume !(0 == ~E_4~0); 446525#L720-1 assume !(0 == ~E_5~0); 446526#L725-1 assume !(0 == ~E_6~0); 446575#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 446622#L320 assume !(1 == ~m_pc~0); 446771#L320-2 is_master_triggered_~__retres1~0#1 := 0; 446461#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 446453#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 446410#L825 assume !(0 != activate_threads_~tmp~1#1); 446411#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 446415#L339 assume !(1 == ~t1_pc~0); 446416#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 446383#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 446233#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 446234#L833 assume !(0 != activate_threads_~tmp___0~0#1); 446256#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 446167#L358 assume !(1 == ~t2_pc~0); 446168#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 446724#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 446635#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 446578#L841 assume !(0 != activate_threads_~tmp___1~0#1); 446405#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 446406#L377 assume !(1 == ~t3_pc~0); 446677#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 446678#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 446163#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 446164#L849 assume !(0 != activate_threads_~tmp___2~0#1); 446414#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 446335#L396 assume !(1 == ~t4_pc~0); 446336#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 446169#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 446170#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 446318#L857 assume !(0 != activate_threads_~tmp___3~0#1); 446302#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 446303#L415 assume !(1 == ~t5_pc~0); 446388#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 446443#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 446464#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 446465#L865 assume !(0 != activate_threads_~tmp___4~0#1); 446211#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 446212#L434 assume !(1 == ~t6_pc~0); 446558#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 446559#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 446626#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 446627#L873 assume !(0 != activate_threads_~tmp___5~0#1); 446430#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 446431#L743 assume !(1 == ~M_E~0); 446293#L743-2 assume !(1 == ~T1_E~0); 446294#L748-1 assume !(1 == ~T2_E~0); 446616#L753-1 assume !(1 == ~T3_E~0); 446617#L758-1 assume !(1 == ~T4_E~0); 446751#L763-1 assume !(1 == ~T5_E~0); 446813#L768-1 assume !(1 == ~T6_E~0); 446424#L773-1 assume !(1 == ~E_1~0); 446425#L778-1 assume !(1 == ~E_2~0); 446399#L783-1 assume !(1 == ~E_3~0); 446400#L788-1 assume !(1 == ~E_4~0); 446699#L793-1 assume !(1 == ~E_5~0); 446641#L798-1 assume !(1 == ~E_6~0); 446273#L803-1 assume { :end_inline_reset_delta_events } true; 446274#L1024-2 assume !false; 461051#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 461041#L645-1 [2023-11-29 07:09:55,479 INFO L750 eck$LassoCheckResult]: Loop: 461041#L645-1 assume !false; 461036#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 461029#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 461026#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 460802#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 460801#L556 assume 0 != eval_~tmp~0#1; 460799#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 460796#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 460789#L564-2 havoc eval_~tmp_ndt_1~0#1; 459330#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 459328#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 459327#L578-2 havoc eval_~tmp_ndt_2~0#1; 459322#L575-1 assume !(0 == ~t2_st~0); 459318#L589-1 assume !(0 == ~t3_st~0); 459314#L603-1 assume !(0 == ~t4_st~0); 459315#L617-1 assume !(0 == ~t5_st~0); 461048#L631-1 assume !(0 == ~t6_st~0); 461041#L645-1 [2023-11-29 07:09:55,479 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:55,479 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 2 times [2023-11-29 07:09:55,479 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:55,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1632947068] [2023-11-29 07:09:55,480 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:55,480 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:55,493 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:55,494 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:55,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:55,521 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:55,521 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:55,522 INFO L85 PathProgramCache]: Analyzing trace with hash 2044493828, now seen corresponding path program 2 times [2023-11-29 07:09:55,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:55,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250125617] [2023-11-29 07:09:55,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:55,523 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:55,527 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:55,527 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:55,529 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:55,532 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:55,532 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:55,532 INFO L85 PathProgramCache]: Analyzing trace with hash 85927246, now seen corresponding path program 1 times [2023-11-29 07:09:55,533 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:55,533 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600334344] [2023-11-29 07:09:55,533 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:55,533 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:55,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:55,576 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:55,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:55,576 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600334344] [2023-11-29 07:09:55,577 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600334344] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:55,577 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:55,577 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:55,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1492421300] [2023-11-29 07:09:55,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:55,667 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:55,667 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:55,668 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:55,668 INFO L87 Difference]: Start difference. First operand 30211 states and 40806 transitions. cyclomatic complexity: 10621 Second operand has 3 states, 3 states have (on average 33.666666666666664) internal successors, (101), 3 states have internal predecessors, (101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:55,830 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:55,830 INFO L93 Difference]: Finished difference Result 40171 states and 53854 transitions. [2023-11-29 07:09:55,830 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40171 states and 53854 transitions. [2023-11-29 07:09:56,007 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 39676 [2023-11-29 07:09:56,095 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40171 states to 40171 states and 53854 transitions. [2023-11-29 07:09:56,095 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40171 [2023-11-29 07:09:56,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40171 [2023-11-29 07:09:56,115 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40171 states and 53854 transitions. [2023-11-29 07:09:56,131 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:56,131 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40171 states and 53854 transitions. [2023-11-29 07:09:56,153 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40171 states and 53854 transitions. [2023-11-29 07:09:56,387 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40171 to 38675. [2023-11-29 07:09:56,578 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38675 states, 38675 states have (on average 1.3438655462184874) internal successors, (51974), 38674 states have internal predecessors, (51974), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:56,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38675 states to 38675 states and 51974 transitions. [2023-11-29 07:09:56,689 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38675 states and 51974 transitions. [2023-11-29 07:09:56,690 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:56,690 INFO L428 stractBuchiCegarLoop]: Abstraction has 38675 states and 51974 transitions. [2023-11-29 07:09:56,691 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-29 07:09:56,691 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38675 states and 51974 transitions. [2023-11-29 07:09:56,807 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 38180 [2023-11-29 07:09:56,807 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:56,807 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:56,808 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:56,808 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:56,809 INFO L748 eck$LassoCheckResult]: Stem: 516876#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 516877#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 517019#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 517020#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 516532#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 516533#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 517090#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 517268#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 516624#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 516625#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 516795#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 516641#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 516642#L670 assume !(0 == ~M_E~0); 517031#L670-2 assume !(0 == ~T1_E~0); 516979#L675-1 assume !(0 == ~T2_E~0); 516980#L680-1 assume !(0 == ~T3_E~0); 517089#L685-1 assume !(0 == ~T4_E~0); 517040#L690-1 assume !(0 == ~T5_E~0); 517041#L695-1 assume !(0 == ~T6_E~0); 517136#L700-1 assume !(0 == ~E_1~0); 517122#L705-1 assume !(0 == ~E_2~0); 517123#L710-1 assume !(0 == ~E_3~0); 516977#L715-1 assume !(0 == ~E_4~0); 516906#L720-1 assume !(0 == ~E_5~0); 516907#L725-1 assume !(0 == ~E_6~0); 516955#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 517009#L320 assume !(1 == ~m_pc~0); 517160#L320-2 is_master_triggered_~__retres1~0#1 := 0; 516843#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 516835#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 516796#L825 assume !(0 != activate_threads_~tmp~1#1); 516797#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 516800#L339 assume !(1 == ~t1_pc~0); 516801#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 516769#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 516622#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 516623#L833 assume !(0 != activate_threads_~tmp___0~0#1); 516646#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 516557#L358 assume !(1 == ~t2_pc~0); 516558#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 517113#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 517022#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 516959#L841 assume !(0 != activate_threads_~tmp___1~0#1); 516791#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 516792#L377 assume !(1 == ~t3_pc~0); 517065#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 517066#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 516553#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 516554#L849 assume !(0 != activate_threads_~tmp___2~0#1); 516799#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 516725#L396 assume !(1 == ~t4_pc~0); 516726#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 516559#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 516560#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 516708#L857 assume !(0 != activate_threads_~tmp___3~0#1); 516692#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 516693#L415 assume !(1 == ~t5_pc~0); 516774#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 516825#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 516846#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 516847#L865 assume !(0 != activate_threads_~tmp___4~0#1); 516600#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 516601#L434 assume !(1 == ~t6_pc~0); 516938#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 516939#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 517013#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 517014#L873 assume !(0 != activate_threads_~tmp___5~0#1); 516813#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 516814#L743 assume !(1 == ~M_E~0); 516683#L743-2 assume !(1 == ~T1_E~0); 516684#L748-1 assume !(1 == ~T2_E~0); 517002#L753-1 assume !(1 == ~T3_E~0); 517003#L758-1 assume !(1 == ~T4_E~0); 517138#L763-1 assume !(1 == ~T5_E~0); 517209#L768-1 assume !(1 == ~T6_E~0); 516807#L773-1 assume !(1 == ~E_1~0); 516808#L778-1 assume !(1 == ~E_2~0); 516785#L783-1 assume !(1 == ~E_3~0); 516786#L788-1 assume !(1 == ~E_4~0); 517087#L793-1 assume !(1 == ~E_5~0); 517027#L798-1 assume !(1 == ~E_6~0); 516663#L803-1 assume { :end_inline_reset_delta_events } true; 516664#L1024-2 assume !false; 536359#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 536355#L645-1 [2023-11-29 07:09:56,809 INFO L750 eck$LassoCheckResult]: Loop: 536355#L645-1 assume !false; 536353#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 536350#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 536348#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 536347#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 536344#L556 assume 0 != eval_~tmp~0#1; 536340#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 536337#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 536335#L564-2 havoc eval_~tmp_ndt_1~0#1; 536332#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 536315#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 536330#L578-2 havoc eval_~tmp_ndt_2~0#1; 536379#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 536377#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 536374#L592-2 havoc eval_~tmp_ndt_3~0#1; 536372#L589-1 assume !(0 == ~t3_st~0); 536369#L603-1 assume !(0 == ~t4_st~0); 536363#L617-1 assume !(0 == ~t5_st~0); 536356#L631-1 assume !(0 == ~t6_st~0); 536355#L645-1 [2023-11-29 07:09:56,809 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:56,809 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 3 times [2023-11-29 07:09:56,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:56,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1452056171] [2023-11-29 07:09:56,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:56,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:56,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:56,821 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:56,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:56,849 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:56,849 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:56,849 INFO L85 PathProgramCache]: Analyzing trace with hash 1877482429, now seen corresponding path program 1 times [2023-11-29 07:09:56,850 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:56,850 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [193140777] [2023-11-29 07:09:56,850 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:56,850 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:56,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:56,855 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:56,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:56,860 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:56,861 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:56,861 INFO L85 PathProgramCache]: Analyzing trace with hash 890672775, now seen corresponding path program 1 times [2023-11-29 07:09:56,861 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:56,861 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1212557053] [2023-11-29 07:09:56,861 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:56,862 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:57,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:57,051 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:57,052 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:57,052 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1212557053] [2023-11-29 07:09:57,052 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1212557053] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:57,052 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:57,052 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:57,052 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [709592177] [2023-11-29 07:09:57,053 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:57,138 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:57,138 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:57,138 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:57,138 INFO L87 Difference]: Start difference. First operand 38675 states and 51974 transitions. cyclomatic complexity: 13327 Second operand has 3 states, 3 states have (on average 34.333333333333336) internal successors, (103), 3 states have internal predecessors, (103), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:57,422 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:57,422 INFO L93 Difference]: Finished difference Result 71281 states and 95256 transitions. [2023-11-29 07:09:57,422 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71281 states and 95256 transitions. [2023-11-29 07:09:57,730 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 70378 [2023-11-29 07:09:57,923 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71281 states to 71281 states and 95256 transitions. [2023-11-29 07:09:57,923 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71281 [2023-11-29 07:09:57,963 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71281 [2023-11-29 07:09:57,963 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71281 states and 95256 transitions. [2023-11-29 07:09:58,004 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:09:58,004 INFO L218 hiAutomatonCegarLoop]: Abstraction has 71281 states and 95256 transitions. [2023-11-29 07:09:58,047 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71281 states and 95256 transitions. [2023-11-29 07:09:58,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71281 to 67801. [2023-11-29 07:09:58,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67801 states, 67801 states have (on average 1.3429890414595655) internal successors, (91056), 67800 states have internal predecessors, (91056), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:59,020 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67801 states to 67801 states and 91056 transitions. [2023-11-29 07:09:59,020 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67801 states and 91056 transitions. [2023-11-29 07:09:59,021 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:09:59,022 INFO L428 stractBuchiCegarLoop]: Abstraction has 67801 states and 91056 transitions. [2023-11-29 07:09:59,022 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-29 07:09:59,022 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67801 states and 91056 transitions. [2023-11-29 07:09:59,199 INFO L131 ngComponentsAnalysis]: Automaton has 28 accepting balls. 66898 [2023-11-29 07:09:59,199 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:09:59,199 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:09:59,200 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:59,200 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:09:59,200 INFO L748 eck$LassoCheckResult]: Stem: 626844#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 626845#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 626993#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 626994#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 626496#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 626497#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 627069#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 627281#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 626589#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 626590#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 626760#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 626606#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 626607#L670 assume !(0 == ~M_E~0); 627007#L670-2 assume !(0 == ~T1_E~0); 626950#L675-1 assume !(0 == ~T2_E~0); 626951#L680-1 assume !(0 == ~T3_E~0); 627068#L685-1 assume !(0 == ~T4_E~0); 627015#L690-1 assume !(0 == ~T5_E~0); 627016#L695-1 assume !(0 == ~T6_E~0); 627121#L700-1 assume !(0 == ~E_1~0); 627105#L705-1 assume !(0 == ~E_2~0); 627106#L710-1 assume !(0 == ~E_3~0); 626949#L715-1 assume !(0 == ~E_4~0); 626874#L720-1 assume !(0 == ~E_5~0); 626875#L725-1 assume !(0 == ~E_6~0); 626927#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 626978#L320 assume !(1 == ~m_pc~0); 627146#L320-2 is_master_triggered_~__retres1~0#1 := 0; 626808#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 626802#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 626761#L825 assume !(0 != activate_threads_~tmp~1#1); 626762#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 626766#L339 assume !(1 == ~t1_pc~0); 626767#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 626736#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 626587#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 626588#L833 assume !(0 != activate_threads_~tmp___0~0#1); 626611#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 626521#L358 assume !(1 == ~t2_pc~0); 626522#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 627093#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 626996#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 626932#L841 assume !(0 != activate_threads_~tmp___1~0#1); 626756#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 626757#L377 assume !(1 == ~t3_pc~0); 627046#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 627047#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 626517#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 626518#L849 assume !(0 != activate_threads_~tmp___2~0#1); 626765#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 626693#L396 assume !(1 == ~t4_pc~0); 626694#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 626523#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 626524#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 626676#L857 assume !(0 != activate_threads_~tmp___3~0#1); 626660#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 626661#L415 assume !(1 == ~t5_pc~0); 626741#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 626792#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 626811#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 626812#L865 assume !(0 != activate_threads_~tmp___4~0#1); 626565#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 626566#L434 assume !(1 == ~t6_pc~0); 626907#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 626908#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 626983#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 626984#L873 assume !(0 != activate_threads_~tmp___5~0#1); 626779#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 626780#L743 assume !(1 == ~M_E~0); 626649#L743-2 assume !(1 == ~T1_E~0); 626650#L748-1 assume !(1 == ~T2_E~0); 626973#L753-1 assume !(1 == ~T3_E~0); 626974#L758-1 assume !(1 == ~T4_E~0); 627123#L763-1 assume !(1 == ~T5_E~0); 627206#L768-1 assume !(1 == ~T6_E~0); 626773#L773-1 assume !(1 == ~E_1~0); 626774#L778-1 assume !(1 == ~E_2~0); 626751#L783-1 assume !(1 == ~E_3~0); 626752#L788-1 assume !(1 == ~E_4~0); 627065#L793-1 assume !(1 == ~E_5~0); 627002#L798-1 assume !(1 == ~E_6~0); 626628#L803-1 assume { :end_inline_reset_delta_events } true; 626629#L1024-2 assume !false; 632119#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 632114#L645-1 [2023-11-29 07:09:59,200 INFO L750 eck$LassoCheckResult]: Loop: 632114#L645-1 assume !false; 632111#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 632108#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 632106#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 632104#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 632101#L556 assume 0 != eval_~tmp~0#1; 632098#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 632095#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 632094#L564-2 havoc eval_~tmp_ndt_1~0#1; 632092#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 631865#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 632088#L578-2 havoc eval_~tmp_ndt_2~0#1; 632086#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 632083#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 632082#L592-2 havoc eval_~tmp_ndt_3~0#1; 632080#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 631360#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 632077#L606-2 havoc eval_~tmp_ndt_4~0#1; 632162#L603-1 assume !(0 == ~t4_st~0); 632157#L617-1 assume !(0 == ~t5_st~0); 632116#L631-1 assume !(0 == ~t6_st~0); 632114#L645-1 [2023-11-29 07:09:59,201 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:59,201 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 4 times [2023-11-29 07:09:59,201 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:59,201 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [747875515] [2023-11-29 07:09:59,201 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:59,201 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:59,216 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:59,216 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:59,224 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:59,247 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:59,247 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:59,247 INFO L85 PathProgramCache]: Analyzing trace with hash -1290620220, now seen corresponding path program 1 times [2023-11-29 07:09:59,248 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:59,248 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [767063924] [2023-11-29 07:09:59,248 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:59,248 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:59,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:59,252 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:09:59,255 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:09:59,257 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:09:59,258 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:09:59,258 INFO L85 PathProgramCache]: Analyzing trace with hash -426925298, now seen corresponding path program 1 times [2023-11-29 07:09:59,258 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:09:59,258 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1547727200] [2023-11-29 07:09:59,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:09:59,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:09:59,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:09:59,308 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:09:59,309 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:09:59,309 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1547727200] [2023-11-29 07:09:59,309 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1547727200] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:09:59,309 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:09:59,309 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:09:59,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [408771590] [2023-11-29 07:09:59,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:09:59,408 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:09:59,409 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:09:59,409 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:09:59,409 INFO L87 Difference]: Start difference. First operand 67801 states and 91056 transitions. cyclomatic complexity: 23283 Second operand has 3 states, 3 states have (on average 35.0) internal successors, (105), 3 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:09:59,960 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:09:59,960 INFO L93 Difference]: Finished difference Result 91830 states and 122575 transitions. [2023-11-29 07:09:59,960 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91830 states and 122575 transitions. [2023-11-29 07:10:00,253 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 90663 [2023-11-29 07:10:00,567 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91830 states to 91830 states and 122575 transitions. [2023-11-29 07:10:00,567 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91830 [2023-11-29 07:10:00,596 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91830 [2023-11-29 07:10:00,596 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91830 states and 122575 transitions. [2023-11-29 07:10:00,624 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:10:00,625 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91830 states and 122575 transitions. [2023-11-29 07:10:00,664 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91830 states and 122575 transitions. [2023-11-29 07:10:01,245 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91830 to 90150. [2023-11-29 07:10:01,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 90150 states, 90150 states have (on average 1.3383804769828065) internal successors, (120655), 90149 states have internal predecessors, (120655), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:10:01,472 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 90150 states to 90150 states and 120655 transitions. [2023-11-29 07:10:01,472 INFO L240 hiAutomatonCegarLoop]: Abstraction has 90150 states and 120655 transitions. [2023-11-29 07:10:01,473 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:10:01,473 INFO L428 stractBuchiCegarLoop]: Abstraction has 90150 states and 120655 transitions. [2023-11-29 07:10:01,473 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-29 07:10:01,474 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 90150 states and 120655 transitions. [2023-11-29 07:10:01,902 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 88983 [2023-11-29 07:10:01,903 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:10:01,903 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:10:01,904 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:10:01,904 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:10:01,904 INFO L748 eck$LassoCheckResult]: Stem: 786482#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 786483#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 786632#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 786633#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 786135#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 786136#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 786710#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 786883#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 786227#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 786228#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 786401#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 786243#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 786244#L670 assume !(0 == ~M_E~0); 786650#L670-2 assume !(0 == ~T1_E~0); 786588#L675-1 assume !(0 == ~T2_E~0); 786589#L680-1 assume !(0 == ~T3_E~0); 786709#L685-1 assume !(0 == ~T4_E~0); 786658#L690-1 assume !(0 == ~T5_E~0); 786659#L695-1 assume !(0 == ~T6_E~0); 786759#L700-1 assume !(0 == ~E_1~0); 786743#L705-1 assume !(0 == ~E_2~0); 786744#L710-1 assume !(0 == ~E_3~0); 786587#L715-1 assume !(0 == ~E_4~0); 786511#L720-1 assume !(0 == ~E_5~0); 786512#L725-1 assume !(0 == ~E_6~0); 786564#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 786619#L320 assume !(1 == ~m_pc~0); 786777#L320-2 is_master_triggered_~__retres1~0#1 := 0; 786448#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 786442#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 786402#L825 assume !(0 != activate_threads_~tmp~1#1); 786403#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 786406#L339 assume !(1 == ~t1_pc~0); 786407#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 786378#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 786225#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 786226#L833 assume !(0 != activate_threads_~tmp___0~0#1); 786250#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 786160#L358 assume !(1 == ~t2_pc~0); 786161#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 786733#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 786635#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 786569#L841 assume !(0 != activate_threads_~tmp___1~0#1); 786397#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 786398#L377 assume !(1 == ~t3_pc~0); 786684#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 786685#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 786156#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 786157#L849 assume !(0 != activate_threads_~tmp___2~0#1); 786405#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 786333#L396 assume !(1 == ~t4_pc~0); 786334#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 786162#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 786163#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 786316#L857 assume !(0 != activate_threads_~tmp___3~0#1); 786300#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 786301#L415 assume !(1 == ~t5_pc~0); 786383#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 786432#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 786451#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 786452#L865 assume !(0 != activate_threads_~tmp___4~0#1); 786203#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 786204#L434 assume !(1 == ~t6_pc~0); 786543#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 786544#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 786623#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 786624#L873 assume !(0 != activate_threads_~tmp___5~0#1); 786419#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 786420#L743 assume !(1 == ~M_E~0); 786289#L743-2 assume !(1 == ~T1_E~0); 786290#L748-1 assume !(1 == ~T2_E~0); 786613#L753-1 assume !(1 == ~T3_E~0); 786614#L758-1 assume !(1 == ~T4_E~0); 786761#L763-1 assume !(1 == ~T5_E~0); 786820#L768-1 assume !(1 == ~T6_E~0); 786413#L773-1 assume !(1 == ~E_1~0); 786414#L778-1 assume !(1 == ~E_2~0); 786392#L783-1 assume !(1 == ~E_3~0); 786393#L788-1 assume !(1 == ~E_4~0); 786707#L793-1 assume !(1 == ~E_5~0); 786642#L798-1 assume !(1 == ~E_6~0); 786269#L803-1 assume { :end_inline_reset_delta_events } true; 786270#L1024-2 assume !false; 805013#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 805008#L645-1 [2023-11-29 07:10:01,904 INFO L750 eck$LassoCheckResult]: Loop: 805008#L645-1 assume !false; 805006#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 805003#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 805001#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 804998#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 804994#L556 assume 0 != eval_~tmp~0#1; 804991#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 804988#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 804985#L564-2 havoc eval_~tmp_ndt_1~0#1; 804983#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 804825#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 804898#L578-2 havoc eval_~tmp_ndt_2~0#1; 805036#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 805033#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 805031#L592-2 havoc eval_~tmp_ndt_3~0#1; 805030#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 804904#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 805027#L606-2 havoc eval_~tmp_ndt_4~0#1; 805025#L603-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 805022#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 805021#L620-2 havoc eval_~tmp_ndt_5~0#1; 805017#L617-1 assume !(0 == ~t5_st~0); 805010#L631-1 assume !(0 == ~t6_st~0); 805008#L645-1 [2023-11-29 07:10:01,905 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:10:01,905 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 5 times [2023-11-29 07:10:01,905 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:10:01,906 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1357949796] [2023-11-29 07:10:01,906 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:10:01,906 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:10:01,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:01,918 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:10:01,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:01,952 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:10:01,952 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:10:01,952 INFO L85 PathProgramCache]: Analyzing trace with hash 767472829, now seen corresponding path program 1 times [2023-11-29 07:10:01,953 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:10:01,953 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1468144975] [2023-11-29 07:10:01,953 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:10:01,953 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:10:01,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:01,958 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:10:01,962 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:01,965 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:10:01,966 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:10:01,966 INFO L85 PathProgramCache]: Analyzing trace with hash 1849604743, now seen corresponding path program 1 times [2023-11-29 07:10:01,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:10:01,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [665049249] [2023-11-29 07:10:01,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:10:01,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:10:01,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:10:02,020 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:10:02,020 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:10:02,021 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [665049249] [2023-11-29 07:10:02,021 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [665049249] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:10:02,021 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:10:02,021 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 07:10:02,021 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1381099111] [2023-11-29 07:10:02,021 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:10:02,134 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:10:02,135 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:10:02,135 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:10:02,135 INFO L87 Difference]: Start difference. First operand 90150 states and 120655 transitions. cyclomatic complexity: 30535 Second operand has 3 states, 3 states have (on average 35.666666666666664) internal successors, (107), 3 states have internal predecessors, (107), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:10:02,658 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:10:02,658 INFO L93 Difference]: Finished difference Result 133761 states and 177880 transitions. [2023-11-29 07:10:02,658 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 133761 states and 177880 transitions. [2023-11-29 07:10:03,275 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 132066 [2023-11-29 07:10:03,537 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 133761 states to 133761 states and 177880 transitions. [2023-11-29 07:10:03,537 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 133761 [2023-11-29 07:10:03,591 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 133761 [2023-11-29 07:10:03,592 INFO L73 IsDeterministic]: Start isDeterministic. Operand 133761 states and 177880 transitions. [2023-11-29 07:10:03,817 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:10:03,817 INFO L218 hiAutomatonCegarLoop]: Abstraction has 133761 states and 177880 transitions. [2023-11-29 07:10:03,867 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 133761 states and 177880 transitions. [2023-11-29 07:10:04,822 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 133761 to 129729. [2023-11-29 07:10:04,898 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 129729 states, 129729 states have (on average 1.3334258338536487) internal successors, (172984), 129728 states have internal predecessors, (172984), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:10:05,432 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 129729 states to 129729 states and 172984 transitions. [2023-11-29 07:10:05,432 INFO L240 hiAutomatonCegarLoop]: Abstraction has 129729 states and 172984 transitions. [2023-11-29 07:10:05,433 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:10:05,433 INFO L428 stractBuchiCegarLoop]: Abstraction has 129729 states and 172984 transitions. [2023-11-29 07:10:05,434 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-29 07:10:05,434 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 129729 states and 172984 transitions. [2023-11-29 07:10:05,807 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 128034 [2023-11-29 07:10:05,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:10:05,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:10:05,809 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:10:05,809 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:10:05,809 INFO L748 eck$LassoCheckResult]: Stem: 1010403#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1010404#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1010559#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1010560#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1010054#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1010055#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1010636#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1010844#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1010147#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1010148#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1010324#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1010164#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1010165#L670 assume !(0 == ~M_E~0); 1010577#L670-2 assume !(0 == ~T1_E~0); 1010514#L675-1 assume !(0 == ~T2_E~0); 1010515#L680-1 assume !(0 == ~T3_E~0); 1010635#L685-1 assume !(0 == ~T4_E~0); 1010584#L690-1 assume !(0 == ~T5_E~0); 1010585#L695-1 assume !(0 == ~T6_E~0); 1010697#L700-1 assume !(0 == ~E_1~0); 1010679#L705-1 assume !(0 == ~E_2~0); 1010680#L710-1 assume !(0 == ~E_3~0); 1010513#L715-1 assume !(0 == ~E_4~0); 1010432#L720-1 assume !(0 == ~E_5~0); 1010433#L725-1 assume !(0 == ~E_6~0); 1010491#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1010546#L320 assume !(1 == ~m_pc~0); 1010720#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1010371#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1010364#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1010325#L825 assume !(0 != activate_threads_~tmp~1#1); 1010326#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1010330#L339 assume !(1 == ~t1_pc~0); 1010331#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1010300#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1010145#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1010146#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1010170#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1010079#L358 assume !(1 == ~t2_pc~0); 1010080#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1010670#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1010564#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1010496#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1010320#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1010321#L377 assume !(1 == ~t3_pc~0); 1010612#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1010613#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1010075#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1010076#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1010329#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1010252#L396 assume !(1 == ~t4_pc~0); 1010253#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1010081#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1010082#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1010234#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1010219#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1010220#L415 assume !(1 == ~t5_pc~0); 1010305#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1010355#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1010374#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1010375#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1010123#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1010124#L434 assume !(1 == ~t6_pc~0); 1010465#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1010466#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1010551#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1010552#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1010342#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1010343#L743 assume !(1 == ~M_E~0); 1010208#L743-2 assume !(1 == ~T1_E~0); 1010209#L748-1 assume !(1 == ~T2_E~0); 1010538#L753-1 assume !(1 == ~T3_E~0); 1010539#L758-1 assume !(1 == ~T4_E~0); 1010700#L763-1 assume !(1 == ~T5_E~0); 1010769#L768-1 assume !(1 == ~T6_E~0); 1010336#L773-1 assume !(1 == ~E_1~0); 1010337#L778-1 assume !(1 == ~E_2~0); 1010315#L783-1 assume !(1 == ~E_3~0); 1010316#L788-1 assume !(1 == ~E_4~0); 1010632#L793-1 assume !(1 == ~E_5~0); 1010572#L798-1 assume !(1 == ~E_6~0); 1010187#L803-1 assume { :end_inline_reset_delta_events } true; 1010188#L1024-2 assume !false; 1095013#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1095008#L645-1 [2023-11-29 07:10:05,810 INFO L750 eck$LassoCheckResult]: Loop: 1095008#L645-1 assume !false; 1095006#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1095003#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1095004#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1122206#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1122205#L556 assume 0 != eval_~tmp~0#1; 1122204#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1122202#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1122203#L564-2 havoc eval_~tmp_ndt_1~0#1; 1057033#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1057030#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1057028#L578-2 havoc eval_~tmp_ndt_2~0#1; 1057026#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1057023#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1057020#L592-2 havoc eval_~tmp_ndt_3~0#1; 1057018#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1056997#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1057016#L606-2 havoc eval_~tmp_ndt_4~0#1; 1057243#L603-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1057240#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1057241#L620-2 havoc eval_~tmp_ndt_5~0#1; 1095032#L617-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1095029#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1095026#L634-2 havoc eval_~tmp_ndt_6~0#1; 1095010#L631-1 assume !(0 == ~t6_st~0); 1095008#L645-1 [2023-11-29 07:10:05,810 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:10:05,810 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 6 times [2023-11-29 07:10:05,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:10:05,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1812778161] [2023-11-29 07:10:05,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:10:05,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:10:05,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:05,825 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:10:05,834 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:05,858 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:10:05,858 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:10:05,859 INFO L85 PathProgramCache]: Analyzing trace with hash -1198969468, now seen corresponding path program 1 times [2023-11-29 07:10:05,859 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:10:05,859 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1827869784] [2023-11-29 07:10:05,859 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:10:05,859 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:10:05,864 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:05,864 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:10:05,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:05,869 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:10:05,870 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:10:05,870 INFO L85 PathProgramCache]: Analyzing trace with hash -652285746, now seen corresponding path program 1 times [2023-11-29 07:10:05,870 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:10:05,870 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592519208] [2023-11-29 07:10:05,871 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:10:05,871 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:10:05,884 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 07:10:05,921 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 07:10:05,921 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 07:10:05,921 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592519208] [2023-11-29 07:10:05,921 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1592519208] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 07:10:05,921 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 07:10:05,921 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 07:10:05,922 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119862308] [2023-11-29 07:10:05,922 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 07:10:06,037 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 07:10:06,038 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 07:10:06,038 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 07:10:06,038 INFO L87 Difference]: Start difference. First operand 129729 states and 172984 transitions. cyclomatic complexity: 43285 Second operand has 3 states, 2 states have (on average 54.5) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:10:07,171 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 07:10:07,172 INFO L93 Difference]: Finished difference Result 245428 states and 325593 transitions. [2023-11-29 07:10:07,172 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 245428 states and 325593 transitions. [2023-11-29 07:10:08,321 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 242125 [2023-11-29 07:10:08,795 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 245428 states to 245428 states and 325593 transitions. [2023-11-29 07:10:08,795 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 245428 [2023-11-29 07:10:08,885 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 245428 [2023-11-29 07:10:08,885 INFO L73 IsDeterministic]: Start isDeterministic. Operand 245428 states and 325593 transitions. [2023-11-29 07:10:08,961 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 07:10:08,961 INFO L218 hiAutomatonCegarLoop]: Abstraction has 245428 states and 325593 transitions. [2023-11-29 07:10:09,061 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 245428 states and 325593 transitions. [2023-11-29 07:10:11,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 245428 to 245428. [2023-11-29 07:10:11,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 245428 states, 245428 states have (on average 1.3266334729533713) internal successors, (325593), 245427 states have internal predecessors, (325593), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 07:10:12,260 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 245428 states to 245428 states and 325593 transitions. [2023-11-29 07:10:12,260 INFO L240 hiAutomatonCegarLoop]: Abstraction has 245428 states and 325593 transitions. [2023-11-29 07:10:12,261 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 07:10:12,261 INFO L428 stractBuchiCegarLoop]: Abstraction has 245428 states and 325593 transitions. [2023-11-29 07:10:12,261 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-29 07:10:12,261 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 245428 states and 325593 transitions. [2023-11-29 07:10:12,888 INFO L131 ngComponentsAnalysis]: Automaton has 30 accepting balls. 242125 [2023-11-29 07:10:12,888 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 07:10:12,888 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 07:10:12,889 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:10:12,889 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 07:10:12,890 INFO L748 eck$LassoCheckResult]: Stem: 1385559#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2; 1385560#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~8#1;havoc main_~__retres1~8#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1; 1385710#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret20#1, start_simulation_#t~ret21#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1385711#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1385219#L461 assume 1 == ~m_i~0;~m_st~0 := 0; 1385220#L461-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1385786#L466-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1385977#L471-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1385310#L476-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1385311#L481-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1385478#L486-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1385326#L491-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1385327#L670 assume !(0 == ~M_E~0); 1385730#L670-2 assume !(0 == ~T1_E~0); 1385668#L675-1 assume !(0 == ~T2_E~0); 1385669#L680-1 assume !(0 == ~T3_E~0); 1385785#L685-1 assume !(0 == ~T4_E~0); 1385738#L690-1 assume !(0 == ~T5_E~0); 1385739#L695-1 assume !(0 == ~T6_E~0); 1385840#L700-1 assume !(0 == ~E_1~0); 1385824#L705-1 assume !(0 == ~E_2~0); 1385825#L710-1 assume !(0 == ~E_3~0); 1385666#L715-1 assume !(0 == ~E_4~0); 1385588#L720-1 assume !(0 == ~E_5~0); 1385589#L725-1 assume !(0 == ~E_6~0); 1385644#L730-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1385697#L320 assume !(1 == ~m_pc~0); 1385863#L320-2 is_master_triggered_~__retres1~0#1 := 0; 1385526#L331 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1385519#is_master_triggered_returnLabel#1 activate_threads_#t~ret12#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret12#1;havoc activate_threads_#t~ret12#1; 1385479#L825 assume !(0 != activate_threads_~tmp~1#1); 1385480#L825-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1385484#L339 assume !(1 == ~t1_pc~0); 1385485#L339-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1385454#L350 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1385308#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1385309#L833 assume !(0 != activate_threads_~tmp___0~0#1); 1385331#L833-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1385244#L358 assume !(1 == ~t2_pc~0); 1385245#L358-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1385814#L369 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1385715#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1385648#L841 assume !(0 != activate_threads_~tmp___1~0#1); 1385474#L841-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1385475#L377 assume !(1 == ~t3_pc~0); 1385764#L377-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1385765#L388 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1385240#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1385241#L849 assume !(0 != activate_threads_~tmp___2~0#1); 1385483#L849-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1385412#L396 assume !(1 == ~t4_pc~0); 1385413#L396-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1385246#L407 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1385247#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1385394#L857 assume !(0 != activate_threads_~tmp___3~0#1); 1385378#L857-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1385379#L415 assume !(1 == ~t5_pc~0); 1385459#L415-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1385509#L426 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1385529#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1385530#L865 assume !(0 != activate_threads_~tmp___4~0#1); 1385286#L865-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1385287#L434 assume !(1 == ~t6_pc~0); 1385622#L434-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1385623#L445 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1385702#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1385703#L873 assume !(0 != activate_threads_~tmp___5~0#1); 1385496#L873-2 havoc activate_threads_#t~ret12#1, activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1385497#L743 assume !(1 == ~M_E~0); 1385368#L743-2 assume !(1 == ~T1_E~0); 1385369#L748-1 assume !(1 == ~T2_E~0); 1385691#L753-1 assume !(1 == ~T3_E~0); 1385692#L758-1 assume !(1 == ~T4_E~0); 1385842#L763-1 assume !(1 == ~T5_E~0); 1385914#L768-1 assume !(1 == ~T6_E~0); 1385490#L773-1 assume !(1 == ~E_1~0); 1385491#L778-1 assume !(1 == ~E_2~0); 1385468#L783-1 assume !(1 == ~E_3~0); 1385469#L788-1 assume !(1 == ~E_4~0); 1385782#L793-1 assume !(1 == ~E_5~0); 1385724#L798-1 assume !(1 == ~E_6~0); 1385348#L803-1 assume { :end_inline_reset_delta_events } true; 1385349#L1024-2 assume !false; 1482364#L1025 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1482362#L645-1 [2023-11-29 07:10:12,890 INFO L750 eck$LassoCheckResult]: Loop: 1482362#L645-1 assume !false; 1482360#L552 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;havoc exists_runnable_thread_~__retres1~7#1; 1482293#L504 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~7#1 := 1; 1482294#L541 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~7#1; 1482287#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~7#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1482283#L556 assume 0 != eval_~tmp~0#1; 1482284#L556-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1488660#L564 assume !(0 != eval_~tmp_ndt_1~0#1); 1488657#L564-2 havoc eval_~tmp_ndt_1~0#1; 1436570#L561-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1436566#L578 assume !(0 != eval_~tmp_ndt_2~0#1); 1436564#L578-2 havoc eval_~tmp_ndt_2~0#1; 1436561#L575-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1436558#L592 assume !(0 != eval_~tmp_ndt_3~0#1); 1436556#L592-2 havoc eval_~tmp_ndt_3~0#1; 1436554#L589-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1436515#L606 assume !(0 != eval_~tmp_ndt_4~0#1); 1436552#L606-2 havoc eval_~tmp_ndt_4~0#1; 1437384#L603-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1437381#L620 assume !(0 != eval_~tmp_ndt_5~0#1); 1437379#L620-2 havoc eval_~tmp_ndt_5~0#1; 1437377#L617-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1437374#L634 assume !(0 != eval_~tmp_ndt_6~0#1); 1437372#L634-2 havoc eval_~tmp_ndt_6~0#1; 1437370#L631-1 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1437353#L648 assume !(0 != eval_~tmp_ndt_7~0#1); 1437368#L648-2 havoc eval_~tmp_ndt_7~0#1; 1482362#L645-1 [2023-11-29 07:10:12,890 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:10:12,891 INFO L85 PathProgramCache]: Analyzing trace with hash 88880503, now seen corresponding path program 7 times [2023-11-29 07:10:12,891 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:10:12,891 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [71739748] [2023-11-29 07:10:12,891 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:10:12,891 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:10:12,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:12,903 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:10:12,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:12,931 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:10:12,931 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:10:12,931 INFO L85 PathProgramCache]: Analyzing trace with hash -1158409573, now seen corresponding path program 1 times [2023-11-29 07:10:12,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:10:12,932 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1457269045] [2023-11-29 07:10:12,932 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:10:12,932 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:10:12,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:12,936 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:10:12,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:12,940 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:10:12,940 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 07:10:12,941 INFO L85 PathProgramCache]: Analyzing trace with hash 218637157, now seen corresponding path program 1 times [2023-11-29 07:10:12,941 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 07:10:12,941 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2126472152] [2023-11-29 07:10:12,941 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 07:10:12,941 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 07:10:12,951 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:12,951 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:10:12,958 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:13,371 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 07:10:15,193 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:15,194 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 07:10:15,221 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 07:10:15,406 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 29.11 07:10:15 BoogieIcfgContainer [2023-11-29 07:10:15,407 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-29 07:10:15,407 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-29 07:10:15,407 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-29 07:10:15,408 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-29 07:10:15,408 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 07:09:41" (3/4) ... [2023-11-29 07:10:15,409 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-29 07:10:15,515 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/witness.graphml [2023-11-29 07:10:15,515 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-29 07:10:15,516 INFO L158 Benchmark]: Toolchain (without parser) took 35754.83ms. Allocated memory was 140.5MB in the beginning and 11.6GB in the end (delta: 11.5GB). Free memory was 94.0MB in the beginning and 8.6GB in the end (delta: -8.5GB). Peak memory consumption was 3.0GB. Max. memory is 16.1GB. [2023-11-29 07:10:15,516 INFO L158 Benchmark]: CDTParser took 0.22ms. Allocated memory is still 140.5MB. Free memory is still 112.8MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-29 07:10:15,516 INFO L158 Benchmark]: CACSL2BoogieTranslator took 429.07ms. Allocated memory is still 140.5MB. Free memory was 93.5MB in the beginning and 76.6MB in the end (delta: 16.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-29 07:10:15,517 INFO L158 Benchmark]: Boogie Procedure Inliner took 75.95ms. Allocated memory is still 140.5MB. Free memory was 76.6MB in the beginning and 71.0MB in the end (delta: 5.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-29 07:10:15,517 INFO L158 Benchmark]: Boogie Preprocessor took 120.95ms. Allocated memory is still 140.5MB. Free memory was 71.0MB in the beginning and 64.1MB in the end (delta: 6.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-29 07:10:15,517 INFO L158 Benchmark]: RCFGBuilder took 1297.47ms. Allocated memory was 140.5MB in the beginning and 195.0MB in the end (delta: 54.5MB). Free memory was 64.1MB in the beginning and 112.2MB in the end (delta: -48.1MB). Peak memory consumption was 32.7MB. Max. memory is 16.1GB. [2023-11-29 07:10:15,518 INFO L158 Benchmark]: BuchiAutomizer took 33716.76ms. Allocated memory was 195.0MB in the beginning and 11.6GB in the end (delta: 11.4GB). Free memory was 112.2MB in the beginning and 8.6GB in the end (delta: -8.5GB). Peak memory consumption was 2.9GB. Max. memory is 16.1GB. [2023-11-29 07:10:15,518 INFO L158 Benchmark]: Witness Printer took 108.07ms. Allocated memory is still 11.6GB. Free memory was 8.6GB in the beginning and 8.6GB in the end (delta: 13.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. [2023-11-29 07:10:15,520 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.22ms. Allocated memory is still 140.5MB. Free memory is still 112.8MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 429.07ms. Allocated memory is still 140.5MB. Free memory was 93.5MB in the beginning and 76.6MB in the end (delta: 16.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 75.95ms. Allocated memory is still 140.5MB. Free memory was 76.6MB in the beginning and 71.0MB in the end (delta: 5.7MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 120.95ms. Allocated memory is still 140.5MB. Free memory was 71.0MB in the beginning and 64.1MB in the end (delta: 6.9MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * RCFGBuilder took 1297.47ms. Allocated memory was 140.5MB in the beginning and 195.0MB in the end (delta: 54.5MB). Free memory was 64.1MB in the beginning and 112.2MB in the end (delta: -48.1MB). Peak memory consumption was 32.7MB. Max. memory is 16.1GB. * BuchiAutomizer took 33716.76ms. Allocated memory was 195.0MB in the beginning and 11.6GB in the end (delta: 11.4GB). Free memory was 112.2MB in the beginning and 8.6GB in the end (delta: -8.5GB). Peak memory consumption was 2.9GB. Max. memory is 16.1GB. * Witness Printer took 108.07ms. Allocated memory is still 11.6GB. Free memory was 8.6GB in the beginning and 8.6GB in the end (delta: 13.6MB). Peak memory consumption was 12.6MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 31 terminating modules (31 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.31 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 245428 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 33.5s and 32 iterations. TraceHistogramMax:1. Analysis of lassos took 6.9s. Construction of modules took 1.1s. Büchi inclusion checks took 22.8s. Highest rank in rank-based complementation 0. Minimization of det autom 31. Minimization of nondet autom 0. Automata minimization 10.8s AutomataMinimizationTime, 31 MinimizatonAttempts, 74539 StatesRemovedByMinimization, 21 NontrivialMinimizations. Non-live state removal took 6.2s Buchi closure took 0.4s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 32416 SdHoareTripleChecker+Valid, 1.4s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 32416 mSDsluCounter, 57339 SdHoareTripleChecker+Invalid, 1.1s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 24112 mSDsCounter, 347 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 970 IncrementalHoareTripleChecker+Invalid, 1317 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 347 mSolverCounterUnsat, 33227 mSDtfsCounter, 970 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc6 concLT0 SILN1 SILU0 SILI19 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 551]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int m_st ; [L33] int t1_st ; [L34] int t2_st ; [L35] int t3_st ; [L36] int t4_st ; [L37] int t5_st ; [L38] int t6_st ; [L39] int m_i ; [L40] int t1_i ; [L41] int t2_i ; [L42] int t3_i ; [L43] int t4_i ; [L44] int t5_i ; [L45] int t6_i ; [L46] int M_E = 2; [L47] int T1_E = 2; [L48] int T2_E = 2; [L49] int T3_E = 2; [L50] int T4_E = 2; [L51] int T5_E = 2; [L52] int T6_E = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0] [L1069] int __retres1 ; [L1073] CALL init_model() [L979] m_i = 1 [L980] t1_i = 1 [L981] t2_i = 1 [L982] t3_i = 1 [L983] t4_i = 1 [L984] t5_i = 1 [L985] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1073] RET init_model() [L1074] CALL start_simulation() [L1010] int kernel_st ; [L1011] int tmp ; [L1012] int tmp___0 ; [L1016] kernel_st = 0 [L1017] FCALL update_channels() [L1018] CALL init_threads() [L461] COND TRUE m_i == 1 [L462] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t1_i == 1 [L467] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t2_i == 1 [L472] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t3_i == 1 [L477] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t4_i == 1 [L482] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L486] COND TRUE t5_i == 1 [L487] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L491] COND TRUE t6_i == 1 [L492] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1018] RET init_threads() [L1019] CALL fire_delta_events() [L670] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L725] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L730] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1019] RET fire_delta_events() [L1020] CALL activate_threads() [L813] int tmp ; [L814] int tmp___0 ; [L815] int tmp___1 ; [L816] int tmp___2 ; [L817] int tmp___3 ; [L818] int tmp___4 ; [L819] int tmp___5 ; [L823] CALL, EXPR is_master_triggered() [L317] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L320] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L330] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L332] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L823] RET, EXPR is_master_triggered() [L823] tmp = is_master_triggered() [L825] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0] [L831] CALL, EXPR is_transmit1_triggered() [L336] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L339] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L349] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L351] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] RET, EXPR is_transmit1_triggered() [L831] tmp___0 = is_transmit1_triggered() [L833] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0] [L839] CALL, EXPR is_transmit2_triggered() [L355] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L358] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L368] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L370] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] RET, EXPR is_transmit2_triggered() [L839] tmp___1 = is_transmit2_triggered() [L841] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0] [L847] CALL, EXPR is_transmit3_triggered() [L374] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L377] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L387] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L389] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] RET, EXPR is_transmit3_triggered() [L847] tmp___2 = is_transmit3_triggered() [L849] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L855] CALL, EXPR is_transmit4_triggered() [L393] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L396] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L406] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L408] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] RET, EXPR is_transmit4_triggered() [L855] tmp___3 = is_transmit4_triggered() [L857] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L863] CALL, EXPR is_transmit5_triggered() [L412] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L415] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L425] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L427] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] RET, EXPR is_transmit5_triggered() [L863] tmp___4 = is_transmit5_triggered() [L865] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L871] CALL, EXPR is_transmit6_triggered() [L431] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L434] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L444] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L446] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] RET, EXPR is_transmit6_triggered() [L871] tmp___5 = is_transmit6_triggered() [L873] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L1020] RET activate_threads() [L1021] CALL reset_delta_events() [L743] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L798] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L803] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1021] RET reset_delta_events() [L1024] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1027] kernel_st = 1 [L1028] CALL eval() [L547] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] Loop: [L551] COND TRUE 1 [L554] CALL, EXPR exists_runnable_thread() [L501] int __retres1 ; [L504] COND TRUE m_st == 0 [L505] __retres1 = 1 [L542] return (__retres1); [L554] RET, EXPR exists_runnable_thread() [L554] tmp = exists_runnable_thread() [L556] COND TRUE \read(tmp) [L561] COND TRUE m_st == 0 [L562] int tmp_ndt_1; [L563] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L564] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L561-L572] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L575] COND TRUE t1_st == 0 [L576] int tmp_ndt_2; [L577] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L578] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L575-L586] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L589] COND TRUE t2_st == 0 [L590] int tmp_ndt_3; [L591] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L592] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L589-L600] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L603] COND TRUE t3_st == 0 [L604] int tmp_ndt_4; [L605] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L606] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L603-L614] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L617] COND TRUE t4_st == 0 [L618] int tmp_ndt_5; [L619] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L620] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L617-L628] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L631] COND TRUE t5_st == 0 [L632] int tmp_ndt_6; [L633] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L634] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L631-L642] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } [L645] COND TRUE t6_st == 0 [L646] int tmp_ndt_7; [L647] EXPR tmp_ndt_7 = __VERIFIER_nondet_int() [L648] COND FALSE, EXPR !(\read(tmp_ndt_7)) [L645-L656] { int tmp_ndt_7; tmp_ndt_7 = __VERIFIER_nondet_int(); if (tmp_ndt_7) { { t6_st = 1; transmit6(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 551]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int m_st ; [L33] int t1_st ; [L34] int t2_st ; [L35] int t3_st ; [L36] int t4_st ; [L37] int t5_st ; [L38] int t6_st ; [L39] int m_i ; [L40] int t1_i ; [L41] int t2_i ; [L42] int t3_i ; [L43] int t4_i ; [L44] int t5_i ; [L45] int t6_i ; [L46] int M_E = 2; [L47] int T1_E = 2; [L48] int T2_E = 2; [L49] int T3_E = 2; [L50] int T4_E = 2; [L51] int T5_E = 2; [L52] int T6_E = 2; [L53] int E_1 = 2; [L54] int E_2 = 2; [L55] int E_3 = 2; [L56] int E_4 = 2; [L57] int E_5 = 2; [L58] int E_6 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0] [L1069] int __retres1 ; [L1073] CALL init_model() [L979] m_i = 1 [L980] t1_i = 1 [L981] t2_i = 1 [L982] t3_i = 1 [L983] t4_i = 1 [L984] t5_i = 1 [L985] t6_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1073] RET init_model() [L1074] CALL start_simulation() [L1010] int kernel_st ; [L1011] int tmp ; [L1012] int tmp___0 ; [L1016] kernel_st = 0 [L1017] FCALL update_channels() [L1018] CALL init_threads() [L461] COND TRUE m_i == 1 [L462] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L466] COND TRUE t1_i == 1 [L467] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L471] COND TRUE t2_i == 1 [L472] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L476] COND TRUE t3_i == 1 [L477] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L481] COND TRUE t4_i == 1 [L482] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L486] COND TRUE t5_i == 1 [L487] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L491] COND TRUE t6_i == 1 [L492] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1018] RET init_threads() [L1019] CALL fire_delta_events() [L670] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L675] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L680] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L685] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L690] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L695] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L700] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L705] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L710] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L715] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L720] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L725] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L730] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1019] RET fire_delta_events() [L1020] CALL activate_threads() [L813] int tmp ; [L814] int tmp___0 ; [L815] int tmp___1 ; [L816] int tmp___2 ; [L817] int tmp___3 ; [L818] int tmp___4 ; [L819] int tmp___5 ; [L823] CALL, EXPR is_master_triggered() [L317] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L320] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L330] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L332] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L823] RET, EXPR is_master_triggered() [L823] tmp = is_master_triggered() [L825] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0] [L831] CALL, EXPR is_transmit1_triggered() [L336] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L339] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L349] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L351] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L831] RET, EXPR is_transmit1_triggered() [L831] tmp___0 = is_transmit1_triggered() [L833] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0] [L839] CALL, EXPR is_transmit2_triggered() [L355] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L358] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L368] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L370] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L839] RET, EXPR is_transmit2_triggered() [L839] tmp___1 = is_transmit2_triggered() [L841] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0] [L847] CALL, EXPR is_transmit3_triggered() [L374] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L377] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L387] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L389] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L847] RET, EXPR is_transmit3_triggered() [L847] tmp___2 = is_transmit3_triggered() [L849] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L855] CALL, EXPR is_transmit4_triggered() [L393] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L396] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L406] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L408] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L855] RET, EXPR is_transmit4_triggered() [L855] tmp___3 = is_transmit4_triggered() [L857] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L863] CALL, EXPR is_transmit5_triggered() [L412] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L415] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L425] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L427] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L863] RET, EXPR is_transmit5_triggered() [L863] tmp___4 = is_transmit5_triggered() [L865] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L871] CALL, EXPR is_transmit6_triggered() [L431] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L434] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L444] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L446] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L871] RET, EXPR is_transmit6_triggered() [L871] tmp___5 = is_transmit6_triggered() [L873] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L1020] RET activate_threads() [L1021] CALL reset_delta_events() [L743] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L748] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L753] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L758] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L763] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L768] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L773] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L778] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L783] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L788] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L793] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L798] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L803] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1021] RET reset_delta_events() [L1024] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] [L1027] kernel_st = 1 [L1028] CALL eval() [L547] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0] Loop: [L551] COND TRUE 1 [L554] CALL, EXPR exists_runnable_thread() [L501] int __retres1 ; [L504] COND TRUE m_st == 0 [L505] __retres1 = 1 [L542] return (__retres1); [L554] RET, EXPR exists_runnable_thread() [L554] tmp = exists_runnable_thread() [L556] COND TRUE \read(tmp) [L561] COND TRUE m_st == 0 [L562] int tmp_ndt_1; [L563] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L564] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L561-L572] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L575] COND TRUE t1_st == 0 [L576] int tmp_ndt_2; [L577] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L578] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L575-L586] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L589] COND TRUE t2_st == 0 [L590] int tmp_ndt_3; [L591] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L592] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L589-L600] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L603] COND TRUE t3_st == 0 [L604] int tmp_ndt_4; [L605] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L606] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L603-L614] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L617] COND TRUE t4_st == 0 [L618] int tmp_ndt_5; [L619] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L620] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L617-L628] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L631] COND TRUE t5_st == 0 [L632] int tmp_ndt_6; [L633] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L634] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L631-L642] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } [L645] COND TRUE t6_st == 0 [L646] int tmp_ndt_7; [L647] EXPR tmp_ndt_7 = __VERIFIER_nondet_int() [L648] COND FALSE, EXPR !(\read(tmp_ndt_7)) [L645-L656] { int tmp_ndt_7; tmp_ndt_7 = __VERIFIER_nondet_int(); if (tmp_ndt_7) { { t6_st = 1; transmit6(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-29 07:10:15,681 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_73a38b3e-82a0-4289-9dd5-023486e0df4e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)