./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.07.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.07.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 01:10:55,498 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 01:10:55,563 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 01:10:55,569 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 01:10:55,570 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 01:10:55,593 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 01:10:55,594 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 01:10:55,594 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 01:10:55,595 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 01:10:55,595 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 01:10:55,596 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 01:10:55,597 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 01:10:55,597 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 01:10:55,598 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 01:10:55,598 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 01:10:55,599 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 01:10:55,599 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 01:10:55,600 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 01:10:55,600 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 01:10:55,601 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 01:10:55,601 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 01:10:55,602 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 01:10:55,602 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 01:10:55,603 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 01:10:55,603 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 01:10:55,603 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 01:10:55,604 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 01:10:55,604 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 01:10:55,605 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 01:10:55,605 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 01:10:55,606 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 01:10:55,606 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 01:10:55,606 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 01:10:55,607 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 01:10:55,607 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 01:10:55,608 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 01:10:55,608 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 01:10:55,609 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 01:10:55,609 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 022987cd4c8c671e376c5c3e5a08e2f1b98444b4d5d48bc73787bff74aa0de0f [2023-11-29 01:10:55,834 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 01:10:55,860 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 01:10:55,863 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 01:10:55,865 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 01:10:55,865 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 01:10:55,867 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/transmitter.07.cil.c [2023-11-29 01:10:59,092 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 01:10:59,271 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 01:10:59,271 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/sv-benchmarks/c/systemc/transmitter.07.cil.c [2023-11-29 01:10:59,283 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/data/ec5b332e9/db27c2f82949401b9d4f9aa6dc2f4954/FLAGf1c68719e [2023-11-29 01:10:59,294 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/data/ec5b332e9/db27c2f82949401b9d4f9aa6dc2f4954 [2023-11-29 01:10:59,297 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 01:10:59,298 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 01:10:59,299 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 01:10:59,300 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 01:10:59,314 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 01:10:59,315 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,316 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@b22f5b2 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59, skipping insertion in model container [2023-11-29 01:10:59,316 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,371 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 01:10:59,592 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 01:10:59,610 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 01:10:59,679 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 01:10:59,698 INFO L206 MainTranslator]: Completed translation [2023-11-29 01:10:59,699 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59 WrapperNode [2023-11-29 01:10:59,699 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 01:10:59,700 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 01:10:59,700 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 01:10:59,700 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 01:10:59,707 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,720 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,795 INFO L138 Inliner]: procedures = 42, calls = 52, calls flagged for inlining = 47, calls inlined = 125, statements flattened = 1861 [2023-11-29 01:10:59,795 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 01:10:59,796 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 01:10:59,796 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 01:10:59,797 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 01:10:59,809 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,809 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,821 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,853 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 01:10:59,854 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,854 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,908 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,934 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,939 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,947 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,960 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 01:10:59,961 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 01:10:59,961 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 01:10:59,962 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 01:10:59,963 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (1/1) ... [2023-11-29 01:10:59,971 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 01:10:59,984 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 01:10:59,997 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 01:11:00,007 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 01:11:00,036 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 01:11:00,036 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 01:11:00,036 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 01:11:00,037 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 01:11:00,145 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 01:11:00,147 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 01:11:01,443 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 01:11:01,475 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 01:11:01,475 INFO L309 CfgBuilder]: Removed 11 assume(true) statements. [2023-11-29 01:11:01,478 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:11:01 BoogieIcfgContainer [2023-11-29 01:11:01,478 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 01:11:01,479 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 01:11:01,479 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 01:11:01,484 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 01:11:01,485 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:11:01,485 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 01:10:59" (1/3) ... [2023-11-29 01:11:01,486 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7ef23a30 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 01:11:01, skipping insertion in model container [2023-11-29 01:11:01,486 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:11:01,487 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 01:10:59" (2/3) ... [2023-11-29 01:11:01,487 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@7ef23a30 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 01:11:01, skipping insertion in model container [2023-11-29 01:11:01,487 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 01:11:01,487 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:11:01" (3/3) ... [2023-11-29 01:11:01,489 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.07.cil.c [2023-11-29 01:11:01,569 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 01:11:01,569 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 01:11:01,569 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 01:11:01,570 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 01:11:01,570 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 01:11:01,570 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 01:11:01,570 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 01:11:01,570 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 01:11:01,579 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:01,647 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 679 [2023-11-29 01:11:01,647 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:01,647 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:01,663 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:01,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:01,663 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 01:11:01,665 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:01,677 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 679 [2023-11-29 01:11:01,677 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:01,677 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:01,682 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:01,683 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:01,692 INFO L748 eck$LassoCheckResult]: Stem: 107#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 718#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 570#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 715#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 650#L521true assume !(1 == ~m_i~0);~m_st~0 := 2; 612#L521-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 643#L526-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 193#L531-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 549#L536-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 240#L541-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 138#L546-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 601#L551-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 122#L556-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 689#L754true assume !(0 == ~M_E~0); 737#L754-2true assume !(0 == ~T1_E~0); 509#L759-1true assume !(0 == ~T2_E~0); 376#L764-1true assume !(0 == ~T3_E~0); 339#L769-1true assume !(0 == ~T4_E~0); 377#L774-1true assume !(0 == ~T5_E~0); 636#L779-1true assume 0 == ~T6_E~0;~T6_E~0 := 1; 519#L784-1true assume !(0 == ~T7_E~0); 337#L789-1true assume !(0 == ~E_1~0); 424#L794-1true assume !(0 == ~E_2~0); 765#L799-1true assume !(0 == ~E_3~0); 346#L804-1true assume !(0 == ~E_4~0); 372#L809-1true assume !(0 == ~E_5~0); 550#L814-1true assume !(0 == ~E_6~0); 9#L819-1true assume 0 == ~E_7~0;~E_7~0 := 1; 171#L824-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 137#L361true assume 1 == ~m_pc~0; 676#L362true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 712#L372true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 499#is_master_triggered_returnLabel#1true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 633#L930true assume !(0 != activate_threads_~tmp~1#1); 272#L930-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134#L380true assume !(1 == ~t1_pc~0); 766#L380-2true is_transmit1_triggered_~__retres1~1#1 := 0; 644#L391true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 770#L938true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 460#L938-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 438#L399true assume 1 == ~t2_pc~0; 638#L400true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 654#L410true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 179#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 175#L946true assume !(0 != activate_threads_~tmp___1~0#1); 414#L946-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13#L418true assume !(1 == ~t3_pc~0); 698#L418-2true is_transmit3_triggered_~__retres1~3#1 := 0; 552#L429true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 777#L954true assume !(0 != activate_threads_~tmp___2~0#1); 361#L954-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 691#L437true assume 1 == ~t4_pc~0; 755#L438true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 494#L448true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209#L962true assume !(0 != activate_threads_~tmp___3~0#1); 592#L962-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 478#L456true assume !(1 == ~t5_pc~0); 330#L456-2true is_transmit5_triggered_~__retres1~5#1 := 0; 681#L467true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 502#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 410#L970true assume !(0 != activate_threads_~tmp___4~0#1); 734#L970-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 45#L475true assume 1 == ~t6_pc~0; 221#L476true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 66#L486true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 402#L978true assume !(0 != activate_threads_~tmp___5~0#1); 351#L978-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 547#L494true assume 1 == ~t7_pc~0; 304#L495true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 316#L505true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 731#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 378#L986true assume !(0 != activate_threads_~tmp___6~0#1); 761#L986-2true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 668#L837true assume !(1 == ~M_E~0); 569#L837-2true assume !(1 == ~T1_E~0); 433#L842-1true assume !(1 == ~T2_E~0); 216#L847-1true assume !(1 == ~T3_E~0); 265#L852-1true assume !(1 == ~T4_E~0); 781#L857-1true assume 1 == ~T5_E~0;~T5_E~0 := 2; 182#L862-1true assume !(1 == ~T6_E~0); 189#L867-1true assume !(1 == ~T7_E~0); 239#L872-1true assume !(1 == ~E_1~0); 391#L877-1true assume !(1 == ~E_2~0); 578#L882-1true assume !(1 == ~E_3~0); 707#L887-1true assume !(1 == ~E_4~0); 454#L892-1true assume !(1 == ~E_5~0); 660#L897-1true assume 1 == ~E_6~0;~E_6~0 := 2; 199#L902-1true assume !(1 == ~E_7~0); 477#L907-1true assume { :end_inline_reset_delta_events } true; 230#L1148-2true [2023-11-29 01:11:01,696 INFO L750 eck$LassoCheckResult]: Loop: 230#L1148-2true assume !false; 10#L1149true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 422#L729-1true assume false; 455#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 271#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 146#L754-3true assume 0 == ~M_E~0;~M_E~0 := 1; 16#L754-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 530#L759-3true assume !(0 == ~T2_E~0); 225#L764-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 616#L769-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 362#L774-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 94#L779-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 14#L784-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 774#L789-3true assume 0 == ~E_1~0;~E_1~0 := 1; 11#L794-3true assume 0 == ~E_2~0;~E_2~0 := 1; 35#L799-3true assume !(0 == ~E_3~0); 150#L804-3true assume 0 == ~E_4~0;~E_4~0 := 1; 293#L809-3true assume 0 == ~E_5~0;~E_5~0 := 1; 33#L814-3true assume 0 == ~E_6~0;~E_6~0 := 1; 526#L819-3true assume 0 == ~E_7~0;~E_7~0 := 1; 487#L824-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 236#L361-24true assume !(1 == ~m_pc~0); 532#L361-26true is_master_triggered_~__retres1~0#1 := 0; 301#L372-8true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 59#is_master_triggered_returnLabel#9true activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 553#L930-24true assume !(0 != activate_threads_~tmp~1#1); 584#L930-26true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 343#L380-24true assume 1 == ~t1_pc~0; 585#L381-8true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 625#L391-8true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 297#is_transmit1_triggered_returnLabel#9true activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 144#L938-24true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 439#L938-26true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 505#L399-24true assume !(1 == ~t2_pc~0); 154#L399-26true is_transmit2_triggered_~__retres1~2#1 := 0; 110#L410-8true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 381#is_transmit2_triggered_returnLabel#9true activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 264#L946-24true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 142#L946-26true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 624#L418-24true assume 1 == ~t3_pc~0; 551#L419-8true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 185#L429-8true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 591#is_transmit3_triggered_returnLabel#9true activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 96#L954-24true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 412#L954-26true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 556#L437-24true assume !(1 == ~t4_pc~0); 784#L437-26true is_transmit4_triggered_~__retres1~4#1 := 0; 740#L448-8true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 263#is_transmit4_triggered_returnLabel#9true activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88#L962-24true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 350#L962-26true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 645#L456-24true assume !(1 == ~t5_pc~0); 738#L456-26true is_transmit5_triggered_~__retres1~5#1 := 0; 307#L467-8true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 533#is_transmit5_triggered_returnLabel#9true activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 574#L970-24true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 273#L970-26true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 769#L475-24true assume 1 == ~t6_pc~0; 15#L476-8true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 315#L486-8true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 85#is_transmit6_triggered_returnLabel#9true activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 347#L978-24true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6#L978-26true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 309#L494-24true assume 1 == ~t7_pc~0; 248#L495-8true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 174#L505-8true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 257#is_transmit7_triggered_returnLabel#9true activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 140#L986-24true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 490#L986-26true havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 515#L837-3true assume 1 == ~M_E~0;~M_E~0 := 2; 670#L837-5true assume !(1 == ~T1_E~0); 269#L842-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 608#L847-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 408#L852-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 313#L857-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 746#L862-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 703#L867-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 247#L872-3true assume 1 == ~E_1~0;~E_1~0 := 2; 306#L877-3true assume !(1 == ~E_2~0); 728#L882-3true assume 1 == ~E_3~0;~E_3~0 := 2; 354#L887-3true assume 1 == ~E_4~0;~E_4~0 := 2; 104#L892-3true assume 1 == ~E_5~0;~E_5~0 := 2; 514#L897-3true assume 1 == ~E_6~0;~E_6~0 := 2; 773#L902-3true assume 1 == ~E_7~0;~E_7~0 := 2; 196#L907-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 581#L569-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 365#L611-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 155#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 686#L1167true assume !(0 == start_simulation_~tmp~3#1); 233#L1167-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 745#L569-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 254#L611-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 19#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 308#L1122true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 222#L1129true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 282#stop_simulation_returnLabel#1true start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 121#L1180true assume !(0 != start_simulation_~tmp___0~1#1); 230#L1148-2true [2023-11-29 01:11:01,704 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:01,704 INFO L85 PathProgramCache]: Analyzing trace with hash -171938705, now seen corresponding path program 1 times [2023-11-29 01:11:01,714 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:01,714 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [229963625] [2023-11-29 01:11:01,714 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:01,715 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:01,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:02,011 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:02,011 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:02,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [229963625] [2023-11-29 01:11:02,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [229963625] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:02,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:02,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:02,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [733281664] [2023-11-29 01:11:02,015 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:02,020 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:02,021 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:02,021 INFO L85 PathProgramCache]: Analyzing trace with hash 661713836, now seen corresponding path program 1 times [2023-11-29 01:11:02,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:02,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [599796052] [2023-11-29 01:11:02,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:02,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:02,042 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:02,087 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:02,088 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:02,088 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [599796052] [2023-11-29 01:11:02,088 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [599796052] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:02,088 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:02,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:02,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [123050151] [2023-11-29 01:11:02,089 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:02,090 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:02,091 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:02,148 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:02,149 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:02,152 INFO L87 Difference]: Start difference. First operand has 784 states, 783 states have (on average 1.5172413793103448) internal successors, (1188), 783 states have internal predecessors, (1188), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:02,219 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:02,219 INFO L93 Difference]: Finished difference Result 782 states and 1162 transitions. [2023-11-29 01:11:02,220 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 782 states and 1162 transitions. [2023-11-29 01:11:02,232 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:02,245 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 782 states to 776 states and 1156 transitions. [2023-11-29 01:11:02,246 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-29 01:11:02,248 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-29 01:11:02,249 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1156 transitions. [2023-11-29 01:11:02,255 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:02,256 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1156 transitions. [2023-11-29 01:11:02,279 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1156 transitions. [2023-11-29 01:11:02,324 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-29 01:11:02,326 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4896907216494846) internal successors, (1156), 775 states have internal predecessors, (1156), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:02,331 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1156 transitions. [2023-11-29 01:11:02,332 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1156 transitions. [2023-11-29 01:11:02,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:02,338 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1156 transitions. [2023-11-29 01:11:02,338 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 01:11:02,338 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1156 transitions. [2023-11-29 01:11:02,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:02,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:02,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:02,349 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:02,350 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:02,350 INFO L748 eck$LassoCheckResult]: Stem: 1790#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1791#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2318#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2319#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2338#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2330#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2331#L526-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 1939#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 1940#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2009#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 1853#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1854#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 1820#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1821#L754 assume !(0 == ~M_E~0); 2346#L754-2 assume !(0 == ~T1_E~0); 2288#L759-1 assume !(0 == ~T2_E~0); 2170#L764-1 assume !(0 == ~T3_E~0); 2135#L769-1 assume !(0 == ~T4_E~0); 2136#L774-1 assume !(0 == ~T5_E~0); 2171#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2293#L784-1 assume !(0 == ~T7_E~0); 2132#L789-1 assume !(0 == ~E_1~0); 2133#L794-1 assume !(0 == ~E_2~0); 2207#L799-1 assume !(0 == ~E_3~0); 2143#L804-1 assume !(0 == ~E_4~0); 2144#L809-1 assume !(0 == ~E_5~0); 2165#L814-1 assume !(0 == ~E_6~0); 1591#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 1592#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1850#L361 assume 1 == ~m_pc~0; 1851#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2314#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2274#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2275#L930 assume !(0 != activate_threads_~tmp~1#1); 2052#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1844#L380 assume !(1 == ~t1_pc~0); 1845#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2213#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1613#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1614#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2233#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2214#L399 assume 1 == ~t2_pc~0; 2215#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1762#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1922#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1915#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1916#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1599#L418 assume !(1 == ~t3_pc~0); 1578#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1579#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1589#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1590#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2155#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2156#L437 assume 1 == ~t4_pc~0; 2347#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2269#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1672#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1673#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1968#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2251#L456 assume !(1 == ~t5_pc~0); 1776#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1775#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2278#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2196#L970 assume !(0 != activate_threads_~tmp___4~0#1); 2197#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1666#L475 assume 1 == ~t6_pc~0; 1667#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1708#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1709#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1908#L978 assume !(0 != activate_threads_~tmp___5~0#1); 2148#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2149#L494 assume 1 == ~t7_pc~0; 2097#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1893#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2108#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2172#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2173#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2343#L837 assume !(1 == ~M_E~0); 2317#L837-2 assume !(1 == ~T1_E~0); 2210#L842-1 assume !(1 == ~T2_E~0); 1975#L847-1 assume !(1 == ~T3_E~0); 1976#L852-1 assume !(1 == ~T4_E~0); 2042#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1928#L862-1 assume !(1 == ~T6_E~0); 1929#L867-1 assume !(1 == ~T7_E~0); 1935#L872-1 assume !(1 == ~E_1~0); 2008#L877-1 assume !(1 == ~E_2~0); 2185#L882-1 assume !(1 == ~E_3~0); 2322#L887-1 assume !(1 == ~E_4~0); 2229#L892-1 assume !(1 == ~E_5~0); 2230#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 1951#L902-1 assume !(1 == ~E_7~0); 1952#L907-1 assume { :end_inline_reset_delta_events } true; 1819#L1148-2 [2023-11-29 01:11:02,351 INFO L750 eck$LassoCheckResult]: Loop: 1819#L1148-2 assume !false; 1593#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1594#L729-1 assume !false; 2205#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1792#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1793#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1941#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1837#L626 assume !(0 != eval_~tmp~0#1); 1838#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2051#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1866#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1605#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1606#L759-3 assume !(0 == ~T2_E~0); 1987#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1988#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2157#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1765#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1600#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1601#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 1595#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1596#L799-3 assume !(0 == ~E_3~0); 1647#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1873#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1643#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1644#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2261#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2005#L361-24 assume 1 == ~m_pc~0; 1749#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1750#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1695#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1696#L930-24 assume !(0 != activate_threads_~tmp~1#1); 2306#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2140#L380-24 assume 1 == ~t1_pc~0; 2141#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 1678#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2087#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1862#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1863#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2216#L399-24 assume !(1 == ~t2_pc~0); 1881#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 1797#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1798#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2041#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1859#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1860#L418-24 assume 1 == ~t3_pc~0; 2305#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1642#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1932#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1768#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1769#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2199#L437-24 assume 1 == ~t4_pc~0; 2265#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2267#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2040#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1752#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1753#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2147#L456-24 assume 1 == ~t5_pc~0; 2121#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2101#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2102#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2300#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2053#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2054#L475-24 assume 1 == ~t6_pc~0; 1602#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 1603#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1745#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1746#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1584#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1585#L494-24 assume 1 == ~t7_pc~0; 2024#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1913#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1914#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1856#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1857#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2264#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2291#L837-5 assume !(1 == ~T1_E~0); 2048#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2049#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2195#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2105#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2106#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2348#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2022#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2023#L877-3 assume !(1 == ~E_2~0); 2100#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2151#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1784#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1785#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2290#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1945#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1946#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1598#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1882#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 1883#L1167 assume !(0 == start_simulation_~tmp~3#1); 2000#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2001#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1806#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1611#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 1612#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1982#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1983#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 1818#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 1819#L1148-2 [2023-11-29 01:11:02,352 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:02,352 INFO L85 PathProgramCache]: Analyzing trace with hash 598794861, now seen corresponding path program 1 times [2023-11-29 01:11:02,353 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:02,353 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1043801688] [2023-11-29 01:11:02,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:02,354 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:02,377 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:02,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:02,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:02,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1043801688] [2023-11-29 01:11:02,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1043801688] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:02,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:02,450 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:02,450 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1389889586] [2023-11-29 01:11:02,450 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:02,451 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:02,451 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:02,452 INFO L85 PathProgramCache]: Analyzing trace with hash -716299096, now seen corresponding path program 1 times [2023-11-29 01:11:02,452 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:02,452 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [166158072] [2023-11-29 01:11:02,452 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:02,453 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:02,485 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:02,575 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:02,576 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:02,576 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [166158072] [2023-11-29 01:11:02,576 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [166158072] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:02,577 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:02,577 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:02,577 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1626223124] [2023-11-29 01:11:02,577 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:02,578 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:02,578 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:02,579 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:02,579 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:02,580 INFO L87 Difference]: Start difference. First operand 776 states and 1156 transitions. cyclomatic complexity: 381 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:02,613 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:02,613 INFO L93 Difference]: Finished difference Result 776 states and 1155 transitions. [2023-11-29 01:11:02,613 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1155 transitions. [2023-11-29 01:11:02,621 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:02,629 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1155 transitions. [2023-11-29 01:11:02,629 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-29 01:11:02,630 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-29 01:11:02,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1155 transitions. [2023-11-29 01:11:02,632 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:02,632 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1155 transitions. [2023-11-29 01:11:02,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1155 transitions. [2023-11-29 01:11:02,647 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-29 01:11:02,649 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4884020618556701) internal successors, (1155), 775 states have internal predecessors, (1155), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:02,653 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1155 transitions. [2023-11-29 01:11:02,653 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1155 transitions. [2023-11-29 01:11:02,654 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:02,655 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1155 transitions. [2023-11-29 01:11:02,655 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 01:11:02,655 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1155 transitions. [2023-11-29 01:11:02,660 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:02,660 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:02,660 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:02,663 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:02,663 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:02,664 INFO L748 eck$LassoCheckResult]: Stem: 3349#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 3350#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 3877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3897#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 3889#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3890#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3498#L531-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3499#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 3568#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3412#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3413#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3379#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3380#L754 assume !(0 == ~M_E~0); 3905#L754-2 assume !(0 == ~T1_E~0); 3847#L759-1 assume !(0 == ~T2_E~0); 3729#L764-1 assume !(0 == ~T3_E~0); 3694#L769-1 assume !(0 == ~T4_E~0); 3695#L774-1 assume !(0 == ~T5_E~0); 3730#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3852#L784-1 assume !(0 == ~T7_E~0); 3691#L789-1 assume !(0 == ~E_1~0); 3692#L794-1 assume !(0 == ~E_2~0); 3766#L799-1 assume !(0 == ~E_3~0); 3702#L804-1 assume !(0 == ~E_4~0); 3703#L809-1 assume !(0 == ~E_5~0); 3724#L814-1 assume !(0 == ~E_6~0); 3150#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 3151#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3409#L361 assume 1 == ~m_pc~0; 3410#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3873#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3833#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3834#L930 assume !(0 != activate_threads_~tmp~1#1); 3611#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3403#L380 assume !(1 == ~t1_pc~0); 3404#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3772#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3172#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3173#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3792#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3773#L399 assume 1 == ~t2_pc~0; 3774#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3321#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3481#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3474#L946 assume !(0 != activate_threads_~tmp___1~0#1); 3475#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3158#L418 assume !(1 == ~t3_pc~0); 3137#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3138#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3148#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3149#L954 assume !(0 != activate_threads_~tmp___2~0#1); 3714#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3715#L437 assume 1 == ~t4_pc~0; 3906#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3828#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3231#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3232#L962 assume !(0 != activate_threads_~tmp___3~0#1); 3527#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3810#L456 assume !(1 == ~t5_pc~0); 3335#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3334#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3837#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3755#L970 assume !(0 != activate_threads_~tmp___4~0#1); 3756#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3225#L475 assume 1 == ~t6_pc~0; 3226#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3267#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3268#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3467#L978 assume !(0 != activate_threads_~tmp___5~0#1); 3707#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3708#L494 assume 1 == ~t7_pc~0; 3656#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3452#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3667#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3731#L986 assume !(0 != activate_threads_~tmp___6~0#1); 3732#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3902#L837 assume !(1 == ~M_E~0); 3876#L837-2 assume !(1 == ~T1_E~0); 3769#L842-1 assume !(1 == ~T2_E~0); 3534#L847-1 assume !(1 == ~T3_E~0); 3535#L852-1 assume !(1 == ~T4_E~0); 3601#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3487#L862-1 assume !(1 == ~T6_E~0); 3488#L867-1 assume !(1 == ~T7_E~0); 3494#L872-1 assume !(1 == ~E_1~0); 3567#L877-1 assume !(1 == ~E_2~0); 3744#L882-1 assume !(1 == ~E_3~0); 3881#L887-1 assume !(1 == ~E_4~0); 3788#L892-1 assume !(1 == ~E_5~0); 3789#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 3510#L902-1 assume !(1 == ~E_7~0); 3511#L907-1 assume { :end_inline_reset_delta_events } true; 3378#L1148-2 [2023-11-29 01:11:02,664 INFO L750 eck$LassoCheckResult]: Loop: 3378#L1148-2 assume !false; 3152#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3153#L729-1 assume !false; 3764#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3351#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3352#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3500#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3396#L626 assume !(0 != eval_~tmp~0#1); 3397#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3610#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3425#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3164#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3165#L759-3 assume !(0 == ~T2_E~0); 3546#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3547#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3716#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3324#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3159#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3160#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3154#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3155#L799-3 assume !(0 == ~E_3~0); 3206#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3432#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3202#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3203#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3820#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3564#L361-24 assume 1 == ~m_pc~0; 3308#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3309#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3254#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 3255#L930-24 assume !(0 != activate_threads_~tmp~1#1); 3865#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3699#L380-24 assume 1 == ~t1_pc~0; 3700#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3237#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3646#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3421#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3422#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3775#L399-24 assume !(1 == ~t2_pc~0); 3440#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 3356#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3357#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3600#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3418#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3419#L418-24 assume !(1 == ~t3_pc~0); 3200#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 3201#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3491#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3327#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3328#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3758#L437-24 assume 1 == ~t4_pc~0; 3824#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3826#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3599#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3311#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3312#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3706#L456-24 assume 1 == ~t5_pc~0; 3680#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 3660#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3661#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3859#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3612#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3613#L475-24 assume 1 == ~t6_pc~0; 3161#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3162#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3304#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3305#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3143#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3144#L494-24 assume !(1 == ~t7_pc~0); 3492#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 3472#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3473#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3415#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3416#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3823#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3850#L837-5 assume !(1 == ~T1_E~0); 3607#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3608#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3754#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3664#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3665#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3907#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3581#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3582#L877-3 assume !(1 == ~E_2~0); 3659#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3710#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3343#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3344#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3849#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3504#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3505#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3157#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3441#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 3442#L1167 assume !(0 == start_simulation_~tmp~3#1); 3559#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 3560#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 3365#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 3170#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 3171#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3541#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3542#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 3377#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 3378#L1148-2 [2023-11-29 01:11:02,665 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:02,665 INFO L85 PathProgramCache]: Analyzing trace with hash 1185071083, now seen corresponding path program 1 times [2023-11-29 01:11:02,665 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:02,665 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2109512327] [2023-11-29 01:11:02,666 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:02,666 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:02,683 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:02,729 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:02,730 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:02,730 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2109512327] [2023-11-29 01:11:02,730 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2109512327] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:02,730 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:02,731 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:02,731 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1037044632] [2023-11-29 01:11:02,731 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:02,731 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:02,732 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:02,732 INFO L85 PathProgramCache]: Analyzing trace with hash 808370534, now seen corresponding path program 1 times [2023-11-29 01:11:02,732 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:02,733 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [65929257] [2023-11-29 01:11:02,733 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:02,733 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:02,753 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:02,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:02,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:02,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [65929257] [2023-11-29 01:11:02,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [65929257] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:02,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:02,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:02,824 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125394221] [2023-11-29 01:11:02,824 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:02,824 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:02,825 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:02,825 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:02,825 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:02,825 INFO L87 Difference]: Start difference. First operand 776 states and 1155 transitions. cyclomatic complexity: 380 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:02,852 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:02,852 INFO L93 Difference]: Finished difference Result 776 states and 1154 transitions. [2023-11-29 01:11:02,852 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1154 transitions. [2023-11-29 01:11:02,859 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:02,866 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1154 transitions. [2023-11-29 01:11:02,866 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-29 01:11:02,868 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-29 01:11:02,868 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1154 transitions. [2023-11-29 01:11:02,869 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:02,870 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1154 transitions. [2023-11-29 01:11:02,871 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1154 transitions. [2023-11-29 01:11:02,885 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-29 01:11:02,887 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4871134020618557) internal successors, (1154), 775 states have internal predecessors, (1154), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:02,891 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1154 transitions. [2023-11-29 01:11:02,891 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1154 transitions. [2023-11-29 01:11:02,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:02,892 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1154 transitions. [2023-11-29 01:11:02,893 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 01:11:02,893 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1154 transitions. [2023-11-29 01:11:02,898 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:02,898 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:02,898 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:02,900 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:02,901 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:02,901 INFO L748 eck$LassoCheckResult]: Stem: 4908#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 4909#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 5436#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5437#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5456#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 5448#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5449#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5057#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5058#L536-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5127#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4971#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4972#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4938#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4939#L754 assume !(0 == ~M_E~0); 5464#L754-2 assume !(0 == ~T1_E~0); 5406#L759-1 assume !(0 == ~T2_E~0); 5288#L764-1 assume !(0 == ~T3_E~0); 5254#L769-1 assume !(0 == ~T4_E~0); 5255#L774-1 assume !(0 == ~T5_E~0); 5289#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 5411#L784-1 assume !(0 == ~T7_E~0); 5251#L789-1 assume !(0 == ~E_1~0); 5252#L794-1 assume !(0 == ~E_2~0); 5325#L799-1 assume !(0 == ~E_3~0); 5261#L804-1 assume !(0 == ~E_4~0); 5262#L809-1 assume !(0 == ~E_5~0); 5283#L814-1 assume !(0 == ~E_6~0); 4711#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 4712#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4968#L361 assume 1 == ~m_pc~0; 4969#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5432#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5392#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 5393#L930 assume !(0 != activate_threads_~tmp~1#1); 5170#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4962#L380 assume !(1 == ~t1_pc~0); 4963#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5331#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4731#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4732#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5351#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5332#L399 assume 1 == ~t2_pc~0; 5333#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4880#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5040#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5033#L946 assume !(0 != activate_threads_~tmp___1~0#1); 5034#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4717#L418 assume !(1 == ~t3_pc~0); 4696#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4697#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4707#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4708#L954 assume !(0 != activate_threads_~tmp___2~0#1); 5273#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5274#L437 assume 1 == ~t4_pc~0; 5465#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5388#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4791#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4792#L962 assume !(0 != activate_threads_~tmp___3~0#1); 5086#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5374#L456 assume !(1 == ~t5_pc~0); 4894#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4893#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5396#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5315#L970 assume !(0 != activate_threads_~tmp___4~0#1); 5316#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4784#L475 assume 1 == ~t6_pc~0; 4785#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4826#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4827#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5026#L978 assume !(0 != activate_threads_~tmp___5~0#1); 5266#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5267#L494 assume 1 == ~t7_pc~0; 5215#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5011#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5226#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5290#L986 assume !(0 != activate_threads_~tmp___6~0#1); 5291#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5461#L837 assume !(1 == ~M_E~0); 5435#L837-2 assume !(1 == ~T1_E~0); 5328#L842-1 assume !(1 == ~T2_E~0); 5093#L847-1 assume !(1 == ~T3_E~0); 5094#L852-1 assume !(1 == ~T4_E~0); 5160#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5046#L862-1 assume !(1 == ~T6_E~0); 5047#L867-1 assume !(1 == ~T7_E~0); 5053#L872-1 assume !(1 == ~E_1~0); 5126#L877-1 assume !(1 == ~E_2~0); 5304#L882-1 assume !(1 == ~E_3~0); 5440#L887-1 assume !(1 == ~E_4~0); 5347#L892-1 assume !(1 == ~E_5~0); 5348#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 5069#L902-1 assume !(1 == ~E_7~0); 5070#L907-1 assume { :end_inline_reset_delta_events } true; 4937#L1148-2 [2023-11-29 01:11:02,902 INFO L750 eck$LassoCheckResult]: Loop: 4937#L1148-2 assume !false; 4713#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4714#L729-1 assume !false; 5323#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 4910#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4911#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5064#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4957#L626 assume !(0 != eval_~tmp~0#1); 4958#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5169#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4984#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4723#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4724#L759-3 assume !(0 == ~T2_E~0); 5106#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 5107#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5275#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4883#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4718#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4719#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 4709#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4710#L799-3 assume !(0 == ~E_3~0); 4765#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4991#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4761#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4762#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5379#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5123#L361-24 assume 1 == ~m_pc~0; 4867#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4868#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4813#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 4814#L930-24 assume !(0 != activate_threads_~tmp~1#1); 5424#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5258#L380-24 assume 1 == ~t1_pc~0; 5259#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4796#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5205#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4980#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4981#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5334#L399-24 assume !(1 == ~t2_pc~0); 4999#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 4915#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4916#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5159#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4977#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4978#L418-24 assume !(1 == ~t3_pc~0); 4759#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 4760#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5050#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4886#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4887#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5317#L437-24 assume 1 == ~t4_pc~0; 5383#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5385#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5158#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4870#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4871#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5265#L456-24 assume 1 == ~t5_pc~0; 5239#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5219#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5220#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5418#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5171#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5172#L475-24 assume 1 == ~t6_pc~0; 4720#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4721#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4863#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4864#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4702#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4703#L494-24 assume 1 == ~t7_pc~0; 5142#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5031#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5032#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4974#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4975#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5382#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5409#L837-5 assume !(1 == ~T1_E~0); 5166#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5167#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5313#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5223#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5224#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5466#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5137#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5138#L877-3 assume !(1 == ~E_2~0); 5218#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5269#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4902#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4903#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5408#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5062#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5063#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4716#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 5000#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 5001#L1167 assume !(0 == start_simulation_~tmp~3#1); 5118#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 5119#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 4924#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 4729#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 4730#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5100#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5101#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 4936#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 4937#L1148-2 [2023-11-29 01:11:02,902 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:02,902 INFO L85 PathProgramCache]: Analyzing trace with hash -1151321427, now seen corresponding path program 1 times [2023-11-29 01:11:02,903 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:02,903 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [349391969] [2023-11-29 01:11:02,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:02,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:02,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:02,952 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:02,952 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:02,952 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [349391969] [2023-11-29 01:11:02,953 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [349391969] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:02,953 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:02,953 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:02,953 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [663827110] [2023-11-29 01:11:02,953 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:02,954 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:02,954 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:02,954 INFO L85 PathProgramCache]: Analyzing trace with hash -1857946489, now seen corresponding path program 1 times [2023-11-29 01:11:02,955 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:02,955 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1982429464] [2023-11-29 01:11:02,955 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:02,955 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:02,973 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:03,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:03,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:03,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1982429464] [2023-11-29 01:11:03,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1982429464] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:03,024 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:03,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:03,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [402599558] [2023-11-29 01:11:03,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:03,025 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:03,025 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:03,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:03,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:03,026 INFO L87 Difference]: Start difference. First operand 776 states and 1154 transitions. cyclomatic complexity: 379 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:03,052 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:03,052 INFO L93 Difference]: Finished difference Result 776 states and 1153 transitions. [2023-11-29 01:11:03,052 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1153 transitions. [2023-11-29 01:11:03,059 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:03,066 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1153 transitions. [2023-11-29 01:11:03,066 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-29 01:11:03,067 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-29 01:11:03,067 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1153 transitions. [2023-11-29 01:11:03,069 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:03,069 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1153 transitions. [2023-11-29 01:11:03,071 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1153 transitions. [2023-11-29 01:11:03,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-29 01:11:03,086 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4858247422680413) internal successors, (1153), 775 states have internal predecessors, (1153), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:03,090 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1153 transitions. [2023-11-29 01:11:03,090 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1153 transitions. [2023-11-29 01:11:03,091 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:03,092 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1153 transitions. [2023-11-29 01:11:03,092 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 01:11:03,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1153 transitions. [2023-11-29 01:11:03,097 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:03,097 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:03,097 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:03,099 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:03,100 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:03,100 INFO L748 eck$LassoCheckResult]: Stem: 6467#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 6468#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 6995#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6996#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7015#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 7007#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7008#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6616#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6617#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6686#L541-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6530#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6531#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6497#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6498#L754 assume !(0 == ~M_E~0); 7023#L754-2 assume !(0 == ~T1_E~0); 6965#L759-1 assume !(0 == ~T2_E~0); 6847#L764-1 assume !(0 == ~T3_E~0); 6812#L769-1 assume !(0 == ~T4_E~0); 6813#L774-1 assume !(0 == ~T5_E~0); 6848#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6970#L784-1 assume !(0 == ~T7_E~0); 6809#L789-1 assume !(0 == ~E_1~0); 6810#L794-1 assume !(0 == ~E_2~0); 6884#L799-1 assume !(0 == ~E_3~0); 6820#L804-1 assume !(0 == ~E_4~0); 6821#L809-1 assume !(0 == ~E_5~0); 6842#L814-1 assume !(0 == ~E_6~0); 6268#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 6269#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6527#L361 assume 1 == ~m_pc~0; 6528#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6991#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6951#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6952#L930 assume !(0 != activate_threads_~tmp~1#1); 6729#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6521#L380 assume !(1 == ~t1_pc~0); 6522#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6890#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6290#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6291#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6910#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6891#L399 assume 1 == ~t2_pc~0; 6892#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6439#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6599#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6592#L946 assume !(0 != activate_threads_~tmp___1~0#1); 6593#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6276#L418 assume !(1 == ~t3_pc~0); 6255#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6256#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6267#L954 assume !(0 != activate_threads_~tmp___2~0#1); 6832#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6833#L437 assume 1 == ~t4_pc~0; 7024#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6946#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6349#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6350#L962 assume !(0 != activate_threads_~tmp___3~0#1); 6645#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6930#L456 assume !(1 == ~t5_pc~0); 6453#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6452#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6955#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6874#L970 assume !(0 != activate_threads_~tmp___4~0#1); 6875#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6343#L475 assume 1 == ~t6_pc~0; 6344#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6385#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6386#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6585#L978 assume !(0 != activate_threads_~tmp___5~0#1); 6825#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6826#L494 assume 1 == ~t7_pc~0; 6774#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6570#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6785#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6849#L986 assume !(0 != activate_threads_~tmp___6~0#1); 6850#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7020#L837 assume !(1 == ~M_E~0); 6994#L837-2 assume !(1 == ~T1_E~0); 6887#L842-1 assume !(1 == ~T2_E~0); 6652#L847-1 assume !(1 == ~T3_E~0); 6653#L852-1 assume !(1 == ~T4_E~0); 6719#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6605#L862-1 assume !(1 == ~T6_E~0); 6606#L867-1 assume !(1 == ~T7_E~0); 6612#L872-1 assume !(1 == ~E_1~0); 6685#L877-1 assume !(1 == ~E_2~0); 6862#L882-1 assume !(1 == ~E_3~0); 6999#L887-1 assume !(1 == ~E_4~0); 6906#L892-1 assume !(1 == ~E_5~0); 6907#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 6628#L902-1 assume !(1 == ~E_7~0); 6629#L907-1 assume { :end_inline_reset_delta_events } true; 6496#L1148-2 [2023-11-29 01:11:03,101 INFO L750 eck$LassoCheckResult]: Loop: 6496#L1148-2 assume !false; 6270#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6271#L729-1 assume !false; 6882#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6469#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6470#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6620#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6514#L626 assume !(0 != eval_~tmp~0#1); 6515#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6728#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6543#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6282#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6283#L759-3 assume !(0 == ~T2_E~0); 6664#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6665#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6834#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6442#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6277#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6278#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 6272#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6273#L799-3 assume !(0 == ~E_3~0); 6324#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6550#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6320#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6321#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6938#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6682#L361-24 assume 1 == ~m_pc~0; 6426#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6427#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6372#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 6373#L930-24 assume !(0 != activate_threads_~tmp~1#1); 6983#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6817#L380-24 assume 1 == ~t1_pc~0; 6818#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6355#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6764#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6539#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6540#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6893#L399-24 assume !(1 == ~t2_pc~0); 6558#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 6474#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6475#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6718#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6536#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6537#L418-24 assume 1 == ~t3_pc~0; 6982#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6319#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6609#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6445#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6446#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6876#L437-24 assume 1 == ~t4_pc~0; 6942#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6944#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6717#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6429#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6430#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6824#L456-24 assume 1 == ~t5_pc~0; 6798#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 6778#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6779#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6977#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6730#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6731#L475-24 assume 1 == ~t6_pc~0; 6279#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6280#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6422#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6423#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6261#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6262#L494-24 assume !(1 == ~t7_pc~0); 6610#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 6590#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6591#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6533#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6534#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6941#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6968#L837-5 assume !(1 == ~T1_E~0); 6725#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6726#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6872#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6782#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6783#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7025#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6696#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6697#L877-3 assume !(1 == ~E_2~0); 6777#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6828#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 6461#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6462#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6967#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6618#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6619#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6275#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6559#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 6560#L1167 assume !(0 == start_simulation_~tmp~3#1); 6677#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 6678#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 6480#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 6288#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 6289#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6659#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6660#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 6495#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 6496#L1148-2 [2023-11-29 01:11:03,101 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:03,102 INFO L85 PathProgramCache]: Analyzing trace with hash 1267163051, now seen corresponding path program 1 times [2023-11-29 01:11:03,102 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:03,102 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2065610446] [2023-11-29 01:11:03,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:03,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:03,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:03,150 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:03,150 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:03,150 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2065610446] [2023-11-29 01:11:03,151 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2065610446] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:03,151 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:03,151 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:03,151 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1950729434] [2023-11-29 01:11:03,151 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:03,152 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:03,152 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:03,152 INFO L85 PathProgramCache]: Analyzing trace with hash 1950017927, now seen corresponding path program 1 times [2023-11-29 01:11:03,153 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:03,153 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1440932726] [2023-11-29 01:11:03,153 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:03,153 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:03,170 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:03,217 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:03,217 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:03,218 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1440932726] [2023-11-29 01:11:03,218 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1440932726] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:03,218 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:03,218 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:03,218 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2145506995] [2023-11-29 01:11:03,218 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:03,219 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:03,219 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:03,219 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:03,220 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:03,220 INFO L87 Difference]: Start difference. First operand 776 states and 1153 transitions. cyclomatic complexity: 378 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:03,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:03,263 INFO L93 Difference]: Finished difference Result 776 states and 1152 transitions. [2023-11-29 01:11:03,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1152 transitions. [2023-11-29 01:11:03,270 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:03,276 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1152 transitions. [2023-11-29 01:11:03,276 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-29 01:11:03,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-29 01:11:03,277 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1152 transitions. [2023-11-29 01:11:03,279 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:03,279 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1152 transitions. [2023-11-29 01:11:03,281 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1152 transitions. [2023-11-29 01:11:03,293 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-29 01:11:03,295 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4845360824742269) internal successors, (1152), 775 states have internal predecessors, (1152), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:03,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1152 transitions. [2023-11-29 01:11:03,299 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1152 transitions. [2023-11-29 01:11:03,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:03,300 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1152 transitions. [2023-11-29 01:11:03,301 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 01:11:03,301 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1152 transitions. [2023-11-29 01:11:03,305 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:03,305 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:03,305 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:03,307 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:03,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:03,308 INFO L748 eck$LassoCheckResult]: Stem: 8026#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 8027#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 8554#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8555#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8574#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 8566#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8567#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8175#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8176#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8245#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8089#L546-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8090#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8056#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8057#L754 assume !(0 == ~M_E~0); 8582#L754-2 assume !(0 == ~T1_E~0); 8524#L759-1 assume !(0 == ~T2_E~0); 8406#L764-1 assume !(0 == ~T3_E~0); 8371#L769-1 assume !(0 == ~T4_E~0); 8372#L774-1 assume !(0 == ~T5_E~0); 8407#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8529#L784-1 assume !(0 == ~T7_E~0); 8368#L789-1 assume !(0 == ~E_1~0); 8369#L794-1 assume !(0 == ~E_2~0); 8443#L799-1 assume !(0 == ~E_3~0); 8379#L804-1 assume !(0 == ~E_4~0); 8380#L809-1 assume !(0 == ~E_5~0); 8401#L814-1 assume !(0 == ~E_6~0); 7827#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 7828#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8086#L361 assume 1 == ~m_pc~0; 8087#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8550#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8510#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 8511#L930 assume !(0 != activate_threads_~tmp~1#1); 8288#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8080#L380 assume !(1 == ~t1_pc~0); 8081#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8449#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7849#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7850#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8469#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8450#L399 assume 1 == ~t2_pc~0; 8451#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7998#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8158#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8151#L946 assume !(0 != activate_threads_~tmp___1~0#1); 8152#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7835#L418 assume !(1 == ~t3_pc~0); 7814#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7815#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7825#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7826#L954 assume !(0 != activate_threads_~tmp___2~0#1); 8391#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8392#L437 assume 1 == ~t4_pc~0; 8583#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8505#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7908#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7909#L962 assume !(0 != activate_threads_~tmp___3~0#1); 8204#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8487#L456 assume !(1 == ~t5_pc~0); 8012#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8011#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8514#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8432#L970 assume !(0 != activate_threads_~tmp___4~0#1); 8433#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7902#L475 assume 1 == ~t6_pc~0; 7903#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7944#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7945#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8144#L978 assume !(0 != activate_threads_~tmp___5~0#1); 8384#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8385#L494 assume 1 == ~t7_pc~0; 8333#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8129#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8344#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8408#L986 assume !(0 != activate_threads_~tmp___6~0#1); 8409#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8579#L837 assume !(1 == ~M_E~0); 8553#L837-2 assume !(1 == ~T1_E~0); 8446#L842-1 assume !(1 == ~T2_E~0); 8211#L847-1 assume !(1 == ~T3_E~0); 8212#L852-1 assume !(1 == ~T4_E~0); 8278#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8164#L862-1 assume !(1 == ~T6_E~0); 8165#L867-1 assume !(1 == ~T7_E~0); 8171#L872-1 assume !(1 == ~E_1~0); 8244#L877-1 assume !(1 == ~E_2~0); 8421#L882-1 assume !(1 == ~E_3~0); 8558#L887-1 assume !(1 == ~E_4~0); 8465#L892-1 assume !(1 == ~E_5~0); 8466#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 8187#L902-1 assume !(1 == ~E_7~0); 8188#L907-1 assume { :end_inline_reset_delta_events } true; 8055#L1148-2 [2023-11-29 01:11:03,308 INFO L750 eck$LassoCheckResult]: Loop: 8055#L1148-2 assume !false; 7829#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7830#L729-1 assume !false; 8441#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8028#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8029#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8177#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8073#L626 assume !(0 != eval_~tmp~0#1); 8074#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8287#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8102#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7841#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7842#L759-3 assume !(0 == ~T2_E~0); 8223#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8224#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8393#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8001#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7836#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7837#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7831#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7832#L799-3 assume !(0 == ~E_3~0); 7883#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 8109#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7879#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7880#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8497#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8241#L361-24 assume 1 == ~m_pc~0; 7985#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7986#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7931#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 7932#L930-24 assume !(0 != activate_threads_~tmp~1#1); 8542#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8376#L380-24 assume 1 == ~t1_pc~0; 8377#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7914#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8323#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8098#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8099#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8452#L399-24 assume !(1 == ~t2_pc~0); 8117#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 8033#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8034#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8277#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8095#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8096#L418-24 assume !(1 == ~t3_pc~0); 7877#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 7878#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8168#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8004#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8005#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8435#L437-24 assume 1 == ~t4_pc~0; 8501#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8503#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8276#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7988#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7989#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8383#L456-24 assume 1 == ~t5_pc~0; 8357#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8337#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8338#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8536#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8289#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8290#L475-24 assume !(1 == ~t6_pc~0); 7840#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 7839#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7981#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7982#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7820#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7821#L494-24 assume 1 == ~t7_pc~0; 8260#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8149#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8150#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8092#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8093#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8500#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8527#L837-5 assume !(1 == ~T1_E~0); 8284#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 8285#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8431#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8341#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8342#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8584#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8258#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8259#L877-3 assume !(1 == ~E_2~0); 8336#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8387#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 8020#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8021#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8526#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8181#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8182#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 7834#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 8118#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 8119#L1167 assume !(0 == start_simulation_~tmp~3#1); 8236#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 8237#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 8042#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 7847#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 7848#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8218#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8219#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 8054#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 8055#L1148-2 [2023-11-29 01:11:03,309 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:03,309 INFO L85 PathProgramCache]: Analyzing trace with hash -1148673299, now seen corresponding path program 1 times [2023-11-29 01:11:03,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:03,309 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [791584631] [2023-11-29 01:11:03,310 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:03,310 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:03,325 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:03,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:03,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:03,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [791584631] [2023-11-29 01:11:03,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [791584631] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:03,357 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:03,357 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:03,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1337628392] [2023-11-29 01:11:03,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:03,358 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:03,358 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:03,359 INFO L85 PathProgramCache]: Analyzing trace with hash -1457955290, now seen corresponding path program 1 times [2023-11-29 01:11:03,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:03,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [85632417] [2023-11-29 01:11:03,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:03,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:03,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:03,420 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:03,420 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:03,420 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [85632417] [2023-11-29 01:11:03,420 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [85632417] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:03,421 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:03,421 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:03,421 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1345521925] [2023-11-29 01:11:03,421 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:03,421 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:03,422 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:03,422 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:03,422 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:03,423 INFO L87 Difference]: Start difference. First operand 776 states and 1152 transitions. cyclomatic complexity: 377 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:03,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:03,450 INFO L93 Difference]: Finished difference Result 776 states and 1151 transitions. [2023-11-29 01:11:03,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1151 transitions. [2023-11-29 01:11:03,456 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:03,463 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1151 transitions. [2023-11-29 01:11:03,463 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-29 01:11:03,464 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-29 01:11:03,464 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1151 transitions. [2023-11-29 01:11:03,466 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:03,466 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1151 transitions. [2023-11-29 01:11:03,467 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1151 transitions. [2023-11-29 01:11:03,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-29 01:11:03,481 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.4832474226804124) internal successors, (1151), 775 states have internal predecessors, (1151), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:03,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1151 transitions. [2023-11-29 01:11:03,485 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1151 transitions. [2023-11-29 01:11:03,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:03,487 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1151 transitions. [2023-11-29 01:11:03,487 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 01:11:03,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1151 transitions. [2023-11-29 01:11:03,492 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:03,492 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:03,492 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:03,494 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:03,494 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:03,494 INFO L748 eck$LassoCheckResult]: Stem: 9585#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 9586#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 10113#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10114#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10133#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 10125#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10126#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9734#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9735#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9804#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9648#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9649#L551-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9615#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9616#L754 assume !(0 == ~M_E~0); 10141#L754-2 assume !(0 == ~T1_E~0); 10083#L759-1 assume !(0 == ~T2_E~0); 9965#L764-1 assume !(0 == ~T3_E~0); 9930#L769-1 assume !(0 == ~T4_E~0); 9931#L774-1 assume !(0 == ~T5_E~0); 9966#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10088#L784-1 assume !(0 == ~T7_E~0); 9927#L789-1 assume !(0 == ~E_1~0); 9928#L794-1 assume !(0 == ~E_2~0); 10002#L799-1 assume !(0 == ~E_3~0); 9938#L804-1 assume !(0 == ~E_4~0); 9939#L809-1 assume !(0 == ~E_5~0); 9960#L814-1 assume !(0 == ~E_6~0); 9386#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 9387#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9645#L361 assume 1 == ~m_pc~0; 9646#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10109#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10069#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 10070#L930 assume !(0 != activate_threads_~tmp~1#1); 9847#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9639#L380 assume !(1 == ~t1_pc~0); 9640#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10008#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9408#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9409#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10028#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10009#L399 assume 1 == ~t2_pc~0; 10010#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9557#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9717#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9710#L946 assume !(0 != activate_threads_~tmp___1~0#1); 9711#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9394#L418 assume !(1 == ~t3_pc~0); 9373#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9374#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9384#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9385#L954 assume !(0 != activate_threads_~tmp___2~0#1); 9950#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9951#L437 assume 1 == ~t4_pc~0; 10142#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10064#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9467#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9468#L962 assume !(0 != activate_threads_~tmp___3~0#1); 9763#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10046#L456 assume !(1 == ~t5_pc~0); 9571#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9570#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10073#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9991#L970 assume !(0 != activate_threads_~tmp___4~0#1); 9992#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9461#L475 assume 1 == ~t6_pc~0; 9462#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9503#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9504#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9703#L978 assume !(0 != activate_threads_~tmp___5~0#1); 9943#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9944#L494 assume 1 == ~t7_pc~0; 9892#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 9688#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9903#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9967#L986 assume !(0 != activate_threads_~tmp___6~0#1); 9968#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10138#L837 assume !(1 == ~M_E~0); 10112#L837-2 assume !(1 == ~T1_E~0); 10005#L842-1 assume !(1 == ~T2_E~0); 9770#L847-1 assume !(1 == ~T3_E~0); 9771#L852-1 assume !(1 == ~T4_E~0); 9837#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9723#L862-1 assume !(1 == ~T6_E~0); 9724#L867-1 assume !(1 == ~T7_E~0); 9730#L872-1 assume !(1 == ~E_1~0); 9803#L877-1 assume !(1 == ~E_2~0); 9980#L882-1 assume !(1 == ~E_3~0); 10117#L887-1 assume !(1 == ~E_4~0); 10024#L892-1 assume !(1 == ~E_5~0); 10025#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 9746#L902-1 assume !(1 == ~E_7~0); 9747#L907-1 assume { :end_inline_reset_delta_events } true; 9614#L1148-2 [2023-11-29 01:11:03,495 INFO L750 eck$LassoCheckResult]: Loop: 9614#L1148-2 assume !false; 9388#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9389#L729-1 assume !false; 10000#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9587#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9588#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9736#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9632#L626 assume !(0 != eval_~tmp~0#1); 9633#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9846#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9661#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9400#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9401#L759-3 assume !(0 == ~T2_E~0); 9782#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9783#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9952#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9560#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9395#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9396#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9390#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9391#L799-3 assume !(0 == ~E_3~0); 9442#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9668#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9438#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9439#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10056#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9800#L361-24 assume 1 == ~m_pc~0; 9544#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9545#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9490#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 9491#L930-24 assume !(0 != activate_threads_~tmp~1#1); 10101#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9935#L380-24 assume 1 == ~t1_pc~0; 9936#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9473#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9882#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9657#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9658#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10011#L399-24 assume !(1 == ~t2_pc~0); 9676#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 9592#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9593#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9836#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9654#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9655#L418-24 assume 1 == ~t3_pc~0; 10100#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9437#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9727#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9563#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9564#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9994#L437-24 assume 1 == ~t4_pc~0; 10060#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10062#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9835#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9547#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9548#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9942#L456-24 assume 1 == ~t5_pc~0; 9916#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9896#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9897#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10095#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9848#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9849#L475-24 assume 1 == ~t6_pc~0; 9397#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9398#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9540#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9541#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9379#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9380#L494-24 assume !(1 == ~t7_pc~0); 9728#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 9708#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9709#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9651#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9652#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10059#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10086#L837-5 assume !(1 == ~T1_E~0); 9843#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9844#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9990#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9900#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9901#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10143#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9817#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9818#L877-3 assume !(1 == ~E_2~0); 9895#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9946#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9579#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9580#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10085#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9740#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9741#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9393#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9677#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 9678#L1167 assume !(0 == start_simulation_~tmp~3#1); 9795#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 9796#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 9601#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 9406#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 9407#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9777#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9778#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 9613#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 9614#L1148-2 [2023-11-29 01:11:03,495 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:03,495 INFO L85 PathProgramCache]: Analyzing trace with hash 1821437803, now seen corresponding path program 1 times [2023-11-29 01:11:03,496 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:03,496 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1706023636] [2023-11-29 01:11:03,496 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:03,496 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:03,509 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:03,540 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:03,540 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:03,541 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1706023636] [2023-11-29 01:11:03,541 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1706023636] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:03,541 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:03,541 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:03,541 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [9004889] [2023-11-29 01:11:03,541 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:03,542 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:03,542 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:03,542 INFO L85 PathProgramCache]: Analyzing trace with hash 1950017927, now seen corresponding path program 2 times [2023-11-29 01:11:03,542 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:03,543 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1854037609] [2023-11-29 01:11:03,543 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:03,543 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:03,558 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:03,600 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:03,600 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:03,601 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1854037609] [2023-11-29 01:11:03,601 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1854037609] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:03,601 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:03,601 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:03,601 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2088013638] [2023-11-29 01:11:03,601 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:03,602 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:03,602 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:03,602 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:03,602 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:03,603 INFO L87 Difference]: Start difference. First operand 776 states and 1151 transitions. cyclomatic complexity: 376 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:03,629 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:03,629 INFO L93 Difference]: Finished difference Result 776 states and 1150 transitions. [2023-11-29 01:11:03,629 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 776 states and 1150 transitions. [2023-11-29 01:11:03,636 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:03,642 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 776 states to 776 states and 1150 transitions. [2023-11-29 01:11:03,642 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 776 [2023-11-29 01:11:03,643 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 776 [2023-11-29 01:11:03,643 INFO L73 IsDeterministic]: Start isDeterministic. Operand 776 states and 1150 transitions. [2023-11-29 01:11:03,645 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:03,645 INFO L218 hiAutomatonCegarLoop]: Abstraction has 776 states and 1150 transitions. [2023-11-29 01:11:03,647 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 776 states and 1150 transitions. [2023-11-29 01:11:03,659 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 776 to 776. [2023-11-29 01:11:03,662 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 776 states, 776 states have (on average 1.481958762886598) internal successors, (1150), 775 states have internal predecessors, (1150), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:03,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 776 states to 776 states and 1150 transitions. [2023-11-29 01:11:03,665 INFO L240 hiAutomatonCegarLoop]: Abstraction has 776 states and 1150 transitions. [2023-11-29 01:11:03,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:03,667 INFO L428 stractBuchiCegarLoop]: Abstraction has 776 states and 1150 transitions. [2023-11-29 01:11:03,667 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 01:11:03,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 776 states and 1150 transitions. [2023-11-29 01:11:03,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 675 [2023-11-29 01:11:03,672 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:03,672 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:03,674 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:03,674 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:03,674 INFO L748 eck$LassoCheckResult]: Stem: 11144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 11145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 11672#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11673#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11692#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 11684#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11685#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11293#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11294#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11363#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11208#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11209#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 11174#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11175#L754 assume !(0 == ~M_E~0); 11700#L754-2 assume !(0 == ~T1_E~0); 11642#L759-1 assume !(0 == ~T2_E~0); 11524#L764-1 assume !(0 == ~T3_E~0); 11490#L769-1 assume !(0 == ~T4_E~0); 11491#L774-1 assume !(0 == ~T5_E~0); 11525#L779-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11647#L784-1 assume !(0 == ~T7_E~0); 11487#L789-1 assume !(0 == ~E_1~0); 11488#L794-1 assume !(0 == ~E_2~0); 11561#L799-1 assume !(0 == ~E_3~0); 11497#L804-1 assume !(0 == ~E_4~0); 11498#L809-1 assume !(0 == ~E_5~0); 11519#L814-1 assume !(0 == ~E_6~0); 10949#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 10950#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11204#L361 assume 1 == ~m_pc~0; 11205#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11668#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11628#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11629#L930 assume !(0 != activate_threads_~tmp~1#1); 11406#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11198#L380 assume !(1 == ~t1_pc~0); 11199#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 11567#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10967#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10968#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11587#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11568#L399 assume 1 == ~t2_pc~0; 11569#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11116#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11276#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11269#L946 assume !(0 != activate_threads_~tmp___1~0#1); 11270#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10953#L418 assume !(1 == ~t3_pc~0); 10932#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10933#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10943#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10944#L954 assume !(0 != activate_threads_~tmp___2~0#1); 11509#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11510#L437 assume 1 == ~t4_pc~0; 11701#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11624#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11027#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11028#L962 assume !(0 != activate_threads_~tmp___3~0#1); 11322#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11610#L456 assume !(1 == ~t5_pc~0); 11130#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11129#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11632#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11551#L970 assume !(0 != activate_threads_~tmp___4~0#1); 11552#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11020#L475 assume 1 == ~t6_pc~0; 11021#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11062#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11063#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11262#L978 assume !(0 != activate_threads_~tmp___5~0#1); 11502#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11503#L494 assume 1 == ~t7_pc~0; 11451#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11247#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11462#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11526#L986 assume !(0 != activate_threads_~tmp___6~0#1); 11527#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11697#L837 assume !(1 == ~M_E~0); 11671#L837-2 assume !(1 == ~T1_E~0); 11564#L842-1 assume !(1 == ~T2_E~0); 11329#L847-1 assume !(1 == ~T3_E~0); 11330#L852-1 assume !(1 == ~T4_E~0); 11396#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11282#L862-1 assume !(1 == ~T6_E~0); 11283#L867-1 assume !(1 == ~T7_E~0); 11289#L872-1 assume !(1 == ~E_1~0); 11362#L877-1 assume !(1 == ~E_2~0); 11539#L882-1 assume !(1 == ~E_3~0); 11676#L887-1 assume !(1 == ~E_4~0); 11583#L892-1 assume !(1 == ~E_5~0); 11584#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 11305#L902-1 assume !(1 == ~E_7~0); 11306#L907-1 assume { :end_inline_reset_delta_events } true; 11173#L1148-2 [2023-11-29 01:11:03,675 INFO L750 eck$LassoCheckResult]: Loop: 11173#L1148-2 assume !false; 10945#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10946#L729-1 assume !false; 11559#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11146#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11147#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11295#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11191#L626 assume !(0 != eval_~tmp~0#1); 11192#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11405#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11220#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10959#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10960#L759-3 assume !(0 == ~T2_E~0); 11341#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11342#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11511#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11119#L779-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10954#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10955#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10947#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10948#L799-3 assume !(0 == ~E_3~0); 11001#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11227#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10997#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10998#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11615#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11359#L361-24 assume !(1 == ~m_pc~0); 11105#L361-26 is_master_triggered_~__retres1~0#1 := 0; 11104#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11049#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 11050#L930-24 assume !(0 != activate_threads_~tmp~1#1); 11660#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11494#L380-24 assume 1 == ~t1_pc~0; 11495#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11032#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11441#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11216#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 11217#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11570#L399-24 assume !(1 == ~t2_pc~0); 11235#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 11151#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11152#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11395#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11213#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11214#L418-24 assume !(1 == ~t3_pc~0); 10995#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 10996#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11286#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11122#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11123#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11553#L437-24 assume 1 == ~t4_pc~0; 11619#L438-8 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11621#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11394#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11106#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11107#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11501#L456-24 assume 1 == ~t5_pc~0; 11475#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11455#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11456#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11654#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11407#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11408#L475-24 assume 1 == ~t6_pc~0; 10956#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10957#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11099#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11100#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10938#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10939#L494-24 assume 1 == ~t7_pc~0; 11378#L495-8 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11267#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11268#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11210#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11211#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11618#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11645#L837-5 assume !(1 == ~T1_E~0); 11402#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11403#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11549#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11459#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 11460#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11702#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11376#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11377#L877-3 assume !(1 == ~E_2~0); 11454#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11505#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11138#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 11139#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 11644#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11299#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11300#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 10952#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 11236#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 11237#L1167 assume !(0 == start_simulation_~tmp~3#1); 11354#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 11355#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 11160#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 10965#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 10966#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11336#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11337#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 11172#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 11173#L1148-2 [2023-11-29 01:11:03,675 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:03,676 INFO L85 PathProgramCache]: Analyzing trace with hash 254679853, now seen corresponding path program 1 times [2023-11-29 01:11:03,676 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:03,676 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265489023] [2023-11-29 01:11:03,676 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:03,676 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:03,693 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:03,790 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:03,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:03,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265489023] [2023-11-29 01:11:03,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265489023] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:03,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:03,791 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:03,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1718246583] [2023-11-29 01:11:03,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:03,791 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:03,792 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:03,792 INFO L85 PathProgramCache]: Analyzing trace with hash -1778828634, now seen corresponding path program 1 times [2023-11-29 01:11:03,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:03,792 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [80925851] [2023-11-29 01:11:03,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:03,793 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:03,810 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:03,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:03,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:03,855 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [80925851] [2023-11-29 01:11:03,855 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [80925851] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:03,855 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:03,855 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:03,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1461865889] [2023-11-29 01:11:03,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:03,856 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:03,856 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:03,856 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:11:03,856 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:11:03,857 INFO L87 Difference]: Start difference. First operand 776 states and 1150 transitions. cyclomatic complexity: 375 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:03,987 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:03,987 INFO L93 Difference]: Finished difference Result 1464 states and 2164 transitions. [2023-11-29 01:11:03,987 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1464 states and 2164 transitions. [2023-11-29 01:11:03,998 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2023-11-29 01:11:04,010 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1464 states to 1464 states and 2164 transitions. [2023-11-29 01:11:04,011 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1464 [2023-11-29 01:11:04,012 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1464 [2023-11-29 01:11:04,013 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1464 states and 2164 transitions. [2023-11-29 01:11:04,015 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:04,016 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2164 transitions. [2023-11-29 01:11:04,019 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states and 2164 transitions. [2023-11-29 01:11:04,049 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1464. [2023-11-29 01:11:04,053 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.4781420765027322) internal successors, (2164), 1463 states have internal predecessors, (2164), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:04,059 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2164 transitions. [2023-11-29 01:11:04,059 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2164 transitions. [2023-11-29 01:11:04,060 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:11:04,060 INFO L428 stractBuchiCegarLoop]: Abstraction has 1464 states and 2164 transitions. [2023-11-29 01:11:04,060 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 01:11:04,061 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2164 transitions. [2023-11-29 01:11:04,069 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2023-11-29 01:11:04,069 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:04,069 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:04,071 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:04,071 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:04,072 INFO L748 eck$LassoCheckResult]: Stem: 13395#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 13396#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 13972#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 13973#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14004#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 13990#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13991#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13547#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13548#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13625#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13459#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13460#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13425#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13426#L754 assume !(0 == ~M_E~0); 14022#L754-2 assume !(0 == ~T1_E~0); 13932#L759-1 assume !(0 == ~T2_E~0); 13799#L764-1 assume !(0 == ~T3_E~0); 13762#L769-1 assume !(0 == ~T4_E~0); 13763#L774-1 assume !(0 == ~T5_E~0); 13800#L779-1 assume !(0 == ~T6_E~0); 13940#L784-1 assume !(0 == ~T7_E~0); 13759#L789-1 assume !(0 == ~E_1~0); 13760#L794-1 assume !(0 == ~E_2~0); 13839#L799-1 assume !(0 == ~E_3~0); 13769#L804-1 assume !(0 == ~E_4~0); 13770#L809-1 assume !(0 == ~E_5~0); 13794#L814-1 assume !(0 == ~E_6~0); 13195#L819-1 assume 0 == ~E_7~0;~E_7~0 := 1; 13196#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13456#L361 assume 1 == ~m_pc~0; 13457#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13966#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13917#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13918#L930 assume !(0 != activate_threads_~tmp~1#1); 13671#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13450#L380 assume !(1 == ~t1_pc~0); 13451#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 13848#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13217#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13218#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13873#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13849#L399 assume 1 == ~t2_pc~0; 13850#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13367#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13529#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13522#L946 assume !(0 != activate_threads_~tmp___1~0#1); 13523#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13203#L418 assume !(1 == ~t3_pc~0); 13182#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 13183#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13193#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13194#L954 assume !(0 != activate_threads_~tmp___2~0#1); 13782#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13783#L437 assume 1 == ~t4_pc~0; 14023#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13912#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13276#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13277#L962 assume !(0 != activate_threads_~tmp___3~0#1); 13576#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13897#L456 assume !(1 == ~t5_pc~0); 13381#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13380#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13921#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13828#L970 assume !(0 != activate_threads_~tmp___4~0#1); 13829#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13270#L475 assume 1 == ~t6_pc~0; 13271#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13312#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13313#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13515#L978 assume !(0 != activate_threads_~tmp___5~0#1); 13775#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13776#L494 assume 1 == ~t7_pc~0; 13720#L495 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13500#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13734#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13801#L986 assume !(0 != activate_threads_~tmp___6~0#1); 13802#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14012#L837 assume !(1 == ~M_E~0); 13971#L837-2 assume !(1 == ~T1_E~0); 13844#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13845#L847-1 assume !(1 == ~T3_E~0); 14069#L852-1 assume !(1 == ~T4_E~0); 14067#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14066#L862-1 assume !(1 == ~T6_E~0); 13536#L867-1 assume !(1 == ~T7_E~0); 13623#L872-1 assume !(1 == ~E_1~0); 13624#L877-1 assume !(1 == ~E_2~0); 13816#L882-1 assume !(1 == ~E_3~0); 13977#L887-1 assume !(1 == ~E_4~0); 14026#L892-1 assume !(1 == ~E_5~0); 14007#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 13559#L902-1 assume !(1 == ~E_7~0); 13560#L907-1 assume { :end_inline_reset_delta_events } true; 13424#L1148-2 [2023-11-29 01:11:04,072 INFO L750 eck$LassoCheckResult]: Loop: 13424#L1148-2 assume !false; 13197#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13198#L729-1 assume !false; 14049#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14045#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 13946#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13554#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13445#L626 assume !(0 != eval_~tmp~0#1); 13446#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13670#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13472#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13209#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13210#L759-3 assume !(0 == ~T2_E~0); 14036#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14213#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14212#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 14211#L779-3 assume !(0 == ~T6_E~0); 14210#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14209#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14208#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 14207#L799-3 assume !(0 == ~E_3~0); 14206#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14205#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 14204#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 14203#L819-3 assume 0 == ~E_7~0;~E_7~0 := 1; 14202#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 14201#L361-24 assume 1 == ~m_pc~0; 13353#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13354#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13299#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 13300#L930-24 assume !(0 != activate_threads_~tmp~1#1); 13957#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13766#L380-24 assume !(1 == ~t1_pc~0); 13281#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 13282#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13710#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13468#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13469#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13851#L399-24 assume !(1 == ~t2_pc~0); 13924#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 14188#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 14187#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 14186#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13465#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13466#L418-24 assume 1 == ~t3_pc~0; 14184#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14183#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 14182#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14181#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 14180#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14179#L437-24 assume !(1 == ~t4_pc~0); 14177#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 14176#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14175#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 14174#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14173#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14172#L456-24 assume 1 == ~t5_pc~0; 14170#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 14169#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14168#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14167#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13672#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13673#L475-24 assume !(1 == ~t6_pc~0); 14034#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 13733#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13349#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13350#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13771#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14127#L494-24 assume !(1 == ~t7_pc~0); 13541#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 13519#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13520#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14118#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13906#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13907#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13937#L837-5 assume !(1 == ~T1_E~0); 13667#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13668#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14110#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14108#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14107#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14031#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 14105#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14104#L877-3 assume !(1 == ~E_2~0); 14101#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14100#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14099#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13935#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13936#L902-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13552#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 13553#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14084#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 13489#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 13490#L1167 assume !(0 == start_simulation_~tmp~3#1); 14082#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 14081#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 14073#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 14072#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 14071#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14070#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14068#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 13423#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 13424#L1148-2 [2023-11-29 01:11:04,073 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:04,073 INFO L85 PathProgramCache]: Analyzing trace with hash -2141947347, now seen corresponding path program 1 times [2023-11-29 01:11:04,073 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:04,073 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [738575696] [2023-11-29 01:11:04,073 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:04,073 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:04,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:04,147 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:04,147 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:04,147 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [738575696] [2023-11-29 01:11:04,148 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [738575696] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:04,148 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:04,148 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:04,148 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2024355419] [2023-11-29 01:11:04,148 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:04,149 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:04,149 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:04,150 INFO L85 PathProgramCache]: Analyzing trace with hash 596622562, now seen corresponding path program 1 times [2023-11-29 01:11:04,150 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:04,150 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [642403045] [2023-11-29 01:11:04,150 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:04,151 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:04,178 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:04,229 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:04,230 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:04,230 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [642403045] [2023-11-29 01:11:04,230 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [642403045] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:04,231 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:04,231 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:04,231 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1383382301] [2023-11-29 01:11:04,231 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:04,232 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:04,232 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:04,232 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:04,233 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:04,233 INFO L87 Difference]: Start difference. First operand 1464 states and 2164 transitions. cyclomatic complexity: 702 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:04,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:04,296 INFO L93 Difference]: Finished difference Result 1464 states and 2138 transitions. [2023-11-29 01:11:04,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1464 states and 2138 transitions. [2023-11-29 01:11:04,307 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2023-11-29 01:11:04,319 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1464 states to 1464 states and 2138 transitions. [2023-11-29 01:11:04,319 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1464 [2023-11-29 01:11:04,321 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1464 [2023-11-29 01:11:04,321 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1464 states and 2138 transitions. [2023-11-29 01:11:04,324 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:04,325 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2138 transitions. [2023-11-29 01:11:04,327 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1464 states and 2138 transitions. [2023-11-29 01:11:04,355 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1464 to 1464. [2023-11-29 01:11:04,358 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1464 states, 1464 states have (on average 1.460382513661202) internal successors, (2138), 1463 states have internal predecessors, (2138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:04,365 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1464 states to 1464 states and 2138 transitions. [2023-11-29 01:11:04,365 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1464 states and 2138 transitions. [2023-11-29 01:11:04,365 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:04,366 INFO L428 stractBuchiCegarLoop]: Abstraction has 1464 states and 2138 transitions. [2023-11-29 01:11:04,366 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 01:11:04,366 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1464 states and 2138 transitions. [2023-11-29 01:11:04,375 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1350 [2023-11-29 01:11:04,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:04,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:04,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:04,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:04,377 INFO L748 eck$LassoCheckResult]: Stem: 16327#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 16328#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 16893#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16894#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16922#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 16911#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16912#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16480#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16481#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16552#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16390#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16391#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16357#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 16358#L754 assume !(0 == ~M_E~0); 16934#L754-2 assume !(0 == ~T1_E~0); 16860#L759-1 assume !(0 == ~T2_E~0); 16721#L764-1 assume !(0 == ~T3_E~0); 16681#L769-1 assume !(0 == ~T4_E~0); 16682#L774-1 assume !(0 == ~T5_E~0); 16722#L779-1 assume !(0 == ~T6_E~0); 16865#L784-1 assume !(0 == ~T7_E~0); 16678#L789-1 assume !(0 == ~E_1~0); 16679#L794-1 assume !(0 == ~E_2~0); 16764#L799-1 assume !(0 == ~E_3~0); 16689#L804-1 assume !(0 == ~E_4~0); 16690#L809-1 assume !(0 == ~E_5~0); 16716#L814-1 assume !(0 == ~E_6~0); 16130#L819-1 assume !(0 == ~E_7~0); 16131#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16387#L361 assume 1 == ~m_pc~0; 16388#L362 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16888#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16846#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 16847#L930 assume !(0 != activate_threads_~tmp~1#1); 16597#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16381#L380 assume !(1 == ~t1_pc~0); 16382#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 16773#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16152#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 16153#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16800#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16774#L399 assume 1 == ~t2_pc~0; 16775#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16299#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16463#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16456#L946 assume !(0 != activate_threads_~tmp___1~0#1); 16457#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16138#L418 assume !(1 == ~t3_pc~0); 16117#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 16118#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16128#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16129#L954 assume !(0 != activate_threads_~tmp___2~0#1); 16702#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16703#L437 assume 1 == ~t4_pc~0; 16935#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16841#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16211#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16212#L962 assume !(0 != activate_threads_~tmp___3~0#1); 16510#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16820#L456 assume !(1 == ~t5_pc~0); 16313#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 16312#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16850#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16752#L970 assume !(0 != activate_threads_~tmp___4~0#1); 16753#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16205#L475 assume 1 == ~t6_pc~0; 16206#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 16247#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16248#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16449#L978 assume !(0 != activate_threads_~tmp___5~0#1); 16694#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16695#L494 assume !(1 == ~t7_pc~0); 16433#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 16434#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16653#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16723#L986 assume !(0 != activate_threads_~tmp___6~0#1); 16724#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16928#L837 assume !(1 == ~M_E~0); 16892#L837-2 assume !(1 == ~T1_E~0); 16769#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16517#L847-1 assume !(1 == ~T3_E~0); 16518#L852-1 assume !(1 == ~T4_E~0); 16586#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16469#L862-1 assume !(1 == ~T6_E~0); 16470#L867-1 assume !(1 == ~T7_E~0); 16476#L872-1 assume !(1 == ~E_1~0); 16551#L877-1 assume !(1 == ~E_2~0); 16738#L882-1 assume !(1 == ~E_3~0); 16985#L887-1 assume !(1 == ~E_4~0); 16792#L892-1 assume !(1 == ~E_5~0); 16793#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 16493#L902-1 assume !(1 == ~E_7~0); 16494#L907-1 assume { :end_inline_reset_delta_events } true; 16538#L1148-2 [2023-11-29 01:11:04,377 INFO L750 eck$LassoCheckResult]: Loop: 16538#L1148-2 assume !false; 16539#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16761#L729-1 assume !false; 16762#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16329#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16330#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16948#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16374#L626 assume !(0 != eval_~tmp~0#1); 16375#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16596#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16405#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16144#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16145#L759-3 assume !(0 == ~T2_E~0); 16945#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17451#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17450#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17449#L779-3 assume !(0 == ~T6_E~0); 17448#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17447#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 17446#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 17445#L799-3 assume !(0 == ~E_3~0); 17444#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 17443#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17442#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17441#L819-3 assume !(0 == ~E_7~0); 17440#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17439#L361-24 assume 1 == ~m_pc~0; 17437#L362-8 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17436#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17435#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 17434#L930-24 assume !(0 != activate_threads_~tmp~1#1); 17433#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17432#L380-24 assume 1 == ~t1_pc~0; 17430#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17429#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17428#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17427#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17426#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17425#L399-24 assume !(1 == ~t2_pc~0); 17424#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 17422#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17421#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17420#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 17419#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17418#L418-24 assume 1 == ~t3_pc~0; 17416#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17415#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17414#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17413#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17412#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17411#L437-24 assume !(1 == ~t4_pc~0); 17409#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 17408#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17407#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17406#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17405#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17404#L456-24 assume 1 == ~t5_pc~0; 17402#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17401#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17400#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17399#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17398#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17397#L475-24 assume !(1 == ~t6_pc~0); 17395#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 17394#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17393#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17392#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17391#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17390#L494-24 assume !(1 == ~t7_pc~0); 17388#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 17387#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17386#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17385#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17384#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17383#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17382#L837-5 assume !(1 == ~T1_E~0); 17381#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16593#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17380#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17379#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 17378#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16942#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16565#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16566#L877-3 assume !(1 == ~E_2~0); 16645#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16697#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16321#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16322#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16862#L902-3 assume !(1 == ~E_7~0); 16487#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16488#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16137#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16422#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 16423#L1167 assume !(0 == start_simulation_~tmp~3#1); 16543#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 16544#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 16343#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 16982#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 16981#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16979#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16977#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 16961#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 16538#L1148-2 [2023-11-29 01:11:04,378 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:04,378 INFO L85 PathProgramCache]: Analyzing trace with hash 1307665866, now seen corresponding path program 1 times [2023-11-29 01:11:04,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:04,378 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1274016802] [2023-11-29 01:11:04,378 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:04,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:04,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:04,470 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:04,471 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:04,471 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1274016802] [2023-11-29 01:11:04,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1274016802] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:04,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:04,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:04,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1546651387] [2023-11-29 01:11:04,473 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:04,473 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:04,474 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:04,474 INFO L85 PathProgramCache]: Analyzing trace with hash -482217473, now seen corresponding path program 1 times [2023-11-29 01:11:04,474 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:04,474 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1696867281] [2023-11-29 01:11:04,475 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:04,475 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:04,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:04,544 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:04,545 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:04,545 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1696867281] [2023-11-29 01:11:04,545 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1696867281] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:04,545 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:04,546 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:04,546 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [881462779] [2023-11-29 01:11:04,546 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:04,547 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:04,547 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:04,547 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:04,548 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:04,548 INFO L87 Difference]: Start difference. First operand 1464 states and 2138 transitions. cyclomatic complexity: 676 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:04,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:04,671 INFO L93 Difference]: Finished difference Result 2793 states and 4040 transitions. [2023-11-29 01:11:04,671 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2793 states and 4040 transitions. [2023-11-29 01:11:04,693 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2676 [2023-11-29 01:11:04,716 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2793 states to 2793 states and 4040 transitions. [2023-11-29 01:11:04,716 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2793 [2023-11-29 01:11:04,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2793 [2023-11-29 01:11:04,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2793 states and 4040 transitions. [2023-11-29 01:11:04,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:04,725 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2793 states and 4040 transitions. [2023-11-29 01:11:04,730 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2793 states and 4040 transitions. [2023-11-29 01:11:04,777 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2793 to 2679. [2023-11-29 01:11:04,783 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2679 states, 2679 states have (on average 1.4497946995147444) internal successors, (3884), 2678 states have internal predecessors, (3884), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:04,794 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2679 states to 2679 states and 3884 transitions. [2023-11-29 01:11:04,794 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2679 states and 3884 transitions. [2023-11-29 01:11:04,795 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:04,795 INFO L428 stractBuchiCegarLoop]: Abstraction has 2679 states and 3884 transitions. [2023-11-29 01:11:04,795 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 01:11:04,795 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2679 states and 3884 transitions. [2023-11-29 01:11:04,807 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2562 [2023-11-29 01:11:04,808 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:04,808 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:04,809 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:04,810 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:04,810 INFO L748 eck$LassoCheckResult]: Stem: 20589#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 20590#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 21204#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21205#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21256#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 21238#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21239#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20743#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20744#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20818#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 20651#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20652#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20619#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20620#L754 assume !(0 == ~M_E~0); 21273#L754-2 assume !(0 == ~T1_E~0); 21157#L759-1 assume !(0 == ~T2_E~0); 21013#L764-1 assume !(0 == ~T3_E~0); 20966#L769-1 assume !(0 == ~T4_E~0); 20967#L774-1 assume !(0 == ~T5_E~0); 21014#L779-1 assume !(0 == ~T6_E~0); 21165#L784-1 assume !(0 == ~T7_E~0); 20962#L789-1 assume !(0 == ~E_1~0); 20963#L794-1 assume !(0 == ~E_2~0); 21062#L799-1 assume !(0 == ~E_3~0); 20976#L804-1 assume !(0 == ~E_4~0); 20977#L809-1 assume !(0 == ~E_5~0); 21007#L814-1 assume !(0 == ~E_6~0); 20394#L819-1 assume !(0 == ~E_7~0); 20395#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20649#L361 assume !(1 == ~m_pc~0); 20650#L361-2 is_master_triggered_~__retres1~0#1 := 0; 21198#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21144#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 21145#L930 assume !(0 != activate_threads_~tmp~1#1); 20870#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20643#L380 assume !(1 == ~t1_pc~0); 20644#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 21073#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20416#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20417#L938 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21096#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21074#L399 assume 1 == ~t2_pc~0; 21075#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 20561#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20722#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20715#L946 assume !(0 != activate_threads_~tmp___1~0#1); 20716#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 20402#L418 assume !(1 == ~t3_pc~0); 20381#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20382#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20392#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20393#L954 assume !(0 != activate_threads_~tmp___2~0#1); 20994#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20995#L437 assume 1 == ~t4_pc~0; 21275#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21137#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20475#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20476#L962 assume !(0 != activate_threads_~tmp___3~0#1); 20773#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21116#L456 assume !(1 == ~t5_pc~0); 20575#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 20574#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21148#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21049#L970 assume !(0 != activate_threads_~tmp___4~0#1); 21050#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20469#L475 assume 1 == ~t6_pc~0; 20470#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20510#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20511#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20708#L978 assume !(0 != activate_threads_~tmp___5~0#1); 20983#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20984#L494 assume !(1 == ~t7_pc~0); 20692#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20693#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20934#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21015#L986 assume !(0 != activate_threads_~tmp___6~0#1); 21016#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21264#L837 assume !(1 == ~M_E~0); 21203#L837-2 assume !(1 == ~T1_E~0); 21068#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20781#L847-1 assume !(1 == ~T3_E~0); 20782#L852-1 assume !(1 == ~T4_E~0); 22571#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22563#L862-1 assume !(1 == ~T6_E~0); 20729#L867-1 assume !(1 == ~T7_E~0); 22560#L872-1 assume !(1 == ~E_1~0); 22559#L877-1 assume !(1 == ~E_2~0); 22558#L882-1 assume !(1 == ~E_3~0); 22557#L887-1 assume !(1 == ~E_4~0); 22556#L892-1 assume !(1 == ~E_5~0); 22554#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 22552#L902-1 assume !(1 == ~E_7~0); 22551#L907-1 assume { :end_inline_reset_delta_events } true; 22549#L1148-2 [2023-11-29 01:11:04,810 INFO L750 eck$LassoCheckResult]: Loop: 22549#L1148-2 assume !false; 22528#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22527#L729-1 assume !false; 22526#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20591#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20592#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20745#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 20746#L626 assume !(0 != eval_~tmp~0#1); 21091#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21092#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20664#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20408#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 20409#L759-3 assume !(0 == ~T2_E~0); 22517#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 22691#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 22690#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 22689#L779-3 assume !(0 == ~T6_E~0); 22688#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 22687#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 22686#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 22685#L799-3 assume !(0 == ~E_3~0); 22684#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22683#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 22682#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 22681#L819-3 assume !(0 == ~E_7~0); 22680#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 22679#L361-24 assume !(1 == ~m_pc~0); 22678#L361-26 is_master_triggered_~__retres1~0#1 := 0; 22677#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 22676#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 22675#L930-24 assume !(0 != activate_threads_~tmp~1#1); 22674#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 22673#L380-24 assume !(1 == ~t1_pc~0); 22672#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 22670#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 22669#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 22668#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22667#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22666#L399-24 assume 1 == ~t2_pc~0; 22664#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22663#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22662#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 22661#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 22660#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22659#L418-24 assume 1 == ~t3_pc~0; 22657#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20734#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20735#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20567#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20568#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21052#L437-24 assume !(1 == ~t4_pc~0); 22630#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 21287#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21288#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20553#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20554#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21250#L456-24 assume 1 == ~t5_pc~0; 21251#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22627#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22626#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21207#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21208#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22623#L475-24 assume 1 == ~t6_pc~0; 20405#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20406#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 20546#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20547#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20978#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20924#L494-24 assume !(1 == ~t7_pc~0); 20834#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 20713#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20714#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22604#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21131#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21132#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21265#L837-5 assume !(1 == ~T1_E~0); 21266#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20865#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 21232#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 20929#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 20930#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21294#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 20831#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20832#L877-3 assume !(1 == ~E_2~0); 22591#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 20987#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20988#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21160#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21161#L902-3 assume !(1 == ~E_7~0); 20750#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 20751#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 21000#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20680#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 20681#L1167 assume !(0 == start_simulation_~tmp~3#1); 21234#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 21292#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 20605#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 20414#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 20415#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22555#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 22553#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 22550#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 22549#L1148-2 [2023-11-29 01:11:04,811 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:04,811 INFO L85 PathProgramCache]: Analyzing trace with hash 2012584553, now seen corresponding path program 1 times [2023-11-29 01:11:04,811 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:04,811 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [613839570] [2023-11-29 01:11:04,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:04,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:04,825 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:04,885 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:04,885 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:04,886 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [613839570] [2023-11-29 01:11:04,886 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [613839570] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:04,886 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:04,886 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:11:04,886 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [280663676] [2023-11-29 01:11:04,886 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:04,887 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:04,887 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:04,887 INFO L85 PathProgramCache]: Analyzing trace with hash -601253057, now seen corresponding path program 1 times [2023-11-29 01:11:04,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:04,887 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [666706535] [2023-11-29 01:11:04,887 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:04,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:04,899 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:04,928 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:04,928 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:04,928 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [666706535] [2023-11-29 01:11:04,928 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [666706535] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:04,928 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:04,929 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:04,929 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1953412741] [2023-11-29 01:11:04,929 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:04,929 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:04,929 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:04,930 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:11:04,930 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:11:04,930 INFO L87 Difference]: Start difference. First operand 2679 states and 3884 transitions. cyclomatic complexity: 1209 Second operand has 5 states, 5 states have (on average 18.6) internal successors, (93), 5 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:05,236 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:05,236 INFO L93 Difference]: Finished difference Result 6723 states and 9613 transitions. [2023-11-29 01:11:05,237 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 6723 states and 9613 transitions. [2023-11-29 01:11:05,265 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 6484 [2023-11-29 01:11:05,306 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 6723 states to 6723 states and 9613 transitions. [2023-11-29 01:11:05,307 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 6723 [2023-11-29 01:11:05,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 6723 [2023-11-29 01:11:05,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 6723 states and 9613 transitions. [2023-11-29 01:11:05,320 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:05,320 INFO L218 hiAutomatonCegarLoop]: Abstraction has 6723 states and 9613 transitions. [2023-11-29 01:11:05,326 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 6723 states and 9613 transitions. [2023-11-29 01:11:05,371 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 6723 to 2784. [2023-11-29 01:11:05,376 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2784 states, 2784 states have (on average 1.432830459770115) internal successors, (3989), 2783 states have internal predecessors, (3989), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:05,381 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2784 states to 2784 states and 3989 transitions. [2023-11-29 01:11:05,382 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2784 states and 3989 transitions. [2023-11-29 01:11:05,382 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 01:11:05,383 INFO L428 stractBuchiCegarLoop]: Abstraction has 2784 states and 3989 transitions. [2023-11-29 01:11:05,383 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 01:11:05,383 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2784 states and 3989 transitions. [2023-11-29 01:11:05,391 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2664 [2023-11-29 01:11:05,391 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:05,391 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:05,392 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:05,392 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:05,393 INFO L748 eck$LassoCheckResult]: Stem: 30006#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 30007#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 30608#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 30609#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 30657#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 30636#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 30637#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 30159#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 30160#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 30231#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 30068#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 30069#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 30036#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 30037#L754 assume !(0 == ~M_E~0); 30679#L754-2 assume !(0 == ~T1_E~0); 30564#L759-1 assume !(0 == ~T2_E~0); 30419#L764-1 assume !(0 == ~T3_E~0); 30374#L769-1 assume !(0 == ~T4_E~0); 30375#L774-1 assume !(0 == ~T5_E~0); 30420#L779-1 assume !(0 == ~T6_E~0); 30574#L784-1 assume !(0 == ~T7_E~0); 30371#L789-1 assume !(0 == ~E_1~0); 30372#L794-1 assume !(0 == ~E_2~0); 30467#L799-1 assume !(0 == ~E_3~0); 30383#L804-1 assume !(0 == ~E_4~0); 30384#L809-1 assume !(0 == ~E_5~0); 30414#L814-1 assume !(0 == ~E_6~0); 29809#L819-1 assume !(0 == ~E_7~0); 29810#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30066#L361 assume !(1 == ~m_pc~0); 30067#L361-2 is_master_triggered_~__retres1~0#1 := 0; 30602#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30550#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 30551#L930 assume !(0 != activate_threads_~tmp~1#1); 30280#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30060#L380 assume !(1 == ~t1_pc~0); 30061#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 30654#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30655#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30702#L938 assume !(0 != activate_threads_~tmp___0~0#1); 30502#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30480#L399 assume 1 == ~t2_pc~0; 30481#L400 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29978#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 30139#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30132#L946 assume !(0 != activate_threads_~tmp___1~0#1); 30133#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29817#L418 assume !(1 == ~t3_pc~0); 29796#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 29797#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29807#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29808#L954 assume !(0 != activate_threads_~tmp___2~0#1); 30402#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 30403#L437 assume 1 == ~t4_pc~0; 30682#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 30543#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29890#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29891#L962 assume !(0 != activate_threads_~tmp___3~0#1); 30188#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 30521#L456 assume !(1 == ~t5_pc~0); 29992#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 29991#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 30554#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 30452#L970 assume !(0 != activate_threads_~tmp___4~0#1); 30453#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29884#L475 assume 1 == ~t6_pc~0; 29885#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 29927#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29928#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 30125#L978 assume !(0 != activate_threads_~tmp___5~0#1); 30389#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30390#L494 assume !(1 == ~t7_pc~0); 30109#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 30110#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30340#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30421#L986 assume !(0 != activate_threads_~tmp___6~0#1); 30422#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 30667#L837 assume !(1 == ~M_E~0); 30607#L837-2 assume !(1 == ~T1_E~0); 30475#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30195#L847-1 assume !(1 == ~T3_E~0); 30196#L852-1 assume !(1 == ~T4_E~0); 31849#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 30145#L862-1 assume !(1 == ~T6_E~0); 30146#L867-1 assume !(1 == ~T7_E~0); 30153#L872-1 assume !(1 == ~E_1~0); 30230#L877-1 assume !(1 == ~E_2~0); 30436#L882-1 assume !(1 == ~E_3~0); 31836#L887-1 assume !(1 == ~E_4~0); 31834#L892-1 assume !(1 == ~E_5~0); 31832#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 31824#L902-1 assume !(1 == ~E_7~0); 31817#L907-1 assume { :end_inline_reset_delta_events } true; 31810#L1148-2 [2023-11-29 01:11:05,393 INFO L750 eck$LassoCheckResult]: Loop: 31810#L1148-2 assume !false; 31806#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 31805#L729-1 assume !false; 31804#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31800#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31795#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31794#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 31792#L626 assume !(0 != eval_~tmp~0#1); 31793#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 32541#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 30081#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 29823#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 29824#L759-3 assume !(0 == ~T2_E~0); 32539#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 32538#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 32537#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 29981#L779-3 assume !(0 == ~T6_E~0); 29818#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 29819#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 29813#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 29814#L799-3 assume !(0 == ~E_3~0); 29865#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 30088#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 29861#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 29862#L819-3 assume !(0 == ~E_7~0); 30533#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 30225#L361-24 assume !(1 == ~m_pc~0); 30226#L361-26 is_master_triggered_~__retres1~0#1 := 0; 30324#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29914#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 29915#L930-24 assume !(0 != activate_threads_~tmp~1#1); 30593#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 30618#L380-24 assume !(1 == ~t1_pc~0); 29896#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 29897#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 30645#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 30077#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 30078#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 30482#L399-24 assume 1 == ~t2_pc~0; 32427#L400-8 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 32426#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 32425#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 32424#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 32423#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 32422#L418-24 assume !(1 == ~t3_pc~0); 32416#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 32405#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 32402#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 32379#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 32378#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 32377#L437-24 assume !(1 == ~t4_pc~0); 32374#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 32372#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 32370#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 32367#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 32365#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 32348#L456-24 assume 1 == ~t5_pc~0; 32340#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 32337#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 32334#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 32329#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 32326#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 32323#L475-24 assume 1 == ~t6_pc~0; 32320#L476-8 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 32316#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 32313#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 32308#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 32271#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 30334#L494-24 assume !(1 == ~t7_pc~0); 30150#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 30130#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 30131#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 30071#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 30072#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 31936#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 31935#L837-5 assume !(1 == ~T1_E~0); 31934#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 30275#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 31933#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 31932#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 31930#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 30699#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 31927#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 31925#L877-3 assume !(1 == ~E_2~0); 31924#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 31922#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 31920#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 31918#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 31917#L902-3 assume !(1 == ~E_7~0); 31915#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31908#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31902#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31900#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 31898#L1167 assume !(0 == start_simulation_~tmp~3#1); 31895#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 31886#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 31875#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 31870#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 31863#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 31831#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 31823#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 31816#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 31810#L1148-2 [2023-11-29 01:11:05,393 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:05,393 INFO L85 PathProgramCache]: Analyzing trace with hash -1406363737, now seen corresponding path program 1 times [2023-11-29 01:11:05,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:05,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1459987524] [2023-11-29 01:11:05,394 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:05,394 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:05,405 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:05,439 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:05,439 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:05,439 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1459987524] [2023-11-29 01:11:05,439 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1459987524] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:05,440 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:05,440 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:05,440 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1808388589] [2023-11-29 01:11:05,440 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:05,440 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:05,441 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:05,441 INFO L85 PathProgramCache]: Analyzing trace with hash 1820099420, now seen corresponding path program 1 times [2023-11-29 01:11:05,441 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:05,441 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1510099300] [2023-11-29 01:11:05,442 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:05,442 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:05,455 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:05,482 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:05,482 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:05,482 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1510099300] [2023-11-29 01:11:05,483 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1510099300] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:05,483 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:05,483 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:05,483 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [451002234] [2023-11-29 01:11:05,483 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:05,483 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:05,483 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:05,484 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:05,484 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:05,484 INFO L87 Difference]: Start difference. First operand 2784 states and 3989 transitions. cyclomatic complexity: 1209 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:05,567 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:05,567 INFO L93 Difference]: Finished difference Result 5175 states and 7372 transitions. [2023-11-29 01:11:05,567 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5175 states and 7372 transitions. [2023-11-29 01:11:05,585 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5044 [2023-11-29 01:11:05,610 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5175 states to 5175 states and 7372 transitions. [2023-11-29 01:11:05,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5175 [2023-11-29 01:11:05,614 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5175 [2023-11-29 01:11:05,615 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5175 states and 7372 transitions. [2023-11-29 01:11:05,619 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:05,620 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5175 states and 7372 transitions. [2023-11-29 01:11:05,625 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5175 states and 7372 transitions. [2023-11-29 01:11:05,715 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5175 to 5167. [2023-11-29 01:11:05,723 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5167 states, 5167 states have (on average 1.4251983742984324) internal successors, (7364), 5166 states have internal predecessors, (7364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:05,734 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5167 states to 5167 states and 7364 transitions. [2023-11-29 01:11:05,734 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5167 states and 7364 transitions. [2023-11-29 01:11:05,734 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:05,735 INFO L428 stractBuchiCegarLoop]: Abstraction has 5167 states and 7364 transitions. [2023-11-29 01:11:05,735 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 01:11:05,735 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5167 states and 7364 transitions. [2023-11-29 01:11:05,751 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5036 [2023-11-29 01:11:05,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:05,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:05,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:05,753 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:05,753 INFO L748 eck$LassoCheckResult]: Stem: 37975#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 37976#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 38576#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 38577#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 38618#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 38602#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 38603#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 38135#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 38136#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38210#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38043#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 38044#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 38008#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38009#L754 assume !(0 == ~M_E~0); 38638#L754-2 assume !(0 == ~T1_E~0); 38532#L759-1 assume !(0 == ~T2_E~0); 38390#L764-1 assume !(0 == ~T3_E~0); 38349#L769-1 assume !(0 == ~T4_E~0); 38350#L774-1 assume !(0 == ~T5_E~0); 38391#L779-1 assume !(0 == ~T6_E~0); 38543#L784-1 assume !(0 == ~T7_E~0); 38346#L789-1 assume !(0 == ~E_1~0); 38347#L794-1 assume !(0 == ~E_2~0); 38437#L799-1 assume !(0 == ~E_3~0); 38357#L804-1 assume !(0 == ~E_4~0); 38358#L809-1 assume !(0 == ~E_5~0); 38384#L814-1 assume !(0 == ~E_6~0); 37779#L819-1 assume !(0 == ~E_7~0); 37780#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38039#L361 assume !(1 == ~m_pc~0); 38040#L361-2 is_master_triggered_~__retres1~0#1 := 0; 38570#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 38517#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 38518#L930 assume !(0 != activate_threads_~tmp~1#1); 38255#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38033#L380 assume !(1 == ~t1_pc~0); 38034#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 38669#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 37797#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 37798#L938 assume !(0 != activate_threads_~tmp___0~0#1); 38469#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38450#L399 assume !(1 == ~t2_pc~0); 37946#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 37947#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38114#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 38107#L946 assume !(0 != activate_threads_~tmp___1~0#1); 38108#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 37783#L418 assume !(1 == ~t3_pc~0); 37762#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 37763#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 37773#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 37774#L954 assume !(0 != activate_threads_~tmp___2~0#1); 38373#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38374#L437 assume 1 == ~t4_pc~0; 38639#L438 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38511#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 37858#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 37859#L962 assume !(0 != activate_threads_~tmp___3~0#1); 38165#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38494#L456 assume !(1 == ~t5_pc~0); 37961#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 37960#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38522#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38426#L970 assume !(0 != activate_threads_~tmp___4~0#1); 38427#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 37850#L475 assume 1 == ~t6_pc~0; 37851#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 37894#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 37895#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38100#L978 assume !(0 != activate_threads_~tmp___5~0#1); 38364#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38365#L494 assume !(1 == ~t7_pc~0); 38084#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 38085#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 38320#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38392#L986 assume !(0 != activate_threads_~tmp___6~0#1); 38393#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38630#L837 assume !(1 == ~M_E~0); 38575#L837-2 assume !(1 == ~T1_E~0); 38444#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 38174#L847-1 assume !(1 == ~T3_E~0); 38175#L852-1 assume !(1 == ~T4_E~0); 38245#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 38120#L862-1 assume !(1 == ~T6_E~0); 38121#L867-1 assume !(1 == ~T7_E~0); 38129#L872-1 assume !(1 == ~E_1~0); 38209#L877-1 assume !(1 == ~E_2~0); 38583#L882-1 assume !(1 == ~E_3~0); 38584#L887-1 assume !(1 == ~E_4~0); 38465#L892-1 assume !(1 == ~E_5~0); 38466#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 38149#L902-1 assume !(1 == ~E_7~0); 38150#L907-1 assume { :end_inline_reset_delta_events } true; 38488#L1148-2 [2023-11-29 01:11:05,753 INFO L750 eck$LassoCheckResult]: Loop: 38488#L1148-2 assume !false; 39659#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 39660#L729-1 assume !false; 38666#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 37977#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 37978#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 38137#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 38026#L626 assume !(0 != eval_~tmp~0#1); 38027#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 38254#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 38055#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37789#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 37790#L759-3 assume !(0 == ~T2_E~0); 38185#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 38186#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 38375#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 37950#L779-3 assume !(0 == ~T6_E~0); 37784#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 37785#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 37775#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 37776#L799-3 assume !(0 == ~E_3~0); 37831#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 38063#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 37827#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 37828#L819-3 assume !(0 == ~E_7~0); 38500#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38205#L361-24 assume !(1 == ~m_pc~0); 38206#L361-26 is_master_triggered_~__retres1~0#1 := 0; 42922#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42921#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 42920#L930-24 assume !(0 != activate_threads_~tmp~1#1); 42919#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42918#L380-24 assume !(1 == ~t1_pc~0); 42916#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 42914#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 42912#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 42911#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 42873#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 42872#L399-24 assume !(1 == ~t2_pc~0); 42865#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 42863#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42860#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42858#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 42856#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 42854#L418-24 assume 1 == ~t3_pc~0; 42851#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 42850#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 42849#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 42848#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 42847#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 42846#L437-24 assume !(1 == ~t4_pc~0); 42844#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 42843#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 42842#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 42841#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 42840#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38613#L456-24 assume 1 == ~t5_pc~0; 38614#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 42836#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 42785#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 42784#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 42783#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 42782#L475-24 assume !(1 == ~t6_pc~0); 42780#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 38318#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38319#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 42776#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 37768#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 37769#L494-24 assume !(1 == ~t7_pc~0); 42773#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 42772#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 42771#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 42770#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 42769#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 42768#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 42767#L837-5 assume !(1 == ~T1_E~0); 42766#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 41998#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 42765#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 42738#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 42735#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 41983#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38223#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 38224#L877-3 assume !(1 == ~E_2~0); 38652#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 38367#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 37969#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 37970#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 38537#L902-3 assume !(1 == ~E_7~0); 38141#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 38142#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 40024#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 40025#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 40015#L1167 assume !(0 == start_simulation_~tmp~3#1); 40014#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 39804#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 39789#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 39782#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 39773#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 39766#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 39767#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 39684#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 38488#L1148-2 [2023-11-29 01:11:05,754 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:05,754 INFO L85 PathProgramCache]: Analyzing trace with hash -2107931962, now seen corresponding path program 1 times [2023-11-29 01:11:05,754 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:05,754 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [502935315] [2023-11-29 01:11:05,754 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:05,754 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:05,764 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:05,793 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:05,793 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:05,793 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [502935315] [2023-11-29 01:11:05,794 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [502935315] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:05,794 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:05,794 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:05,794 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1125913704] [2023-11-29 01:11:05,794 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:05,794 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:05,795 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:05,795 INFO L85 PathProgramCache]: Analyzing trace with hash -228310597, now seen corresponding path program 1 times [2023-11-29 01:11:05,795 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:05,795 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1037989238] [2023-11-29 01:11:05,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:05,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:05,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:05,831 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:05,831 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:05,831 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1037989238] [2023-11-29 01:11:05,831 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1037989238] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:05,832 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:05,832 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:05,832 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1005419676] [2023-11-29 01:11:05,832 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:05,832 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:05,832 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:05,833 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:05,833 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:05,833 INFO L87 Difference]: Start difference. First operand 5167 states and 7364 transitions. cyclomatic complexity: 2205 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:05,935 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:05,935 INFO L93 Difference]: Finished difference Result 9674 states and 13721 transitions. [2023-11-29 01:11:05,935 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9674 states and 13721 transitions. [2023-11-29 01:11:05,971 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9512 [2023-11-29 01:11:06,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9674 states to 9674 states and 13721 transitions. [2023-11-29 01:11:06,006 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9674 [2023-11-29 01:11:06,014 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9674 [2023-11-29 01:11:06,014 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9674 states and 13721 transitions. [2023-11-29 01:11:06,023 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:06,023 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9674 states and 13721 transitions. [2023-11-29 01:11:06,034 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9674 states and 13721 transitions. [2023-11-29 01:11:06,190 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9674 to 9658. [2023-11-29 01:11:06,209 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9658 states, 9658 states have (on average 1.419030855249534) internal successors, (13705), 9657 states have internal predecessors, (13705), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:06,234 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9658 states to 9658 states and 13705 transitions. [2023-11-29 01:11:06,234 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9658 states and 13705 transitions. [2023-11-29 01:11:06,234 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:06,235 INFO L428 stractBuchiCegarLoop]: Abstraction has 9658 states and 13705 transitions. [2023-11-29 01:11:06,235 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 01:11:06,235 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9658 states and 13705 transitions. [2023-11-29 01:11:06,261 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 9496 [2023-11-29 01:11:06,261 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:06,261 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:06,263 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:06,263 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:06,263 INFO L748 eck$LassoCheckResult]: Stem: 52824#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 52825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 53409#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 53410#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 53452#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 53431#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53432#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 52978#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 52979#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53050#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 52890#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 52891#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 52857#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 52858#L754 assume !(0 == ~M_E~0); 53469#L754-2 assume !(0 == ~T1_E~0); 53364#L759-1 assume !(0 == ~T2_E~0); 53224#L764-1 assume !(0 == ~T3_E~0); 53184#L769-1 assume !(0 == ~T4_E~0); 53185#L774-1 assume !(0 == ~T5_E~0); 53225#L779-1 assume !(0 == ~T6_E~0); 53373#L784-1 assume !(0 == ~T7_E~0); 53181#L789-1 assume !(0 == ~E_1~0); 53182#L794-1 assume !(0 == ~E_2~0); 53266#L799-1 assume !(0 == ~E_3~0); 53191#L804-1 assume !(0 == ~E_4~0); 53192#L809-1 assume !(0 == ~E_5~0); 53219#L814-1 assume !(0 == ~E_6~0); 52624#L819-1 assume !(0 == ~E_7~0); 52625#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 52888#L361 assume !(1 == ~m_pc~0); 52889#L361-2 is_master_triggered_~__retres1~0#1 := 0; 53404#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53349#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 53350#L930 assume !(0 != activate_threads_~tmp~1#1); 53094#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 52882#L380 assume !(1 == ~t1_pc~0); 52883#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 53493#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 52644#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 52645#L938 assume !(0 != activate_threads_~tmp___0~0#1); 53301#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 53279#L399 assume !(1 == ~t2_pc~0); 52793#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 52794#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 52960#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 52953#L946 assume !(0 != activate_threads_~tmp___1~0#1); 52954#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 52630#L418 assume !(1 == ~t3_pc~0); 52610#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 52611#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 52620#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 52621#L954 assume !(0 != activate_threads_~tmp___2~0#1); 53205#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53206#L437 assume !(1 == ~t4_pc~0); 53433#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 53343#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 52703#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 52704#L962 assume !(0 != activate_threads_~tmp___3~0#1); 53007#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53326#L456 assume !(1 == ~t5_pc~0); 52807#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 52806#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53353#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53256#L970 assume !(0 != activate_threads_~tmp___4~0#1); 53257#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 52697#L475 assume 1 == ~t6_pc~0; 52698#L476 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 52741#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 52742#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 52946#L978 assume !(0 != activate_threads_~tmp___5~0#1); 53196#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53197#L494 assume !(1 == ~t7_pc~0); 52930#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 52931#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53150#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53226#L986 assume !(0 != activate_threads_~tmp___6~0#1); 53227#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53459#L837 assume !(1 == ~M_E~0); 53408#L837-2 assume !(1 == ~T1_E~0); 53274#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53016#L847-1 assume !(1 == ~T3_E~0); 53017#L852-1 assume !(1 == ~T4_E~0); 53083#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 52966#L862-1 assume !(1 == ~T6_E~0); 52967#L867-1 assume !(1 == ~T7_E~0); 52974#L872-1 assume !(1 == ~E_1~0); 53241#L877-1 assume !(1 == ~E_2~0); 53242#L882-1 assume !(1 == ~E_3~0); 56900#L887-1 assume !(1 == ~E_4~0); 53295#L892-1 assume !(1 == ~E_5~0); 53296#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 53456#L902-1 assume !(1 == ~E_7~0); 53319#L907-1 assume { :end_inline_reset_delta_events } true; 53320#L1148-2 [2023-11-29 01:11:06,263 INFO L750 eck$LassoCheckResult]: Loop: 53320#L1148-2 assume !false; 57148#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 57146#L729-1 assume !false; 57144#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 57107#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 57101#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 57099#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 57096#L626 assume !(0 != eval_~tmp~0#1); 57097#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57759#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57757#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 57755#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 57753#L759-3 assume !(0 == ~T2_E~0); 57751#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57749#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57747#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 57745#L779-3 assume !(0 == ~T6_E~0); 57743#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 57741#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 57739#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57737#L799-3 assume !(0 == ~E_3~0); 57735#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 57733#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 57731#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57729#L819-3 assume !(0 == ~E_7~0); 57727#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57725#L361-24 assume !(1 == ~m_pc~0); 57723#L361-26 is_master_triggered_~__retres1~0#1 := 0; 57720#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57717#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 57714#L930-24 assume !(0 != activate_threads_~tmp~1#1); 57711#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57708#L380-24 assume 1 == ~t1_pc~0; 57704#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 57700#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57696#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57692#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57689#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57686#L399-24 assume !(1 == ~t2_pc~0); 57682#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 57677#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57673#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57669#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 57666#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57663#L418-24 assume 1 == ~t3_pc~0; 57659#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57656#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57653#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57650#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57647#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57644#L437-24 assume !(1 == ~t4_pc~0); 57640#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 57636#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57632#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 57628#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 57624#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 57620#L456-24 assume !(1 == ~t5_pc~0); 57616#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 57609#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 57605#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 57601#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 57596#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 57592#L475-24 assume !(1 == ~t6_pc~0); 57585#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 57582#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 57579#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 57575#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 57570#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 57565#L494-24 assume !(1 == ~t7_pc~0); 57558#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 57553#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 57547#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 57541#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 57534#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 57525#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 57518#L837-5 assume !(1 == ~T1_E~0); 57511#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 57248#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 57501#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 57496#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 57491#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 57238#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 57482#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 57477#L877-3 assume !(1 == ~E_2~0); 57472#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 57466#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 57460#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 57456#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 57451#L902-3 assume !(1 == ~E_7~0); 57449#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 57440#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 57431#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 57426#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 57420#L1167 assume !(0 == start_simulation_~tmp~3#1); 57416#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 57377#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 57364#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 57359#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 57355#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 57349#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 57344#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 57341#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 53320#L1148-2 [2023-11-29 01:11:06,263 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:06,264 INFO L85 PathProgramCache]: Analyzing trace with hash -1707940763, now seen corresponding path program 1 times [2023-11-29 01:11:06,264 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:06,264 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [280275668] [2023-11-29 01:11:06,264 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:06,264 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:06,275 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:06,306 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:06,306 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:06,307 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [280275668] [2023-11-29 01:11:06,307 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [280275668] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:06,307 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:06,307 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:06,307 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [436767668] [2023-11-29 01:11:06,308 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:06,308 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:06,308 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:06,309 INFO L85 PathProgramCache]: Analyzing trace with hash -1711104387, now seen corresponding path program 1 times [2023-11-29 01:11:06,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:06,309 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [663841936] [2023-11-29 01:11:06,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:06,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:06,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:06,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:06,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:06,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [663841936] [2023-11-29 01:11:06,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [663841936] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:06,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:06,345 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:06,345 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [107531949] [2023-11-29 01:11:06,345 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:06,346 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:06,346 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:06,346 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:06,346 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:06,347 INFO L87 Difference]: Start difference. First operand 9658 states and 13705 transitions. cyclomatic complexity: 4063 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:06,582 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:06,582 INFO L93 Difference]: Finished difference Result 18129 states and 25606 transitions. [2023-11-29 01:11:06,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18129 states and 25606 transitions. [2023-11-29 01:11:06,682 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17888 [2023-11-29 01:11:06,765 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18129 states to 18129 states and 25606 transitions. [2023-11-29 01:11:06,766 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18129 [2023-11-29 01:11:06,788 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18129 [2023-11-29 01:11:06,789 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18129 states and 25606 transitions. [2023-11-29 01:11:06,807 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:06,807 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18129 states and 25606 transitions. [2023-11-29 01:11:06,835 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18129 states and 25606 transitions. [2023-11-29 01:11:07,110 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18129 to 18097. [2023-11-29 01:11:07,139 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 18097 states, 18097 states have (on average 1.413162402608167) internal successors, (25574), 18096 states have internal predecessors, (25574), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:07,188 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 18097 states to 18097 states and 25574 transitions. [2023-11-29 01:11:07,189 INFO L240 hiAutomatonCegarLoop]: Abstraction has 18097 states and 25574 transitions. [2023-11-29 01:11:07,189 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:07,189 INFO L428 stractBuchiCegarLoop]: Abstraction has 18097 states and 25574 transitions. [2023-11-29 01:11:07,190 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 01:11:07,190 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 18097 states and 25574 transitions. [2023-11-29 01:11:07,249 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17856 [2023-11-29 01:11:07,249 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:07,249 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:07,251 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:07,251 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:07,251 INFO L748 eck$LassoCheckResult]: Stem: 80616#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 80617#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 81212#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 81213#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 81255#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 81239#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 81240#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 80774#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 80775#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 80844#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 80682#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 80683#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 80649#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 80650#L754 assume !(0 == ~M_E~0); 81274#L754-2 assume !(0 == ~T1_E~0); 81170#L759-1 assume !(0 == ~T2_E~0); 81028#L764-1 assume !(0 == ~T3_E~0); 80986#L769-1 assume !(0 == ~T4_E~0); 80987#L774-1 assume !(0 == ~T5_E~0); 81029#L779-1 assume !(0 == ~T6_E~0); 81178#L784-1 assume !(0 == ~T7_E~0); 80982#L789-1 assume !(0 == ~E_1~0); 80983#L794-1 assume !(0 == ~E_2~0); 81080#L799-1 assume !(0 == ~E_3~0); 80995#L804-1 assume !(0 == ~E_4~0); 80996#L809-1 assume !(0 == ~E_5~0); 81023#L814-1 assume !(0 == ~E_6~0); 80420#L819-1 assume !(0 == ~E_7~0); 80421#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 80679#L361 assume !(1 == ~m_pc~0); 80680#L361-2 is_master_triggered_~__retres1~0#1 := 0; 81207#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 81157#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 81158#L930 assume !(0 != activate_threads_~tmp~1#1); 80892#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 80673#L380 assume !(1 == ~t1_pc~0); 80674#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 81300#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 80438#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 80439#L938 assume !(0 != activate_threads_~tmp___0~0#1); 81111#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81092#L399 assume !(1 == ~t2_pc~0); 80586#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 80587#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80753#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 80746#L946 assume !(0 != activate_threads_~tmp___1~0#1); 80747#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80424#L418 assume !(1 == ~t3_pc~0); 80404#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 80405#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80414#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 80415#L954 assume !(0 != activate_threads_~tmp___2~0#1); 81010#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81011#L437 assume !(1 == ~t4_pc~0); 81241#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 81153#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 80498#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 80499#L962 assume !(0 != activate_threads_~tmp___3~0#1); 80802#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81139#L456 assume !(1 == ~t5_pc~0); 80600#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 80599#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 81161#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81065#L970 assume !(0 != activate_threads_~tmp___4~0#1); 81066#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80491#L475 assume !(1 == ~t6_pc~0); 80492#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 80534#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 80535#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 80737#L978 assume !(0 != activate_threads_~tmp___5~0#1); 81002#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 81003#L494 assume !(1 == ~t7_pc~0); 80721#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 80722#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 80953#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 81030#L986 assume !(0 != activate_threads_~tmp___6~0#1); 81031#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 81265#L837 assume !(1 == ~M_E~0); 81211#L837-2 assume !(1 == ~T1_E~0); 81087#L842-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 80809#L847-1 assume !(1 == ~T3_E~0); 80810#L852-1 assume !(1 == ~T4_E~0); 80881#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 80759#L862-1 assume !(1 == ~T6_E~0); 80760#L867-1 assume !(1 == ~T7_E~0); 80770#L872-1 assume !(1 == ~E_1~0); 80843#L877-1 assume !(1 == ~E_2~0); 81046#L882-1 assume !(1 == ~E_3~0); 81217#L887-1 assume !(1 == ~E_4~0); 81279#L892-1 assume !(1 == ~E_5~0); 85742#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 80786#L902-1 assume !(1 == ~E_7~0); 80787#L907-1 assume { :end_inline_reset_delta_events } true; 81133#L1148-2 [2023-11-29 01:11:07,251 INFO L750 eck$LassoCheckResult]: Loop: 81133#L1148-2 assume !false; 84824#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 84823#L729-1 assume !false; 84818#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 84798#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 84794#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 84785#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 84786#L626 assume !(0 != eval_~tmp~0#1); 85681#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 97916#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 97915#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 97913#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 97912#L759-3 assume !(0 == ~T2_E~0); 97911#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 97910#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 97909#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 97908#L779-3 assume !(0 == ~T6_E~0); 97906#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 97904#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 97902#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 97900#L799-3 assume !(0 == ~E_3~0); 97898#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 97896#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 97895#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 97891#L819-3 assume !(0 == ~E_7~0); 97889#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 97886#L361-24 assume !(1 == ~m_pc~0); 97887#L361-26 is_master_triggered_~__retres1~0#1 := 0; 98212#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 98211#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 98210#L930-24 assume !(0 != activate_threads_~tmp~1#1); 98209#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 98208#L380-24 assume !(1 == ~t1_pc~0); 98205#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 98204#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 98203#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 98202#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 97737#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 81164#L399-24 assume !(1 == ~t2_pc~0); 80708#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 80624#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 80625#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 80880#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 80687#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 80688#L418-24 assume !(1 == ~t3_pc~0); 80466#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 80467#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 80764#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 80591#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 80592#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 81067#L437-24 assume !(1 == ~t4_pc~0); 81201#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 81307#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 97413#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 80579#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 80580#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 81001#L456-24 assume 1 == ~t5_pc~0; 80967#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 80946#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 80947#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 81191#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 80893#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 80894#L475-24 assume !(1 == ~t6_pc~0); 81301#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 91931#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 91929#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 91927#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 89491#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 86373#L494-24 assume !(1 == ~t7_pc~0); 86370#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 86368#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 86366#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 86363#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 86361#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86359#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 86357#L837-5 assume !(1 == ~T1_E~0); 86355#L842-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 85836#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 86351#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86349#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86347#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 85827#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86344#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 86342#L877-3 assume !(1 == ~E_2~0); 86339#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86337#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86335#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86333#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86331#L902-3 assume !(1 == ~E_7~0); 86330#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 86326#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 86320#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 86318#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 86315#L1167 assume !(0 == start_simulation_~tmp~3#1); 86312#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 86308#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 86299#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 86297#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 86295#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86292#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86290#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 86288#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 81133#L1148-2 [2023-11-29 01:11:07,252 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:07,252 INFO L85 PathProgramCache]: Analyzing trace with hash -2016379772, now seen corresponding path program 1 times [2023-11-29 01:11:07,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:07,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [326497854] [2023-11-29 01:11:07,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:07,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:07,267 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:07,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:07,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:07,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [326497854] [2023-11-29 01:11:07,390 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [326497854] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:07,390 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:07,390 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:07,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [390416865] [2023-11-29 01:11:07,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:07,390 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:07,391 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:07,391 INFO L85 PathProgramCache]: Analyzing trace with hash -1369957990, now seen corresponding path program 1 times [2023-11-29 01:11:07,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:07,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [11650968] [2023-11-29 01:11:07,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:07,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:07,404 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:07,433 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:07,433 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:07,433 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [11650968] [2023-11-29 01:11:07,434 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [11650968] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:07,434 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:07,434 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:07,434 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [814019688] [2023-11-29 01:11:07,434 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:07,434 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:07,434 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:07,435 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:07,435 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:07,435 INFO L87 Difference]: Start difference. First operand 18097 states and 25574 transitions. cyclomatic complexity: 7509 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:07,512 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:07,512 INFO L93 Difference]: Finished difference Result 18093 states and 25485 transitions. [2023-11-29 01:11:07,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18093 states and 25485 transitions. [2023-11-29 01:11:07,585 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 17856 [2023-11-29 01:11:07,694 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18093 states to 18093 states and 25485 transitions. [2023-11-29 01:11:07,694 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18093 [2023-11-29 01:11:07,711 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18093 [2023-11-29 01:11:07,712 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18093 states and 25485 transitions. [2023-11-29 01:11:07,725 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:07,725 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18093 states and 25485 transitions. [2023-11-29 01:11:07,743 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18093 states and 25485 transitions. [2023-11-29 01:11:07,924 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18093 to 9092. [2023-11-29 01:11:07,939 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.4083809942806864) internal successors, (12805), 9091 states have internal predecessors, (12805), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:07,971 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12805 transitions. [2023-11-29 01:11:07,971 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12805 transitions. [2023-11-29 01:11:07,972 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:07,972 INFO L428 stractBuchiCegarLoop]: Abstraction has 9092 states and 12805 transitions. [2023-11-29 01:11:07,973 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 01:11:07,973 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12805 transitions. [2023-11-29 01:11:08,009 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2023-11-29 01:11:08,009 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:08,009 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:08,011 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:08,011 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:08,012 INFO L748 eck$LassoCheckResult]: Stem: 116812#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 116813#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 117398#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 117399#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 117431#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 117418#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 117419#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 116963#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 116964#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 117035#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 116877#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 116878#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 116845#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 116846#L754 assume !(0 == ~M_E~0); 117445#L754-2 assume !(0 == ~T1_E~0); 117350#L759-1 assume !(0 == ~T2_E~0); 117214#L764-1 assume !(0 == ~T3_E~0); 117171#L769-1 assume !(0 == ~T4_E~0); 117172#L774-1 assume !(0 == ~T5_E~0); 117215#L779-1 assume !(0 == ~T6_E~0); 117362#L784-1 assume !(0 == ~T7_E~0); 117168#L789-1 assume !(0 == ~E_1~0); 117169#L794-1 assume !(0 == ~E_2~0); 117261#L799-1 assume !(0 == ~E_3~0); 117180#L804-1 assume !(0 == ~E_4~0); 117181#L809-1 assume !(0 == ~E_5~0); 117209#L814-1 assume !(0 == ~E_6~0); 116613#L819-1 assume !(0 == ~E_7~0); 116614#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 116875#L361 assume !(1 == ~m_pc~0); 116876#L361-2 is_master_triggered_~__retres1~0#1 := 0; 117394#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 117337#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 117338#L930 assume !(0 != activate_threads_~tmp~1#1); 117079#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 116869#L380 assume !(1 == ~t1_pc~0); 116870#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 117465#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 116635#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 116636#L938 assume !(0 != activate_threads_~tmp___0~0#1); 117294#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 117272#L399 assume !(1 == ~t2_pc~0); 116781#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 116782#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 116946#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 116939#L946 assume !(0 != activate_threads_~tmp___1~0#1); 116940#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 116621#L418 assume !(1 == ~t3_pc~0); 116601#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 116602#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 116611#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 116612#L954 assume !(0 != activate_threads_~tmp___2~0#1); 117196#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 117197#L437 assume !(1 == ~t4_pc~0); 117420#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 117331#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 116693#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 116694#L962 assume !(0 != activate_threads_~tmp___3~0#1); 116992#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 117312#L456 assume !(1 == ~t5_pc~0); 116795#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 116794#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 117341#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 117245#L970 assume !(0 != activate_threads_~tmp___4~0#1); 117246#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 116688#L475 assume !(1 == ~t6_pc~0); 116689#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 116730#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 116731#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 116932#L978 assume !(0 != activate_threads_~tmp___5~0#1); 117185#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 117186#L494 assume !(1 == ~t7_pc~0); 116916#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 116917#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 117137#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 117216#L986 assume !(0 != activate_threads_~tmp___6~0#1); 117217#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 117441#L837 assume !(1 == ~M_E~0); 117397#L837-2 assume !(1 == ~T1_E~0); 117267#L842-1 assume !(1 == ~T2_E~0); 117001#L847-1 assume !(1 == ~T3_E~0); 117002#L852-1 assume !(1 == ~T4_E~0); 117069#L857-1 assume 1 == ~T5_E~0;~T5_E~0 := 2; 116952#L862-1 assume !(1 == ~T6_E~0); 116953#L867-1 assume !(1 == ~T7_E~0); 116959#L872-1 assume !(1 == ~E_1~0); 117034#L877-1 assume !(1 == ~E_2~0); 117231#L882-1 assume !(1 == ~E_3~0); 117402#L887-1 assume !(1 == ~E_4~0); 117287#L892-1 assume !(1 == ~E_5~0); 117288#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 116974#L902-1 assume !(1 == ~E_7~0); 116975#L907-1 assume { :end_inline_reset_delta_events } true; 117311#L1148-2 [2023-11-29 01:11:08,012 INFO L750 eck$LassoCheckResult]: Loop: 117311#L1148-2 assume !false; 118736#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 118735#L729-1 assume !false; 118734#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 118729#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 118722#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 118721#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 118718#L626 assume !(0 != eval_~tmp~0#1); 118719#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 119694#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 119691#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 119690#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 119689#L759-3 assume !(0 == ~T2_E~0); 119685#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 119683#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 119681#L774-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 119680#L779-3 assume !(0 == ~T6_E~0); 119679#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 119678#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 119677#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 119676#L799-3 assume !(0 == ~E_3~0); 119667#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 119665#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 119663#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 119660#L819-3 assume !(0 == ~E_7~0); 119659#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 119658#L361-24 assume !(1 == ~m_pc~0); 119657#L361-26 is_master_triggered_~__retres1~0#1 := 0; 119656#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 119655#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 119654#L930-24 assume !(0 != activate_threads_~tmp~1#1); 119653#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 119652#L380-24 assume 1 == ~t1_pc~0; 119651#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 119649#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 119647#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 119644#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 119643#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 119642#L399-24 assume !(1 == ~t2_pc~0); 119641#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 119639#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 119638#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 119637#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 119636#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 119635#L418-24 assume !(1 == ~t3_pc~0); 119633#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 119630#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 119628#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 119626#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 119624#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 119622#L437-24 assume !(1 == ~t4_pc~0); 119618#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 119616#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 119614#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 119612#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 119609#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 119607#L456-24 assume !(1 == ~t5_pc~0); 119605#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 119601#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 119599#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 119597#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 119595#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 119593#L475-24 assume !(1 == ~t6_pc~0); 119591#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 119588#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 119586#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 119584#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 119582#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 119580#L494-24 assume !(1 == ~t7_pc~0); 119577#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 119575#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 119573#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 119571#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 119569#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 119567#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 119565#L837-5 assume !(1 == ~T1_E~0); 119562#L842-3 assume !(1 == ~T2_E~0); 119560#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 119558#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 119556#L857-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 119554#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 119552#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 119549#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 119547#L877-3 assume !(1 == ~E_2~0); 119545#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 119543#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 119541#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 119538#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 119536#L902-3 assume !(1 == ~E_7~0); 119534#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 118909#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 118901#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 118897#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 118892#L1167 assume !(0 == start_simulation_~tmp~3#1); 118887#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 118884#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 118874#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 118873#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 118872#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 118870#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 118868#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 118866#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 117311#L1148-2 [2023-11-29 01:11:08,013 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:08,013 INFO L85 PathProgramCache]: Analyzing trace with hash 1267470274, now seen corresponding path program 1 times [2023-11-29 01:11:08,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:08,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2097329265] [2023-11-29 01:11:08,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:08,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:08,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:08,091 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:08,091 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:08,091 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2097329265] [2023-11-29 01:11:08,091 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2097329265] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:08,091 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:08,092 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:08,092 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [909750924] [2023-11-29 01:11:08,092 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:08,093 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:08,093 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:08,093 INFO L85 PathProgramCache]: Analyzing trace with hash 1504255130, now seen corresponding path program 1 times [2023-11-29 01:11:08,093 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:08,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1617272372] [2023-11-29 01:11:08,094 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:08,094 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:08,111 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:08,153 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:08,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:08,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1617272372] [2023-11-29 01:11:08,154 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1617272372] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:08,154 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:08,154 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:08,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [673516607] [2023-11-29 01:11:08,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:08,155 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:08,155 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:08,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:08,156 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:08,156 INFO L87 Difference]: Start difference. First operand 9092 states and 12805 transitions. cyclomatic complexity: 3729 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:08,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:08,229 INFO L93 Difference]: Finished difference Result 9092 states and 12755 transitions. [2023-11-29 01:11:08,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9092 states and 12755 transitions. [2023-11-29 01:11:08,285 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2023-11-29 01:11:08,320 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9092 states to 9092 states and 12755 transitions. [2023-11-29 01:11:08,320 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9092 [2023-11-29 01:11:08,327 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9092 [2023-11-29 01:11:08,327 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9092 states and 12755 transitions. [2023-11-29 01:11:08,335 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:08,335 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12755 transitions. [2023-11-29 01:11:08,343 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9092 states and 12755 transitions. [2023-11-29 01:11:08,444 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9092 to 9092. [2023-11-29 01:11:08,456 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.402881654201496) internal successors, (12755), 9091 states have internal predecessors, (12755), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:08,485 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12755 transitions. [2023-11-29 01:11:08,486 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12755 transitions. [2023-11-29 01:11:08,486 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:08,487 INFO L428 stractBuchiCegarLoop]: Abstraction has 9092 states and 12755 transitions. [2023-11-29 01:11:08,487 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 01:11:08,487 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12755 transitions. [2023-11-29 01:11:08,517 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2023-11-29 01:11:08,517 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:08,517 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:08,519 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:08,520 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:08,520 INFO L748 eck$LassoCheckResult]: Stem: 135002#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 135003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 135598#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 135599#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 135632#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 135617#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 135618#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 135158#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 135159#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 135234#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 135067#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 135068#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 135035#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 135036#L754 assume !(0 == ~M_E~0); 135646#L754-2 assume !(0 == ~T1_E~0); 135556#L759-1 assume !(0 == ~T2_E~0); 135415#L764-1 assume !(0 == ~T3_E~0); 135371#L769-1 assume !(0 == ~T4_E~0); 135372#L774-1 assume !(0 == ~T5_E~0); 135416#L779-1 assume !(0 == ~T6_E~0); 135568#L784-1 assume !(0 == ~T7_E~0); 135368#L789-1 assume !(0 == ~E_1~0); 135369#L794-1 assume !(0 == ~E_2~0); 135461#L799-1 assume !(0 == ~E_3~0); 135379#L804-1 assume !(0 == ~E_4~0); 135380#L809-1 assume !(0 == ~E_5~0); 135410#L814-1 assume !(0 == ~E_6~0); 134809#L819-1 assume !(0 == ~E_7~0); 134810#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 135065#L361 assume !(1 == ~m_pc~0); 135066#L361-2 is_master_triggered_~__retres1~0#1 := 0; 135594#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 135542#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 135543#L930 assume !(0 != activate_threads_~tmp~1#1); 135278#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 135059#L380 assume !(1 == ~t1_pc~0); 135060#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 135628#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 135629#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 135666#L938 assume !(0 != activate_threads_~tmp___0~0#1); 135495#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 135471#L399 assume !(1 == ~t2_pc~0); 134973#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 134974#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 135137#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 135130#L946 assume !(0 != activate_threads_~tmp___1~0#1); 135131#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134813#L418 assume !(1 == ~t3_pc~0); 134792#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 134793#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134803#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 134804#L954 assume !(0 != activate_threads_~tmp___2~0#1); 135395#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 135396#L437 assume !(1 == ~t4_pc~0); 135619#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 135537#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134886#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 134887#L962 assume !(0 != activate_threads_~tmp___3~0#1); 135188#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 135522#L456 assume !(1 == ~t5_pc~0); 134988#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 134987#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 135546#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 135448#L970 assume !(0 != activate_threads_~tmp___4~0#1); 135449#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134879#L475 assume !(1 == ~t6_pc~0); 134880#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 134921#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 134922#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 135123#L978 assume !(0 != activate_threads_~tmp___5~0#1); 135384#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 135385#L494 assume !(1 == ~t7_pc~0); 135107#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 135108#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 135338#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 135417#L986 assume !(0 != activate_threads_~tmp___6~0#1); 135418#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 135637#L837 assume !(1 == ~M_E~0); 135597#L837-2 assume !(1 == ~T1_E~0); 135467#L842-1 assume !(1 == ~T2_E~0); 135197#L847-1 assume !(1 == ~T3_E~0); 135198#L852-1 assume !(1 == ~T4_E~0); 135268#L857-1 assume !(1 == ~T5_E~0); 135143#L862-1 assume !(1 == ~T6_E~0); 135144#L867-1 assume !(1 == ~T7_E~0); 135154#L872-1 assume !(1 == ~E_1~0); 135233#L877-1 assume !(1 == ~E_2~0); 135433#L882-1 assume !(1 == ~E_3~0); 135602#L887-1 assume !(1 == ~E_4~0); 135489#L892-1 assume !(1 == ~E_5~0); 135490#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 135169#L902-1 assume !(1 == ~E_7~0); 135170#L907-1 assume { :end_inline_reset_delta_events } true; 135516#L1148-2 [2023-11-29 01:11:08,521 INFO L750 eck$LassoCheckResult]: Loop: 135516#L1148-2 assume !false; 138628#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 138626#L729-1 assume !false; 138624#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 138614#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 138608#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 138605#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 138602#L626 assume !(0 != eval_~tmp~0#1); 138603#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 138878#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 138877#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 138876#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 138875#L759-3 assume !(0 == ~T2_E~0); 138874#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 138873#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 138872#L774-3 assume !(0 == ~T5_E~0); 138870#L779-3 assume !(0 == ~T6_E~0); 138869#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 138868#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 138866#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 138865#L799-3 assume !(0 == ~E_3~0); 138864#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 138863#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 138862#L814-3 assume 0 == ~E_6~0;~E_6~0 := 1; 138860#L819-3 assume !(0 == ~E_7~0); 138858#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 138856#L361-24 assume !(1 == ~m_pc~0); 138854#L361-26 is_master_triggered_~__retres1~0#1 := 0; 138852#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 138850#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 138846#L930-24 assume !(0 != activate_threads_~tmp~1#1); 138844#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 138842#L380-24 assume !(1 == ~t1_pc~0); 138838#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 138835#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 138833#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 138831#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 138828#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 138826#L399-24 assume !(1 == ~t2_pc~0); 138824#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 138822#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 138820#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 138818#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 138815#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 138813#L418-24 assume 1 == ~t3_pc~0; 138810#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 138808#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 138806#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 138804#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 138802#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 138800#L437-24 assume !(1 == ~t4_pc~0); 138798#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 138796#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 138794#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 138792#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 138789#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 138787#L456-24 assume 1 == ~t5_pc~0; 138784#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 138782#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 138780#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 138778#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 138776#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 138774#L475-24 assume !(1 == ~t6_pc~0); 138772#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 138770#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 138768#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 138765#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 138763#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 138761#L494-24 assume !(1 == ~t7_pc~0); 138758#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 138756#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 138754#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 138752#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 138750#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 138748#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 138746#L837-5 assume !(1 == ~T1_E~0); 138744#L842-3 assume !(1 == ~T2_E~0); 138742#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 138740#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 138738#L857-3 assume !(1 == ~T5_E~0); 138736#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 138734#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 138732#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 138730#L877-3 assume !(1 == ~E_2~0); 138728#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 138726#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 138724#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 138723#L897-3 assume 1 == ~E_6~0;~E_6~0 := 2; 138722#L902-3 assume !(1 == ~E_7~0); 138721#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 138715#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 138709#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 138706#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 138703#L1167 assume !(0 == start_simulation_~tmp~3#1); 138700#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 138698#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 138689#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 138687#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 138685#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 138683#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 138681#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 138679#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 135516#L1148-2 [2023-11-29 01:11:08,521 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:08,521 INFO L85 PathProgramCache]: Analyzing trace with hash 1968534852, now seen corresponding path program 1 times [2023-11-29 01:11:08,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:08,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2129954649] [2023-11-29 01:11:08,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:08,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:08,588 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:08,670 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:08,671 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:08,671 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2129954649] [2023-11-29 01:11:08,671 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2129954649] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:08,671 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:08,671 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:08,671 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709809487] [2023-11-29 01:11:08,671 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:08,672 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:08,672 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:08,672 INFO L85 PathProgramCache]: Analyzing trace with hash 1736981757, now seen corresponding path program 1 times [2023-11-29 01:11:08,672 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:08,672 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1806496633] [2023-11-29 01:11:08,672 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:08,673 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:08,684 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:08,715 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:08,715 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:08,715 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1806496633] [2023-11-29 01:11:08,715 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1806496633] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:08,715 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:08,715 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:08,715 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2119549475] [2023-11-29 01:11:08,716 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:08,716 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:08,716 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:08,716 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:11:08,716 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:11:08,717 INFO L87 Difference]: Start difference. First operand 9092 states and 12755 transitions. cyclomatic complexity: 3679 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:08,867 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:08,867 INFO L93 Difference]: Finished difference Result 18501 states and 25862 transitions. [2023-11-29 01:11:08,867 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 18501 states and 25862 transitions. [2023-11-29 01:11:08,935 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 18184 [2023-11-29 01:11:08,994 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 18501 states to 18501 states and 25862 transitions. [2023-11-29 01:11:08,994 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 18501 [2023-11-29 01:11:09,005 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 18501 [2023-11-29 01:11:09,006 INFO L73 IsDeterministic]: Start isDeterministic. Operand 18501 states and 25862 transitions. [2023-11-29 01:11:09,017 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:09,017 INFO L218 hiAutomatonCegarLoop]: Abstraction has 18501 states and 25862 transitions. [2023-11-29 01:11:09,029 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 18501 states and 25862 transitions. [2023-11-29 01:11:09,127 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 18501 to 10331. [2023-11-29 01:11:09,137 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10331 states, 10331 states have (on average 1.3969606040073566) internal successors, (14432), 10330 states have internal predecessors, (14432), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:09,157 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10331 states to 10331 states and 14432 transitions. [2023-11-29 01:11:09,157 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10331 states and 14432 transitions. [2023-11-29 01:11:09,158 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:11:09,158 INFO L428 stractBuchiCegarLoop]: Abstraction has 10331 states and 14432 transitions. [2023-11-29 01:11:09,158 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 01:11:09,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10331 states and 14432 transitions. [2023-11-29 01:11:09,188 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10096 [2023-11-29 01:11:09,188 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:09,188 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:09,190 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:09,190 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:09,191 INFO L748 eck$LassoCheckResult]: Stem: 162609#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 162610#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 163204#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 163205#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 163242#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 163227#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 163228#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 162766#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 162767#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 162836#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 162672#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 162673#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 162640#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 162641#L754 assume !(0 == ~M_E~0); 163262#L754-2 assume !(0 == ~T1_E~0); 163154#L759-1 assume !(0 == ~T2_E~0); 163020#L764-1 assume !(0 == ~T3_E~0); 162977#L769-1 assume !(0 == ~T4_E~0); 162978#L774-1 assume !(0 == ~T5_E~0); 163021#L779-1 assume !(0 == ~T6_E~0); 163166#L784-1 assume !(0 == ~T7_E~0); 162974#L789-1 assume !(0 == ~E_1~0); 162975#L794-1 assume !(0 == ~E_2~0); 163068#L799-1 assume !(0 == ~E_3~0); 162985#L804-1 assume !(0 == ~E_4~0); 162986#L809-1 assume !(0 == ~E_5~0); 163015#L814-1 assume 0 == ~E_6~0;~E_6~0 := 1; 162407#L819-1 assume !(0 == ~E_7~0); 162408#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 162670#L361 assume !(1 == ~m_pc~0); 162671#L361-2 is_master_triggered_~__retres1~0#1 := 0; 163270#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 163271#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 163234#L930 assume !(0 != activate_threads_~tmp~1#1); 163235#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 162664#L380 assume !(1 == ~t1_pc~0); 162665#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 163318#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 163316#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 163293#L938 assume !(0 != activate_threads_~tmp___0~0#1); 163098#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 163078#L399 assume !(1 == ~t2_pc~0); 163079#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 163243#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 163244#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 162737#L946 assume !(0 != activate_threads_~tmp___1~0#1); 162738#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 163311#L418 assume !(1 == ~t3_pc~0); 162395#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 162396#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 163310#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 163297#L954 assume !(0 != activate_threads_~tmp___2~0#1); 163298#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 163263#L437 assume !(1 == ~t4_pc~0); 163264#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 163309#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 162487#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 162488#L962 assume !(0 != activate_threads_~tmp___3~0#1); 163217#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 163116#L456 assume !(1 == ~t5_pc~0); 163117#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 163258#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 163146#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 163054#L970 assume !(0 != activate_threads_~tmp___4~0#1); 163055#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 162482#L475 assume !(1 == ~t6_pc~0); 162483#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 162525#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 162526#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 163048#L978 assume !(0 != activate_threads_~tmp___5~0#1); 163049#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 163184#L494 assume !(1 == ~t7_pc~0); 162930#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 162945#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 162946#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 163022#L986 assume !(0 != activate_threads_~tmp___6~0#1); 163023#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 163254#L837 assume !(1 == ~M_E~0); 163255#L837-2 assume !(1 == ~T1_E~0); 163304#L842-1 assume !(1 == ~T2_E~0); 163303#L847-1 assume !(1 == ~T3_E~0); 162871#L852-1 assume !(1 == ~T4_E~0); 162872#L857-1 assume !(1 == ~T5_E~0); 162751#L862-1 assume !(1 == ~T6_E~0); 162752#L867-1 assume !(1 == ~T7_E~0); 163302#L872-1 assume !(1 == ~E_1~0); 163036#L877-1 assume !(1 == ~E_2~0); 163037#L882-1 assume !(1 == ~E_3~0); 163269#L887-1 assume !(1 == ~E_4~0); 163093#L892-1 assume !(1 == ~E_5~0); 163094#L897-1 assume 1 == ~E_6~0;~E_6~0 := 2; 162777#L902-1 assume !(1 == ~E_7~0); 162778#L907-1 assume { :end_inline_reset_delta_events } true; 163115#L1148-2 [2023-11-29 01:11:09,191 INFO L750 eck$LassoCheckResult]: Loop: 163115#L1148-2 assume !false; 168797#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 168795#L729-1 assume !false; 168793#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 168782#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 168776#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 168771#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 168769#L626 assume !(0 != eval_~tmp~0#1); 168770#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 169682#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 169676#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 169670#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 169664#L759-3 assume !(0 == ~T2_E~0); 169659#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 169653#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 169647#L774-3 assume !(0 == ~T5_E~0); 169642#L779-3 assume !(0 == ~T6_E~0); 169637#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 169632#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 169627#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 169622#L799-3 assume !(0 == ~E_3~0); 169616#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 169611#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 169605#L814-3 assume !(0 == ~E_6~0); 169606#L819-3 assume !(0 == ~E_7~0); 169979#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 169977#L361-24 assume !(1 == ~m_pc~0); 169975#L361-26 is_master_triggered_~__retres1~0#1 := 0; 169945#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 169936#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 169930#L930-24 assume !(0 != activate_threads_~tmp~1#1); 169909#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 169905#L380-24 assume 1 == ~t1_pc~0; 169900#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 169894#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 169889#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 169883#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 169877#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169870#L399-24 assume !(1 == ~t2_pc~0); 169864#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 169857#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 169851#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 169846#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 169839#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169834#L418-24 assume 1 == ~t3_pc~0; 169827#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 169820#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 169815#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 169810#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 169804#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169798#L437-24 assume !(1 == ~t4_pc~0); 169793#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 169787#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 169782#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 169777#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 169771#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169766#L456-24 assume !(1 == ~t5_pc~0); 169760#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 169755#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169750#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 169745#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 169740#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 169734#L475-24 assume !(1 == ~t6_pc~0); 169730#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 169727#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169724#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 169719#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 169712#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169707#L494-24 assume !(1 == ~t7_pc~0); 169701#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 169696#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169692#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 169688#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 169681#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 169675#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 169669#L837-5 assume !(1 == ~T1_E~0); 169663#L842-3 assume !(1 == ~T2_E~0); 169658#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 169652#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 169646#L857-3 assume !(1 == ~T5_E~0); 169641#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 169636#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 169631#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 169626#L877-3 assume !(1 == ~E_2~0); 169621#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 169615#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 169610#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 169534#L897-3 assume !(1 == ~E_6~0); 169529#L902-3 assume !(1 == ~E_7~0); 169526#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 169520#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 169512#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 169508#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 169399#L1167 assume !(0 == start_simulation_~tmp~3#1); 169396#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 169394#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 169380#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 169368#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 169289#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 168930#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 168929#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 168928#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 163115#L1148-2 [2023-11-29 01:11:09,191 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:09,192 INFO L85 PathProgramCache]: Analyzing trace with hash -1110278718, now seen corresponding path program 1 times [2023-11-29 01:11:09,192 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:09,192 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [137441353] [2023-11-29 01:11:09,192 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:09,192 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:09,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:09,277 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:09,277 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:09,278 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [137441353] [2023-11-29 01:11:09,278 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [137441353] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:09,278 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:09,278 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:09,278 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [257362716] [2023-11-29 01:11:09,278 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:09,279 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:09,279 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:09,279 INFO L85 PathProgramCache]: Analyzing trace with hash -785435965, now seen corresponding path program 1 times [2023-11-29 01:11:09,279 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:09,279 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [755249431] [2023-11-29 01:11:09,279 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:09,279 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:09,292 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:09,346 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:09,346 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:09,346 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [755249431] [2023-11-29 01:11:09,346 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [755249431] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:09,347 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:09,347 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:09,347 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1175647456] [2023-11-29 01:11:09,347 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:09,347 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:09,348 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:09,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 01:11:09,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 01:11:09,348 INFO L87 Difference]: Start difference. First operand 10331 states and 14432 transitions. cyclomatic complexity: 4117 Second operand has 4 states, 4 states have (on average 23.25) internal successors, (93), 3 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:09,471 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:09,471 INFO L93 Difference]: Finished difference Result 17156 states and 23937 transitions. [2023-11-29 01:11:09,471 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17156 states and 23937 transitions. [2023-11-29 01:11:09,539 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 16912 [2023-11-29 01:11:09,589 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17156 states to 17156 states and 23937 transitions. [2023-11-29 01:11:09,589 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17156 [2023-11-29 01:11:09,599 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17156 [2023-11-29 01:11:09,600 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17156 states and 23937 transitions. [2023-11-29 01:11:09,610 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:09,610 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17156 states and 23937 transitions. [2023-11-29 01:11:09,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17156 states and 23937 transitions. [2023-11-29 01:11:09,712 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17156 to 9092. [2023-11-29 01:11:09,721 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.3916630004399473) internal successors, (12653), 9091 states have internal predecessors, (12653), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:09,738 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12653 transitions. [2023-11-29 01:11:09,738 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12653 transitions. [2023-11-29 01:11:09,739 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 01:11:09,739 INFO L428 stractBuchiCegarLoop]: Abstraction has 9092 states and 12653 transitions. [2023-11-29 01:11:09,739 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 01:11:09,739 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12653 transitions. [2023-11-29 01:11:09,764 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2023-11-29 01:11:09,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:09,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:09,766 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:09,766 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:09,766 INFO L748 eck$LassoCheckResult]: Stem: 190102#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 190103#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 190696#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 190697#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 190730#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 190714#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 190715#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 190259#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 190260#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 190330#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 190167#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 190168#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 190135#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 190136#L754 assume !(0 == ~M_E~0); 190750#L754-2 assume !(0 == ~T1_E~0); 190645#L759-1 assume !(0 == ~T2_E~0); 190509#L764-1 assume !(0 == ~T3_E~0); 190464#L769-1 assume !(0 == ~T4_E~0); 190465#L774-1 assume !(0 == ~T5_E~0); 190510#L779-1 assume !(0 == ~T6_E~0); 190657#L784-1 assume !(0 == ~T7_E~0); 190461#L789-1 assume !(0 == ~E_1~0); 190462#L794-1 assume !(0 == ~E_2~0); 190559#L799-1 assume !(0 == ~E_3~0); 190472#L804-1 assume !(0 == ~E_4~0); 190473#L809-1 assume !(0 == ~E_5~0); 190504#L814-1 assume !(0 == ~E_6~0); 189904#L819-1 assume !(0 == ~E_7~0); 189905#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 190165#L361 assume !(1 == ~m_pc~0); 190166#L361-2 is_master_triggered_~__retres1~0#1 := 0; 190691#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 190633#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 190634#L930 assume !(0 != activate_threads_~tmp~1#1); 190373#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190159#L380 assume !(1 == ~t1_pc~0); 190160#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 190726#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 190727#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190777#L938 assume !(0 != activate_threads_~tmp___0~0#1); 190593#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 190570#L399 assume !(1 == ~t2_pc~0); 190071#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 190072#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 190239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 190232#L946 assume !(0 != activate_threads_~tmp___1~0#1); 190233#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 189912#L418 assume !(1 == ~t3_pc~0); 189892#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 189893#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 189902#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 189903#L954 assume !(0 != activate_threads_~tmp___2~0#1); 190490#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 190491#L437 assume !(1 == ~t4_pc~0); 190716#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 190628#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 189981#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 189982#L962 assume !(0 != activate_threads_~tmp___3~0#1); 190288#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 190610#L456 assume !(1 == ~t5_pc~0); 190085#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 190084#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 190637#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 190543#L970 assume !(0 != activate_threads_~tmp___4~0#1); 190544#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 189976#L475 assume !(1 == ~t6_pc~0); 189977#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 190019#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 190020#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 190225#L978 assume !(0 != activate_threads_~tmp___5~0#1); 190479#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 190480#L494 assume !(1 == ~t7_pc~0); 190209#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 190210#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 190434#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 190511#L986 assume !(0 != activate_threads_~tmp___6~0#1); 190512#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 190740#L837 assume !(1 == ~M_E~0); 190695#L837-2 assume !(1 == ~T1_E~0); 190565#L842-1 assume !(1 == ~T2_E~0); 190297#L847-1 assume !(1 == ~T3_E~0); 190298#L852-1 assume !(1 == ~T4_E~0); 190363#L857-1 assume !(1 == ~T5_E~0); 190245#L862-1 assume !(1 == ~T6_E~0); 190246#L867-1 assume !(1 == ~T7_E~0); 190255#L872-1 assume !(1 == ~E_1~0); 190329#L877-1 assume !(1 == ~E_2~0); 190526#L882-1 assume !(1 == ~E_3~0); 190701#L887-1 assume !(1 == ~E_4~0); 190586#L892-1 assume !(1 == ~E_5~0); 190587#L897-1 assume !(1 == ~E_6~0); 190270#L902-1 assume !(1 == ~E_7~0); 190271#L907-1 assume { :end_inline_reset_delta_events } true; 190609#L1148-2 [2023-11-29 01:11:09,767 INFO L750 eck$LassoCheckResult]: Loop: 190609#L1148-2 assume !false; 197954#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 197951#L729-1 assume !false; 197949#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 195402#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 195396#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 195393#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 195391#L626 assume !(0 != eval_~tmp~0#1); 195392#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 198979#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 198977#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 189917#L754-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 189918#L759-3 assume !(0 == ~T2_E~0); 190669#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 198962#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 190492#L774-3 assume !(0 == ~T5_E~0); 190075#L779-3 assume !(0 == ~T6_E~0); 189913#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 189914#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 189908#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 189909#L799-3 assume !(0 == ~E_3~0); 189957#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 190189#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 189953#L814-3 assume !(0 == ~E_6~0); 189954#L819-3 assume !(0 == ~E_7~0); 190620#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 190324#L361-24 assume !(1 == ~m_pc~0); 190325#L361-26 is_master_triggered_~__retres1~0#1 := 0; 190415#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 190005#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 190006#L930-24 assume !(0 != activate_threads_~tmp~1#1); 190681#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 190469#L380-24 assume !(1 == ~t1_pc~0); 189987#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 189988#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 190408#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 190177#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 190178#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 198914#L399-24 assume !(1 == ~t2_pc~0); 198912#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 198910#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 198908#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 198906#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 198904#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 198902#L418-24 assume 1 == ~t3_pc~0; 198899#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 198897#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 198894#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 198892#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 198890#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 198888#L437-24 assume !(1 == ~t4_pc~0); 198886#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 198884#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 198881#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 198878#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 198875#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 198872#L456-24 assume !(1 == ~t5_pc~0); 198870#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 198867#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 198865#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198863#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 198861#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 198859#L475-24 assume !(1 == ~t6_pc~0); 198857#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 198855#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 198852#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 198850#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 198848#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 198846#L494-24 assume !(1 == ~t7_pc~0); 198843#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 198837#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 198836#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 198835#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 198624#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 198623#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 198622#L837-5 assume !(1 == ~T1_E~0); 198620#L842-3 assume !(1 == ~T2_E~0); 198618#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 198616#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 198614#L857-3 assume !(1 == ~T5_E~0); 198613#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 198612#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 198611#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 198610#L877-3 assume !(1 == ~E_2~0); 198609#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 198608#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 198607#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 198286#L897-3 assume !(1 == ~E_6~0); 198285#L902-3 assume !(1 == ~E_7~0); 198284#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 198276#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 198270#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 198268#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 198265#L1167 assume !(0 == start_simulation_~tmp~3#1); 198262#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 198258#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 198249#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 198247#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 198246#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 198245#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 198240#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 198081#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 190609#L1148-2 [2023-11-29 01:11:09,767 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:09,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 1 times [2023-11-29 01:11:09,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:09,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [151447537] [2023-11-29 01:11:09,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:09,768 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:09,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:09,781 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:09,789 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:09,839 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:09,839 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:09,839 INFO L85 PathProgramCache]: Analyzing trace with hash -610646944, now seen corresponding path program 1 times [2023-11-29 01:11:09,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:09,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1048727879] [2023-11-29 01:11:09,840 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:09,840 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:09,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:09,889 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:09,889 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:09,890 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1048727879] [2023-11-29 01:11:09,890 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1048727879] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:09,890 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:09,890 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:09,890 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [281191328] [2023-11-29 01:11:09,890 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:09,891 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:09,891 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:09,891 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:09,891 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:09,891 INFO L87 Difference]: Start difference. First operand 9092 states and 12653 transitions. cyclomatic complexity: 3577 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:09,952 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:09,952 INFO L93 Difference]: Finished difference Result 10331 states and 14356 transitions. [2023-11-29 01:11:09,952 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 10331 states and 14356 transitions. [2023-11-29 01:11:09,999 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10096 [2023-11-29 01:11:10,034 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 10331 states to 10331 states and 14356 transitions. [2023-11-29 01:11:10,034 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 10331 [2023-11-29 01:11:10,041 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 10331 [2023-11-29 01:11:10,041 INFO L73 IsDeterministic]: Start isDeterministic. Operand 10331 states and 14356 transitions. [2023-11-29 01:11:10,049 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:10,049 INFO L218 hiAutomatonCegarLoop]: Abstraction has 10331 states and 14356 transitions. [2023-11-29 01:11:10,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 10331 states and 14356 transitions. [2023-11-29 01:11:10,170 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 10331 to 10331. [2023-11-29 01:11:10,178 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 10331 states, 10331 states have (on average 1.3896041041525506) internal successors, (14356), 10330 states have internal predecessors, (14356), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:10,196 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 10331 states to 10331 states and 14356 transitions. [2023-11-29 01:11:10,196 INFO L240 hiAutomatonCegarLoop]: Abstraction has 10331 states and 14356 transitions. [2023-11-29 01:11:10,197 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:10,197 INFO L428 stractBuchiCegarLoop]: Abstraction has 10331 states and 14356 transitions. [2023-11-29 01:11:10,197 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 01:11:10,197 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 10331 states and 14356 transitions. [2023-11-29 01:11:10,222 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 10096 [2023-11-29 01:11:10,222 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:10,222 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:10,224 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:10,224 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:10,224 INFO L748 eck$LassoCheckResult]: Stem: 209534#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 209535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 210147#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 210148#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 210186#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 210170#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 210171#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 209695#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 209696#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 209766#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 209597#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 209598#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 209565#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 209566#L754 assume !(0 == ~M_E~0); 210203#L754-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 210097#L759-1 assume !(0 == ~T2_E~0); 210098#L764-1 assume !(0 == ~T3_E~0); 209908#L769-1 assume !(0 == ~T4_E~0); 209909#L774-1 assume !(0 == ~T5_E~0); 210180#L779-1 assume !(0 == ~T6_E~0); 210181#L784-1 assume !(0 == ~T7_E~0); 209905#L789-1 assume !(0 == ~E_1~0); 209906#L794-1 assume !(0 == ~E_2~0); 210225#L799-1 assume !(0 == ~E_3~0); 210226#L804-1 assume !(0 == ~E_4~0); 209947#L809-1 assume !(0 == ~E_5~0); 209948#L814-1 assume !(0 == ~E_6~0); 209334#L819-1 assume !(0 == ~E_7~0); 209335#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 209595#L361 assume !(1 == ~m_pc~0); 209596#L361-2 is_master_triggered_~__retres1~0#1 := 0; 210214#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 210084#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 210085#L930 assume !(0 != activate_threads_~tmp~1#1); 209814#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 209815#L380 assume !(1 == ~t1_pc~0); 210013#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 210184#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 209358#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 209359#L938 assume !(0 != activate_threads_~tmp___0~0#1); 210036#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 210014#L399 assume !(1 == ~t2_pc~0); 210015#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 210188#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 210189#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 209667#L946 assume !(0 != activate_threads_~tmp___1~0#1); 209668#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 209342#L418 assume !(1 == ~t3_pc~0); 209343#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 210131#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 209332#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 209333#L954 assume !(0 != activate_threads_~tmp___2~0#1); 210232#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 210204#L437 assume !(1 == ~t4_pc~0); 210205#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 210251#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 209416#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209417#L962 assume !(0 != activate_threads_~tmp___3~0#1); 209724#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 210249#L456 assume !(1 == ~t5_pc~0); 209520#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 209519#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 210248#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 210247#L970 assume !(0 != activate_threads_~tmp___4~0#1); 210219#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 209411#L475 assume !(1 == ~t6_pc~0); 209412#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 210245#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 209656#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 209657#L978 assume !(0 != activate_threads_~tmp___5~0#1); 209925#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 209926#L494 assume !(1 == ~t7_pc~0); 209640#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 209641#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 209879#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 209957#L986 assume !(0 != activate_threads_~tmp___6~0#1); 209958#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 210197#L837 assume !(1 == ~M_E~0); 210146#L837-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 210007#L842-1 assume !(1 == ~T2_E~0); 209733#L847-1 assume !(1 == ~T3_E~0); 209734#L852-1 assume !(1 == ~T4_E~0); 209803#L857-1 assume !(1 == ~T5_E~0); 209681#L862-1 assume !(1 == ~T6_E~0); 209682#L867-1 assume !(1 == ~T7_E~0); 209691#L872-1 assume !(1 == ~E_1~0); 209765#L877-1 assume !(1 == ~E_2~0); 209972#L882-1 assume !(1 == ~E_3~0); 210152#L887-1 assume !(1 == ~E_4~0); 210029#L892-1 assume !(1 == ~E_5~0); 210030#L897-1 assume !(1 == ~E_6~0); 209706#L902-1 assume !(1 == ~E_7~0); 209707#L907-1 assume { :end_inline_reset_delta_events } true; 210055#L1148-2 [2023-11-29 01:11:10,224 INFO L750 eck$LassoCheckResult]: Loop: 210055#L1148-2 assume !false; 215260#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 215258#L729-1 assume !false; 215256#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 215244#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 215238#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 215236#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 215233#L626 assume !(0 != eval_~tmp~0#1); 215234#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 215493#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 215491#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 215488#L754-5 assume !(0 == ~T1_E~0); 215489#L759-3 assume !(0 == ~T2_E~0); 215579#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 215577#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 215575#L774-3 assume !(0 == ~T5_E~0); 215573#L779-3 assume !(0 == ~T6_E~0); 215571#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 215569#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 215567#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 215565#L799-3 assume !(0 == ~E_3~0); 215562#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 215560#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 215558#L814-3 assume !(0 == ~E_6~0); 215556#L819-3 assume !(0 == ~E_7~0); 215554#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 215552#L361-24 assume !(1 == ~m_pc~0); 215551#L361-26 is_master_triggered_~__retres1~0#1 := 0; 215547#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 215545#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 215543#L930-24 assume !(0 != activate_threads_~tmp~1#1); 215540#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 215539#L380-24 assume 1 == ~t1_pc~0; 215538#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 215536#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 215534#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 215531#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 215530#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 215529#L399-24 assume !(1 == ~t2_pc~0); 215528#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 215527#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 215525#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 215524#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 215523#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 215522#L418-24 assume !(1 == ~t3_pc~0); 215521#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 215519#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 215518#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 215517#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 215516#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 215515#L437-24 assume !(1 == ~t4_pc~0); 215514#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 215513#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 215511#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 215509#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 215507#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 215505#L456-24 assume !(1 == ~t5_pc~0); 215503#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 215500#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 215499#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 215498#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 215497#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 215496#L475-24 assume !(1 == ~t6_pc~0); 215495#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 215494#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 215492#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 215490#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 215487#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 215485#L494-24 assume !(1 == ~t7_pc~0); 215482#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 215480#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 215478#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 215476#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 215474#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 215472#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 215360#L837-5 assume !(1 == ~T1_E~0); 215358#L842-3 assume !(1 == ~T2_E~0); 215355#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 215353#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 215351#L857-3 assume !(1 == ~T5_E~0); 215349#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 215347#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 215345#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 215343#L877-3 assume !(1 == ~E_2~0); 215341#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 215339#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 215337#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 215335#L897-3 assume !(1 == ~E_6~0); 215333#L902-3 assume !(1 == ~E_7~0); 215331#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 215321#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 215315#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 215313#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 215311#L1167 assume !(0 == start_simulation_~tmp~3#1); 215306#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 215304#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 215295#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 215293#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 215290#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 215288#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 215286#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 215283#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 210055#L1148-2 [2023-11-29 01:11:10,225 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:10,225 INFO L85 PathProgramCache]: Analyzing trace with hash -1286806590, now seen corresponding path program 1 times [2023-11-29 01:11:10,225 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:10,225 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [949234430] [2023-11-29 01:11:10,225 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:10,226 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:10,235 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:10,260 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:10,260 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:10,260 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [949234430] [2023-11-29 01:11:10,260 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [949234430] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:10,260 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:10,260 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:10,260 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [312234013] [2023-11-29 01:11:10,261 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:10,261 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:10,261 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:10,261 INFO L85 PathProgramCache]: Analyzing trace with hash 427301924, now seen corresponding path program 1 times [2023-11-29 01:11:10,261 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:10,262 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [698768424] [2023-11-29 01:11:10,262 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:10,262 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:10,272 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:10,296 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:10,297 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:10,297 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [698768424] [2023-11-29 01:11:10,297 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [698768424] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:10,297 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:10,297 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:10,297 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1768243702] [2023-11-29 01:11:10,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:10,298 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:10,298 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:10,298 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:10,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:10,299 INFO L87 Difference]: Start difference. First operand 10331 states and 14356 transitions. cyclomatic complexity: 4041 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:10,345 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:10,345 INFO L93 Difference]: Finished difference Result 9092 states and 12603 transitions. [2023-11-29 01:11:10,345 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9092 states and 12603 transitions. [2023-11-29 01:11:10,381 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2023-11-29 01:11:10,408 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9092 states to 9092 states and 12603 transitions. [2023-11-29 01:11:10,409 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9092 [2023-11-29 01:11:10,414 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9092 [2023-11-29 01:11:10,414 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9092 states and 12603 transitions. [2023-11-29 01:11:10,420 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:10,420 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12603 transitions. [2023-11-29 01:11:10,426 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9092 states and 12603 transitions. [2023-11-29 01:11:10,502 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9092 to 9092. [2023-11-29 01:11:10,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.3861636603607568) internal successors, (12603), 9091 states have internal predecessors, (12603), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:10,531 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12603 transitions. [2023-11-29 01:11:10,531 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12603 transitions. [2023-11-29 01:11:10,532 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:10,533 INFO L428 stractBuchiCegarLoop]: Abstraction has 9092 states and 12603 transitions. [2023-11-29 01:11:10,533 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 01:11:10,533 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12603 transitions. [2023-11-29 01:11:10,567 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2023-11-29 01:11:10,568 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:10,568 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:10,570 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:10,570 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:10,570 INFO L748 eck$LassoCheckResult]: Stem: 228961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 228962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 229558#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 229559#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 229601#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 229584#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 229585#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 229116#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 229117#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 229188#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 229026#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 229027#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 228994#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 228995#L754 assume !(0 == ~M_E~0); 229613#L754-2 assume !(0 == ~T1_E~0); 229515#L759-1 assume !(0 == ~T2_E~0); 229376#L764-1 assume !(0 == ~T3_E~0); 229326#L769-1 assume !(0 == ~T4_E~0); 229327#L774-1 assume !(0 == ~T5_E~0); 229377#L779-1 assume !(0 == ~T6_E~0); 229524#L784-1 assume !(0 == ~T7_E~0); 229323#L789-1 assume !(0 == ~E_1~0); 229324#L794-1 assume !(0 == ~E_2~0); 229425#L799-1 assume !(0 == ~E_3~0); 229334#L804-1 assume !(0 == ~E_4~0); 229335#L809-1 assume !(0 == ~E_5~0); 229371#L814-1 assume !(0 == ~E_6~0); 228763#L819-1 assume !(0 == ~E_7~0); 228764#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 229024#L361 assume !(1 == ~m_pc~0); 229025#L361-2 is_master_triggered_~__retres1~0#1 := 0; 229553#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 229501#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 229502#L930 assume !(0 != activate_threads_~tmp~1#1); 229235#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 229018#L380 assume !(1 == ~t1_pc~0); 229019#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 229598#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 229599#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 229635#L938 assume !(0 != activate_threads_~tmp___0~0#1); 229457#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 229436#L399 assume !(1 == ~t2_pc~0); 228929#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 228930#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 229095#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 229088#L946 assume !(0 != activate_threads_~tmp___1~0#1); 229089#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 228771#L418 assume !(1 == ~t3_pc~0); 228751#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 228752#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 228761#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 228762#L954 assume !(0 != activate_threads_~tmp___2~0#1); 229353#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 229354#L437 assume !(1 == ~t4_pc~0); 229586#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 229496#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 228840#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 228841#L962 assume !(0 != activate_threads_~tmp___3~0#1); 229145#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 229477#L456 assume !(1 == ~t5_pc~0); 228944#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 228943#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 229505#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 229410#L970 assume !(0 != activate_threads_~tmp___4~0#1); 229411#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 228835#L475 assume !(1 == ~t6_pc~0); 228836#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 228876#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 228877#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 229081#L978 assume !(0 != activate_threads_~tmp___5~0#1); 229340#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 229341#L494 assume !(1 == ~t7_pc~0); 229065#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 229066#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 229294#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 229378#L986 assume !(0 != activate_threads_~tmp___6~0#1); 229379#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 229608#L837 assume !(1 == ~M_E~0); 229557#L837-2 assume !(1 == ~T1_E~0); 229432#L842-1 assume !(1 == ~T2_E~0); 229153#L847-1 assume !(1 == ~T3_E~0); 229154#L852-1 assume !(1 == ~T4_E~0); 229225#L857-1 assume !(1 == ~T5_E~0); 229101#L862-1 assume !(1 == ~T6_E~0); 229102#L867-1 assume !(1 == ~T7_E~0); 229112#L872-1 assume !(1 == ~E_1~0); 229187#L877-1 assume !(1 == ~E_2~0); 229393#L882-1 assume !(1 == ~E_3~0); 229563#L887-1 assume !(1 == ~E_4~0); 229451#L892-1 assume !(1 == ~E_5~0); 229452#L897-1 assume !(1 == ~E_6~0); 229127#L902-1 assume !(1 == ~E_7~0); 229128#L907-1 assume { :end_inline_reset_delta_events } true; 229476#L1148-2 [2023-11-29 01:11:10,571 INFO L750 eck$LassoCheckResult]: Loop: 229476#L1148-2 assume !false; 232136#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 232135#L729-1 assume !false; 232134#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 232130#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 232125#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 232124#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 232121#L626 assume !(0 != eval_~tmp~0#1); 232122#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 232886#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 232885#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 232884#L754-5 assume !(0 == ~T1_E~0); 232883#L759-3 assume !(0 == ~T2_E~0); 232882#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 232881#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 232880#L774-3 assume !(0 == ~T5_E~0); 232879#L779-3 assume !(0 == ~T6_E~0); 232878#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 232877#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 232876#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 232875#L799-3 assume !(0 == ~E_3~0); 232874#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 232873#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 232872#L814-3 assume !(0 == ~E_6~0); 232871#L819-3 assume !(0 == ~E_7~0); 232870#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 232869#L361-24 assume !(1 == ~m_pc~0); 232867#L361-26 is_master_triggered_~__retres1~0#1 := 0; 232866#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 232865#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 232864#L930-24 assume !(0 != activate_threads_~tmp~1#1); 232863#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 232861#L380-24 assume 1 == ~t1_pc~0; 232859#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 232860#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 232862#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 232852#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 232850#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 232848#L399-24 assume !(1 == ~t2_pc~0); 232846#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 232844#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 232840#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 232838#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 232836#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 232834#L418-24 assume !(1 == ~t3_pc~0); 232831#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 232828#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 232826#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 232824#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 232822#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 232820#L437-24 assume !(1 == ~t4_pc~0); 232818#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 232816#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 232814#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 232811#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 232809#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 232807#L456-24 assume !(1 == ~t5_pc~0); 232805#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 232802#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 232800#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 232798#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 232796#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 232794#L475-24 assume !(1 == ~t6_pc~0); 232792#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 232790#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 232788#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 232785#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 232783#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 232781#L494-24 assume !(1 == ~t7_pc~0); 232778#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 232776#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 232774#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 232772#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 232770#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 232768#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 232766#L837-5 assume !(1 == ~T1_E~0); 232764#L842-3 assume !(1 == ~T2_E~0); 232761#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 232759#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 232757#L857-3 assume !(1 == ~T5_E~0); 232755#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 232753#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 232751#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 232749#L877-3 assume !(1 == ~E_2~0); 232747#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 232745#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 232743#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 232741#L897-3 assume !(1 == ~E_6~0); 232739#L902-3 assume !(1 == ~E_7~0); 232737#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 232727#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 232721#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 232719#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 232717#L1167 assume !(0 == start_simulation_~tmp~3#1); 232715#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 232714#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 232705#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 232703#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 232701#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 232699#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 232698#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 232697#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 229476#L1148-2 [2023-11-29 01:11:10,572 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:10,572 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 2 times [2023-11-29 01:11:10,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:10,573 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [615747503] [2023-11-29 01:11:10,573 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:10,573 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:10,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:10,590 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:10,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:10,632 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:10,632 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:10,633 INFO L85 PathProgramCache]: Analyzing trace with hash 427301924, now seen corresponding path program 2 times [2023-11-29 01:11:10,633 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:10,633 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [567539840] [2023-11-29 01:11:10,633 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:10,633 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:10,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:10,681 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:10,681 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:10,681 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [567539840] [2023-11-29 01:11:10,682 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [567539840] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:10,682 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:10,682 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:10,682 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062411856] [2023-11-29 01:11:10,682 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:10,683 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:10,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:10,683 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:10,683 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:10,684 INFO L87 Difference]: Start difference. First operand 9092 states and 12603 transitions. cyclomatic complexity: 3527 Second operand has 3 states, 3 states have (on average 34.0) internal successors, (102), 3 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:10,806 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:10,807 INFO L93 Difference]: Finished difference Result 13563 states and 18702 transitions. [2023-11-29 01:11:10,807 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13563 states and 18702 transitions. [2023-11-29 01:11:10,877 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13304 [2023-11-29 01:11:10,931 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13563 states to 13563 states and 18702 transitions. [2023-11-29 01:11:10,931 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13563 [2023-11-29 01:11:10,941 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13563 [2023-11-29 01:11:10,941 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13563 states and 18702 transitions. [2023-11-29 01:11:10,952 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:10,952 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13563 states and 18702 transitions. [2023-11-29 01:11:10,962 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13563 states and 18702 transitions. [2023-11-29 01:11:11,109 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13563 to 13555. [2023-11-29 01:11:11,122 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13555 states, 13555 states have (on average 1.3791220951678347) internal successors, (18694), 13554 states have internal predecessors, (18694), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:11,159 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13555 states to 13555 states and 18694 transitions. [2023-11-29 01:11:11,160 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13555 states and 18694 transitions. [2023-11-29 01:11:11,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:11,161 INFO L428 stractBuchiCegarLoop]: Abstraction has 13555 states and 18694 transitions. [2023-11-29 01:11:11,161 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 01:11:11,161 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13555 states and 18694 transitions. [2023-11-29 01:11:11,212 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13296 [2023-11-29 01:11:11,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:11,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:11,215 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:11,215 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:11,215 INFO L748 eck$LassoCheckResult]: Stem: 251620#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 251621#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 252232#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 252233#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 252273#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 252256#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 252257#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 251776#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 251777#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 251847#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 251681#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 251682#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 251650#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 251651#L754 assume !(0 == ~M_E~0); 252287#L754-2 assume !(0 == ~T1_E~0); 252181#L759-1 assume !(0 == ~T2_E~0); 252027#L764-1 assume !(0 == ~T3_E~0); 251982#L769-1 assume !(0 == ~T4_E~0); 251983#L774-1 assume !(0 == ~T5_E~0); 252028#L779-1 assume !(0 == ~T6_E~0); 252191#L784-1 assume !(0 == ~T7_E~0); 251979#L789-1 assume !(0 == ~E_1~0); 251980#L794-1 assume 0 == ~E_2~0;~E_2~0 := 1; 252074#L799-1 assume !(0 == ~E_3~0); 251990#L804-1 assume !(0 == ~E_4~0); 251991#L809-1 assume !(0 == ~E_5~0); 252212#L814-1 assume !(0 == ~E_6~0); 252213#L819-1 assume !(0 == ~E_7~0); 251744#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 251745#L361 assume !(1 == ~m_pc~0); 252225#L361-2 is_master_triggered_~__retres1~0#1 := 0; 252226#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 252166#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 252167#L930 assume !(0 != activate_threads_~tmp~1#1); 251891#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 251892#L380 assume !(1 == ~t1_pc~0); 252091#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 252315#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 252353#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 252350#L938 assume !(0 != activate_threads_~tmp___0~0#1); 252349#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 252348#L399 assume !(1 == ~t2_pc~0); 251590#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 251591#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 251757#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 251758#L946 assume !(0 != activate_threads_~tmp___1~0#1); 252347#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 252346#L418 assume !(1 == ~t3_pc~0); 251412#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 251413#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 252345#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 252321#L954 assume !(0 != activate_threads_~tmp___2~0#1); 252322#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 252288#L437 assume !(1 == ~t4_pc~0); 252289#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 252344#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 251503#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 251504#L962 assume !(0 != activate_threads_~tmp___3~0#1); 251804#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 252342#L456 assume !(1 == ~t5_pc~0); 251604#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 251603#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 252341#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 252340#L970 assume !(0 != activate_threads_~tmp___4~0#1); 252304#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 252305#L475 assume !(1 == ~t6_pc~0); 251942#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 251943#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 251740#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 251741#L978 assume !(0 != activate_threads_~tmp___5~0#1); 252057#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 252210#L494 assume !(1 == ~t7_pc~0); 251936#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 252337#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 252336#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 252335#L986 assume !(0 != activate_threads_~tmp___6~0#1); 252334#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 252333#L837 assume !(1 == ~M_E~0); 252332#L837-2 assume !(1 == ~T1_E~0); 252331#L842-1 assume !(1 == ~T2_E~0); 252330#L847-1 assume !(1 == ~T3_E~0); 251880#L852-1 assume !(1 == ~T4_E~0); 251881#L857-1 assume !(1 == ~T5_E~0); 251764#L862-1 assume !(1 == ~T6_E~0); 251765#L867-1 assume !(1 == ~T7_E~0); 251772#L872-1 assume !(1 == ~E_1~0); 251846#L877-1 assume 1 == ~E_2~0;~E_2~0 := 2; 252044#L882-1 assume !(1 == ~E_3~0); 252239#L887-1 assume !(1 == ~E_4~0); 252111#L892-1 assume !(1 == ~E_5~0); 252112#L897-1 assume !(1 == ~E_6~0); 251787#L902-1 assume !(1 == ~E_7~0); 251788#L907-1 assume { :end_inline_reset_delta_events } true; 252135#L1148-2 [2023-11-29 01:11:11,216 INFO L750 eck$LassoCheckResult]: Loop: 252135#L1148-2 assume !false; 254124#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 254122#L729-1 assume !false; 254121#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 254044#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 254034#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 254028#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 254020#L626 assume !(0 != eval_~tmp~0#1); 254021#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 254780#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 254778#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 254776#L754-5 assume !(0 == ~T1_E~0); 254774#L759-3 assume !(0 == ~T2_E~0); 254772#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 254770#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 254768#L774-3 assume !(0 == ~T5_E~0); 254766#L779-3 assume !(0 == ~T6_E~0); 254763#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 254761#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 254758#L794-3 assume 0 == ~E_2~0;~E_2~0 := 1; 254759#L799-3 assume !(0 == ~E_3~0); 256356#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 256353#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 256351#L814-3 assume !(0 == ~E_6~0); 256349#L819-3 assume !(0 == ~E_7~0); 256347#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 256345#L361-24 assume !(1 == ~m_pc~0); 256343#L361-26 is_master_triggered_~__retres1~0#1 := 0; 256341#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 256339#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 256337#L930-24 assume !(0 != activate_threads_~tmp~1#1); 256334#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 256332#L380-24 assume 1 == ~t1_pc~0; 256330#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 256331#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 256383#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 256321#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 256318#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 256316#L399-24 assume !(1 == ~t2_pc~0); 256314#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 256312#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 256310#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 256307#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 256305#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 256303#L418-24 assume !(1 == ~t3_pc~0); 256283#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 256280#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 256278#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 256276#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 256274#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 256272#L437-24 assume !(1 == ~t4_pc~0); 256269#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 256267#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 256243#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 256235#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 254837#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 254834#L456-24 assume !(1 == ~t5_pc~0); 254832#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 254829#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 254686#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 254683#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 254681#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 254668#L475-24 assume !(1 == ~t6_pc~0); 254658#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 254649#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 254648#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 254647#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 254645#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 254643#L494-24 assume !(1 == ~t7_pc~0); 254632#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 254626#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 254619#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 254612#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 254607#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 254602#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 254597#L837-5 assume !(1 == ~T1_E~0); 254592#L842-3 assume !(1 == ~T2_E~0); 254587#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 254582#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 254577#L857-3 assume !(1 == ~T5_E~0); 254572#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 254567#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 254561#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 254518#L877-3 assume 1 == ~E_2~0;~E_2~0 := 2; 254515#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 254513#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 254511#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 254509#L897-3 assume !(1 == ~E_6~0); 254507#L902-3 assume !(1 == ~E_7~0); 254505#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 254404#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 254395#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 254388#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 254381#L1167 assume !(0 == start_simulation_~tmp~3#1); 254375#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 254194#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 254185#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 254183#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 254181#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 254179#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 254176#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 254174#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 252135#L1148-2 [2023-11-29 01:11:11,217 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:11,217 INFO L85 PathProgramCache]: Analyzing trace with hash 1160880066, now seen corresponding path program 1 times [2023-11-29 01:11:11,217 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:11,217 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1801380696] [2023-11-29 01:11:11,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:11,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:11,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:11,267 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:11,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:11,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1801380696] [2023-11-29 01:11:11,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1801380696] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:11,268 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:11,268 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:11,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [53602130] [2023-11-29 01:11:11,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:11,269 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:11,270 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:11,270 INFO L85 PathProgramCache]: Analyzing trace with hash 2116245666, now seen corresponding path program 1 times [2023-11-29 01:11:11,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:11,270 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [337491477] [2023-11-29 01:11:11,270 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:11,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:11,285 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:11,337 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:11,338 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:11,338 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [337491477] [2023-11-29 01:11:11,338 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [337491477] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:11,338 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:11,339 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:11:11,339 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1502387008] [2023-11-29 01:11:11,339 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:11,340 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:11,340 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:11,340 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:11,340 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:11,341 INFO L87 Difference]: Start difference. First operand 13555 states and 18694 transitions. cyclomatic complexity: 5155 Second operand has 3 states, 3 states have (on average 31.0) internal successors, (93), 2 states have internal predecessors, (93), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:11,413 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:11,413 INFO L93 Difference]: Finished difference Result 9092 states and 12493 transitions. [2023-11-29 01:11:11,413 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 9092 states and 12493 transitions. [2023-11-29 01:11:11,457 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2023-11-29 01:11:11,488 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 9092 states to 9092 states and 12493 transitions. [2023-11-29 01:11:11,488 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 9092 [2023-11-29 01:11:11,495 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 9092 [2023-11-29 01:11:11,495 INFO L73 IsDeterministic]: Start isDeterministic. Operand 9092 states and 12493 transitions. [2023-11-29 01:11:11,502 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:11,502 INFO L218 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12493 transitions. [2023-11-29 01:11:11,510 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 9092 states and 12493 transitions. [2023-11-29 01:11:11,606 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 9092 to 9092. [2023-11-29 01:11:11,615 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9092 states, 9092 states have (on average 1.3740651121865377) internal successors, (12493), 9091 states have internal predecessors, (12493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:11,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9092 states to 9092 states and 12493 transitions. [2023-11-29 01:11:11,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9092 states and 12493 transitions. [2023-11-29 01:11:11,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:11,639 INFO L428 stractBuchiCegarLoop]: Abstraction has 9092 states and 12493 transitions. [2023-11-29 01:11:11,639 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 01:11:11,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9092 states and 12493 transitions. [2023-11-29 01:11:11,671 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8928 [2023-11-29 01:11:11,671 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:11,671 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:11,673 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:11,673 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:11,673 INFO L748 eck$LassoCheckResult]: Stem: 274273#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 274274#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 274847#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 274848#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 274877#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 274864#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 274865#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 274427#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 274428#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 274496#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 274336#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 274337#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 274305#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 274306#L754 assume !(0 == ~M_E~0); 274890#L754-2 assume !(0 == ~T1_E~0); 274804#L759-1 assume !(0 == ~T2_E~0); 274670#L764-1 assume !(0 == ~T3_E~0); 274629#L769-1 assume !(0 == ~T4_E~0); 274630#L774-1 assume !(0 == ~T5_E~0); 274671#L779-1 assume !(0 == ~T6_E~0); 274815#L784-1 assume !(0 == ~T7_E~0); 274626#L789-1 assume !(0 == ~E_1~0); 274627#L794-1 assume !(0 == ~E_2~0); 274718#L799-1 assume !(0 == ~E_3~0); 274637#L804-1 assume !(0 == ~E_4~0); 274638#L809-1 assume !(0 == ~E_5~0); 274665#L814-1 assume !(0 == ~E_6~0); 274080#L819-1 assume !(0 == ~E_7~0); 274081#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 274334#L361 assume !(1 == ~m_pc~0); 274335#L361-2 is_master_triggered_~__retres1~0#1 := 0; 274841#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 274791#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 274792#L930 assume !(0 != activate_threads_~tmp~1#1); 274540#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 274328#L380 assume !(1 == ~t1_pc~0); 274329#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 274873#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 274874#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 274910#L938 assume !(0 != activate_threads_~tmp___0~0#1); 274748#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 274728#L399 assume !(1 == ~t2_pc~0); 274244#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 274245#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 274407#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 274400#L946 assume !(0 != activate_threads_~tmp___1~0#1); 274401#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 274088#L418 assume !(1 == ~t3_pc~0); 274068#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 274069#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 274078#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 274079#L954 assume !(0 != activate_threads_~tmp___2~0#1); 274653#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 274654#L437 assume !(1 == ~t4_pc~0); 274866#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 274785#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 274158#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 274159#L962 assume !(0 != activate_threads_~tmp___3~0#1); 274455#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 274767#L456 assume !(1 == ~t5_pc~0); 274259#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 274258#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 274795#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 274702#L970 assume !(0 != activate_threads_~tmp___4~0#1); 274703#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 274153#L475 assume !(1 == ~t6_pc~0); 274154#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 274195#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 274196#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 274393#L978 assume !(0 != activate_threads_~tmp___5~0#1); 274642#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 274643#L494 assume !(1 == ~t7_pc~0); 274377#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 274378#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 274597#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 274672#L986 assume !(0 != activate_threads_~tmp___6~0#1); 274673#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 274886#L837 assume !(1 == ~M_E~0); 274846#L837-2 assume !(1 == ~T1_E~0); 274724#L842-1 assume !(1 == ~T2_E~0); 274463#L847-1 assume !(1 == ~T3_E~0); 274464#L852-1 assume !(1 == ~T4_E~0); 274530#L857-1 assume !(1 == ~T5_E~0); 274413#L862-1 assume !(1 == ~T6_E~0); 274414#L867-1 assume !(1 == ~T7_E~0); 274423#L872-1 assume !(1 == ~E_1~0); 274495#L877-1 assume !(1 == ~E_2~0); 274687#L882-1 assume !(1 == ~E_3~0); 274852#L887-1 assume !(1 == ~E_4~0); 274743#L892-1 assume !(1 == ~E_5~0); 274744#L897-1 assume !(1 == ~E_6~0); 274438#L902-1 assume !(1 == ~E_7~0); 274439#L907-1 assume { :end_inline_reset_delta_events } true; 274766#L1148-2 [2023-11-29 01:11:11,674 INFO L750 eck$LassoCheckResult]: Loop: 274766#L1148-2 assume !false; 277318#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 277315#L729-1 assume !false; 277313#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 277271#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 277263#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 277259#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 277251#L626 assume !(0 != eval_~tmp~0#1); 277252#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 277964#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 277963#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 277961#L754-5 assume !(0 == ~T1_E~0); 277959#L759-3 assume !(0 == ~T2_E~0); 277957#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 277955#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 277953#L774-3 assume !(0 == ~T5_E~0); 277951#L779-3 assume !(0 == ~T6_E~0); 277949#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 277946#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 277944#L794-3 assume !(0 == ~E_2~0); 277942#L799-3 assume !(0 == ~E_3~0); 277927#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 277921#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 277914#L814-3 assume !(0 == ~E_6~0); 277907#L819-3 assume !(0 == ~E_7~0); 277862#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 277859#L361-24 assume !(1 == ~m_pc~0); 277857#L361-26 is_master_triggered_~__retres1~0#1 := 0; 277855#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 277853#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 277851#L930-24 assume !(0 != activate_threads_~tmp~1#1); 277849#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 277847#L380-24 assume !(1 == ~t1_pc~0); 277844#L380-26 is_transmit1_triggered_~__retres1~1#1 := 0; 277863#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 277827#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 277820#L938-24 assume !(0 != activate_threads_~tmp___0~0#1); 277812#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 277805#L399-24 assume !(1 == ~t2_pc~0); 277798#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 277791#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 277784#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 277777#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 277769#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 277730#L418-24 assume 1 == ~t3_pc~0; 277726#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 277724#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 277722#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 277720#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 277719#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 277705#L437-24 assume !(1 == ~t4_pc~0); 277698#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 277692#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 277683#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 277662#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 277658#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 277654#L456-24 assume 1 == ~t5_pc~0; 277650#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 277624#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 277621#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 277618#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 277614#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 277611#L475-24 assume !(1 == ~t6_pc~0); 277607#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 277603#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 277599#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 277595#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 277590#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 277584#L494-24 assume !(1 == ~t7_pc~0); 277578#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 277572#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 277567#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 277562#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 277557#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 277553#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 277549#L837-5 assume !(1 == ~T1_E~0); 277545#L842-3 assume !(1 == ~T2_E~0); 277541#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 277537#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 277532#L857-3 assume !(1 == ~T5_E~0); 277527#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 277523#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 277517#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 277512#L877-3 assume !(1 == ~E_2~0); 277507#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 277501#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 277496#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 277491#L897-3 assume !(1 == ~E_6~0); 277486#L902-3 assume !(1 == ~E_7~0); 277472#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 277416#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 277407#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 277402#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 277395#L1167 assume !(0 == start_simulation_~tmp~3#1); 277391#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 277368#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 277358#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 277353#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 277350#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 277344#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 277338#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 277331#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 274766#L1148-2 [2023-11-29 01:11:11,674 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:11,674 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 3 times [2023-11-29 01:11:11,675 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:11,675 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414617542] [2023-11-29 01:11:11,675 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:11,675 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:11,692 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:11,692 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:11,702 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:11,730 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:11,731 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:11,731 INFO L85 PathProgramCache]: Analyzing trace with hash 81632005, now seen corresponding path program 1 times [2023-11-29 01:11:11,731 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:11,732 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1389569835] [2023-11-29 01:11:11,732 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:11,732 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:11,747 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:11,799 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:11,799 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:11,800 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1389569835] [2023-11-29 01:11:11,800 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1389569835] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:11,800 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:11,800 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:11:11,801 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1017969885] [2023-11-29 01:11:11,801 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:11,801 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:11,801 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:11,802 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:11:11,802 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:11:11,802 INFO L87 Difference]: Start difference. First operand 9092 states and 12493 transitions. cyclomatic complexity: 3417 Second operand has 5 states, 5 states have (on average 20.4) internal successors, (102), 5 states have internal predecessors, (102), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:11,984 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:11,984 INFO L93 Difference]: Finished difference Result 16468 states and 22405 transitions. [2023-11-29 01:11:11,984 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16468 states and 22405 transitions. [2023-11-29 01:11:12,055 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16240 [2023-11-29 01:11:12,092 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16468 states to 16468 states and 22405 transitions. [2023-11-29 01:11:12,093 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16468 [2023-11-29 01:11:12,103 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16468 [2023-11-29 01:11:12,104 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16468 states and 22405 transitions. [2023-11-29 01:11:12,117 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:12,118 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16468 states and 22405 transitions. [2023-11-29 01:11:12,131 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16468 states and 22405 transitions. [2023-11-29 01:11:12,234 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16468 to 9140. [2023-11-29 01:11:12,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 9140 states, 9140 states have (on average 1.3721006564551423) internal successors, (12541), 9139 states have internal predecessors, (12541), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:12,259 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 9140 states to 9140 states and 12541 transitions. [2023-11-29 01:11:12,259 INFO L240 hiAutomatonCegarLoop]: Abstraction has 9140 states and 12541 transitions. [2023-11-29 01:11:12,259 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-29 01:11:12,260 INFO L428 stractBuchiCegarLoop]: Abstraction has 9140 states and 12541 transitions. [2023-11-29 01:11:12,260 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 01:11:12,260 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 9140 states and 12541 transitions. [2023-11-29 01:11:12,285 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 8976 [2023-11-29 01:11:12,285 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:12,286 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:12,287 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:12,287 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:12,287 INFO L748 eck$LassoCheckResult]: Stem: 299854#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 299855#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 300451#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 300452#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 300488#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 300473#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 300474#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 300010#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 300011#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 300081#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 299917#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 299918#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 299886#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 299887#L754 assume !(0 == ~M_E~0); 300503#L754-2 assume !(0 == ~T1_E~0); 300403#L759-1 assume !(0 == ~T2_E~0); 300263#L764-1 assume !(0 == ~T3_E~0); 300219#L769-1 assume !(0 == ~T4_E~0); 300220#L774-1 assume !(0 == ~T5_E~0); 300264#L779-1 assume !(0 == ~T6_E~0); 300415#L784-1 assume !(0 == ~T7_E~0); 300216#L789-1 assume !(0 == ~E_1~0); 300217#L794-1 assume !(0 == ~E_2~0); 300314#L799-1 assume !(0 == ~E_3~0); 300226#L804-1 assume !(0 == ~E_4~0); 300227#L809-1 assume !(0 == ~E_5~0); 300258#L814-1 assume !(0 == ~E_6~0); 299659#L819-1 assume !(0 == ~E_7~0); 299660#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 299915#L361 assume !(1 == ~m_pc~0); 299916#L361-2 is_master_triggered_~__retres1~0#1 := 0; 300447#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 300390#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 300391#L930 assume !(0 != activate_threads_~tmp~1#1); 300130#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 299909#L380 assume !(1 == ~t1_pc~0); 299910#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 300484#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 300485#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 300530#L938 assume !(0 != activate_threads_~tmp___0~0#1); 300346#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 300325#L399 assume !(1 == ~t2_pc~0); 299823#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 299824#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 299991#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 299984#L946 assume !(0 != activate_threads_~tmp___1~0#1); 299985#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 299665#L418 assume !(1 == ~t3_pc~0); 299645#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 299646#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 299655#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 299656#L954 assume !(0 != activate_threads_~tmp___2~0#1); 300243#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 300244#L437 assume !(1 == ~t4_pc~0); 300475#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 300384#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 299734#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 299735#L962 assume !(0 != activate_threads_~tmp___3~0#1); 300040#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 300369#L456 assume !(1 == ~t5_pc~0); 299837#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 299836#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 300394#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 300301#L970 assume !(0 != activate_threads_~tmp___4~0#1); 300302#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 299729#L475 assume !(1 == ~t6_pc~0); 299730#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 299772#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 299773#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 299977#L978 assume !(0 != activate_threads_~tmp___5~0#1); 300233#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 300234#L494 assume !(1 == ~t7_pc~0); 299961#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 299962#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 300188#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 300265#L986 assume !(0 != activate_threads_~tmp___6~0#1); 300266#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 300495#L837 assume !(1 == ~M_E~0); 300450#L837-2 assume !(1 == ~T1_E~0); 300321#L842-1 assume !(1 == ~T2_E~0); 300049#L847-1 assume !(1 == ~T3_E~0); 300050#L852-1 assume !(1 == ~T4_E~0); 300119#L857-1 assume !(1 == ~T5_E~0); 299997#L862-1 assume !(1 == ~T6_E~0); 299998#L867-1 assume !(1 == ~T7_E~0); 300006#L872-1 assume !(1 == ~E_1~0); 300080#L877-1 assume !(1 == ~E_2~0); 300280#L882-1 assume !(1 == ~E_3~0); 300456#L887-1 assume !(1 == ~E_4~0); 300340#L892-1 assume !(1 == ~E_5~0); 300341#L897-1 assume !(1 == ~E_6~0); 300022#L902-1 assume !(1 == ~E_7~0); 300023#L907-1 assume { :end_inline_reset_delta_events } true; 300363#L1148-2 [2023-11-29 01:11:12,288 INFO L750 eck$LassoCheckResult]: Loop: 300363#L1148-2 assume !false; 307851#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 307059#L729-1 assume !false; 306941#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 306925#L569 assume !(0 == ~m_st~0); 306926#L573 assume !(0 == ~t1_st~0); 306929#L577 assume !(0 == ~t2_st~0); 306923#L581 assume !(0 == ~t3_st~0); 306924#L585 assume !(0 == ~t4_st~0); 306928#L589 assume !(0 == ~t5_st~0); 306921#L593 assume !(0 == ~t6_st~0); 306922#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 306927#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 303240#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 303241#L626 assume !(0 != eval_~tmp~0#1); 306895#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 306896#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 306887#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 306888#L754-5 assume !(0 == ~T1_E~0); 306876#L759-3 assume !(0 == ~T2_E~0); 306877#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 306871#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 306872#L774-3 assume !(0 == ~T5_E~0); 306867#L779-3 assume !(0 == ~T6_E~0); 306868#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 306781#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 306782#L794-3 assume !(0 == ~E_2~0); 306777#L799-3 assume !(0 == ~E_3~0); 306778#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 300160#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 299708#L814-3 assume !(0 == ~E_6~0); 299709#L819-3 assume !(0 == ~E_7~0); 300375#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 300077#L361-24 assume !(1 == ~m_pc~0); 300078#L361-26 is_master_triggered_~__retres1~0#1 := 0; 307971#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 307970#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 307969#L930-24 assume !(0 != activate_threads_~tmp~1#1); 307968#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 307967#L380-24 assume 1 == ~t1_pc~0; 307965#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 307963#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 307961#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 307959#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 307958#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 307957#L399-24 assume !(1 == ~t2_pc~0); 307956#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 307955#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 307954#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 307953#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 307952#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 307951#L418-24 assume 1 == ~t3_pc~0; 307949#L419-8 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 307948#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 307947#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 307946#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 307945#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 307944#L437-24 assume !(1 == ~t4_pc~0); 307943#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 307942#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 307941#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 307940#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 307939#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 307938#L456-24 assume 1 == ~t5_pc~0; 307936#L457-8 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 307935#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 307934#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 307933#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 307932#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 307931#L475-24 assume !(1 == ~t6_pc~0); 307930#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 307929#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 307928#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 307927#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 307926#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 307925#L494-24 assume !(1 == ~t7_pc~0); 307923#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 307922#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 307921#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 307920#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 307919#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 307918#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 307917#L837-5 assume !(1 == ~T1_E~0); 307916#L842-3 assume !(1 == ~T2_E~0); 307915#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 307914#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 307913#L857-3 assume !(1 == ~T5_E~0); 307912#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 307911#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 307910#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 307909#L877-3 assume !(1 == ~E_2~0); 307908#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 307907#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 307906#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 307905#L897-3 assume !(1 == ~E_6~0); 307904#L902-3 assume !(1 == ~E_7~0); 307903#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 307899#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 307893#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 307878#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 307876#L1167 assume !(0 == start_simulation_~tmp~3#1); 307874#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 307873#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 307864#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 307863#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 307862#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 307861#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 307860#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 307858#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 300363#L1148-2 [2023-11-29 01:11:12,288 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:12,289 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 4 times [2023-11-29 01:11:12,289 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:12,289 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1396328084] [2023-11-29 01:11:12,289 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:12,289 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:12,302 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:12,302 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:12,309 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:12,332 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:12,333 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:12,333 INFO L85 PathProgramCache]: Analyzing trace with hash 594487404, now seen corresponding path program 1 times [2023-11-29 01:11:12,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:12,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [711231057] [2023-11-29 01:11:12,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:12,334 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:12,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:12,375 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:12,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:12,376 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [711231057] [2023-11-29 01:11:12,376 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [711231057] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:12,376 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:12,376 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:12,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1917567307] [2023-11-29 01:11:12,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:12,377 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:12,377 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:12,378 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:12,378 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:12,378 INFO L87 Difference]: Start difference. First operand 9140 states and 12541 transitions. cyclomatic complexity: 3417 Second operand has 3 states, 3 states have (on average 36.333333333333336) internal successors, (109), 3 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:12,463 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:12,464 INFO L93 Difference]: Finished difference Result 17268 states and 23397 transitions. [2023-11-29 01:11:12,464 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 17268 states and 23397 transitions. [2023-11-29 01:11:12,582 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 17056 [2023-11-29 01:11:12,619 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 17268 states to 17268 states and 23397 transitions. [2023-11-29 01:11:12,619 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 17268 [2023-11-29 01:11:12,628 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 17268 [2023-11-29 01:11:12,628 INFO L73 IsDeterministic]: Start isDeterministic. Operand 17268 states and 23397 transitions. [2023-11-29 01:11:12,636 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:12,637 INFO L218 hiAutomatonCegarLoop]: Abstraction has 17268 states and 23397 transitions. [2023-11-29 01:11:12,645 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 17268 states and 23397 transitions. [2023-11-29 01:11:12,744 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 17268 to 16832. [2023-11-29 01:11:12,756 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16832 states, 16832 states have (on average 1.356523288973384) internal successors, (22833), 16831 states have internal predecessors, (22833), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:12,786 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16832 states to 16832 states and 22833 transitions. [2023-11-29 01:11:12,787 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16832 states and 22833 transitions. [2023-11-29 01:11:12,787 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:12,788 INFO L428 stractBuchiCegarLoop]: Abstraction has 16832 states and 22833 transitions. [2023-11-29 01:11:12,788 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-29 01:11:12,788 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16832 states and 22833 transitions. [2023-11-29 01:11:12,825 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16620 [2023-11-29 01:11:12,825 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:12,825 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:12,826 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:12,827 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:12,827 INFO L748 eck$LassoCheckResult]: Stem: 326268#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 326269#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 326854#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 326855#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 326892#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 326879#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 326880#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 326419#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 326420#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 326490#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 326328#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 326329#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 326297#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 326298#L754 assume !(0 == ~M_E~0); 326911#L754-2 assume !(0 == ~T1_E~0); 326806#L759-1 assume !(0 == ~T2_E~0); 326668#L764-1 assume !(0 == ~T3_E~0); 326624#L769-1 assume !(0 == ~T4_E~0); 326625#L774-1 assume !(0 == ~T5_E~0); 326669#L779-1 assume !(0 == ~T6_E~0); 326815#L784-1 assume !(0 == ~T7_E~0); 326621#L789-1 assume !(0 == ~E_1~0); 326622#L794-1 assume !(0 == ~E_2~0); 326718#L799-1 assume !(0 == ~E_3~0); 326632#L804-1 assume !(0 == ~E_4~0); 326633#L809-1 assume !(0 == ~E_5~0); 326663#L814-1 assume !(0 == ~E_6~0); 326071#L819-1 assume !(0 == ~E_7~0); 326072#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 326326#L361 assume !(1 == ~m_pc~0); 326327#L361-2 is_master_triggered_~__retres1~0#1 := 0; 326849#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 326793#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 326794#L930 assume !(0 != activate_threads_~tmp~1#1); 326535#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 326320#L380 assume !(1 == ~t1_pc~0); 326321#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 326889#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 326890#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 326938#L938 assume !(0 != activate_threads_~tmp___0~0#1); 326746#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 326727#L399 assume !(1 == ~t2_pc~0); 326237#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 326238#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 326400#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 326393#L946 assume !(0 != activate_threads_~tmp___1~0#1); 326394#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 326079#L418 assume !(1 == ~t3_pc~0); 326059#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 326060#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 326069#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 326070#L954 assume !(0 != activate_threads_~tmp___2~0#1); 326649#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 326650#L437 assume !(1 == ~t4_pc~0); 326881#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 326787#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 326149#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 326150#L962 assume !(0 != activate_threads_~tmp___3~0#1); 326448#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 326766#L456 assume !(1 == ~t5_pc~0); 326251#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 326250#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 326797#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 326702#L970 assume !(0 != activate_threads_~tmp___4~0#1); 326703#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 326144#L475 assume !(1 == ~t6_pc~0); 326145#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 326186#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 326187#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 326385#L978 assume !(0 != activate_threads_~tmp___5~0#1); 326639#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 326640#L494 assume !(1 == ~t7_pc~0); 326369#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 326370#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 326593#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 326670#L986 assume !(0 != activate_threads_~tmp___6~0#1); 326671#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 326901#L837 assume !(1 == ~M_E~0); 326853#L837-2 assume !(1 == ~T1_E~0); 326723#L842-1 assume !(1 == ~T2_E~0); 326458#L847-1 assume !(1 == ~T3_E~0); 326459#L852-1 assume !(1 == ~T4_E~0); 326525#L857-1 assume !(1 == ~T5_E~0); 326406#L862-1 assume !(1 == ~T6_E~0); 326407#L867-1 assume !(1 == ~T7_E~0); 326415#L872-1 assume !(1 == ~E_1~0); 326489#L877-1 assume !(1 == ~E_2~0); 326684#L882-1 assume !(1 == ~E_3~0); 326860#L887-1 assume !(1 == ~E_4~0); 326741#L892-1 assume !(1 == ~E_5~0); 326742#L897-1 assume !(1 == ~E_6~0); 326431#L902-1 assume !(1 == ~E_7~0); 326432#L907-1 assume { :end_inline_reset_delta_events } true; 326765#L1148-2 [2023-11-29 01:11:12,827 INFO L750 eck$LassoCheckResult]: Loop: 326765#L1148-2 assume !false; 337079#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 337077#L729-1 assume !false; 337075#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 337072#L569 assume !(0 == ~m_st~0); 337073#L573 assume !(0 == ~t1_st~0); 338464#L577 assume !(0 == ~t2_st~0); 338460#L581 assume !(0 == ~t3_st~0); 338461#L585 assume !(0 == ~t4_st~0); 338463#L589 assume !(0 == ~t5_st~0); 338458#L593 assume !(0 == ~t6_st~0); 338459#L597 assume !(0 == ~t7_st~0);exists_runnable_thread_~__retres1~8#1 := 0; 338462#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 338452#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 338453#L626 assume !(0 != eval_~tmp~0#1); 341000#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 340998#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 340996#L754-3 assume 0 == ~M_E~0;~M_E~0 := 1; 340994#L754-5 assume !(0 == ~T1_E~0); 340992#L759-3 assume !(0 == ~T2_E~0); 340990#L764-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 340987#L769-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 340973#L774-3 assume !(0 == ~T5_E~0); 340966#L779-3 assume !(0 == ~T6_E~0); 340959#L784-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 340952#L789-3 assume 0 == ~E_1~0;~E_1~0 := 1; 340945#L794-3 assume !(0 == ~E_2~0); 340937#L799-3 assume !(0 == ~E_3~0); 340930#L804-3 assume 0 == ~E_4~0;~E_4~0 := 1; 340922#L809-3 assume 0 == ~E_5~0;~E_5~0 := 1; 340915#L814-3 assume !(0 == ~E_6~0); 340908#L819-3 assume !(0 == ~E_7~0); 340901#L824-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 340887#L361-24 assume !(1 == ~m_pc~0); 340882#L361-26 is_master_triggered_~__retres1~0#1 := 0; 340877#L372-8 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 340873#is_master_triggered_returnLabel#9 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 340866#L930-24 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 340860#L930-26 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 337423#L380-24 assume 1 == ~t1_pc~0; 337421#L381-8 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 337422#L391-8 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 337429#is_transmit1_triggered_returnLabel#9 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 337412#L938-24 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 337410#L938-26 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 337408#L399-24 assume !(1 == ~t2_pc~0); 337406#L399-26 is_transmit2_triggered_~__retres1~2#1 := 0; 337404#L410-8 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 337402#is_transmit2_triggered_returnLabel#9 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 337399#L946-24 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 337397#L946-26 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 337395#L418-24 assume !(1 == ~t3_pc~0); 337393#L418-26 is_transmit3_triggered_~__retres1~3#1 := 0; 337390#L429-8 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 337388#is_transmit3_triggered_returnLabel#9 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 337386#L954-24 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 337384#L954-26 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 337382#L437-24 assume !(1 == ~t4_pc~0); 337380#L437-26 is_transmit4_triggered_~__retres1~4#1 := 0; 337378#L448-8 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 337375#is_transmit4_triggered_returnLabel#9 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 337373#L962-24 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 337371#L962-26 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 337369#L456-24 assume !(1 == ~t5_pc~0); 337367#L456-26 is_transmit5_triggered_~__retres1~5#1 := 0; 337364#L467-8 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 337363#is_transmit5_triggered_returnLabel#9 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 337362#L970-24 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 337361#L970-26 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 337360#L475-24 assume !(1 == ~t6_pc~0); 337358#L475-26 is_transmit6_triggered_~__retres1~6#1 := 0; 337355#L486-8 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 337353#is_transmit6_triggered_returnLabel#9 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 337351#L978-24 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 337349#L978-26 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 337347#L494-24 assume !(1 == ~t7_pc~0); 337196#L494-26 is_transmit7_triggered_~__retres1~7#1 := 0; 337188#L505-8 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 337184#is_transmit7_triggered_returnLabel#9 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 337182#L986-24 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 337180#L986-26 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 337178#L837-3 assume 1 == ~M_E~0;~M_E~0 := 2; 337175#L837-5 assume !(1 == ~T1_E~0); 337173#L842-3 assume !(1 == ~T2_E~0); 337170#L847-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 337168#L852-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 337166#L857-3 assume !(1 == ~T5_E~0); 337164#L862-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 337162#L867-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 337160#L872-3 assume 1 == ~E_1~0;~E_1~0 := 2; 337158#L877-3 assume !(1 == ~E_2~0); 337155#L882-3 assume 1 == ~E_3~0;~E_3~0 := 2; 337153#L887-3 assume 1 == ~E_4~0;~E_4~0 := 2; 337151#L892-3 assume 1 == ~E_5~0;~E_5~0 := 2; 337149#L897-3 assume !(1 == ~E_6~0); 337147#L902-3 assume !(1 == ~E_7~0); 337145#L907-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 337141#L569-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 337139#L611-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 337137#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret22#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret22#1;havoc start_simulation_#t~ret22#1; 337134#L1167 assume !(0 == start_simulation_~tmp~3#1); 337131#L1167-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 337128#L569-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 337125#L611-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 337123#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret21#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret21#1;havoc stop_simulation_#t~ret21#1; 337121#L1122 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 337119#L1129 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 337117#stop_simulation_returnLabel#1 start_simulation_#t~ret23#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret21#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret23#1;havoc start_simulation_#t~ret23#1; 337116#L1180 assume !(0 != start_simulation_~tmp___0~1#1); 326765#L1148-2 [2023-11-29 01:11:12,828 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:12,828 INFO L85 PathProgramCache]: Analyzing trace with hash 1968536774, now seen corresponding path program 5 times [2023-11-29 01:11:12,828 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:12,828 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [432305724] [2023-11-29 01:11:12,828 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:12,829 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:12,843 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:12,843 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:12,850 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:12,873 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:12,874 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:12,874 INFO L85 PathProgramCache]: Analyzing trace with hash -1932065556, now seen corresponding path program 1 times [2023-11-29 01:11:12,874 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:12,875 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1096160920] [2023-11-29 01:11:12,875 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:12,875 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:12,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:12,951 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:12,951 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:12,951 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1096160920] [2023-11-29 01:11:12,951 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1096160920] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:12,951 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:12,952 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 01:11:12,952 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1189514890] [2023-11-29 01:11:12,952 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:12,952 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 01:11:12,953 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:12,953 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 01:11:12,953 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 01:11:12,953 INFO L87 Difference]: Start difference. First operand 16832 states and 22833 transitions. cyclomatic complexity: 6017 Second operand has 5 states, 5 states have (on average 21.8) internal successors, (109), 5 states have internal predecessors, (109), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:13,212 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:13,212 INFO L93 Difference]: Finished difference Result 26062 states and 35014 transitions. [2023-11-29 01:11:13,212 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26062 states and 35014 transitions. [2023-11-29 01:11:13,303 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 25800 [2023-11-29 01:11:13,355 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26062 states to 26062 states and 35014 transitions. [2023-11-29 01:11:13,355 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26062 [2023-11-29 01:11:13,368 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26062 [2023-11-29 01:11:13,369 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26062 states and 35014 transitions. [2023-11-29 01:11:13,385 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:13,385 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26062 states and 35014 transitions. [2023-11-29 01:11:13,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26062 states and 35014 transitions. [2023-11-29 01:11:13,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26062 to 15906. [2023-11-29 01:11:13,516 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 15906 states, 15906 states have (on average 1.3440211241041116) internal successors, (21378), 15905 states have internal predecessors, (21378), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:13,541 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 15906 states to 15906 states and 21378 transitions. [2023-11-29 01:11:13,541 INFO L240 hiAutomatonCegarLoop]: Abstraction has 15906 states and 21378 transitions. [2023-11-29 01:11:13,541 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 01:11:13,542 INFO L428 stractBuchiCegarLoop]: Abstraction has 15906 states and 21378 transitions. [2023-11-29 01:11:13,542 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-29 01:11:13,542 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 15906 states and 21378 transitions. [2023-11-29 01:11:13,577 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 15692 [2023-11-29 01:11:13,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:13,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:13,578 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:13,578 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:13,578 INFO L748 eck$LassoCheckResult]: Stem: 369172#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 369173#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 369747#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 369748#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 369783#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 369767#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 369768#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 369321#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 369322#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 369392#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 369232#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 369233#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 369201#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 369202#L754 assume !(0 == ~M_E~0); 369803#L754-2 assume !(0 == ~T1_E~0); 369710#L759-1 assume !(0 == ~T2_E~0); 369568#L764-1 assume !(0 == ~T3_E~0); 369526#L769-1 assume !(0 == ~T4_E~0); 369527#L774-1 assume !(0 == ~T5_E~0); 369569#L779-1 assume !(0 == ~T6_E~0); 369719#L784-1 assume !(0 == ~T7_E~0); 369523#L789-1 assume !(0 == ~E_1~0); 369524#L794-1 assume !(0 == ~E_2~0); 369618#L799-1 assume !(0 == ~E_3~0); 369534#L804-1 assume !(0 == ~E_4~0); 369535#L809-1 assume !(0 == ~E_5~0); 369563#L814-1 assume !(0 == ~E_6~0); 368978#L819-1 assume !(0 == ~E_7~0); 368979#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 369230#L361 assume !(1 == ~m_pc~0); 369231#L361-2 is_master_triggered_~__retres1~0#1 := 0; 369743#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 369696#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 369697#L930 assume !(0 != activate_threads_~tmp~1#1); 369436#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 369224#L380 assume !(1 == ~t1_pc~0); 369225#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 369780#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 369781#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 369830#L938 assume !(0 != activate_threads_~tmp___0~0#1); 369651#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 369626#L399 assume !(1 == ~t2_pc~0); 369142#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 369143#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 369302#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 369295#L946 assume !(0 != activate_threads_~tmp___1~0#1); 369296#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 368986#L418 assume !(1 == ~t3_pc~0); 368965#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 368966#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 368976#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 368977#L954 assume !(0 != activate_threads_~tmp___2~0#1); 369549#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 369550#L437 assume !(1 == ~t4_pc~0); 369769#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 369690#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 369055#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 369056#L962 assume !(0 != activate_threads_~tmp___3~0#1); 369349#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 369669#L456 assume !(1 == ~t5_pc~0); 369156#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 369155#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 369700#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 369601#L970 assume !(0 != activate_threads_~tmp___4~0#1); 369602#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 369050#L475 assume !(1 == ~t6_pc~0); 369051#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 369092#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 369093#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 369288#L978 assume !(0 != activate_threads_~tmp___5~0#1); 369540#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 369541#L494 assume !(1 == ~t7_pc~0); 369272#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 369273#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 369494#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 369570#L986 assume !(0 != activate_threads_~tmp___6~0#1); 369571#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 369792#L837 assume !(1 == ~M_E~0); 369746#L837-2 assume !(1 == ~T1_E~0); 369622#L842-1 assume !(1 == ~T2_E~0); 369357#L847-1 assume !(1 == ~T3_E~0); 369358#L852-1 assume !(1 == ~T4_E~0); 369425#L857-1 assume !(1 == ~T5_E~0); 369308#L862-1 assume !(1 == ~T6_E~0); 369309#L867-1 assume !(1 == ~T7_E~0); 369317#L872-1 assume !(1 == ~E_1~0); 369391#L877-1 assume !(1 == ~E_2~0); 369587#L882-1 assume !(1 == ~E_3~0); 369751#L887-1 assume !(1 == ~E_4~0); 369646#L892-1 assume !(1 == ~E_5~0); 369647#L897-1 assume !(1 == ~E_6~0); 369332#L902-1 assume !(1 == ~E_7~0); 369333#L907-1 assume { :end_inline_reset_delta_events } true; 369668#L1148-2 assume !false; 370922#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 370920#L729-1 [2023-11-29 01:11:13,579 INFO L750 eck$LassoCheckResult]: Loop: 370920#L729-1 assume !false; 370917#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 370914#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 370912#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 370910#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 370908#L626 assume 0 != eval_~tmp~0#1; 370905#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 370902#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 370900#L634-2 havoc eval_~tmp_ndt_1~0#1; 370611#L631-1 assume !(0 == ~t1_st~0); 370607#L645-1 assume !(0 == ~t2_st~0); 370603#L659-1 assume !(0 == ~t3_st~0); 370600#L673-1 assume !(0 == ~t4_st~0); 370601#L687-1 assume !(0 == ~t5_st~0); 370928#L701-1 assume !(0 == ~t6_st~0); 370924#L715-1 assume !(0 == ~t7_st~0); 370920#L729-1 [2023-11-29 01:11:13,579 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:13,579 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 1 times [2023-11-29 01:11:13,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:13,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1091472863] [2023-11-29 01:11:13,580 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:13,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:13,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:13,593 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:13,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:13,618 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:13,618 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:13,619 INFO L85 PathProgramCache]: Analyzing trace with hash -1739844173, now seen corresponding path program 1 times [2023-11-29 01:11:13,619 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:13,619 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [623998778] [2023-11-29 01:11:13,619 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:13,619 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:13,622 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:13,622 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:13,624 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:13,626 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:13,626 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:13,626 INFO L85 PathProgramCache]: Analyzing trace with hash 729268538, now seen corresponding path program 1 times [2023-11-29 01:11:13,627 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:13,627 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1028331184] [2023-11-29 01:11:13,627 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:13,627 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:13,636 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:13,664 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:13,664 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:13,664 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1028331184] [2023-11-29 01:11:13,665 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1028331184] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:13,665 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:13,665 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:13,665 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701594005] [2023-11-29 01:11:13,665 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:13,778 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:13,779 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:13,779 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:13,779 INFO L87 Difference]: Start difference. First operand 15906 states and 21378 transitions. cyclomatic complexity: 5496 Second operand has 3 states, 3 states have (on average 37.0) internal successors, (111), 3 states have internal predecessors, (111), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:13,892 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:13,892 INFO L93 Difference]: Finished difference Result 30126 states and 40221 transitions. [2023-11-29 01:11:13,892 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 30126 states and 40221 transitions. [2023-11-29 01:11:13,986 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 29704 [2023-11-29 01:11:14,046 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 30126 states to 30126 states and 40221 transitions. [2023-11-29 01:11:14,046 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 30126 [2023-11-29 01:11:14,061 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 30126 [2023-11-29 01:11:14,061 INFO L73 IsDeterministic]: Start isDeterministic. Operand 30126 states and 40221 transitions. [2023-11-29 01:11:14,073 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:14,073 INFO L218 hiAutomatonCegarLoop]: Abstraction has 30126 states and 40221 transitions. [2023-11-29 01:11:14,088 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 30126 states and 40221 transitions. [2023-11-29 01:11:14,247 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 30126 to 28702. [2023-11-29 01:11:14,265 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28702 states, 28702 states have (on average 1.3372238868371542) internal successors, (38381), 28701 states have internal predecessors, (38381), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:14,313 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28702 states to 28702 states and 38381 transitions. [2023-11-29 01:11:14,313 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28702 states and 38381 transitions. [2023-11-29 01:11:14,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:14,314 INFO L428 stractBuchiCegarLoop]: Abstraction has 28702 states and 38381 transitions. [2023-11-29 01:11:14,314 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-29 01:11:14,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28702 states and 38381 transitions. [2023-11-29 01:11:14,422 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28280 [2023-11-29 01:11:14,422 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:14,422 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:14,423 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:14,423 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:14,423 INFO L748 eck$LassoCheckResult]: Stem: 415214#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 415215#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 415820#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 415821#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 415871#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 415848#L521-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 415849#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 419567#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 419566#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 419565#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 419564#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 419563#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 419562#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 419561#L754 assume !(0 == ~M_E~0); 419560#L754-2 assume !(0 == ~T1_E~0); 419559#L759-1 assume !(0 == ~T2_E~0); 419558#L764-1 assume !(0 == ~T3_E~0); 419557#L769-1 assume !(0 == ~T4_E~0); 419556#L774-1 assume !(0 == ~T5_E~0); 419555#L779-1 assume !(0 == ~T6_E~0); 419554#L784-1 assume !(0 == ~T7_E~0); 419553#L789-1 assume !(0 == ~E_1~0); 419552#L794-1 assume !(0 == ~E_2~0); 419551#L799-1 assume !(0 == ~E_3~0); 419550#L804-1 assume !(0 == ~E_4~0); 419549#L809-1 assume !(0 == ~E_5~0); 419548#L814-1 assume !(0 == ~E_6~0); 419547#L819-1 assume !(0 == ~E_7~0); 419546#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 419545#L361 assume !(1 == ~m_pc~0); 419544#L361-2 is_master_triggered_~__retres1~0#1 := 0; 419543#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 419542#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 419541#L930 assume !(0 != activate_threads_~tmp~1#1); 419540#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 419539#L380 assume !(1 == ~t1_pc~0); 419536#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 419535#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 419534#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 419533#L938 assume !(0 != activate_threads_~tmp___0~0#1); 419531#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 419530#L399 assume !(1 == ~t2_pc~0); 419529#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 419528#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 419527#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 419526#L946 assume !(0 != activate_threads_~tmp___1~0#1); 419525#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 419524#L418 assume !(1 == ~t3_pc~0); 419522#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 419521#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 419520#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 419519#L954 assume !(0 != activate_threads_~tmp___2~0#1); 419518#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 419517#L437 assume !(1 == ~t4_pc~0); 419516#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 419515#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 419514#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 419513#L962 assume !(0 != activate_threads_~tmp___3~0#1); 419512#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 419511#L456 assume !(1 == ~t5_pc~0); 419509#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 419508#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 419507#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 419506#L970 assume !(0 != activate_threads_~tmp___4~0#1); 419505#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 419504#L475 assume !(1 == ~t6_pc~0); 419503#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 419502#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 419501#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 419500#L978 assume !(0 != activate_threads_~tmp___5~0#1); 419499#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 419498#L494 assume !(1 == ~t7_pc~0); 419496#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 419495#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 419494#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 419493#L986 assume !(0 != activate_threads_~tmp___6~0#1); 419492#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 419491#L837 assume !(1 == ~M_E~0); 419490#L837-2 assume !(1 == ~T1_E~0); 419489#L842-1 assume !(1 == ~T2_E~0); 419488#L847-1 assume !(1 == ~T3_E~0); 419487#L852-1 assume !(1 == ~T4_E~0); 419486#L857-1 assume !(1 == ~T5_E~0); 419485#L862-1 assume !(1 == ~T6_E~0); 419484#L867-1 assume !(1 == ~T7_E~0); 419483#L872-1 assume !(1 == ~E_1~0); 419482#L877-1 assume !(1 == ~E_2~0); 419481#L882-1 assume !(1 == ~E_3~0); 419480#L887-1 assume !(1 == ~E_4~0); 419479#L892-1 assume !(1 == ~E_5~0); 419477#L897-1 assume !(1 == ~E_6~0); 419475#L902-1 assume !(1 == ~E_7~0); 419473#L907-1 assume { :end_inline_reset_delta_events } true; 419472#L1148-2 assume !false; 419216#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 419215#L729-1 [2023-11-29 01:11:14,424 INFO L750 eck$LassoCheckResult]: Loop: 419215#L729-1 assume !false; 419214#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 419212#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 419211#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 419210#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 419209#L626 assume 0 != eval_~tmp~0#1; 419207#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 419205#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 419206#L634-2 havoc eval_~tmp_ndt_1~0#1; 419248#L631-1 assume !(0 == ~t1_st~0); 419244#L645-1 assume !(0 == ~t2_st~0); 419240#L659-1 assume !(0 == ~t3_st~0); 419230#L673-1 assume !(0 == ~t4_st~0); 419227#L687-1 assume !(0 == ~t5_st~0); 419223#L701-1 assume !(0 == ~t6_st~0); 419218#L715-1 assume !(0 == ~t7_st~0); 419215#L729-1 [2023-11-29 01:11:14,424 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:14,424 INFO L85 PathProgramCache]: Analyzing trace with hash -439660602, now seen corresponding path program 1 times [2023-11-29 01:11:14,424 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:14,424 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175781648] [2023-11-29 01:11:14,424 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:14,424 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:14,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:14,458 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:14,458 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:14,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175781648] [2023-11-29 01:11:14,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [175781648] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:14,458 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:14,459 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:14,459 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1178806879] [2023-11-29 01:11:14,459 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:14,459 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 01:11:14,460 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:14,460 INFO L85 PathProgramCache]: Analyzing trace with hash -1739844173, now seen corresponding path program 2 times [2023-11-29 01:11:14,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:14,460 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1209138142] [2023-11-29 01:11:14,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:14,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:14,464 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:14,464 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:14,466 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:14,469 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:14,574 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:14,574 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:14,574 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:14,574 INFO L87 Difference]: Start difference. First operand 28702 states and 38381 transitions. cyclomatic complexity: 9703 Second operand has 3 states, 3 states have (on average 31.666666666666668) internal successors, (95), 3 states have internal predecessors, (95), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:14,670 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:14,670 INFO L93 Difference]: Finished difference Result 28606 states and 38253 transitions. [2023-11-29 01:11:14,670 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28606 states and 38253 transitions. [2023-11-29 01:11:14,778 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28280 [2023-11-29 01:11:14,838 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28606 states to 28606 states and 38253 transitions. [2023-11-29 01:11:14,838 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28606 [2023-11-29 01:11:14,853 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28606 [2023-11-29 01:11:14,853 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28606 states and 38253 transitions. [2023-11-29 01:11:14,865 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:14,865 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28606 states and 38253 transitions. [2023-11-29 01:11:14,879 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28606 states and 38253 transitions. [2023-11-29 01:11:15,043 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28606 to 28606. [2023-11-29 01:11:15,060 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28606 states, 28606 states have (on average 1.3372369432986086) internal successors, (38253), 28605 states have internal predecessors, (38253), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:15,109 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28606 states to 28606 states and 38253 transitions. [2023-11-29 01:11:15,109 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28606 states and 38253 transitions. [2023-11-29 01:11:15,109 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:15,110 INFO L428 stractBuchiCegarLoop]: Abstraction has 28606 states and 38253 transitions. [2023-11-29 01:11:15,110 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-29 01:11:15,110 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28606 states and 38253 transitions. [2023-11-29 01:11:15,179 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 28280 [2023-11-29 01:11:15,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:15,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:15,180 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:15,180 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:15,180 INFO L748 eck$LassoCheckResult]: Stem: 472526#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 472527#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 473135#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 473136#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 473177#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 473163#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 473164#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 472678#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 472679#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 472754#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 472587#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 472588#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 472555#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 472556#L754 assume !(0 == ~M_E~0); 473192#L754-2 assume !(0 == ~T1_E~0); 473083#L759-1 assume !(0 == ~T2_E~0); 472946#L764-1 assume !(0 == ~T3_E~0); 472900#L769-1 assume !(0 == ~T4_E~0); 472901#L774-1 assume !(0 == ~T5_E~0); 472947#L779-1 assume !(0 == ~T6_E~0); 473096#L784-1 assume !(0 == ~T7_E~0); 472897#L789-1 assume !(0 == ~E_1~0); 472898#L794-1 assume !(0 == ~E_2~0); 472996#L799-1 assume !(0 == ~E_3~0); 472909#L804-1 assume !(0 == ~E_4~0); 472910#L809-1 assume !(0 == ~E_5~0); 472941#L814-1 assume !(0 == ~E_6~0); 472335#L819-1 assume !(0 == ~E_7~0); 472336#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 472584#L361 assume !(1 == ~m_pc~0); 472585#L361-2 is_master_triggered_~__retres1~0#1 := 0; 473130#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 473069#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 473070#L930 assume !(0 != activate_threads_~tmp~1#1); 472802#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 472578#L380 assume !(1 == ~t1_pc~0); 472579#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 473172#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 473173#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 473217#L938 assume !(0 != activate_threads_~tmp___0~0#1); 473025#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 473005#L399 assume !(1 == ~t2_pc~0); 472496#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 472497#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 472657#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 472650#L946 assume !(0 != activate_threads_~tmp___1~0#1); 472651#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 472339#L418 assume !(1 == ~t3_pc~0); 472319#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 472320#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 472329#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 472330#L954 assume !(0 != activate_threads_~tmp___2~0#1); 472926#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 472927#L437 assume !(1 == ~t4_pc~0); 473165#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 473063#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 472409#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 472410#L962 assume !(0 != activate_threads_~tmp___3~0#1); 472708#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 473049#L456 assume !(1 == ~t5_pc~0); 472510#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 472509#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 473073#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 472984#L970 assume !(0 != activate_threads_~tmp___4~0#1); 472985#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 472404#L475 assume !(1 == ~t6_pc~0); 472405#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 472445#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 472446#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 472643#L978 assume !(0 != activate_threads_~tmp___5~0#1); 472914#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 472915#L494 assume !(1 == ~t7_pc~0); 472627#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 472628#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 472867#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 472948#L986 assume !(0 != activate_threads_~tmp___6~0#1); 472949#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 473187#L837 assume !(1 == ~M_E~0); 473134#L837-2 assume !(1 == ~T1_E~0); 473001#L842-1 assume !(1 == ~T2_E~0); 472716#L847-1 assume !(1 == ~T3_E~0); 472717#L852-1 assume !(1 == ~T4_E~0); 472792#L857-1 assume !(1 == ~T5_E~0); 472664#L862-1 assume !(1 == ~T6_E~0); 472665#L867-1 assume !(1 == ~T7_E~0); 472674#L872-1 assume !(1 == ~E_1~0); 472753#L877-1 assume !(1 == ~E_2~0); 472964#L882-1 assume !(1 == ~E_3~0); 473140#L887-1 assume !(1 == ~E_4~0); 473020#L892-1 assume !(1 == ~E_5~0); 473021#L897-1 assume !(1 == ~E_6~0); 472691#L902-1 assume !(1 == ~E_7~0); 472692#L907-1 assume { :end_inline_reset_delta_events } true; 473043#L1148-2 assume !false; 493718#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 493713#L729-1 [2023-11-29 01:11:15,180 INFO L750 eck$LassoCheckResult]: Loop: 493713#L729-1 assume !false; 493705#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 493700#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 493638#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 493630#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 493625#L626 assume 0 != eval_~tmp~0#1; 493620#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 473212#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 473214#L634-2 havoc eval_~tmp_ndt_1~0#1; 476254#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 476251#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 476249#L648-2 havoc eval_~tmp_ndt_2~0#1; 475781#L645-1 assume !(0 == ~t2_st~0); 475777#L659-1 assume !(0 == ~t3_st~0); 475772#L673-1 assume !(0 == ~t4_st~0); 475773#L687-1 assume !(0 == ~t5_st~0); 492523#L701-1 assume !(0 == ~t6_st~0); 492524#L715-1 assume !(0 == ~t7_st~0); 493713#L729-1 [2023-11-29 01:11:15,181 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:15,181 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 2 times [2023-11-29 01:11:15,181 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:15,181 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993210706] [2023-11-29 01:11:15,181 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:15,181 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:15,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:15,193 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:15,202 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:15,229 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:15,229 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:15,229 INFO L85 PathProgramCache]: Analyzing trace with hash 230138997, now seen corresponding path program 1 times [2023-11-29 01:11:15,230 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:15,230 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [867929049] [2023-11-29 01:11:15,230 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:15,230 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:15,233 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:15,234 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:15,236 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:15,238 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:15,238 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:15,239 INFO L85 PathProgramCache]: Analyzing trace with hash -2069460420, now seen corresponding path program 1 times [2023-11-29 01:11:15,239 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:15,239 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414787058] [2023-11-29 01:11:15,239 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:15,239 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:15,252 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:15,289 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:15,289 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:15,290 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414787058] [2023-11-29 01:11:15,290 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414787058] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:15,290 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:15,290 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:15,290 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [760761283] [2023-11-29 01:11:15,290 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:15,401 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:15,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:15,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:15,401 INFO L87 Difference]: Start difference. First operand 28606 states and 38253 transitions. cyclomatic complexity: 9671 Second operand has 3 states, 3 states have (on average 37.666666666666664) internal successors, (113), 3 states have internal predecessors, (113), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:15,566 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:15,566 INFO L93 Difference]: Finished difference Result 38374 states and 51041 transitions. [2023-11-29 01:11:15,567 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 38374 states and 51041 transitions. [2023-11-29 01:11:15,713 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 37968 [2023-11-29 01:11:15,792 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 38374 states to 38374 states and 51041 transitions. [2023-11-29 01:11:15,792 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 38374 [2023-11-29 01:11:15,811 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 38374 [2023-11-29 01:11:15,811 INFO L73 IsDeterministic]: Start isDeterministic. Operand 38374 states and 51041 transitions. [2023-11-29 01:11:15,826 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:15,826 INFO L218 hiAutomatonCegarLoop]: Abstraction has 38374 states and 51041 transitions. [2023-11-29 01:11:15,845 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 38374 states and 51041 transitions. [2023-11-29 01:11:16,068 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 38374 to 37158. [2023-11-29 01:11:16,091 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37158 states, 37158 states have (on average 1.3309919801926906) internal successors, (49457), 37157 states have internal predecessors, (49457), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:16,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37158 states to 37158 states and 49457 transitions. [2023-11-29 01:11:16,321 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37158 states and 49457 transitions. [2023-11-29 01:11:16,334 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:16,340 INFO L428 stractBuchiCegarLoop]: Abstraction has 37158 states and 49457 transitions. [2023-11-29 01:11:16,341 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-29 01:11:16,351 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37158 states and 49457 transitions. [2023-11-29 01:11:16,527 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 36752 [2023-11-29 01:11:16,527 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:16,527 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:16,528 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:16,529 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:16,529 INFO L748 eck$LassoCheckResult]: Stem: 539512#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 539513#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 540132#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 540133#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 540178#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 540158#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 540159#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 539665#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 539666#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 539739#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 539574#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 539575#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 539543#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 539544#L754 assume !(0 == ~M_E~0); 540198#L754-2 assume !(0 == ~T1_E~0); 540079#L759-1 assume !(0 == ~T2_E~0); 539928#L764-1 assume !(0 == ~T3_E~0); 539882#L769-1 assume !(0 == ~T4_E~0); 539883#L774-1 assume !(0 == ~T5_E~0); 539929#L779-1 assume !(0 == ~T6_E~0); 540089#L784-1 assume !(0 == ~T7_E~0); 539879#L789-1 assume !(0 == ~E_1~0); 539880#L794-1 assume !(0 == ~E_2~0); 539980#L799-1 assume !(0 == ~E_3~0); 539891#L804-1 assume !(0 == ~E_4~0); 539892#L809-1 assume !(0 == ~E_5~0); 539923#L814-1 assume !(0 == ~E_6~0); 539321#L819-1 assume !(0 == ~E_7~0); 539322#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 539571#L361 assume !(1 == ~m_pc~0); 539572#L361-2 is_master_triggered_~__retres1~0#1 := 0; 540124#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 540064#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 540065#L930 assume !(0 != activate_threads_~tmp~1#1); 539786#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 539565#L380 assume !(1 == ~t1_pc~0); 539566#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 540174#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 540175#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 540236#L938 assume !(0 != activate_threads_~tmp___0~0#1); 540016#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 539992#L399 assume !(1 == ~t2_pc~0); 539483#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 539484#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 539645#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 539638#L946 assume !(0 != activate_threads_~tmp___1~0#1); 539639#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 539327#L418 assume !(1 == ~t3_pc~0); 539307#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 539308#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 539317#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 539318#L954 assume !(0 != activate_threads_~tmp___2~0#1); 539907#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 539908#L437 assume !(1 == ~t4_pc~0); 540160#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 540059#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 539398#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 539399#L962 assume !(0 != activate_threads_~tmp___3~0#1); 539696#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 540043#L456 assume !(1 == ~t5_pc~0); 539498#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 539497#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 540070#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 539965#L970 assume !(0 != activate_threads_~tmp___4~0#1); 539966#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 539393#L475 assume !(1 == ~t6_pc~0); 539394#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 539434#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 539435#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 539631#L978 assume !(0 != activate_threads_~tmp___5~0#1); 539897#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 539898#L494 assume !(1 == ~t7_pc~0); 539615#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 539616#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 539849#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 539930#L986 assume !(0 != activate_threads_~tmp___6~0#1); 539931#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 540188#L837 assume !(1 == ~M_E~0); 540131#L837-2 assume !(1 == ~T1_E~0); 539988#L842-1 assume !(1 == ~T2_E~0); 539705#L847-1 assume !(1 == ~T3_E~0); 539706#L852-1 assume !(1 == ~T4_E~0); 539775#L857-1 assume !(1 == ~T5_E~0); 539651#L862-1 assume !(1 == ~T6_E~0); 539652#L867-1 assume !(1 == ~T7_E~0); 539660#L872-1 assume !(1 == ~E_1~0); 539738#L877-1 assume !(1 == ~E_2~0); 539947#L882-1 assume !(1 == ~E_3~0); 540139#L887-1 assume !(1 == ~E_4~0); 540008#L892-1 assume !(1 == ~E_5~0); 540009#L897-1 assume !(1 == ~E_6~0); 539678#L902-1 assume !(1 == ~E_7~0); 539679#L907-1 assume { :end_inline_reset_delta_events } true; 540037#L1148-2 assume !false; 551275#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 551273#L729-1 [2023-11-29 01:11:16,530 INFO L750 eck$LassoCheckResult]: Loop: 551273#L729-1 assume !false; 551271#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 551268#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 551265#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 551263#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 551261#L626 assume 0 != eval_~tmp~0#1; 551258#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 551255#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 551253#L634-2 havoc eval_~tmp_ndt_1~0#1; 551251#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 551248#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 551246#L648-2 havoc eval_~tmp_ndt_2~0#1; 551244#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 551241#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 551238#L662-2 havoc eval_~tmp_ndt_3~0#1; 551235#L659-1 assume !(0 == ~t3_st~0); 551231#L673-1 assume !(0 == ~t4_st~0); 551232#L687-1 assume !(0 == ~t5_st~0); 551281#L701-1 assume !(0 == ~t6_st~0); 551277#L715-1 assume !(0 == ~t7_st~0); 551273#L729-1 [2023-11-29 01:11:16,531 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:16,531 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 3 times [2023-11-29 01:11:16,531 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:16,531 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1529260853] [2023-11-29 01:11:16,531 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:16,531 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:16,543 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:16,543 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:16,548 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:16,569 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:16,569 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:16,569 INFO L85 PathProgramCache]: Analyzing trace with hash -2126794573, now seen corresponding path program 1 times [2023-11-29 01:11:16,570 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:16,570 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [267380501] [2023-11-29 01:11:16,570 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:16,570 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:16,574 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:16,574 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:16,576 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:16,578 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:16,579 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:16,579 INFO L85 PathProgramCache]: Analyzing trace with hash -133676870, now seen corresponding path program 1 times [2023-11-29 01:11:16,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:16,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [897796749] [2023-11-29 01:11:16,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:16,580 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:16,593 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:16,628 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:16,628 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:16,628 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [897796749] [2023-11-29 01:11:16,629 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [897796749] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:16,629 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:16,629 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:16,629 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2133308889] [2023-11-29 01:11:16,629 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:16,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:16,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:16,762 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:16,762 INFO L87 Difference]: Start difference. First operand 37158 states and 49457 transitions. cyclomatic complexity: 12323 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:17,031 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:17,032 INFO L93 Difference]: Finished difference Result 69846 states and 92717 transitions. [2023-11-29 01:11:17,032 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 69846 states and 92717 transitions. [2023-11-29 01:11:17,343 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 69136 [2023-11-29 01:11:17,529 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 69846 states to 69846 states and 92717 transitions. [2023-11-29 01:11:17,529 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 69846 [2023-11-29 01:11:17,570 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 69846 [2023-11-29 01:11:17,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 69846 states and 92717 transitions. [2023-11-29 01:11:17,611 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:17,612 INFO L218 hiAutomatonCegarLoop]: Abstraction has 69846 states and 92717 transitions. [2023-11-29 01:11:17,658 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 69846 states and 92717 transitions. [2023-11-29 01:11:18,417 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 69846 to 66870. [2023-11-29 01:11:18,452 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 66870 states, 66870 states have (on average 1.3298190518917303) internal successors, (88925), 66869 states have internal predecessors, (88925), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:18,584 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 66870 states to 66870 states and 88925 transitions. [2023-11-29 01:11:18,584 INFO L240 hiAutomatonCegarLoop]: Abstraction has 66870 states and 88925 transitions. [2023-11-29 01:11:18,585 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:18,586 INFO L428 stractBuchiCegarLoop]: Abstraction has 66870 states and 88925 transitions. [2023-11-29 01:11:18,586 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-29 01:11:18,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 66870 states and 88925 transitions. [2023-11-29 01:11:18,753 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 66160 [2023-11-29 01:11:18,753 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:18,753 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:18,754 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:18,754 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:18,754 INFO L748 eck$LassoCheckResult]: Stem: 646529#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 646530#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 647149#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 647150#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 647206#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 647181#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 647182#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 646684#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 646685#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 646758#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 646591#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 646592#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 646560#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 646561#L754 assume !(0 == ~M_E~0); 647225#L754-2 assume !(0 == ~T1_E~0); 647097#L759-1 assume !(0 == ~T2_E~0); 646940#L764-1 assume !(0 == ~T3_E~0); 646897#L769-1 assume !(0 == ~T4_E~0); 646898#L774-1 assume !(0 == ~T5_E~0); 646941#L779-1 assume !(0 == ~T6_E~0); 647107#L784-1 assume !(0 == ~T7_E~0); 646894#L789-1 assume !(0 == ~E_1~0); 646895#L794-1 assume !(0 == ~E_2~0); 646988#L799-1 assume !(0 == ~E_3~0); 646906#L804-1 assume !(0 == ~E_4~0); 646907#L809-1 assume !(0 == ~E_5~0); 646934#L814-1 assume !(0 == ~E_6~0); 646332#L819-1 assume !(0 == ~E_7~0); 646333#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 646589#L361 assume !(1 == ~m_pc~0); 646590#L361-2 is_master_triggered_~__retres1~0#1 := 0; 647143#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 647082#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 647083#L930 assume !(0 != activate_threads_~tmp~1#1); 646806#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 646583#L380 assume !(1 == ~t1_pc~0); 646584#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 647201#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 647202#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 647260#L938 assume !(0 != activate_threads_~tmp___0~0#1); 647033#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 647004#L399 assume !(1 == ~t2_pc~0); 646499#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 646500#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 646664#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 646657#L946 assume !(0 != activate_threads_~tmp___1~0#1); 646658#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 646340#L418 assume !(1 == ~t3_pc~0); 646319#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 646320#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 646330#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 646331#L954 assume !(0 != activate_threads_~tmp___2~0#1); 646922#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 646923#L437 assume !(1 == ~t4_pc~0); 647183#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 647077#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 646412#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 646413#L962 assume !(0 != activate_threads_~tmp___3~0#1); 646715#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 647057#L456 assume !(1 == ~t5_pc~0); 646515#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 646514#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 647087#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 646972#L970 assume !(0 != activate_threads_~tmp___4~0#1); 646973#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 646407#L475 assume !(1 == ~t6_pc~0); 646408#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 646450#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 646451#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 646649#L978 assume !(0 != activate_threads_~tmp___5~0#1); 646912#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 646913#L494 assume !(1 == ~t7_pc~0); 646633#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 646634#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 646867#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 646942#L986 assume !(0 != activate_threads_~tmp___6~0#1); 646943#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 647215#L837 assume !(1 == ~M_E~0); 647148#L837-2 assume !(1 == ~T1_E~0); 646999#L842-1 assume !(1 == ~T2_E~0); 646724#L847-1 assume !(1 == ~T3_E~0); 646725#L852-1 assume !(1 == ~T4_E~0); 646795#L857-1 assume !(1 == ~T5_E~0); 646671#L862-1 assume !(1 == ~T6_E~0); 646672#L867-1 assume !(1 == ~T7_E~0); 646680#L872-1 assume !(1 == ~E_1~0); 646757#L877-1 assume !(1 == ~E_2~0); 646956#L882-1 assume !(1 == ~E_3~0); 647160#L887-1 assume !(1 == ~E_4~0); 647025#L892-1 assume !(1 == ~E_5~0); 647026#L897-1 assume !(1 == ~E_6~0); 646696#L902-1 assume !(1 == ~E_7~0); 646697#L907-1 assume { :end_inline_reset_delta_events } true; 647056#L1148-2 assume !false; 651418#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 651416#L729-1 [2023-11-29 01:11:18,754 INFO L750 eck$LassoCheckResult]: Loop: 651416#L729-1 assume !false; 651414#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 651410#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 651409#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 651405#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 651401#L626 assume 0 != eval_~tmp~0#1; 651396#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 651393#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 651391#L634-2 havoc eval_~tmp_ndt_1~0#1; 651388#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 651356#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 651385#L648-2 havoc eval_~tmp_ndt_2~0#1; 651838#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 651835#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 651833#L662-2 havoc eval_~tmp_ndt_3~0#1; 651829#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 651826#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 651824#L676-2 havoc eval_~tmp_ndt_4~0#1; 651820#L673-1 assume !(0 == ~t4_st~0); 651821#L687-1 assume !(0 == ~t5_st~0); 655056#L701-1 assume !(0 == ~t6_st~0); 651420#L715-1 assume !(0 == ~t7_st~0); 651416#L729-1 [2023-11-29 01:11:18,754 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:18,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 4 times [2023-11-29 01:11:18,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:18,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [191222397] [2023-11-29 01:11:18,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:18,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:18,767 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:18,767 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:18,776 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:18,804 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:18,805 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:18,805 INFO L85 PathProgramCache]: Analyzing trace with hash 833736693, now seen corresponding path program 1 times [2023-11-29 01:11:18,805 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:18,805 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [516594894] [2023-11-29 01:11:18,805 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:18,805 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:18,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:18,810 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:18,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:18,815 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:18,815 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:18,816 INFO L85 PathProgramCache]: Analyzing trace with hash 664435260, now seen corresponding path program 1 times [2023-11-29 01:11:18,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:18,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [76866553] [2023-11-29 01:11:18,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:18,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:18,829 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:19,016 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:19,016 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:19,016 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [76866553] [2023-11-29 01:11:19,016 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [76866553] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:19,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:19,017 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:19,017 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1190566965] [2023-11-29 01:11:19,017 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:19,139 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:19,139 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:19,139 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:19,139 INFO L87 Difference]: Start difference. First operand 66870 states and 88925 transitions. cyclomatic complexity: 22079 Second operand has 3 states, 3 states have (on average 39.0) internal successors, (117), 3 states have internal predecessors, (117), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:19,490 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:19,490 INFO L93 Difference]: Finished difference Result 91642 states and 121597 transitions. [2023-11-29 01:11:19,490 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 91642 states and 121597 transitions. [2023-11-29 01:11:20,011 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 90724 [2023-11-29 01:11:20,242 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 91642 states to 91642 states and 121597 transitions. [2023-11-29 01:11:20,242 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 91642 [2023-11-29 01:11:20,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 91642 [2023-11-29 01:11:20,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 91642 states and 121597 transitions. [2023-11-29 01:11:20,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:20,337 INFO L218 hiAutomatonCegarLoop]: Abstraction has 91642 states and 121597 transitions. [2023-11-29 01:11:20,390 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 91642 states and 121597 transitions. [2023-11-29 01:11:21,140 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 91642 to 89290. [2023-11-29 01:11:21,189 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 89290 states, 89290 states have (on average 1.3284914324112442) internal successors, (118621), 89289 states have internal predecessors, (118621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:21,357 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 89290 states to 89290 states and 118621 transitions. [2023-11-29 01:11:21,357 INFO L240 hiAutomatonCegarLoop]: Abstraction has 89290 states and 118621 transitions. [2023-11-29 01:11:21,358 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:21,358 INFO L428 stractBuchiCegarLoop]: Abstraction has 89290 states and 118621 transitions. [2023-11-29 01:11:21,358 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-29 01:11:21,358 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 89290 states and 118621 transitions. [2023-11-29 01:11:21,736 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 88372 [2023-11-29 01:11:21,736 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:21,737 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:21,737 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:21,738 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:21,738 INFO L748 eck$LassoCheckResult]: Stem: 805052#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 805053#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 805695#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 805696#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 805756#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 805727#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 805728#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 805211#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 805212#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 805290#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 805117#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 805118#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 805085#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 805086#L754 assume !(0 == ~M_E~0); 805777#L754-2 assume !(0 == ~T1_E~0); 805640#L759-1 assume !(0 == ~T2_E~0); 805485#L764-1 assume !(0 == ~T3_E~0); 805443#L769-1 assume !(0 == ~T4_E~0); 805444#L774-1 assume !(0 == ~T5_E~0); 805486#L779-1 assume !(0 == ~T6_E~0); 805651#L784-1 assume !(0 == ~T7_E~0); 805441#L789-1 assume !(0 == ~E_1~0); 805442#L794-1 assume !(0 == ~E_2~0); 805537#L799-1 assume !(0 == ~E_3~0); 805451#L804-1 assume !(0 == ~E_4~0); 805452#L809-1 assume !(0 == ~E_5~0); 805480#L814-1 assume !(0 == ~E_6~0); 804853#L819-1 assume !(0 == ~E_7~0); 804854#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 805114#L361 assume !(1 == ~m_pc~0); 805115#L361-2 is_master_triggered_~__retres1~0#1 := 0; 805686#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 805625#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 805626#L930 assume !(0 != activate_threads_~tmp~1#1); 805343#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 805108#L380 assume !(1 == ~t1_pc~0); 805109#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 805818#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 804872#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 804873#L938 assume !(0 != activate_threads_~tmp___0~0#1); 805577#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 805548#L399 assume !(1 == ~t2_pc~0); 805019#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 805020#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 805189#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 805183#L946 assume !(0 != activate_threads_~tmp___1~0#1); 805184#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 804859#L418 assume !(1 == ~t3_pc~0); 804839#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 804840#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 804849#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 804850#L954 assume !(0 != activate_threads_~tmp___2~0#1); 805467#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 805468#L437 assume !(1 == ~t4_pc~0); 805729#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 805619#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 804931#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 804932#L962 assume !(0 != activate_threads_~tmp___3~0#1); 805242#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 805599#L456 assume !(1 == ~t5_pc~0); 805035#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 805034#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 805630#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 805525#L970 assume !(0 != activate_threads_~tmp___4~0#1); 805526#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 804926#L475 assume !(1 == ~t6_pc~0); 804927#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 804969#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 804970#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 805176#L978 assume !(0 != activate_threads_~tmp___5~0#1); 805457#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 805458#L494 assume !(1 == ~t7_pc~0); 805160#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 805161#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 805409#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 805487#L986 assume !(0 != activate_threads_~tmp___6~0#1); 805488#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 805765#L837 assume !(1 == ~M_E~0); 805694#L837-2 assume !(1 == ~T1_E~0); 805544#L842-1 assume !(1 == ~T2_E~0); 805253#L847-1 assume !(1 == ~T3_E~0); 805254#L852-1 assume !(1 == ~T4_E~0); 805331#L857-1 assume !(1 == ~T5_E~0); 805196#L862-1 assume !(1 == ~T6_E~0); 805197#L867-1 assume !(1 == ~T7_E~0); 805204#L872-1 assume !(1 == ~E_1~0); 805289#L877-1 assume !(1 == ~E_2~0); 805503#L882-1 assume !(1 == ~E_3~0); 805703#L887-1 assume !(1 == ~E_4~0); 805566#L892-1 assume !(1 == ~E_5~0); 805567#L897-1 assume !(1 == ~E_6~0); 805225#L902-1 assume !(1 == ~E_7~0); 805226#L907-1 assume { :end_inline_reset_delta_events } true; 805596#L1148-2 assume !false; 827716#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 827714#L729-1 [2023-11-29 01:11:21,738 INFO L750 eck$LassoCheckResult]: Loop: 827714#L729-1 assume !false; 827712#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 827709#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 827707#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 827705#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 827703#L626 assume 0 != eval_~tmp~0#1; 827698#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 827700#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 843261#L634-2 havoc eval_~tmp_ndt_1~0#1; 824550#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 824547#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 824538#L648-2 havoc eval_~tmp_ndt_2~0#1; 824492#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 824482#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 824474#L662-2 havoc eval_~tmp_ndt_3~0#1; 822389#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 822386#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 814156#L676-2 havoc eval_~tmp_ndt_4~0#1; 814154#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 814149#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 814151#L690-2 havoc eval_~tmp_ndt_5~0#1; 840345#L687-1 assume !(0 == ~t5_st~0); 828101#L701-1 assume !(0 == ~t6_st~0); 827718#L715-1 assume !(0 == ~t7_st~0); 827714#L729-1 [2023-11-29 01:11:21,739 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:21,739 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 5 times [2023-11-29 01:11:21,739 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:21,739 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1867505098] [2023-11-29 01:11:21,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:21,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:21,751 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:21,751 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:21,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:21,787 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:21,787 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:21,788 INFO L85 PathProgramCache]: Analyzing trace with hash 10984371, now seen corresponding path program 1 times [2023-11-29 01:11:21,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:21,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1205489965] [2023-11-29 01:11:21,788 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:21,788 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:21,792 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:21,793 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:21,795 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:21,798 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:21,798 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:21,798 INFO L85 PathProgramCache]: Analyzing trace with hash 521064506, now seen corresponding path program 1 times [2023-11-29 01:11:21,798 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:21,799 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [143896308] [2023-11-29 01:11:21,799 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:21,799 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:21,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:21,848 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:21,848 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:21,848 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [143896308] [2023-11-29 01:11:21,848 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [143896308] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:21,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:21,849 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:21,849 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [14636854] [2023-11-29 01:11:21,849 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:21,972 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:21,973 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:21,973 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:21,973 INFO L87 Difference]: Start difference. First operand 89290 states and 118621 transitions. cyclomatic complexity: 29355 Second operand has 3 states, 3 states have (on average 39.666666666666664) internal successors, (119), 3 states have internal predecessors, (119), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:22,707 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:22,707 INFO L93 Difference]: Finished difference Result 162814 states and 215493 transitions. [2023-11-29 01:11:22,707 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 162814 states and 215493 transitions. [2023-11-29 01:11:23,408 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 161080 [2023-11-29 01:11:24,114 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 162814 states to 162814 states and 215493 transitions. [2023-11-29 01:11:24,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 162814 [2023-11-29 01:11:24,196 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 162814 [2023-11-29 01:11:24,196 INFO L73 IsDeterministic]: Start isDeterministic. Operand 162814 states and 215493 transitions. [2023-11-29 01:11:24,245 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:24,246 INFO L218 hiAutomatonCegarLoop]: Abstraction has 162814 states and 215493 transitions. [2023-11-29 01:11:24,319 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 162814 states and 215493 transitions. [2023-11-29 01:11:25,547 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 162814 to 157774. [2023-11-29 01:11:25,631 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 157774 states, 157774 states have (on average 1.3265873971630306) internal successors, (209301), 157773 states have internal predecessors, (209301), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:25,945 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 157774 states to 157774 states and 209301 transitions. [2023-11-29 01:11:25,945 INFO L240 hiAutomatonCegarLoop]: Abstraction has 157774 states and 209301 transitions. [2023-11-29 01:11:25,946 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:25,946 INFO L428 stractBuchiCegarLoop]: Abstraction has 157774 states and 209301 transitions. [2023-11-29 01:11:25,946 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-29 01:11:25,946 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 157774 states and 209301 transitions. [2023-11-29 01:11:26,764 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 156040 [2023-11-29 01:11:26,764 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:26,764 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:26,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:26,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:26,766 INFO L748 eck$LassoCheckResult]: Stem: 1057165#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1057166#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1057819#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1057820#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1057887#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1057857#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1057858#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1057323#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1057324#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1057399#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1057229#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1057230#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1057197#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1057198#L754 assume !(0 == ~M_E~0); 1057911#L754-2 assume !(0 == ~T1_E~0); 1057759#L759-1 assume !(0 == ~T2_E~0); 1057603#L764-1 assume !(0 == ~T3_E~0); 1057551#L769-1 assume !(0 == ~T4_E~0); 1057552#L774-1 assume !(0 == ~T5_E~0); 1057604#L779-1 assume !(0 == ~T6_E~0); 1057770#L784-1 assume !(0 == ~T7_E~0); 1057548#L789-1 assume !(0 == ~E_1~0); 1057549#L794-1 assume !(0 == ~E_2~0); 1057660#L799-1 assume !(0 == ~E_3~0); 1057562#L804-1 assume !(0 == ~E_4~0); 1057563#L809-1 assume !(0 == ~E_5~0); 1057598#L814-1 assume !(0 == ~E_6~0); 1056965#L819-1 assume !(0 == ~E_7~0); 1056966#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1057227#L361 assume !(1 == ~m_pc~0); 1057228#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1057812#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1057743#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1057744#L930 assume !(0 != activate_threads_~tmp~1#1); 1057450#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1057221#L380 assume !(1 == ~t1_pc~0); 1057222#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1057949#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1056984#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1056985#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1057692#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1057668#L399 assume !(1 == ~t2_pc~0); 1057132#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1057133#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1057301#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1057294#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1057295#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1056971#L418 assume !(1 == ~t3_pc~0); 1056951#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1056952#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1056961#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1056962#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1057579#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1057580#L437 assume !(1 == ~t4_pc~0); 1057859#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1057737#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1057043#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1057044#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1057353#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1057717#L456 assume !(1 == ~t5_pc~0); 1057149#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1057148#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1057748#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1057644#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1057645#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1057038#L475 assume !(1 == ~t6_pc~0); 1057039#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1057081#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1057082#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1057287#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1057569#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1057570#L494 assume !(1 == ~t7_pc~0); 1057271#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1057272#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1057514#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1057605#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1057606#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1057898#L837 assume !(1 == ~M_E~0); 1057818#L837-2 assume !(1 == ~T1_E~0); 1057664#L842-1 assume !(1 == ~T2_E~0); 1057362#L847-1 assume !(1 == ~T3_E~0); 1057363#L852-1 assume !(1 == ~T4_E~0); 1057438#L857-1 assume !(1 == ~T5_E~0); 1057308#L862-1 assume !(1 == ~T6_E~0); 1057309#L867-1 assume !(1 == ~T7_E~0); 1057317#L872-1 assume !(1 == ~E_1~0); 1057398#L877-1 assume !(1 == ~E_2~0); 1057621#L882-1 assume !(1 == ~E_3~0); 1057831#L887-1 assume !(1 == ~E_4~0); 1057685#L892-1 assume !(1 == ~E_5~0); 1057686#L897-1 assume !(1 == ~E_6~0); 1057334#L902-1 assume !(1 == ~E_7~0); 1057335#L907-1 assume { :end_inline_reset_delta_events } true; 1057714#L1148-2 assume !false; 1091234#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1091233#L729-1 [2023-11-29 01:11:26,766 INFO L750 eck$LassoCheckResult]: Loop: 1091233#L729-1 assume !false; 1091232#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1091228#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1091226#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1091224#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1091221#L626 assume 0 != eval_~tmp~0#1; 1091213#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1091210#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1091205#L634-2 havoc eval_~tmp_ndt_1~0#1; 1091200#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1091197#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1091195#L648-2 havoc eval_~tmp_ndt_2~0#1; 1091193#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1091191#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1091189#L662-2 havoc eval_~tmp_ndt_3~0#1; 1091188#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1091167#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1091187#L676-2 havoc eval_~tmp_ndt_4~0#1; 1091262#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1091260#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 1091258#L690-2 havoc eval_~tmp_ndt_5~0#1; 1091247#L687-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1091245#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 1091244#L704-2 havoc eval_~tmp_ndt_6~0#1; 1091241#L701-1 assume !(0 == ~t6_st~0); 1091236#L715-1 assume !(0 == ~t7_st~0); 1091233#L729-1 [2023-11-29 01:11:26,766 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:26,767 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 6 times [2023-11-29 01:11:26,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:26,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1647986915] [2023-11-29 01:11:26,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:26,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:26,779 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:26,779 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:26,787 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:26,808 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:26,808 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:26,808 INFO L85 PathProgramCache]: Analyzing trace with hash 1752066933, now seen corresponding path program 1 times [2023-11-29 01:11:26,809 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:26,809 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1799944774] [2023-11-29 01:11:26,809 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:26,809 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:26,813 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:26,813 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:26,815 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:26,818 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:26,818 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:26,818 INFO L85 PathProgramCache]: Analyzing trace with hash -1982162372, now seen corresponding path program 1 times [2023-11-29 01:11:26,819 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:26,819 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272470763] [2023-11-29 01:11:26,819 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:26,819 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:26,832 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:26,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:26,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:26,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272470763] [2023-11-29 01:11:26,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272470763] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:26,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:26,867 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 01:11:26,867 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [277619904] [2023-11-29 01:11:26,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:27,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:27,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:27,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:27,011 INFO L87 Difference]: Start difference. First operand 157774 states and 209301 transitions. cyclomatic complexity: 51551 Second operand has 3 states, 3 states have (on average 40.333333333333336) internal successors, (121), 3 states have internal predecessors, (121), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:28,123 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:28,123 INFO L93 Difference]: Finished difference Result 216142 states and 285669 transitions. [2023-11-29 01:11:28,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 216142 states and 285669 transitions. [2023-11-29 01:11:28,977 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 213880 [2023-11-29 01:11:29,814 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 216142 states to 216142 states and 285669 transitions. [2023-11-29 01:11:29,814 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 216142 [2023-11-29 01:11:29,888 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 216142 [2023-11-29 01:11:29,888 INFO L73 IsDeterministic]: Start isDeterministic. Operand 216142 states and 285669 transitions. [2023-11-29 01:11:29,950 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:29,951 INFO L218 hiAutomatonCegarLoop]: Abstraction has 216142 states and 285669 transitions. [2023-11-29 01:11:30,044 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216142 states and 285669 transitions. [2023-11-29 01:11:31,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216142 to 212974. [2023-11-29 01:11:31,983 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212974 states, 212974 states have (on average 1.3224008564425704) internal successors, (281637), 212973 states have internal predecessors, (281637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:32,598 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212974 states to 212974 states and 281637 transitions. [2023-11-29 01:11:32,599 INFO L240 hiAutomatonCegarLoop]: Abstraction has 212974 states and 281637 transitions. [2023-11-29 01:11:32,599 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:32,600 INFO L428 stractBuchiCegarLoop]: Abstraction has 212974 states and 281637 transitions. [2023-11-29 01:11:32,600 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2023-11-29 01:11:32,600 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212974 states and 281637 transitions. [2023-11-29 01:11:33,718 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 210712 [2023-11-29 01:11:33,718 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:33,719 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:33,719 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:33,719 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:33,720 INFO L748 eck$LassoCheckResult]: Stem: 1431085#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 1431086#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 1431740#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1431741#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1431802#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 1431775#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1431776#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1431240#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1431241#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1431316#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1431149#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1431150#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1431117#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1431118#L754 assume !(0 == ~M_E~0); 1431828#L754-2 assume !(0 == ~T1_E~0); 1431688#L759-1 assume !(0 == ~T2_E~0); 1431524#L764-1 assume !(0 == ~T3_E~0); 1431469#L769-1 assume !(0 == ~T4_E~0); 1431470#L774-1 assume !(0 == ~T5_E~0); 1431525#L779-1 assume !(0 == ~T6_E~0); 1431698#L784-1 assume !(0 == ~T7_E~0); 1431465#L789-1 assume !(0 == ~E_1~0); 1431466#L794-1 assume !(0 == ~E_2~0); 1431583#L799-1 assume !(0 == ~E_3~0); 1431482#L804-1 assume !(0 == ~E_4~0); 1431483#L809-1 assume !(0 == ~E_5~0); 1431519#L814-1 assume !(0 == ~E_6~0); 1430887#L819-1 assume !(0 == ~E_7~0); 1430888#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1431147#L361 assume !(1 == ~m_pc~0); 1431148#L361-2 is_master_triggered_~__retres1~0#1 := 0; 1431734#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1431674#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 1431675#L930 assume !(0 != activate_threads_~tmp~1#1); 1431367#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1431141#L380 assume !(1 == ~t1_pc~0); 1431142#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1431869#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1430908#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1430909#L938 assume !(0 != activate_threads_~tmp___0~0#1); 1431626#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1431595#L399 assume !(1 == ~t2_pc~0); 1431055#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1431056#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1431222#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1431215#L946 assume !(0 != activate_threads_~tmp___1~0#1); 1431216#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1430895#L418 assume !(1 == ~t3_pc~0); 1430875#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1430876#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1430885#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1430886#L954 assume !(0 != activate_threads_~tmp___2~0#1); 1431502#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1431503#L437 assume !(1 == ~t4_pc~0); 1431777#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1431669#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1430966#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1430967#L962 assume !(0 != activate_threads_~tmp___3~0#1); 1431269#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1431650#L456 assume !(1 == ~t5_pc~0); 1431071#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1431070#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1431679#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1431566#L970 assume !(0 != activate_threads_~tmp___4~0#1); 1431567#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1430961#L475 assume !(1 == ~t6_pc~0); 1430962#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1431003#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1431004#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1431208#L978 assume !(0 != activate_threads_~tmp___5~0#1); 1431490#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1431491#L494 assume !(1 == ~t7_pc~0); 1431192#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1431193#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1431431#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1431526#L986 assume !(0 != activate_threads_~tmp___6~0#1); 1431527#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1431814#L837 assume !(1 == ~M_E~0); 1431739#L837-2 assume !(1 == ~T1_E~0); 1431591#L842-1 assume !(1 == ~T2_E~0); 1431278#L847-1 assume !(1 == ~T3_E~0); 1431279#L852-1 assume !(1 == ~T4_E~0); 1431355#L857-1 assume !(1 == ~T5_E~0); 1431228#L862-1 assume !(1 == ~T6_E~0); 1431229#L867-1 assume !(1 == ~T7_E~0); 1431236#L872-1 assume !(1 == ~E_1~0); 1431315#L877-1 assume !(1 == ~E_2~0); 1431543#L882-1 assume !(1 == ~E_3~0); 1431749#L887-1 assume !(1 == ~E_4~0); 1431618#L892-1 assume !(1 == ~E_5~0); 1431619#L897-1 assume !(1 == ~E_6~0); 1431251#L902-1 assume !(1 == ~E_7~0); 1431252#L907-1 assume { :end_inline_reset_delta_events } true; 1431649#L1148-2 assume !false; 1446040#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1446039#L729-1 [2023-11-29 01:11:33,720 INFO L750 eck$LassoCheckResult]: Loop: 1446039#L729-1 assume !false; 1446036#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 1446033#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 1446031#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 1446029#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1446026#L626 assume 0 != eval_~tmp~0#1; 1446023#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 1446019#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 1446017#L634-2 havoc eval_~tmp_ndt_1~0#1; 1446015#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 1444844#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 1446011#L648-2 havoc eval_~tmp_ndt_2~0#1; 1446009#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 1446006#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 1446004#L662-2 havoc eval_~tmp_ndt_3~0#1; 1446002#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 1444269#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 1445998#L676-2 havoc eval_~tmp_ndt_4~0#1; 1445996#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 1445993#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 1445991#L690-2 havoc eval_~tmp_ndt_5~0#1; 1445989#L687-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 1445774#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 1445977#L704-2 havoc eval_~tmp_ndt_6~0#1; 1446049#L701-1 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 1446047#L718 assume !(0 != eval_~tmp_ndt_7~0#1); 1446044#L718-2 havoc eval_~tmp_ndt_7~0#1; 1446042#L715-1 assume !(0 == ~t7_st~0); 1446039#L729-1 [2023-11-29 01:11:33,720 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:33,720 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 7 times [2023-11-29 01:11:33,720 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:33,720 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115830289] [2023-11-29 01:11:33,720 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:33,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:33,728 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:33,729 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:33,734 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:33,755 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:33,755 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:33,755 INFO L85 PathProgramCache]: Analyzing trace with hash 102487731, now seen corresponding path program 1 times [2023-11-29 01:11:33,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:33,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971841372] [2023-11-29 01:11:33,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:33,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:33,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:33,759 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:33,762 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:33,765 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:33,765 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:33,765 INFO L85 PathProgramCache]: Analyzing trace with hash 2100785082, now seen corresponding path program 1 times [2023-11-29 01:11:33,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:33,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1325829366] [2023-11-29 01:11:33,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:33,766 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:33,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 01:11:33,815 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 01:11:33,816 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 01:11:33,816 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1325829366] [2023-11-29 01:11:33,816 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1325829366] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 01:11:33,816 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 01:11:33,816 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 01:11:33,816 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [238769080] [2023-11-29 01:11:33,817 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 01:11:33,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 01:11:33,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 01:11:33,938 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 01:11:33,939 INFO L87 Difference]: Start difference. First operand 212974 states and 281637 transitions. cyclomatic complexity: 68687 Second operand has 3 states, 2 states have (on average 61.5) internal successors, (123), 3 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:35,581 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 01:11:35,581 INFO L93 Difference]: Finished difference Result 417924 states and 551751 transitions. [2023-11-29 01:11:35,582 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 417924 states and 551751 transitions. [2023-11-29 01:11:37,689 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 413502 [2023-11-29 01:11:38,593 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 417924 states to 417924 states and 551751 transitions. [2023-11-29 01:11:38,593 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 417924 [2023-11-29 01:11:38,772 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 417924 [2023-11-29 01:11:38,772 INFO L73 IsDeterministic]: Start isDeterministic. Operand 417924 states and 551751 transitions. [2023-11-29 01:11:39,300 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 01:11:39,301 INFO L218 hiAutomatonCegarLoop]: Abstraction has 417924 states and 551751 transitions. [2023-11-29 01:11:39,580 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 417924 states and 551751 transitions. [2023-11-29 01:11:42,948 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 417924 to 417924. [2023-11-29 01:11:43,191 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 417924 states, 417924 states have (on average 1.320218508628363) internal successors, (551751), 417923 states have internal predecessors, (551751), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 01:11:44,765 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 417924 states to 417924 states and 551751 transitions. [2023-11-29 01:11:44,765 INFO L240 hiAutomatonCegarLoop]: Abstraction has 417924 states and 551751 transitions. [2023-11-29 01:11:44,766 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 01:11:44,766 INFO L428 stractBuchiCegarLoop]: Abstraction has 417924 states and 551751 transitions. [2023-11-29 01:11:44,766 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2023-11-29 01:11:44,766 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 417924 states and 551751 transitions. [2023-11-29 01:11:46,279 INFO L131 ngComponentsAnalysis]: Automaton has 24 accepting balls. 413502 [2023-11-29 01:11:46,279 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 01:11:46,279 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 01:11:46,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:46,280 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 01:11:46,281 INFO L748 eck$LassoCheckResult]: Stem: 2061991#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2; 2061992#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~9#1;havoc main_~__retres1~9#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1; 2062643#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret22#1, start_simulation_#t~ret23#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2062644#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2062698#L521 assume 1 == ~m_i~0;~m_st~0 := 0; 2062677#L521-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2062678#L526-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2062149#L531-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2062150#L536-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2062225#L541-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2062056#L546-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2062057#L551-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2062023#L556-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2062024#L754 assume !(0 == ~M_E~0); 2062721#L754-2 assume !(0 == ~T1_E~0); 2062592#L759-1 assume !(0 == ~T2_E~0); 2062428#L764-1 assume !(0 == ~T3_E~0); 2062374#L769-1 assume !(0 == ~T4_E~0); 2062375#L774-1 assume !(0 == ~T5_E~0); 2062429#L779-1 assume !(0 == ~T6_E~0); 2062603#L784-1 assume !(0 == ~T7_E~0); 2062371#L789-1 assume !(0 == ~E_1~0); 2062372#L794-1 assume !(0 == ~E_2~0); 2062484#L799-1 assume !(0 == ~E_3~0); 2062387#L804-1 assume !(0 == ~E_4~0); 2062388#L809-1 assume !(0 == ~E_5~0); 2062423#L814-1 assume !(0 == ~E_6~0); 2061794#L819-1 assume !(0 == ~E_7~0); 2061795#L824-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2062054#L361 assume !(1 == ~m_pc~0); 2062055#L361-2 is_master_triggered_~__retres1~0#1 := 0; 2062638#L372 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2062578#is_master_triggered_returnLabel#1 activate_threads_#t~ret13#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret13#1;havoc activate_threads_#t~ret13#1; 2062579#L930 assume !(0 != activate_threads_~tmp~1#1); 2062275#L930-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2062047#L380 assume !(1 == ~t1_pc~0); 2062048#L380-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2062696#L391 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2061815#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2061816#L938 assume !(0 != activate_threads_~tmp___0~0#1); 2062523#L938-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2062497#L399 assume !(1 == ~t2_pc~0); 2061960#L399-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2061961#L410 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2062127#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2062120#L946 assume !(0 != activate_threads_~tmp___1~0#1); 2062121#L946-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2061802#L418 assume !(1 == ~t3_pc~0); 2061781#L418-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2061782#L429 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2061792#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2061793#L954 assume !(0 != activate_threads_~tmp___2~0#1); 2062406#L954-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2062407#L437 assume !(1 == ~t4_pc~0); 2062679#L437-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2062573#L448 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2061872#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2061873#L962 assume !(0 != activate_threads_~tmp___3~0#1); 2062178#L962-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2062546#L456 assume !(1 == ~t5_pc~0); 2061975#L456-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2061974#L467 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2062583#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2062466#L970 assume !(0 != activate_threads_~tmp___4~0#1); 2062467#L970-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2061867#L475 assume !(1 == ~t6_pc~0); 2061868#L475-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2061910#L486 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2061911#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2062113#L978 assume !(0 != activate_threads_~tmp___5~0#1); 2062395#L978-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2062396#L494 assume !(1 == ~t7_pc~0); 2062097#L494-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2062098#L505 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2062339#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2062430#L986 assume !(0 != activate_threads_~tmp___6~0#1); 2062431#L986-2 havoc activate_threads_#t~ret13#1, activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2062711#L837 assume !(1 == ~M_E~0); 2062642#L837-2 assume !(1 == ~T1_E~0); 2062492#L842-1 assume !(1 == ~T2_E~0); 2062188#L847-1 assume !(1 == ~T3_E~0); 2062189#L852-1 assume !(1 == ~T4_E~0); 2062264#L857-1 assume !(1 == ~T5_E~0); 2062134#L862-1 assume !(1 == ~T6_E~0); 2062135#L867-1 assume !(1 == ~T7_E~0); 2062145#L872-1 assume !(1 == ~E_1~0); 2062224#L877-1 assume !(1 == ~E_2~0); 2062446#L882-1 assume !(1 == ~E_3~0); 2062651#L887-1 assume !(1 == ~E_4~0); 2062514#L892-1 assume !(1 == ~E_5~0); 2062515#L897-1 assume !(1 == ~E_6~0); 2062161#L902-1 assume !(1 == ~E_7~0); 2062162#L907-1 assume { :end_inline_reset_delta_events } true; 2062545#L1148-2 assume !false; 2190732#L1149 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2190729#L729-1 [2023-11-29 01:11:46,281 INFO L750 eck$LassoCheckResult]: Loop: 2190729#L729-1 assume !false; 2190727#L622 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;havoc exists_runnable_thread_~__retres1~8#1; 2190714#L569 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~8#1 := 1; 2190715#L611 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~8#1; 2209652#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~8#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2209649#L626 assume 0 != eval_~tmp~0#1; 2209647#L626-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 2209644#L634 assume !(0 != eval_~tmp_ndt_1~0#1); 2209645#L634-2 havoc eval_~tmp_ndt_1~0#1; 2290618#L631-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 2121377#L648 assume !(0 != eval_~tmp_ndt_2~0#1); 2290614#L648-2 havoc eval_~tmp_ndt_2~0#1; 2290611#L645-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 2290609#L662 assume !(0 != eval_~tmp_ndt_3~0#1); 2290607#L662-2 havoc eval_~tmp_ndt_3~0#1; 2177152#L659-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 2177148#L676 assume !(0 != eval_~tmp_ndt_4~0#1); 2177146#L676-2 havoc eval_~tmp_ndt_4~0#1; 2177144#L673-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 2177140#L690 assume !(0 != eval_~tmp_ndt_5~0#1); 2177138#L690-2 havoc eval_~tmp_ndt_5~0#1; 2177136#L687-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 2177112#L704 assume !(0 != eval_~tmp_ndt_6~0#1); 2177134#L704-2 havoc eval_~tmp_ndt_6~0#1; 2190018#L701-1 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 2190013#L718 assume !(0 != eval_~tmp_ndt_7~0#1); 2190014#L718-2 havoc eval_~tmp_ndt_7~0#1; 2190738#L715-1 assume 0 == ~t7_st~0;havoc eval_~tmp_ndt_8~0#1;havoc eval_#t~nondet12#1;eval_~tmp_ndt_8~0#1 := eval_#t~nondet12#1;havoc eval_#t~nondet12#1; 2121303#L732 assume !(0 != eval_~tmp_ndt_8~0#1); 2190733#L732-2 havoc eval_~tmp_ndt_8~0#1; 2190729#L729-1 [2023-11-29 01:11:46,281 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:46,282 INFO L85 PathProgramCache]: Analyzing trace with hash 1978243464, now seen corresponding path program 8 times [2023-11-29 01:11:46,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:46,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2046041436] [2023-11-29 01:11:46,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:46,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:46,291 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:46,291 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:46,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:46,323 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:46,323 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:46,324 INFO L85 PathProgramCache]: Analyzing trace with hash -293510902, now seen corresponding path program 1 times [2023-11-29 01:11:46,324 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:46,324 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1670653702] [2023-11-29 01:11:46,324 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:46,324 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:46,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:46,329 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:46,331 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:46,334 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:46,335 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 01:11:46,335 INFO L85 PathProgramCache]: Analyzing trace with hash 219862097, now seen corresponding path program 1 times [2023-11-29 01:11:46,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 01:11:46,335 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [261575377] [2023-11-29 01:11:46,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 01:11:46,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 01:11:46,348 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:46,349 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:46,357 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:46,389 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 01:11:48,299 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:48,299 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 01:11:48,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 01:11:48,557 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer CFG 29.11 01:11:48 BoogieIcfgContainer [2023-11-29 01:11:48,557 INFO L131 PluginConnector]: ------------------------ END BuchiAutomizer---------------------------- [2023-11-29 01:11:48,558 INFO L112 PluginConnector]: ------------------------Witness Printer---------------------------- [2023-11-29 01:11:48,558 INFO L270 PluginConnector]: Initializing Witness Printer... [2023-11-29 01:11:48,558 INFO L274 PluginConnector]: Witness Printer initialized [2023-11-29 01:11:48,558 INFO L184 PluginConnector]: Executing the observer RCFGCatcher from plugin Witness Printer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 01:11:01" (3/4) ... [2023-11-29 01:11:48,560 INFO L134 WitnessPrinter]: Generating witness for non-termination counterexample [2023-11-29 01:11:48,688 INFO L149 WitnessManager]: Wrote witness to /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/witness.graphml [2023-11-29 01:11:48,688 INFO L131 PluginConnector]: ------------------------ END Witness Printer---------------------------- [2023-11-29 01:11:48,688 INFO L158 Benchmark]: Toolchain (without parser) took 49390.24ms. Allocated memory was 144.7MB in the beginning and 14.0GB in the end (delta: 13.9GB). Free memory was 104.1MB in the beginning and 9.0GB in the end (delta: -8.9GB). Peak memory consumption was 5.0GB. Max. memory is 16.1GB. [2023-11-29 01:11:48,689 INFO L158 Benchmark]: CDTParser took 0.21ms. Allocated memory is still 102.8MB. Free memory is still 53.2MB. There was no memory consumed. Max. memory is 16.1GB. [2023-11-29 01:11:48,689 INFO L158 Benchmark]: CACSL2BoogieTranslator took 399.89ms. Allocated memory is still 144.7MB. Free memory was 104.1MB in the beginning and 86.0MB in the end (delta: 18.1MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. [2023-11-29 01:11:48,689 INFO L158 Benchmark]: Boogie Procedure Inliner took 95.64ms. Allocated memory is still 144.7MB. Free memory was 86.0MB in the beginning and 79.7MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. [2023-11-29 01:11:48,690 INFO L158 Benchmark]: Boogie Preprocessor took 163.88ms. Allocated memory is still 144.7MB. Free memory was 79.7MB in the beginning and 110.7MB in the end (delta: -31.0MB). Peak memory consumption was 10.6MB. Max. memory is 16.1GB. [2023-11-29 01:11:48,690 INFO L158 Benchmark]: RCFGBuilder took 1517.11ms. Allocated memory is still 144.7MB. Free memory was 110.7MB in the beginning and 89.2MB in the end (delta: 21.4MB). Peak memory consumption was 64.5MB. Max. memory is 16.1GB. [2023-11-29 01:11:48,690 INFO L158 Benchmark]: BuchiAutomizer took 47077.87ms. Allocated memory was 144.7MB in the beginning and 14.0GB in the end (delta: 13.9GB). Free memory was 89.2MB in the beginning and 9.0GB in the end (delta: -8.9GB). Peak memory consumption was 4.9GB. Max. memory is 16.1GB. [2023-11-29 01:11:48,691 INFO L158 Benchmark]: Witness Printer took 130.27ms. Allocated memory is still 14.0GB. Free memory was 9.0GB in the beginning and 9.0GB in the end (delta: 16.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. [2023-11-29 01:11:48,693 INFO L338 ainManager$Toolchain]: ####################### End [Toolchain 1] ####################### --- Results --- * Results from de.uni_freiburg.informatik.ultimate.core: - StatisticsResult: Toolchain Benchmarks Benchmark results are: * CDTParser took 0.21ms. Allocated memory is still 102.8MB. Free memory is still 53.2MB. There was no memory consumed. Max. memory is 16.1GB. * CACSL2BoogieTranslator took 399.89ms. Allocated memory is still 144.7MB. Free memory was 104.1MB in the beginning and 86.0MB in the end (delta: 18.1MB). Peak memory consumption was 18.9MB. Max. memory is 16.1GB. * Boogie Procedure Inliner took 95.64ms. Allocated memory is still 144.7MB. Free memory was 86.0MB in the beginning and 79.7MB in the end (delta: 6.3MB). Peak memory consumption was 6.3MB. Max. memory is 16.1GB. * Boogie Preprocessor took 163.88ms. Allocated memory is still 144.7MB. Free memory was 79.7MB in the beginning and 110.7MB in the end (delta: -31.0MB). Peak memory consumption was 10.6MB. Max. memory is 16.1GB. * RCFGBuilder took 1517.11ms. Allocated memory is still 144.7MB. Free memory was 110.7MB in the beginning and 89.2MB in the end (delta: 21.4MB). Peak memory consumption was 64.5MB. Max. memory is 16.1GB. * BuchiAutomizer took 47077.87ms. Allocated memory was 144.7MB in the beginning and 14.0GB in the end (delta: 13.9GB). Free memory was 89.2MB in the beginning and 9.0GB in the end (delta: -8.9GB). Peak memory consumption was 4.9GB. Max. memory is 16.1GB. * Witness Printer took 130.27ms. Allocated memory is still 14.0GB. Free memory was 9.0GB in the beginning and 9.0GB in the end (delta: 16.8MB). Peak memory consumption was 16.8MB. Max. memory is 16.1GB. * Results from de.uni_freiburg.informatik.ultimate.plugins.generator.traceabstraction: - StatisticsResult: Constructed decomposition of program Your program was decomposed into 33 terminating modules (33 trivial, 0 deterministic, 0 nondeterministic) and one nonterminating remainder module.33 modules have a trivial ranking function, the largest among these consists of 5 locations. The remainder module has 417924 locations. - StatisticsResult: Timing statistics BüchiAutomizer plugin needed 46.8s and 34 iterations. TraceHistogramMax:1. Analysis of lassos took 7.5s. Construction of modules took 1.0s. Büchi inclusion checks took 33.1s. Highest rank in rank-based complementation 0. Minimization of det autom 33. Minimization of nondet autom 0. Automata minimization 15.6s AutomataMinimizationTime, 33 MinimizatonAttempts, 63448 StatesRemovedByMinimization, 18 NontrivialMinimizations. Non-live state removal took 9.7s Buchi closure took 0.6s. Biggest automaton had -1 states and ocurred in iteration -1. Nontrivial modules had stage [0, 0, 0, 0, 0]. InterpolantCoveringCapabilityFinite: 0/0 InterpolantCoveringCapabilityBuchi: 0/0 HoareTripleCheckerStatistics: 0 mSolverCounterUnknown, 38664 SdHoareTripleChecker+Valid, 1.3s IncrementalHoareTripleChecker+Time, 0 mSdLazyCounter, 38664 mSDsluCounter, 68999 SdHoareTripleChecker+Invalid, 1.0s Time, 0 mProtectedAction, 0 SdHoareTripleChecker+Unchecked, 0 IncrementalHoareTripleChecker+Unchecked, 28113 mSDsCounter, 428 IncrementalHoareTripleChecker+Valid, 0 mProtectedPredicate, 869 IncrementalHoareTripleChecker+Invalid, 1297 SdHoareTripleChecker+Unknown, 0 mSolverCounterNotChecked, 428 mSolverCounterUnsat, 40886 mSDtfsCounter, 869 mSolverCounterSat, 0.3s SdHoareTripleChecker+Time, 0 IncrementalHoareTripleChecker+Unknown LassoAnalysisResults: nont1 unkn0 SFLI5 SFLT0 conc7 concLT0 SILN1 SILU0 SILI20 SILT0 lasso0 LassoPreprocessingBenchmarks: LassoTerminationAnalysisBenchmarks: not availableLassoTerminationAnalysisBenchmarks: LassoNonterminationAnalysisSatFixpoint: 0 LassoNonterminationAnalysisSatUnbounded: 0 LassoNonterminationAnalysisUnsat: 0 LassoNonterminationAnalysisUnknown: 0 LassoNonterminationAnalysisTime: 0.0s InitialAbstractionConstructionTime: 0.0s - TerminationAnalysisResult: Nontermination possible Buchi Automizer proved that your program is nonterminating for some inputs - LassoShapedNonTerminationArgument [Line: 621]: Nontermination argument in form of an infinite program execution. Nontermination argument in form of an infinite program execution. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int m_st ; [L34] int t1_st ; [L35] int t2_st ; [L36] int t3_st ; [L37] int t4_st ; [L38] int t5_st ; [L39] int t6_st ; [L40] int t7_st ; [L41] int m_i ; [L42] int t1_i ; [L43] int t2_i ; [L44] int t3_i ; [L45] int t4_i ; [L46] int t5_i ; [L47] int t6_i ; [L48] int t7_i ; [L49] int M_E = 2; [L50] int T1_E = 2; [L51] int T2_E = 2; [L52] int T3_E = 2; [L53] int T4_E = 2; [L54] int T5_E = 2; [L55] int T6_E = 2; [L56] int T7_E = 2; [L57] int E_1 = 2; [L58] int E_2 = 2; [L59] int E_3 = 2; [L60] int E_4 = 2; [L61] int E_5 = 2; [L62] int E_6 = 2; [L63] int E_7 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0, t7_i=0, t7_pc=0, t7_st=0] [L1193] int __retres1 ; [L1197] CALL init_model() [L1102] m_i = 1 [L1103] t1_i = 1 [L1104] t2_i = 1 [L1105] t3_i = 1 [L1106] t4_i = 1 [L1107] t5_i = 1 [L1108] t6_i = 1 [L1109] t7_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L1197] RET init_model() [L1198] CALL start_simulation() [L1134] int kernel_st ; [L1135] int tmp ; [L1136] int tmp___0 ; [L1140] kernel_st = 0 [L1141] FCALL update_channels() [L1142] CALL init_threads() [L521] COND TRUE m_i == 1 [L522] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L526] COND TRUE t1_i == 1 [L527] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L531] COND TRUE t2_i == 1 [L532] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L536] COND TRUE t3_i == 1 [L537] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L541] COND TRUE t4_i == 1 [L542] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L546] COND TRUE t5_i == 1 [L547] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L551] COND TRUE t6_i == 1 [L552] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L556] COND TRUE t7_i == 1 [L557] t7_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L1142] RET init_threads() [L1143] CALL fire_delta_events() [L754] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L759] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L764] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L769] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L774] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L779] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L784] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L789] COND FALSE !(T7_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L794] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L799] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L804] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L809] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L814] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L819] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L824] COND FALSE !(E_7 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L1143] RET fire_delta_events() [L1144] CALL activate_threads() [L917] int tmp ; [L918] int tmp___0 ; [L919] int tmp___1 ; [L920] int tmp___2 ; [L921] int tmp___3 ; [L922] int tmp___4 ; [L923] int tmp___5 ; [L924] int tmp___6 ; [L928] CALL, EXPR is_master_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L361] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L371] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L373] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L928] RET, EXPR is_master_triggered() [L928] tmp = is_master_triggered() [L930] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0] [L936] CALL, EXPR is_transmit1_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L380] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L390] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L936] RET, EXPR is_transmit1_triggered() [L936] tmp___0 = is_transmit1_triggered() [L938] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0] [L944] CALL, EXPR is_transmit2_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L399] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L409] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L411] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L944] RET, EXPR is_transmit2_triggered() [L944] tmp___1 = is_transmit2_triggered() [L946] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0] [L952] CALL, EXPR is_transmit3_triggered() [L415] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L418] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L428] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L430] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L952] RET, EXPR is_transmit3_triggered() [L952] tmp___2 = is_transmit3_triggered() [L954] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L960] CALL, EXPR is_transmit4_triggered() [L434] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L437] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L447] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L449] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L960] RET, EXPR is_transmit4_triggered() [L960] tmp___3 = is_transmit4_triggered() [L962] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L968] CALL, EXPR is_transmit5_triggered() [L453] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L456] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L466] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L468] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L968] RET, EXPR is_transmit5_triggered() [L968] tmp___4 = is_transmit5_triggered() [L970] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L976] CALL, EXPR is_transmit6_triggered() [L472] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L475] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L485] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L487] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L976] RET, EXPR is_transmit6_triggered() [L976] tmp___5 = is_transmit6_triggered() [L978] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L984] CALL, EXPR is_transmit7_triggered() [L491] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L494] COND FALSE !(t7_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L504] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L506] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L984] RET, EXPR is_transmit7_triggered() [L984] tmp___6 = is_transmit7_triggered() [L986] COND FALSE !(\read(tmp___6)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0, tmp___6=0] [L1144] RET activate_threads() [L1145] CALL reset_delta_events() [L837] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L842] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L847] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L852] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L857] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L862] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L867] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L872] COND FALSE !(T7_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L877] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L882] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L887] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L892] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L897] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L902] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L907] COND FALSE !(E_7 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L1145] RET reset_delta_events() [L1148] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L1151] kernel_st = 1 [L1152] CALL eval() [L617] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] Loop: [L621] COND TRUE 1 [L624] CALL, EXPR exists_runnable_thread() [L566] int __retres1 ; [L569] COND TRUE m_st == 0 [L570] __retres1 = 1 [L612] return (__retres1); [L624] RET, EXPR exists_runnable_thread() [L624] tmp = exists_runnable_thread() [L626] COND TRUE \read(tmp) [L631] COND TRUE m_st == 0 [L632] int tmp_ndt_1; [L633] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L634] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L631-L642] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L645] COND TRUE t1_st == 0 [L646] int tmp_ndt_2; [L647] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L648] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L645-L656] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L659] COND TRUE t2_st == 0 [L660] int tmp_ndt_3; [L661] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L662] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L659-L670] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L673] COND TRUE t3_st == 0 [L674] int tmp_ndt_4; [L675] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L676] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L673-L684] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L687] COND TRUE t4_st == 0 [L688] int tmp_ndt_5; [L689] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L690] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L687-L698] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L701] COND TRUE t5_st == 0 [L702] int tmp_ndt_6; [L703] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L704] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L701-L712] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } [L715] COND TRUE t6_st == 0 [L716] int tmp_ndt_7; [L717] EXPR tmp_ndt_7 = __VERIFIER_nondet_int() [L718] COND FALSE, EXPR !(\read(tmp_ndt_7)) [L715-L726] { int tmp_ndt_7; tmp_ndt_7 = __VERIFIER_nondet_int(); if (tmp_ndt_7) { { t6_st = 1; transmit6(); } } else { } } [L729] COND TRUE t7_st == 0 [L730] int tmp_ndt_8; [L731] EXPR tmp_ndt_8 = __VERIFIER_nondet_int() [L732] COND FALSE, EXPR !(\read(tmp_ndt_8)) [L729-L740] { int tmp_ndt_8; tmp_ndt_8 = __VERIFIER_nondet_int(); if (tmp_ndt_8) { { t7_st = 1; transmit7(); } } else { } } End of lasso representation. - StatisticsResult: NonterminationArgumentStatistics Fixpoint - NonterminatingLassoResult [Line: 621]: Nonterminating execution Found a nonterminating execution for the following lasso shaped sequence of statements. Stem: [L25] int m_pc = 0; [L26] int t1_pc = 0; [L27] int t2_pc = 0; [L28] int t3_pc = 0; [L29] int t4_pc = 0; [L30] int t5_pc = 0; [L31] int t6_pc = 0; [L32] int t7_pc = 0; [L33] int m_st ; [L34] int t1_st ; [L35] int t2_st ; [L36] int t3_st ; [L37] int t4_st ; [L38] int t5_st ; [L39] int t6_st ; [L40] int t7_st ; [L41] int m_i ; [L42] int t1_i ; [L43] int t2_i ; [L44] int t3_i ; [L45] int t4_i ; [L46] int t5_i ; [L47] int t6_i ; [L48] int t7_i ; [L49] int M_E = 2; [L50] int T1_E = 2; [L51] int T2_E = 2; [L52] int T3_E = 2; [L53] int T4_E = 2; [L54] int T5_E = 2; [L55] int T6_E = 2; [L56] int T7_E = 2; [L57] int E_1 = 2; [L58] int E_2 = 2; [L59] int E_3 = 2; [L60] int E_4 = 2; [L61] int E_5 = 2; [L62] int E_6 = 2; [L63] int E_7 = 2; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=0, m_pc=0, m_st=0, t1_i=0, t1_pc=0, t1_st=0, t2_i=0, t2_pc=0, t2_st=0, t3_i=0, t3_pc=0, t3_st=0, t4_i=0, t4_pc=0, t4_st=0, t5_i=0, t5_pc=0, t5_st=0, t6_i=0, t6_pc=0, t6_st=0, t7_i=0, t7_pc=0, t7_st=0] [L1193] int __retres1 ; [L1197] CALL init_model() [L1102] m_i = 1 [L1103] t1_i = 1 [L1104] t2_i = 1 [L1105] t3_i = 1 [L1106] t4_i = 1 [L1107] t5_i = 1 [L1108] t6_i = 1 [L1109] t7_i = 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L1197] RET init_model() [L1198] CALL start_simulation() [L1134] int kernel_st ; [L1135] int tmp ; [L1136] int tmp___0 ; [L1140] kernel_st = 0 [L1141] FCALL update_channels() [L1142] CALL init_threads() [L521] COND TRUE m_i == 1 [L522] m_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L526] COND TRUE t1_i == 1 [L527] t1_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L531] COND TRUE t2_i == 1 [L532] t2_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L536] COND TRUE t3_i == 1 [L537] t3_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L541] COND TRUE t4_i == 1 [L542] t4_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L546] COND TRUE t5_i == 1 [L547] t5_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L551] COND TRUE t6_i == 1 [L552] t6_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L556] COND TRUE t7_i == 1 [L557] t7_st = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L1142] RET init_threads() [L1143] CALL fire_delta_events() [L754] COND FALSE !(M_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L759] COND FALSE !(T1_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L764] COND FALSE !(T2_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L769] COND FALSE !(T3_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L774] COND FALSE !(T4_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L779] COND FALSE !(T5_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L784] COND FALSE !(T6_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L789] COND FALSE !(T7_E == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L794] COND FALSE !(E_1 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L799] COND FALSE !(E_2 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L804] COND FALSE !(E_3 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L809] COND FALSE !(E_4 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L814] COND FALSE !(E_5 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L819] COND FALSE !(E_6 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L824] COND FALSE !(E_7 == 0) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L1143] RET fire_delta_events() [L1144] CALL activate_threads() [L917] int tmp ; [L918] int tmp___0 ; [L919] int tmp___1 ; [L920] int tmp___2 ; [L921] int tmp___3 ; [L922] int tmp___4 ; [L923] int tmp___5 ; [L924] int tmp___6 ; [L928] CALL, EXPR is_master_triggered() [L358] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L361] COND FALSE !(m_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L371] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L373] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L928] RET, EXPR is_master_triggered() [L928] tmp = is_master_triggered() [L930] COND FALSE !(\read(tmp)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0] [L936] CALL, EXPR is_transmit1_triggered() [L377] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L380] COND FALSE !(t1_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L390] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L392] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L936] RET, EXPR is_transmit1_triggered() [L936] tmp___0 = is_transmit1_triggered() [L938] COND FALSE !(\read(tmp___0)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0] [L944] CALL, EXPR is_transmit2_triggered() [L396] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L399] COND FALSE !(t2_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L409] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L411] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L944] RET, EXPR is_transmit2_triggered() [L944] tmp___1 = is_transmit2_triggered() [L946] COND FALSE !(\read(tmp___1)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0] [L952] CALL, EXPR is_transmit3_triggered() [L415] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L418] COND FALSE !(t3_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L428] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L430] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L952] RET, EXPR is_transmit3_triggered() [L952] tmp___2 = is_transmit3_triggered() [L954] COND FALSE !(\read(tmp___2)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0] [L960] CALL, EXPR is_transmit4_triggered() [L434] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L437] COND FALSE !(t4_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L447] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L449] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L960] RET, EXPR is_transmit4_triggered() [L960] tmp___3 = is_transmit4_triggered() [L962] COND FALSE !(\read(tmp___3)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0] [L968] CALL, EXPR is_transmit5_triggered() [L453] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L456] COND FALSE !(t5_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L466] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L468] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L968] RET, EXPR is_transmit5_triggered() [L968] tmp___4 = is_transmit5_triggered() [L970] COND FALSE !(\read(tmp___4)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0] [L976] CALL, EXPR is_transmit6_triggered() [L472] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L475] COND FALSE !(t6_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L485] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L487] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L976] RET, EXPR is_transmit6_triggered() [L976] tmp___5 = is_transmit6_triggered() [L978] COND FALSE !(\read(tmp___5)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0] [L984] CALL, EXPR is_transmit7_triggered() [L491] int __retres1 ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L494] COND FALSE !(t7_pc == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L504] __retres1 = 0 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L506] return (__retres1); VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, \result=0, __retres1=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L984] RET, EXPR is_transmit7_triggered() [L984] tmp___6 = is_transmit7_triggered() [L986] COND FALSE !(\read(tmp___6)) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0, tmp=0, tmp___0=0, tmp___1=0, tmp___2=0, tmp___3=0, tmp___4=0, tmp___5=0, tmp___6=0] [L1144] RET activate_threads() [L1145] CALL reset_delta_events() [L837] COND FALSE !(M_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L842] COND FALSE !(T1_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L847] COND FALSE !(T2_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L852] COND FALSE !(T3_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L857] COND FALSE !(T4_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L862] COND FALSE !(T5_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L867] COND FALSE !(T6_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L872] COND FALSE !(T7_E == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L877] COND FALSE !(E_1 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L882] COND FALSE !(E_2 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L887] COND FALSE !(E_3 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L892] COND FALSE !(E_4 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L897] COND FALSE !(E_5 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L902] COND FALSE !(E_6 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L907] COND FALSE !(E_7 == 1) VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L1145] RET reset_delta_events() [L1148] COND TRUE 1 VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, kernel_st=0, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] [L1151] kernel_st = 1 [L1152] CALL eval() [L617] int tmp ; VAL [E_1=2, E_2=2, E_3=2, E_4=2, E_5=2, E_6=2, E_7=2, M_E=2, T1_E=2, T2_E=2, T3_E=2, T4_E=2, T5_E=2, T6_E=2, T7_E=2, m_i=1, m_pc=0, m_st=0, t1_i=1, t1_pc=0, t1_st=0, t2_i=1, t2_pc=0, t2_st=0, t3_i=1, t3_pc=0, t3_st=0, t4_i=1, t4_pc=0, t4_st=0, t5_i=1, t5_pc=0, t5_st=0, t6_i=1, t6_pc=0, t6_st=0, t7_i=1, t7_pc=0, t7_st=0] Loop: [L621] COND TRUE 1 [L624] CALL, EXPR exists_runnable_thread() [L566] int __retres1 ; [L569] COND TRUE m_st == 0 [L570] __retres1 = 1 [L612] return (__retres1); [L624] RET, EXPR exists_runnable_thread() [L624] tmp = exists_runnable_thread() [L626] COND TRUE \read(tmp) [L631] COND TRUE m_st == 0 [L632] int tmp_ndt_1; [L633] EXPR tmp_ndt_1 = __VERIFIER_nondet_int() [L634] COND FALSE, EXPR !(\read(tmp_ndt_1)) [L631-L642] { int tmp_ndt_1; tmp_ndt_1 = __VERIFIER_nondet_int(); if (tmp_ndt_1) { { m_st = 1; master(); } } else { } } [L645] COND TRUE t1_st == 0 [L646] int tmp_ndt_2; [L647] EXPR tmp_ndt_2 = __VERIFIER_nondet_int() [L648] COND FALSE, EXPR !(\read(tmp_ndt_2)) [L645-L656] { int tmp_ndt_2; tmp_ndt_2 = __VERIFIER_nondet_int(); if (tmp_ndt_2) { { t1_st = 1; transmit1(); } } else { } } [L659] COND TRUE t2_st == 0 [L660] int tmp_ndt_3; [L661] EXPR tmp_ndt_3 = __VERIFIER_nondet_int() [L662] COND FALSE, EXPR !(\read(tmp_ndt_3)) [L659-L670] { int tmp_ndt_3; tmp_ndt_3 = __VERIFIER_nondet_int(); if (tmp_ndt_3) { { t2_st = 1; transmit2(); } } else { } } [L673] COND TRUE t3_st == 0 [L674] int tmp_ndt_4; [L675] EXPR tmp_ndt_4 = __VERIFIER_nondet_int() [L676] COND FALSE, EXPR !(\read(tmp_ndt_4)) [L673-L684] { int tmp_ndt_4; tmp_ndt_4 = __VERIFIER_nondet_int(); if (tmp_ndt_4) { { t3_st = 1; transmit3(); } } else { } } [L687] COND TRUE t4_st == 0 [L688] int tmp_ndt_5; [L689] EXPR tmp_ndt_5 = __VERIFIER_nondet_int() [L690] COND FALSE, EXPR !(\read(tmp_ndt_5)) [L687-L698] { int tmp_ndt_5; tmp_ndt_5 = __VERIFIER_nondet_int(); if (tmp_ndt_5) { { t4_st = 1; transmit4(); } } else { } } [L701] COND TRUE t5_st == 0 [L702] int tmp_ndt_6; [L703] EXPR tmp_ndt_6 = __VERIFIER_nondet_int() [L704] COND FALSE, EXPR !(\read(tmp_ndt_6)) [L701-L712] { int tmp_ndt_6; tmp_ndt_6 = __VERIFIER_nondet_int(); if (tmp_ndt_6) { { t5_st = 1; transmit5(); } } else { } } [L715] COND TRUE t6_st == 0 [L716] int tmp_ndt_7; [L717] EXPR tmp_ndt_7 = __VERIFIER_nondet_int() [L718] COND FALSE, EXPR !(\read(tmp_ndt_7)) [L715-L726] { int tmp_ndt_7; tmp_ndt_7 = __VERIFIER_nondet_int(); if (tmp_ndt_7) { { t6_st = 1; transmit6(); } } else { } } [L729] COND TRUE t7_st == 0 [L730] int tmp_ndt_8; [L731] EXPR tmp_ndt_8 = __VERIFIER_nondet_int() [L732] COND FALSE, EXPR !(\read(tmp_ndt_8)) [L729-L740] { int tmp_ndt_8; tmp_ndt_8 = __VERIFIER_nondet_int(); if (tmp_ndt_8) { { t7_st = 1; transmit7(); } } else { } } End of lasso representation. RESULT: Ultimate proved your program to be incorrect! [2023-11-29 01:11:48,899 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_f0879d48-ed61-40eb-8c1e-54e5e202b98d/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Forceful destruction successful, exit code 0 Received shutdown request... --- End real Ultimate output --- Execution finished normally Writing output log to file Ultimate.log Writing human readable error path to file UltimateCounterExample.errorpath Result: FALSE(TERM)