./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.08.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.08.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-28 20:20:41,137 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-28 20:20:41,201 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-28 20:20:41,207 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-28 20:20:41,207 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-28 20:20:41,232 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-28 20:20:41,233 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-28 20:20:41,234 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-28 20:20:41,235 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-28 20:20:41,235 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-28 20:20:41,236 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-28 20:20:41,237 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-28 20:20:41,237 INFO L153 SettingsManager]: * Use SBE=true [2023-11-28 20:20:41,238 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-28 20:20:41,239 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-28 20:20:41,239 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-28 20:20:41,240 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-28 20:20:41,240 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-28 20:20:41,241 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-28 20:20:41,242 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-28 20:20:41,242 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-28 20:20:41,243 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-28 20:20:41,243 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-28 20:20:41,244 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-28 20:20:41,244 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-28 20:20:41,260 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-28 20:20:41,260 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-28 20:20:41,261 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-28 20:20:41,261 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-28 20:20:41,262 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-28 20:20:41,262 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-28 20:20:41,262 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-28 20:20:41,263 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-28 20:20:41,263 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-28 20:20:41,263 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-28 20:20:41,264 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-28 20:20:41,264 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-28 20:20:41,265 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-28 20:20:41,265 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> d0fbb3eaba725aed5c3b8bf09c66f0f1daed4feeee0b9a3792dc033de334e501 [2023-11-28 20:20:41,489 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-28 20:20:41,506 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-28 20:20:41,509 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-28 20:20:41,510 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-28 20:20:41,510 INFO L274 PluginConnector]: CDTParser initialized [2023-11-28 20:20:41,511 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/transmitter.08.cil.c [2023-11-28 20:20:44,268 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-28 20:20:44,462 INFO L384 CDTParser]: Found 1 translation units. [2023-11-28 20:20:44,463 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/sv-benchmarks/c/systemc/transmitter.08.cil.c [2023-11-28 20:20:44,475 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/data/8e8df4904/1b48c0aaaaaa4d758920e65c061bebfc/FLAG7b8035f6a [2023-11-28 20:20:44,486 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/data/8e8df4904/1b48c0aaaaaa4d758920e65c061bebfc [2023-11-28 20:20:44,488 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-28 20:20:44,489 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-28 20:20:44,491 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-28 20:20:44,491 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-28 20:20:44,496 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-28 20:20:44,497 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:44,498 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@7d7c1a37 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44, skipping insertion in model container [2023-11-28 20:20:44,498 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:44,554 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-28 20:20:44,777 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-28 20:20:44,789 INFO L202 MainTranslator]: Completed pre-run [2023-11-28 20:20:44,844 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-28 20:20:44,866 INFO L206 MainTranslator]: Completed translation [2023-11-28 20:20:44,866 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44 WrapperNode [2023-11-28 20:20:44,866 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-28 20:20:44,868 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-28 20:20:44,868 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-28 20:20:44,868 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-28 20:20:44,876 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:44,888 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:44,954 INFO L138 Inliner]: procedures = 44, calls = 55, calls flagged for inlining = 50, calls inlined = 147, statements flattened = 2216 [2023-11-28 20:20:44,954 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-28 20:20:44,955 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-28 20:20:44,955 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-28 20:20:44,955 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-28 20:20:44,965 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:44,965 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:44,973 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:45,000 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-28 20:20:45,001 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:45,001 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:45,031 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:45,076 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:45,080 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:45,089 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:45,099 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-28 20:20:45,100 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-28 20:20:45,101 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-28 20:20:45,101 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-28 20:20:45,102 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (1/1) ... [2023-11-28 20:20:45,108 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:20:45,119 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:20:45,134 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:20:45,141 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-28 20:20:45,171 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-28 20:20:45,172 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-28 20:20:45,172 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-28 20:20:45,172 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-28 20:20:45,274 INFO L241 CfgBuilder]: Building ICFG [2023-11-28 20:20:45,276 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-28 20:20:46,497 INFO L282 CfgBuilder]: Performing block encoding [2023-11-28 20:20:46,529 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-28 20:20:46,529 INFO L309 CfgBuilder]: Removed 12 assume(true) statements. [2023-11-28 20:20:46,532 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 08:20:46 BoogieIcfgContainer [2023-11-28 20:20:46,532 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-28 20:20:46,533 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-28 20:20:46,533 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-28 20:20:46,537 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-28 20:20:46,538 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-28 20:20:46,538 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 28.11 08:20:44" (1/3) ... [2023-11-28 20:20:46,540 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@62ce7b89 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 08:20:46, skipping insertion in model container [2023-11-28 20:20:46,540 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-28 20:20:46,540 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 28.11 08:20:44" (2/3) ... [2023-11-28 20:20:46,540 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@62ce7b89 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 28.11 08:20:46, skipping insertion in model container [2023-11-28 20:20:46,540 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-28 20:20:46,541 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 28.11 08:20:46" (3/3) ... [2023-11-28 20:20:46,542 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.08.cil.c [2023-11-28 20:20:46,628 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-28 20:20:46,628 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-28 20:20:46,629 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-28 20:20:46,629 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-28 20:20:46,629 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-28 20:20:46,629 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-28 20:20:46,629 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-28 20:20:46,630 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-28 20:20:46,638 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:46,697 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2023-11-28 20:20:46,698 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:46,698 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:46,709 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:46,710 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:46,710 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-28 20:20:46,712 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:46,726 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 824 [2023-11-28 20:20:46,726 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:46,727 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:46,732 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:46,732 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:46,743 INFO L748 eck$LassoCheckResult]: Stem: 126#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 859#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 683#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 855#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 685#L581true assume !(1 == ~m_i~0);~m_st~0 := 2; 193#L581-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 827#L586-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 676#L591-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 652#L596-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 239#L601-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 686#L606-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 413#L611-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 771#L616-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 295#L621-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 713#L838true assume !(0 == ~M_E~0); 422#L838-2true assume !(0 == ~T1_E~0); 25#L843-1true assume !(0 == ~T2_E~0); 83#L848-1true assume !(0 == ~T3_E~0); 435#L853-1true assume !(0 == ~T4_E~0); 287#L858-1true assume 0 == ~T5_E~0;~T5_E~0 := 1; 2#L863-1true assume !(0 == ~T6_E~0); 764#L868-1true assume !(0 == ~T7_E~0); 884#L873-1true assume !(0 == ~T8_E~0); 758#L878-1true assume !(0 == ~E_1~0); 722#L883-1true assume !(0 == ~E_2~0); 797#L888-1true assume !(0 == ~E_3~0); 390#L893-1true assume !(0 == ~E_4~0); 798#L898-1true assume 0 == ~E_5~0;~E_5~0 := 1; 928#L903-1true assume !(0 == ~E_6~0); 719#L908-1true assume !(0 == ~E_7~0); 506#L913-1true assume !(0 == ~E_8~0); 30#L918-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 525#L402true assume !(1 == ~m_pc~0); 271#L402-2true is_master_triggered_~__retres1~0#1 := 0; 96#L413true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 575#is_master_triggered_returnLabel#1true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 243#L1035true assume !(0 != activate_threads_~tmp~1#1); 279#L1035-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 710#L421true assume 1 == ~t1_pc~0; 826#L422true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 900#L432true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 32#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 315#L1043true assume !(0 != activate_threads_~tmp___0~0#1); 787#L1043-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912#L440true assume 1 == ~t2_pc~0; 18#L441true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 101#L451true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 209#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 833#L1051true assume !(0 != activate_threads_~tmp___1~0#1); 527#L1051-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 213#L459true assume !(1 == ~t3_pc~0); 702#L459-2true is_transmit3_triggered_~__retres1~3#1 := 0; 782#L470true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 93#L1059true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 934#L1059-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 98#L478true assume 1 == ~t4_pc~0; 394#L479true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 674#L489true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 67#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 198#L1067true assume !(0 != activate_threads_~tmp___3~0#1); 50#L1067-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 432#L497true assume !(1 == ~t5_pc~0); 361#L497-2true is_transmit5_triggered_~__retres1~5#1 := 0; 458#L508true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 577#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 788#L1075true assume !(0 != activate_threads_~tmp___4~0#1); 696#L1075-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 891#L516true assume 1 == ~t6_pc~0; 892#L517true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 412#L527true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 199#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 123#L1083true assume !(0 != activate_threads_~tmp___5~0#1); 472#L1083-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 406#L535true assume !(1 == ~t7_pc~0); 802#L535-2true is_transmit7_triggered_~__retres1~7#1 := 0; 470#L546true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 870#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 500#L1091true assume !(0 != activate_threads_~tmp___6~0#1); 493#L1091-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 687#L554true assume 1 == ~t8_pc~0; 438#L555true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 828#L565true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 518#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 171#L1099true assume !(0 != activate_threads_~tmp___7~0#1); 501#L1099-2true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7#L931true assume !(1 == ~M_E~0); 743#L931-2true assume 1 == ~T1_E~0;~T1_E~0 := 2; 824#L936-1true assume !(1 == ~T2_E~0); 909#L941-1true assume !(1 == ~T3_E~0); 280#L946-1true assume !(1 == ~T4_E~0); 707#L951-1true assume !(1 == ~T5_E~0); 131#L956-1true assume !(1 == ~T6_E~0); 893#L961-1true assume !(1 == ~T7_E~0); 391#L966-1true assume !(1 == ~T8_E~0); 495#L971-1true assume 1 == ~E_1~0;~E_1~0 := 2; 845#L976-1true assume !(1 == ~E_2~0); 463#L981-1true assume !(1 == ~E_3~0); 283#L986-1true assume !(1 == ~E_4~0); 146#L991-1true assume !(1 == ~E_5~0); 874#L996-1true assume !(1 == ~E_6~0); 776#L1001-1true assume !(1 == ~E_7~0); 431#L1006-1true assume !(1 == ~E_8~0); 708#L1011-1true assume { :end_inline_reset_delta_events } true; 36#L1272-2true [2023-11-28 20:20:46,746 INFO L750 eck$LassoCheckResult]: Loop: 36#L1272-2true assume !false; 427#L1273true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 837#L813-1true assume false; 524#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 316#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 657#L838-3true assume 0 == ~M_E~0;~M_E~0 := 1; 478#L838-5true assume !(0 == ~T1_E~0); 808#L843-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 350#L848-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 392#L853-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 585#L858-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 452#L863-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 442#L868-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 461#L873-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 160#L878-3true assume !(0 == ~E_1~0); 19#L883-3true assume 0 == ~E_2~0;~E_2~0 := 1; 671#L888-3true assume 0 == ~E_3~0;~E_3~0 := 1; 20#L893-3true assume 0 == ~E_4~0;~E_4~0 := 1; 298#L898-3true assume 0 == ~E_5~0;~E_5~0 := 1; 606#L903-3true assume 0 == ~E_6~0;~E_6~0 := 1; 796#L908-3true assume 0 == ~E_7~0;~E_7~0 := 1; 303#L913-3true assume 0 == ~E_8~0;~E_8~0 := 1; 38#L918-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 902#L402-27true assume 1 == ~m_pc~0; 14#L403-9true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 850#L413-9true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 471#is_master_triggered_returnLabel#10true activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 748#L1035-27true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 640#L1035-29true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 673#L421-27true assume 1 == ~t1_pc~0; 504#L422-9true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 832#L432-9true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 374#is_transmit1_triggered_returnLabel#10true activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 777#L1043-27true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 898#L1043-29true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 407#L440-27true assume 1 == ~t2_pc~0; 880#L441-9true assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 940#L451-9true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 446#is_transmit2_triggered_returnLabel#10true activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 330#L1051-27true assume !(0 != activate_threads_~tmp___1~0#1); 420#L1051-29true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 148#L459-27true assume !(1 == ~t3_pc~0); 662#L459-29true is_transmit3_triggered_~__retres1~3#1 := 0; 847#L470-9true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 312#is_transmit3_triggered_returnLabel#10true activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 405#L1059-27true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 762#L1059-29true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 895#L478-27true assume !(1 == ~t4_pc~0); 141#L478-29true is_transmit4_triggered_~__retres1~4#1 := 0; 414#L489-9true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 252#is_transmit4_triggered_returnLabel#10true activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 555#L1067-27true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 763#L1067-29true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 607#L497-27true assume 1 == ~t5_pc~0; 840#L498-9true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 166#L508-9true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 602#is_transmit5_triggered_returnLabel#10true activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134#L1075-27true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 678#L1075-29true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 300#L516-27true assume !(1 == ~t6_pc~0); 418#L516-29true is_transmit6_triggered_~__retres1~6#1 := 0; 203#L527-9true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752#is_transmit6_triggered_returnLabel#10true activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 424#L1083-27true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 774#L1083-29true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 254#L535-27true assume !(1 == ~t7_pc~0); 534#L535-29true is_transmit7_triggered_~__retres1~7#1 := 0; 937#L546-9true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180#is_transmit7_triggered_returnLabel#10true activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 842#L1091-27true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 225#L1091-29true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 786#L554-27true assume !(1 == ~t8_pc~0); 26#L554-29true is_transmit8_triggered_~__retres1~8#1 := 0; 100#L565-9true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 550#is_transmit8_triggered_returnLabel#10true activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 335#L1099-27true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 158#L1099-29true havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 529#L931-3true assume 1 == ~M_E~0;~M_E~0 := 2; 91#L931-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 223#L936-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 311#L941-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 531#L946-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 168#L951-3true assume !(1 == ~T5_E~0); 513#L956-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 371#L961-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 232#L966-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 726#L971-3true assume 1 == ~E_1~0;~E_1~0 := 2; 411#L976-3true assume 1 == ~E_2~0;~E_2~0 := 2; 35#L981-3true assume 1 == ~E_3~0;~E_3~0 := 2; 159#L986-3true assume 1 == ~E_4~0;~E_4~0 := 2; 29#L991-3true assume !(1 == ~E_5~0); 482#L996-3true assume 1 == ~E_6~0;~E_6~0 := 2; 611#L1001-3true assume 1 == ~E_7~0;~E_7~0 := 2; 215#L1006-3true assume 1 == ~E_8~0;~E_8~0 := 2; 516#L1011-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 48#L634-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 314#L681-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 183#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 792#L1291true assume !(0 == start_simulation_~tmp~3#1); 759#L1291-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 293#L634-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4#L681-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 31#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 730#L1246true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 267#L1253true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 329#stop_simulation_returnLabel#1true start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 556#L1304true assume !(0 != start_simulation_~tmp___0~1#1); 36#L1272-2true [2023-11-28 20:20:46,755 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:46,755 INFO L85 PathProgramCache]: Analyzing trace with hash -1897256038, now seen corresponding path program 1 times [2023-11-28 20:20:46,765 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:46,766 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [941447850] [2023-11-28 20:20:46,766 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:46,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:46,888 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:47,055 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:47,056 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:47,056 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [941447850] [2023-11-28 20:20:47,057 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [941447850] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:47,057 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:47,057 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:47,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1738597920] [2023-11-28 20:20:47,060 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:47,064 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:47,065 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:47,066 INFO L85 PathProgramCache]: Analyzing trace with hash -651940443, now seen corresponding path program 1 times [2023-11-28 20:20:47,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:47,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [175275610] [2023-11-28 20:20:47,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:47,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:47,086 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:47,129 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:47,129 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:47,129 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [175275610] [2023-11-28 20:20:47,130 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [175275610] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:47,130 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:47,130 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:20:47,131 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1793297005] [2023-11-28 20:20:47,131 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:47,132 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:47,133 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:47,168 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:47,169 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:47,173 INFO L87 Difference]: Start difference. First operand has 941 states, 940 states have (on average 1.5127659574468084) internal successors, (1422), 940 states have internal predecessors, (1422), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:47,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:47,246 INFO L93 Difference]: Finished difference Result 939 states and 1394 transitions. [2023-11-28 20:20:47,248 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 939 states and 1394 transitions. [2023-11-28 20:20:47,259 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:47,274 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 939 states to 933 states and 1388 transitions. [2023-11-28 20:20:47,275 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-28 20:20:47,277 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-28 20:20:47,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1388 transitions. [2023-11-28 20:20:47,285 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:47,285 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1388 transitions. [2023-11-28 20:20:47,306 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1388 transitions. [2023-11-28 20:20:47,348 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-28 20:20:47,351 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.487674169346195) internal successors, (1388), 932 states have internal predecessors, (1388), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:47,355 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1388 transitions. [2023-11-28 20:20:47,356 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1388 transitions. [2023-11-28 20:20:47,357 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:47,361 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1388 transitions. [2023-11-28 20:20:47,362 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-28 20:20:47,362 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1388 transitions. [2023-11-28 20:20:47,369 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:47,369 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:47,369 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:47,372 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:47,373 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:47,373 INFO L748 eck$LassoCheckResult]: Stem: 2139#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2140#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2766#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2767#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2768#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2258#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2259#L586-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 2764#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2760#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2330#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2331#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 2565#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 2566#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2414#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2415#L838 assume !(0 == ~M_E~0); 2573#L838-2 assume !(0 == ~T1_E~0); 1938#L843-1 assume !(0 == ~T2_E~0); 1939#L848-1 assume !(0 == ~T3_E~0); 2059#L853-1 assume !(0 == ~T4_E~0); 2401#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1889#L863-1 assume !(0 == ~T6_E~0); 1890#L868-1 assume !(0 == ~T7_E~0); 2796#L873-1 assume !(0 == ~T8_E~0); 2794#L878-1 assume !(0 == ~E_1~0); 2785#L883-1 assume !(0 == ~E_2~0); 2786#L888-1 assume !(0 == ~E_3~0); 2534#L893-1 assume !(0 == ~E_4~0); 2535#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 2806#L903-1 assume !(0 == ~E_6~0); 2783#L908-1 assume !(0 == ~E_7~0); 2664#L913-1 assume !(0 == ~E_8~0); 1950#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1951#L402 assume !(1 == ~m_pc~0); 2162#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2083#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2084#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2336#L1035 assume !(0 != activate_threads_~tmp~1#1); 2337#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2389#L421 assume 1 == ~t1_pc~0; 2779#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2797#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1953#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1954#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2443#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2804#L440 assume 1 == ~t2_pc~0; 1922#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1923#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2093#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2284#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2679#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2287#L459 assume !(1 == ~t3_pc~0); 2288#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2777#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1911#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1912#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2078#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2087#L478 assume 1 == ~t4_pc~0; 2088#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2539#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2031#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2032#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1992#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1993#L497 assume !(1 == ~t5_pc~0); 2042#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2043#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2610#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2716#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2773#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2774#L516 assume 1 == ~t6_pc~0; 2820#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2564#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2267#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2133#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2134#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2553#L535 assume !(1 == ~t7_pc~0); 2554#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2624#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2625#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2656#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2646#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2647#L554 assume 1 == ~t8_pc~0; 2589#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 1914#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2672#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2221#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2222#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1900#L931 assume !(1 == ~M_E~0); 1901#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2792#L936-1 assume !(1 == ~T2_E~0); 2811#L941-1 assume !(1 == ~T3_E~0); 2390#L946-1 assume !(1 == ~T4_E~0); 2391#L951-1 assume !(1 == ~T5_E~0); 2148#L956-1 assume !(1 == ~T6_E~0); 2149#L961-1 assume !(1 == ~T7_E~0); 2536#L966-1 assume !(1 == ~T8_E~0); 2537#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 2649#L976-1 assume !(1 == ~E_2~0); 2614#L981-1 assume !(1 == ~E_3~0); 2394#L986-1 assume !(1 == ~E_4~0); 2175#L991-1 assume !(1 == ~E_5~0); 2176#L996-1 assume !(1 == ~E_6~0); 2801#L1001-1 assume !(1 == ~E_7~0); 2584#L1006-1 assume !(1 == ~E_8~0); 2585#L1011-1 assume { :end_inline_reset_delta_events } true; 1961#L1272-2 [2023-11-28 20:20:47,374 INFO L750 eck$LassoCheckResult]: Loop: 1961#L1272-2 assume !false; 1962#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2198#L813-1 assume !false; 2734#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2735#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1964#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2303#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2304#L696 assume !(0 != eval_~tmp~0#1); 2677#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2444#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2445#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2633#L838-5 assume !(0 == ~T1_E~0); 2634#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2487#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2488#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2538#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2603#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2593#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2594#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2202#L878-3 assume !(0 == ~E_1~0); 1925#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1926#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1927#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1928#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2420#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2736#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2428#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1966#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1967#L402-27 assume 1 == ~m_pc~0; 1915#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1916#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2626#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2627#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2753#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2754#L421-27 assume !(1 == ~t1_pc~0); 2192#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2193#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2512#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2513#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2802#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2556#L440-27 assume !(1 == ~t2_pc~0); 2557#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 2731#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2598#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2463#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 2464#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2178#L459-27 assume 1 == ~t3_pc~0; 2179#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2619#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2440#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2441#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2552#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2795#L478-27 assume !(1 == ~t4_pc~0); 2167#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2168#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2351#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2352#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2701#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2737#L497-27 assume 1 == ~t5_pc~0; 2738#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2211#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2212#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2154#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2155#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2422#L516-27 assume !(1 == ~t6_pc~0); 2423#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2275#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2276#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2575#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2576#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2355#L535-27 assume 1 == ~t7_pc~0; 2356#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2685#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2235#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2236#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2306#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2307#L554-27 assume !(1 == ~t8_pc~0); 1940#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1941#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2092#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2472#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2199#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2200#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2074#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2075#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 2305#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2439#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2215#L951-3 assume !(1 == ~T5_E~0); 2216#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2510#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2315#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2316#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 2563#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1959#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1960#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1948#L991-3 assume !(1 == ~E_5~0); 1949#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2639#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2292#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2293#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1987#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1988#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2241#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2242#L1291 assume !(0 == start_simulation_~tmp~3#1); 2507#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2410#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1893#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1894#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1952#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2376#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2377#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2462#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1961#L1272-2 [2023-11-28 20:20:47,375 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:47,375 INFO L85 PathProgramCache]: Analyzing trace with hash 500214492, now seen corresponding path program 1 times [2023-11-28 20:20:47,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:47,376 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1957380192] [2023-11-28 20:20:47,376 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:47,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:47,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:47,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:47,448 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:47,448 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1957380192] [2023-11-28 20:20:47,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1957380192] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:47,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:47,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:47,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [104333032] [2023-11-28 20:20:47,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:47,467 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:47,468 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:47,468 INFO L85 PathProgramCache]: Analyzing trace with hash 56067214, now seen corresponding path program 1 times [2023-11-28 20:20:47,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:47,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1464938827] [2023-11-28 20:20:47,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:47,469 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:47,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:47,573 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:47,573 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:47,573 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1464938827] [2023-11-28 20:20:47,574 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1464938827] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:47,574 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:47,574 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:47,574 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1062639189] [2023-11-28 20:20:47,574 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:47,575 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:47,575 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:47,576 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:47,576 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:47,576 INFO L87 Difference]: Start difference. First operand 933 states and 1388 transitions. cyclomatic complexity: 456 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:47,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:47,598 INFO L93 Difference]: Finished difference Result 933 states and 1387 transitions. [2023-11-28 20:20:47,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1387 transitions. [2023-11-28 20:20:47,604 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:47,609 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1387 transitions. [2023-11-28 20:20:47,610 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-28 20:20:47,610 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-28 20:20:47,611 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1387 transitions. [2023-11-28 20:20:47,612 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:47,612 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1387 transitions. [2023-11-28 20:20:47,614 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1387 transitions. [2023-11-28 20:20:47,623 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-28 20:20:47,624 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4866023579849947) internal successors, (1387), 932 states have internal predecessors, (1387), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:47,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1387 transitions. [2023-11-28 20:20:47,627 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1387 transitions. [2023-11-28 20:20:47,627 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:47,628 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1387 transitions. [2023-11-28 20:20:47,628 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-28 20:20:47,629 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1387 transitions. [2023-11-28 20:20:47,633 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:47,633 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:47,633 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:47,635 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:47,636 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:47,636 INFO L748 eck$LassoCheckResult]: Stem: 4012#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4013#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4639#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4640#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4641#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4131#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4132#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4637#L591-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 4633#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 4203#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 4204#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 4438#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 4439#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 4287#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4288#L838 assume !(0 == ~M_E~0); 4446#L838-2 assume !(0 == ~T1_E~0); 3811#L843-1 assume !(0 == ~T2_E~0); 3812#L848-1 assume !(0 == ~T3_E~0); 3932#L853-1 assume !(0 == ~T4_E~0); 4274#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3762#L863-1 assume !(0 == ~T6_E~0); 3763#L868-1 assume !(0 == ~T7_E~0); 4669#L873-1 assume !(0 == ~T8_E~0); 4667#L878-1 assume !(0 == ~E_1~0); 4658#L883-1 assume !(0 == ~E_2~0); 4659#L888-1 assume !(0 == ~E_3~0); 4407#L893-1 assume !(0 == ~E_4~0); 4408#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 4679#L903-1 assume !(0 == ~E_6~0); 4656#L908-1 assume !(0 == ~E_7~0); 4537#L913-1 assume !(0 == ~E_8~0); 3823#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3824#L402 assume !(1 == ~m_pc~0); 4035#L402-2 is_master_triggered_~__retres1~0#1 := 0; 3956#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3957#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4209#L1035 assume !(0 != activate_threads_~tmp~1#1); 4210#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4262#L421 assume 1 == ~t1_pc~0; 4652#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 4670#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3826#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3827#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4316#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4677#L440 assume 1 == ~t2_pc~0; 3795#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3796#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3966#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4157#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4552#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4160#L459 assume !(1 == ~t3_pc~0); 4161#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4650#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3784#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3785#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3951#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3960#L478 assume 1 == ~t4_pc~0; 3961#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4412#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3904#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3905#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 3865#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3866#L497 assume !(1 == ~t5_pc~0); 3915#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3916#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4483#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4589#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4646#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4647#L516 assume 1 == ~t6_pc~0; 4693#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4437#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4140#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4006#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 4007#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4426#L535 assume !(1 == ~t7_pc~0); 4427#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4497#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4498#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4529#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4519#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4520#L554 assume 1 == ~t8_pc~0; 4462#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3787#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4545#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4094#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4095#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3773#L931 assume !(1 == ~M_E~0); 3774#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4665#L936-1 assume !(1 == ~T2_E~0); 4684#L941-1 assume !(1 == ~T3_E~0); 4263#L946-1 assume !(1 == ~T4_E~0); 4264#L951-1 assume !(1 == ~T5_E~0); 4021#L956-1 assume !(1 == ~T6_E~0); 4022#L961-1 assume !(1 == ~T7_E~0); 4409#L966-1 assume !(1 == ~T8_E~0); 4410#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 4522#L976-1 assume !(1 == ~E_2~0); 4487#L981-1 assume !(1 == ~E_3~0); 4267#L986-1 assume !(1 == ~E_4~0); 4048#L991-1 assume !(1 == ~E_5~0); 4049#L996-1 assume !(1 == ~E_6~0); 4674#L1001-1 assume !(1 == ~E_7~0); 4457#L1006-1 assume !(1 == ~E_8~0); 4458#L1011-1 assume { :end_inline_reset_delta_events } true; 3834#L1272-2 [2023-11-28 20:20:47,637 INFO L750 eck$LassoCheckResult]: Loop: 3834#L1272-2 assume !false; 3835#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4071#L813-1 assume !false; 4607#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4608#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3837#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4176#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4177#L696 assume !(0 != eval_~tmp~0#1); 4550#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4317#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4318#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 4506#L838-5 assume !(0 == ~T1_E~0); 4507#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4360#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4361#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4411#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4476#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4466#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4467#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4075#L878-3 assume !(0 == ~E_1~0); 3798#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3799#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3800#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3801#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4293#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4609#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4301#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3839#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3840#L402-27 assume 1 == ~m_pc~0; 3788#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3789#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4499#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4500#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4626#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4627#L421-27 assume !(1 == ~t1_pc~0); 4065#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 4066#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4385#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4386#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4675#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4429#L440-27 assume !(1 == ~t2_pc~0); 4430#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 4604#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4471#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4336#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 4337#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4051#L459-27 assume 1 == ~t3_pc~0; 4052#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4492#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4313#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4314#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4425#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4668#L478-27 assume !(1 == ~t4_pc~0); 4040#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 4041#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4224#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4225#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4574#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4610#L497-27 assume 1 == ~t5_pc~0; 4611#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4084#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4085#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4027#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4028#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4295#L516-27 assume !(1 == ~t6_pc~0); 4296#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 4148#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4149#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4448#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4449#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4228#L535-27 assume 1 == ~t7_pc~0; 4229#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4558#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4108#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4109#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4179#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4180#L554-27 assume !(1 == ~t8_pc~0); 3813#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 3814#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3965#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4345#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4072#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4073#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3947#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3948#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 4178#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4312#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4088#L951-3 assume !(1 == ~T5_E~0); 4089#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4383#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4188#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4189#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 4436#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3832#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3833#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3821#L991-3 assume !(1 == ~E_5~0); 3822#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4512#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4165#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4166#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3860#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3861#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4114#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 4115#L1291 assume !(0 == start_simulation_~tmp~3#1); 4380#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4283#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3766#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3767#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 3825#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4249#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4250#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4335#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 3834#L1272-2 [2023-11-28 20:20:47,637 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:47,637 INFO L85 PathProgramCache]: Analyzing trace with hash -1888349538, now seen corresponding path program 1 times [2023-11-28 20:20:47,638 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:47,638 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533896789] [2023-11-28 20:20:47,638 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:47,638 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:47,654 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:47,694 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:47,694 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:47,694 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533896789] [2023-11-28 20:20:47,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [533896789] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:47,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:47,695 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:47,695 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [220522547] [2023-11-28 20:20:47,695 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:47,696 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:47,696 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:47,697 INFO L85 PathProgramCache]: Analyzing trace with hash 56067214, now seen corresponding path program 2 times [2023-11-28 20:20:47,697 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:47,697 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [423219925] [2023-11-28 20:20:47,697 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:47,697 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:47,714 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:47,758 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:47,758 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:47,759 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [423219925] [2023-11-28 20:20:47,759 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [423219925] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:47,759 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:47,759 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:47,760 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [298202395] [2023-11-28 20:20:47,760 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:47,760 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:47,761 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:47,761 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:47,761 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:47,761 INFO L87 Difference]: Start difference. First operand 933 states and 1387 transitions. cyclomatic complexity: 455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:47,780 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:47,780 INFO L93 Difference]: Finished difference Result 933 states and 1386 transitions. [2023-11-28 20:20:47,781 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1386 transitions. [2023-11-28 20:20:47,785 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:47,790 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1386 transitions. [2023-11-28 20:20:47,791 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-28 20:20:47,791 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-28 20:20:47,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1386 transitions. [2023-11-28 20:20:47,793 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:47,793 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1386 transitions. [2023-11-28 20:20:47,794 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1386 transitions. [2023-11-28 20:20:47,803 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-28 20:20:47,804 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4855305466237942) internal successors, (1386), 932 states have internal predecessors, (1386), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:47,807 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1386 transitions. [2023-11-28 20:20:47,807 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1386 transitions. [2023-11-28 20:20:47,808 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:47,808 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1386 transitions. [2023-11-28 20:20:47,808 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-28 20:20:47,809 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1386 transitions. [2023-11-28 20:20:47,812 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:47,812 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:47,812 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:47,814 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:47,814 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:47,814 INFO L748 eck$LassoCheckResult]: Stem: 5885#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 5886#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6512#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6513#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6514#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 6004#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6005#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6510#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6506#L596-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 6076#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6077#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6311#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6312#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6160#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6161#L838 assume !(0 == ~M_E~0); 6319#L838-2 assume !(0 == ~T1_E~0); 5684#L843-1 assume !(0 == ~T2_E~0); 5685#L848-1 assume !(0 == ~T3_E~0); 5805#L853-1 assume !(0 == ~T4_E~0); 6147#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5635#L863-1 assume !(0 == ~T6_E~0); 5636#L868-1 assume !(0 == ~T7_E~0); 6542#L873-1 assume !(0 == ~T8_E~0); 6540#L878-1 assume !(0 == ~E_1~0); 6531#L883-1 assume !(0 == ~E_2~0); 6532#L888-1 assume !(0 == ~E_3~0); 6280#L893-1 assume !(0 == ~E_4~0); 6281#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 6552#L903-1 assume !(0 == ~E_6~0); 6529#L908-1 assume !(0 == ~E_7~0); 6410#L913-1 assume !(0 == ~E_8~0); 5696#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5697#L402 assume !(1 == ~m_pc~0); 5908#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5829#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5830#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6082#L1035 assume !(0 != activate_threads_~tmp~1#1); 6083#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6135#L421 assume 1 == ~t1_pc~0; 6525#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6543#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5699#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5700#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 6189#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6550#L440 assume 1 == ~t2_pc~0; 5668#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 5669#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5839#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6030#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 6425#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6033#L459 assume !(1 == ~t3_pc~0); 6034#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6523#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5657#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5658#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5824#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5833#L478 assume 1 == ~t4_pc~0; 5834#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6285#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5777#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5778#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5738#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5739#L497 assume !(1 == ~t5_pc~0); 5788#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5789#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6356#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6462#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 6519#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6520#L516 assume 1 == ~t6_pc~0; 6566#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6310#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6013#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5879#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5880#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6299#L535 assume !(1 == ~t7_pc~0); 6300#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6370#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6371#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6402#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 6392#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6393#L554 assume 1 == ~t8_pc~0; 6335#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5660#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6418#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5967#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5968#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5646#L931 assume !(1 == ~M_E~0); 5647#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6538#L936-1 assume !(1 == ~T2_E~0); 6557#L941-1 assume !(1 == ~T3_E~0); 6136#L946-1 assume !(1 == ~T4_E~0); 6137#L951-1 assume !(1 == ~T5_E~0); 5894#L956-1 assume !(1 == ~T6_E~0); 5895#L961-1 assume !(1 == ~T7_E~0); 6282#L966-1 assume !(1 == ~T8_E~0); 6283#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 6395#L976-1 assume !(1 == ~E_2~0); 6360#L981-1 assume !(1 == ~E_3~0); 6140#L986-1 assume !(1 == ~E_4~0); 5921#L991-1 assume !(1 == ~E_5~0); 5922#L996-1 assume !(1 == ~E_6~0); 6547#L1001-1 assume !(1 == ~E_7~0); 6330#L1006-1 assume !(1 == ~E_8~0); 6331#L1011-1 assume { :end_inline_reset_delta_events } true; 5707#L1272-2 [2023-11-28 20:20:47,815 INFO L750 eck$LassoCheckResult]: Loop: 5707#L1272-2 assume !false; 5708#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5944#L813-1 assume !false; 6480#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6481#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5710#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6049#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6050#L696 assume !(0 != eval_~tmp~0#1); 6423#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6190#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6191#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 6379#L838-5 assume !(0 == ~T1_E~0); 6380#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6233#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6234#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6284#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6349#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6339#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6340#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5948#L878-3 assume !(0 == ~E_1~0); 5671#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5672#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5673#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5674#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6166#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 6482#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6174#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5712#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5713#L402-27 assume 1 == ~m_pc~0; 5661#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5662#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6372#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6373#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6499#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6500#L421-27 assume !(1 == ~t1_pc~0); 5938#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 5939#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6258#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6259#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 6548#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6302#L440-27 assume 1 == ~t2_pc~0; 6304#L441-9 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6477#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6344#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6209#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 6210#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5924#L459-27 assume 1 == ~t3_pc~0; 5925#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6365#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6186#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6187#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6298#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6541#L478-27 assume 1 == ~t4_pc~0; 6560#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5914#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6097#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6098#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6447#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6483#L497-27 assume 1 == ~t5_pc~0; 6484#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5957#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5958#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5900#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5901#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6168#L516-27 assume !(1 == ~t6_pc~0); 6169#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 6021#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6022#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6321#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6322#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6101#L535-27 assume 1 == ~t7_pc~0; 6102#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6431#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5981#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5982#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6052#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6053#L554-27 assume !(1 == ~t8_pc~0); 5686#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 5687#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5838#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6218#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5945#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5946#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5820#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5821#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6051#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 6185#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5961#L951-3 assume !(1 == ~T5_E~0); 5962#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 6256#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6061#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6062#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 6309#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5705#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5706#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5694#L991-3 assume !(1 == ~E_5~0); 5695#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6385#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6038#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6039#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5733#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5734#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5987#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 5988#L1291 assume !(0 == start_simulation_~tmp~3#1); 6253#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6156#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5639#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5640#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 5698#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6122#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6123#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 6208#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 5707#L1272-2 [2023-11-28 20:20:47,815 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:47,815 INFO L85 PathProgramCache]: Analyzing trace with hash 805546652, now seen corresponding path program 1 times [2023-11-28 20:20:47,816 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:47,816 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [906486627] [2023-11-28 20:20:47,816 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:47,816 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:47,828 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:47,854 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:47,854 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:47,854 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [906486627] [2023-11-28 20:20:47,854 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [906486627] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:47,855 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:47,855 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:47,855 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [634118392] [2023-11-28 20:20:47,855 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:47,856 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:47,856 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:47,856 INFO L85 PathProgramCache]: Analyzing trace with hash -1847000368, now seen corresponding path program 1 times [2023-11-28 20:20:47,856 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:47,857 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1133229449] [2023-11-28 20:20:47,857 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:47,857 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:47,869 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:47,922 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:47,922 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:47,922 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1133229449] [2023-11-28 20:20:47,922 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1133229449] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:47,923 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:47,923 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:47,923 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1136215042] [2023-11-28 20:20:47,923 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:47,923 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:47,924 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:47,924 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:47,924 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:47,924 INFO L87 Difference]: Start difference. First operand 933 states and 1386 transitions. cyclomatic complexity: 454 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:47,946 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:47,946 INFO L93 Difference]: Finished difference Result 933 states and 1385 transitions. [2023-11-28 20:20:47,946 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1385 transitions. [2023-11-28 20:20:47,951 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:47,956 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1385 transitions. [2023-11-28 20:20:47,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-28 20:20:47,957 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-28 20:20:47,957 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1385 transitions. [2023-11-28 20:20:47,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:47,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1385 transitions. [2023-11-28 20:20:47,960 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1385 transitions. [2023-11-28 20:20:47,969 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-28 20:20:47,971 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4844587352625938) internal successors, (1385), 932 states have internal predecessors, (1385), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:47,973 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1385 transitions. [2023-11-28 20:20:47,974 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1385 transitions. [2023-11-28 20:20:47,974 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:47,975 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1385 transitions. [2023-11-28 20:20:47,975 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-28 20:20:47,975 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1385 transitions. [2023-11-28 20:20:47,979 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:47,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:47,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:47,981 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:47,981 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:47,981 INFO L748 eck$LassoCheckResult]: Stem: 7758#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 7759#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 8385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8387#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 7877#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7878#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8383#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8379#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7949#L601-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7950#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8184#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8185#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8033#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8034#L838 assume !(0 == ~M_E~0); 8192#L838-2 assume !(0 == ~T1_E~0); 7557#L843-1 assume !(0 == ~T2_E~0); 7558#L848-1 assume !(0 == ~T3_E~0); 7678#L853-1 assume !(0 == ~T4_E~0); 8020#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7508#L863-1 assume !(0 == ~T6_E~0); 7509#L868-1 assume !(0 == ~T7_E~0); 8415#L873-1 assume !(0 == ~T8_E~0); 8413#L878-1 assume !(0 == ~E_1~0); 8404#L883-1 assume !(0 == ~E_2~0); 8405#L888-1 assume !(0 == ~E_3~0); 8153#L893-1 assume !(0 == ~E_4~0); 8154#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 8425#L903-1 assume !(0 == ~E_6~0); 8402#L908-1 assume !(0 == ~E_7~0); 8283#L913-1 assume !(0 == ~E_8~0); 7569#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7570#L402 assume !(1 == ~m_pc~0); 7781#L402-2 is_master_triggered_~__retres1~0#1 := 0; 7702#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7703#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7955#L1035 assume !(0 != activate_threads_~tmp~1#1); 7956#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8008#L421 assume 1 == ~t1_pc~0; 8398#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8416#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7572#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7573#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 8062#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8423#L440 assume 1 == ~t2_pc~0; 7541#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7542#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7712#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7903#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 8298#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7906#L459 assume !(1 == ~t3_pc~0); 7907#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8396#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7530#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7531#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7697#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7706#L478 assume 1 == ~t4_pc~0; 7707#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 8158#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7650#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7651#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 7611#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7612#L497 assume !(1 == ~t5_pc~0); 7661#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7662#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8229#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8335#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 8392#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8393#L516 assume 1 == ~t6_pc~0; 8439#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8183#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7886#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7752#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 7753#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8172#L535 assume !(1 == ~t7_pc~0); 8173#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8243#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8244#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8275#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 8265#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8266#L554 assume 1 == ~t8_pc~0; 8208#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7533#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8291#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7840#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 7841#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7519#L931 assume !(1 == ~M_E~0); 7520#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8411#L936-1 assume !(1 == ~T2_E~0); 8430#L941-1 assume !(1 == ~T3_E~0); 8009#L946-1 assume !(1 == ~T4_E~0); 8010#L951-1 assume !(1 == ~T5_E~0); 7767#L956-1 assume !(1 == ~T6_E~0); 7768#L961-1 assume !(1 == ~T7_E~0); 8155#L966-1 assume !(1 == ~T8_E~0); 8156#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 8268#L976-1 assume !(1 == ~E_2~0); 8233#L981-1 assume !(1 == ~E_3~0); 8013#L986-1 assume !(1 == ~E_4~0); 7794#L991-1 assume !(1 == ~E_5~0); 7795#L996-1 assume !(1 == ~E_6~0); 8420#L1001-1 assume !(1 == ~E_7~0); 8203#L1006-1 assume !(1 == ~E_8~0); 8204#L1011-1 assume { :end_inline_reset_delta_events } true; 7580#L1272-2 [2023-11-28 20:20:47,982 INFO L750 eck$LassoCheckResult]: Loop: 7580#L1272-2 assume !false; 7581#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7817#L813-1 assume !false; 8353#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8354#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7583#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7922#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7923#L696 assume !(0 != eval_~tmp~0#1); 8296#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8063#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8064#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 8252#L838-5 assume !(0 == ~T1_E~0); 8253#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8106#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8107#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8157#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8222#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8212#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8213#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7821#L878-3 assume !(0 == ~E_1~0); 7544#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7545#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7546#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7547#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8039#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 8355#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8047#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7585#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7586#L402-27 assume !(1 == ~m_pc~0); 7536#L402-29 is_master_triggered_~__retres1~0#1 := 0; 7535#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8245#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 8246#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8372#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8373#L421-27 assume !(1 == ~t1_pc~0); 7811#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 7812#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8131#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 8132#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8421#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8175#L440-27 assume !(1 == ~t2_pc~0); 8176#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 8350#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8217#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8082#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 8083#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7797#L459-27 assume 1 == ~t3_pc~0; 7798#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8238#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8059#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8060#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8171#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8414#L478-27 assume 1 == ~t4_pc~0; 8433#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7787#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7970#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7971#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8320#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8356#L497-27 assume 1 == ~t5_pc~0; 8357#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7830#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7831#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7773#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7774#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8041#L516-27 assume !(1 == ~t6_pc~0); 8042#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 7894#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7895#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8194#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8195#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7974#L535-27 assume 1 == ~t7_pc~0; 7975#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 8304#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7854#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7855#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7925#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7926#L554-27 assume 1 == ~t8_pc~0; 8128#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7560#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7711#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8091#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7818#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7819#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7693#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7694#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7924#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 8058#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7834#L951-3 assume !(1 == ~T5_E~0); 7835#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8129#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7934#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7935#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 8182#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7578#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7579#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7567#L991-3 assume !(1 == ~E_5~0); 7568#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8258#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7911#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7912#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7606#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7607#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7860#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 7861#L1291 assume !(0 == start_simulation_~tmp~3#1); 8126#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 8029#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7512#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7513#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 7571#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7995#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7996#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 8081#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 7580#L1272-2 [2023-11-28 20:20:47,982 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:47,983 INFO L85 PathProgramCache]: Analyzing trace with hash 1862277854, now seen corresponding path program 1 times [2023-11-28 20:20:47,983 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:47,983 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [533508126] [2023-11-28 20:20:47,983 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:47,983 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:47,994 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:48,018 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:48,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:48,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [533508126] [2023-11-28 20:20:48,019 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [533508126] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:48,019 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:48,020 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:48,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1721052890] [2023-11-28 20:20:48,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:48,021 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:48,021 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:48,021 INFO L85 PathProgramCache]: Analyzing trace with hash -1022505361, now seen corresponding path program 1 times [2023-11-28 20:20:48,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:48,022 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [252997322] [2023-11-28 20:20:48,022 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:48,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:48,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:48,068 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:48,069 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:48,069 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [252997322] [2023-11-28 20:20:48,069 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [252997322] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:48,069 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:48,069 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:48,069 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1422809756] [2023-11-28 20:20:48,070 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:48,070 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:48,070 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:48,070 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:48,071 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:48,071 INFO L87 Difference]: Start difference. First operand 933 states and 1385 transitions. cyclomatic complexity: 453 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:48,090 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:48,091 INFO L93 Difference]: Finished difference Result 933 states and 1384 transitions. [2023-11-28 20:20:48,091 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1384 transitions. [2023-11-28 20:20:48,096 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:48,101 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1384 transitions. [2023-11-28 20:20:48,101 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-28 20:20:48,102 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-28 20:20:48,102 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1384 transitions. [2023-11-28 20:20:48,103 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:48,103 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1384 transitions. [2023-11-28 20:20:48,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1384 transitions. [2023-11-28 20:20:48,114 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-28 20:20:48,116 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4833869239013933) internal successors, (1384), 932 states have internal predecessors, (1384), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:48,118 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1384 transitions. [2023-11-28 20:20:48,118 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1384 transitions. [2023-11-28 20:20:48,119 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:48,119 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1384 transitions. [2023-11-28 20:20:48,120 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-28 20:20:48,120 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1384 transitions. [2023-11-28 20:20:48,124 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:48,124 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:48,124 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:48,125 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:48,125 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:48,126 INFO L748 eck$LassoCheckResult]: Stem: 9631#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9632#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 10258#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10259#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10260#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 9750#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9751#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10256#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10252#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9822#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9823#L606-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 10057#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 10058#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9906#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9907#L838 assume !(0 == ~M_E~0); 10065#L838-2 assume !(0 == ~T1_E~0); 9430#L843-1 assume !(0 == ~T2_E~0); 9431#L848-1 assume !(0 == ~T3_E~0); 9551#L853-1 assume !(0 == ~T4_E~0); 9893#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9381#L863-1 assume !(0 == ~T6_E~0); 9382#L868-1 assume !(0 == ~T7_E~0); 10288#L873-1 assume !(0 == ~T8_E~0); 10286#L878-1 assume !(0 == ~E_1~0); 10277#L883-1 assume !(0 == ~E_2~0); 10278#L888-1 assume !(0 == ~E_3~0); 10026#L893-1 assume !(0 == ~E_4~0); 10027#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 10298#L903-1 assume !(0 == ~E_6~0); 10275#L908-1 assume !(0 == ~E_7~0); 10156#L913-1 assume !(0 == ~E_8~0); 9442#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9443#L402 assume !(1 == ~m_pc~0); 9654#L402-2 is_master_triggered_~__retres1~0#1 := 0; 9575#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9576#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9828#L1035 assume !(0 != activate_threads_~tmp~1#1); 9829#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9881#L421 assume 1 == ~t1_pc~0; 10271#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 10289#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9445#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9446#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 9935#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10296#L440 assume 1 == ~t2_pc~0; 9414#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9415#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9585#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9776#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 10171#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9779#L459 assume !(1 == ~t3_pc~0); 9780#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10269#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9403#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9404#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9570#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9579#L478 assume 1 == ~t4_pc~0; 9580#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10031#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9523#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9524#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 9484#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9485#L497 assume !(1 == ~t5_pc~0); 9534#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9535#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10102#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10208#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 10265#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10266#L516 assume 1 == ~t6_pc~0; 10312#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10056#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9759#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9625#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 9626#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10045#L535 assume !(1 == ~t7_pc~0); 10046#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10116#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10148#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 10138#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10139#L554 assume 1 == ~t8_pc~0; 10081#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9406#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10164#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9713#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 9714#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9392#L931 assume !(1 == ~M_E~0); 9393#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10284#L936-1 assume !(1 == ~T2_E~0); 10303#L941-1 assume !(1 == ~T3_E~0); 9882#L946-1 assume !(1 == ~T4_E~0); 9883#L951-1 assume !(1 == ~T5_E~0); 9640#L956-1 assume !(1 == ~T6_E~0); 9641#L961-1 assume !(1 == ~T7_E~0); 10028#L966-1 assume !(1 == ~T8_E~0); 10029#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 10141#L976-1 assume !(1 == ~E_2~0); 10106#L981-1 assume !(1 == ~E_3~0); 9886#L986-1 assume !(1 == ~E_4~0); 9667#L991-1 assume !(1 == ~E_5~0); 9668#L996-1 assume !(1 == ~E_6~0); 10293#L1001-1 assume !(1 == ~E_7~0); 10076#L1006-1 assume !(1 == ~E_8~0); 10077#L1011-1 assume { :end_inline_reset_delta_events } true; 9453#L1272-2 [2023-11-28 20:20:48,126 INFO L750 eck$LassoCheckResult]: Loop: 9453#L1272-2 assume !false; 9454#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9690#L813-1 assume !false; 10226#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 10227#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9456#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9795#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9796#L696 assume !(0 != eval_~tmp~0#1); 10169#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9936#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9937#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 10125#L838-5 assume !(0 == ~T1_E~0); 10126#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9979#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9980#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10030#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10095#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 10085#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10086#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9694#L878-3 assume !(0 == ~E_1~0); 9417#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9418#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9419#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9420#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9912#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 10228#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9920#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9458#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9459#L402-27 assume !(1 == ~m_pc~0); 9409#L402-29 is_master_triggered_~__retres1~0#1 := 0; 9408#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10118#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 10119#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10245#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10246#L421-27 assume !(1 == ~t1_pc~0); 9684#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 9685#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10004#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 10005#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10294#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10048#L440-27 assume !(1 == ~t2_pc~0); 10049#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 10223#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10090#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9955#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 9956#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9670#L459-27 assume 1 == ~t3_pc~0; 9671#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10111#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9932#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9933#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 10044#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10287#L478-27 assume 1 == ~t4_pc~0; 10306#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9660#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9843#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9844#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 10193#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10229#L497-27 assume 1 == ~t5_pc~0; 10230#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9703#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9704#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9646#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9647#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9914#L516-27 assume !(1 == ~t6_pc~0); 9915#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 9767#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9768#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10067#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10068#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9847#L535-27 assume 1 == ~t7_pc~0; 9848#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10177#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9727#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9728#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9798#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9799#L554-27 assume 1 == ~t8_pc~0; 10001#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9433#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9584#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9964#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9691#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9692#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9566#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9567#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9797#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9931#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9707#L951-3 assume !(1 == ~T5_E~0); 9708#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10002#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9807#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9808#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 10055#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9451#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9452#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9440#L991-3 assume !(1 == ~E_5~0); 9441#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10131#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9784#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9785#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9479#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9480#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9733#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 9734#L1291 assume !(0 == start_simulation_~tmp~3#1); 9999#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9902#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9385#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9386#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 9444#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9868#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9869#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 9954#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 9453#L1272-2 [2023-11-28 20:20:48,126 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:48,126 INFO L85 PathProgramCache]: Analyzing trace with hash 510892636, now seen corresponding path program 1 times [2023-11-28 20:20:48,127 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:48,127 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736529273] [2023-11-28 20:20:48,127 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:48,127 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:48,138 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:48,160 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:48,160 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:48,160 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1736529273] [2023-11-28 20:20:48,160 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1736529273] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:48,161 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:48,161 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:48,161 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [568478920] [2023-11-28 20:20:48,161 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:48,162 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:48,164 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:48,167 INFO L85 PathProgramCache]: Analyzing trace with hash -1022505361, now seen corresponding path program 2 times [2023-11-28 20:20:48,168 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:48,168 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2131006751] [2023-11-28 20:20:48,168 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:48,168 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:48,185 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:48,222 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:48,222 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:48,222 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2131006751] [2023-11-28 20:20:48,222 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2131006751] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:48,222 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:48,223 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:48,223 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1572134965] [2023-11-28 20:20:48,223 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:48,223 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:48,223 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:48,224 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:48,224 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:48,224 INFO L87 Difference]: Start difference. First operand 933 states and 1384 transitions. cyclomatic complexity: 452 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:48,263 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:48,263 INFO L93 Difference]: Finished difference Result 933 states and 1383 transitions. [2023-11-28 20:20:48,263 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1383 transitions. [2023-11-28 20:20:48,271 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:48,278 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1383 transitions. [2023-11-28 20:20:48,278 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-28 20:20:48,279 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-28 20:20:48,280 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1383 transitions. [2023-11-28 20:20:48,281 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:48,281 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1383 transitions. [2023-11-28 20:20:48,283 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1383 transitions. [2023-11-28 20:20:48,297 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-28 20:20:48,300 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.482315112540193) internal successors, (1383), 932 states have internal predecessors, (1383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:48,304 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1383 transitions. [2023-11-28 20:20:48,304 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1383 transitions. [2023-11-28 20:20:48,304 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:48,305 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1383 transitions. [2023-11-28 20:20:48,305 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-28 20:20:48,306 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1383 transitions. [2023-11-28 20:20:48,311 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:48,311 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:48,312 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:48,314 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:48,314 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:48,314 INFO L748 eck$LassoCheckResult]: Stem: 11504#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 11505#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 12131#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12132#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12133#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 11623#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11624#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12129#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12125#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11695#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11696#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 11930#L611-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11931#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11779#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11780#L838 assume !(0 == ~M_E~0); 11938#L838-2 assume !(0 == ~T1_E~0); 11303#L843-1 assume !(0 == ~T2_E~0); 11304#L848-1 assume !(0 == ~T3_E~0); 11424#L853-1 assume !(0 == ~T4_E~0); 11766#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11254#L863-1 assume !(0 == ~T6_E~0); 11255#L868-1 assume !(0 == ~T7_E~0); 12161#L873-1 assume !(0 == ~T8_E~0); 12159#L878-1 assume !(0 == ~E_1~0); 12150#L883-1 assume !(0 == ~E_2~0); 12151#L888-1 assume !(0 == ~E_3~0); 11899#L893-1 assume !(0 == ~E_4~0); 11900#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 12171#L903-1 assume !(0 == ~E_6~0); 12148#L908-1 assume !(0 == ~E_7~0); 12029#L913-1 assume !(0 == ~E_8~0); 11315#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11316#L402 assume !(1 == ~m_pc~0); 11527#L402-2 is_master_triggered_~__retres1~0#1 := 0; 11448#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11449#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11701#L1035 assume !(0 != activate_threads_~tmp~1#1); 11702#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11754#L421 assume 1 == ~t1_pc~0; 12144#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 12162#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11318#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11319#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 11808#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12169#L440 assume 1 == ~t2_pc~0; 11287#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 11288#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11458#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11649#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 12044#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11652#L459 assume !(1 == ~t3_pc~0); 11653#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12142#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11276#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11277#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11443#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11452#L478 assume 1 == ~t4_pc~0; 11453#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11904#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11396#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11397#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 11357#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11358#L497 assume !(1 == ~t5_pc~0); 11407#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11408#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11975#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12081#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 12138#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12139#L516 assume 1 == ~t6_pc~0; 12185#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11929#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11632#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11498#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 11499#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11918#L535 assume !(1 == ~t7_pc~0); 11919#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11989#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11990#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12021#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 12011#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12012#L554 assume 1 == ~t8_pc~0; 11954#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11279#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12037#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11586#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 11587#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11265#L931 assume !(1 == ~M_E~0); 11266#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12157#L936-1 assume !(1 == ~T2_E~0); 12176#L941-1 assume !(1 == ~T3_E~0); 11755#L946-1 assume !(1 == ~T4_E~0); 11756#L951-1 assume !(1 == ~T5_E~0); 11513#L956-1 assume !(1 == ~T6_E~0); 11514#L961-1 assume !(1 == ~T7_E~0); 11901#L966-1 assume !(1 == ~T8_E~0); 11902#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 12014#L976-1 assume !(1 == ~E_2~0); 11979#L981-1 assume !(1 == ~E_3~0); 11759#L986-1 assume !(1 == ~E_4~0); 11540#L991-1 assume !(1 == ~E_5~0); 11541#L996-1 assume !(1 == ~E_6~0); 12166#L1001-1 assume !(1 == ~E_7~0); 11949#L1006-1 assume !(1 == ~E_8~0); 11950#L1011-1 assume { :end_inline_reset_delta_events } true; 11326#L1272-2 [2023-11-28 20:20:48,315 INFO L750 eck$LassoCheckResult]: Loop: 11326#L1272-2 assume !false; 11327#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11563#L813-1 assume !false; 12099#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 12100#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11329#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11668#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11669#L696 assume !(0 != eval_~tmp~0#1); 12042#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11809#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11810#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11998#L838-5 assume !(0 == ~T1_E~0); 11999#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11852#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11853#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11903#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11968#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11958#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11959#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 11567#L878-3 assume !(0 == ~E_1~0); 11290#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 11291#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11292#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11293#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11785#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 12101#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11793#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11331#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11332#L402-27 assume 1 == ~m_pc~0; 11280#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11281#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11991#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 11992#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12118#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12119#L421-27 assume !(1 == ~t1_pc~0); 11557#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 11558#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11877#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11878#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12167#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11921#L440-27 assume !(1 == ~t2_pc~0); 11922#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 12096#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11963#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11828#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 11829#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11543#L459-27 assume 1 == ~t3_pc~0; 11544#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11984#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11805#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11806#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11917#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12160#L478-27 assume 1 == ~t4_pc~0; 12179#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11533#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11716#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11717#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 12066#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12102#L497-27 assume 1 == ~t5_pc~0; 12103#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11576#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11577#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11519#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11520#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11787#L516-27 assume !(1 == ~t6_pc~0); 11788#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 11640#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11641#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11940#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11941#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11720#L535-27 assume 1 == ~t7_pc~0; 11721#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12050#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11600#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11601#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11671#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11672#L554-27 assume 1 == ~t8_pc~0; 11874#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11306#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11457#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11837#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11564#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11565#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11439#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11440#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11670#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 11804#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 11580#L951-3 assume !(1 == ~T5_E~0); 11581#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 11875#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11680#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11681#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11928#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11324#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11325#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 11313#L991-3 assume !(1 == ~E_5~0); 11314#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12004#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 11657#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11658#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11352#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11353#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11606#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 11607#L1291 assume !(0 == start_simulation_~tmp~3#1); 11872#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 11775#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 11258#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 11259#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 11317#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 11741#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11742#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 11827#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 11326#L1272-2 [2023-11-28 20:20:48,315 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:48,316 INFO L85 PathProgramCache]: Analyzing trace with hash 2129867550, now seen corresponding path program 1 times [2023-11-28 20:20:48,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:48,316 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [917333249] [2023-11-28 20:20:48,316 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:48,316 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:48,329 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:48,357 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:48,357 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:48,357 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [917333249] [2023-11-28 20:20:48,357 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [917333249] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:48,357 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:48,358 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:48,358 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1796188281] [2023-11-28 20:20:48,358 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:48,358 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:48,359 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:48,359 INFO L85 PathProgramCache]: Analyzing trace with hash -567599280, now seen corresponding path program 1 times [2023-11-28 20:20:48,359 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:48,359 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [196910265] [2023-11-28 20:20:48,359 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:48,359 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:48,374 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:48,412 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:48,412 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:48,412 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [196910265] [2023-11-28 20:20:48,413 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [196910265] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:48,413 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:48,413 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:48,413 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [891074647] [2023-11-28 20:20:48,413 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:48,414 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:48,414 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:48,414 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:48,414 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:48,415 INFO L87 Difference]: Start difference. First operand 933 states and 1383 transitions. cyclomatic complexity: 451 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:48,443 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:48,443 INFO L93 Difference]: Finished difference Result 933 states and 1382 transitions. [2023-11-28 20:20:48,443 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1382 transitions. [2023-11-28 20:20:48,450 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:48,458 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1382 transitions. [2023-11-28 20:20:48,458 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-28 20:20:48,459 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-28 20:20:48,459 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1382 transitions. [2023-11-28 20:20:48,461 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:48,461 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1382 transitions. [2023-11-28 20:20:48,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1382 transitions. [2023-11-28 20:20:48,475 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-28 20:20:48,478 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.4812433011789925) internal successors, (1382), 932 states have internal predecessors, (1382), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:48,482 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1382 transitions. [2023-11-28 20:20:48,482 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1382 transitions. [2023-11-28 20:20:48,482 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:48,483 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1382 transitions. [2023-11-28 20:20:48,483 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-28 20:20:48,483 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1382 transitions. [2023-11-28 20:20:48,488 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:48,488 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:48,489 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:48,490 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:48,490 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:48,491 INFO L748 eck$LassoCheckResult]: Stem: 13377#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 13378#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 14004#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14005#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14006#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 13496#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 13497#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14002#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13998#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13568#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13569#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 13803#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 13804#L616-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13652#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13653#L838 assume !(0 == ~M_E~0); 13812#L838-2 assume !(0 == ~T1_E~0); 13176#L843-1 assume !(0 == ~T2_E~0); 13177#L848-1 assume !(0 == ~T3_E~0); 13297#L853-1 assume !(0 == ~T4_E~0); 13641#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13129#L863-1 assume !(0 == ~T6_E~0); 13130#L868-1 assume !(0 == ~T7_E~0); 14034#L873-1 assume !(0 == ~T8_E~0); 14032#L878-1 assume !(0 == ~E_1~0); 14023#L883-1 assume !(0 == ~E_2~0); 14024#L888-1 assume !(0 == ~E_3~0); 13775#L893-1 assume !(0 == ~E_4~0); 13776#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 14044#L903-1 assume !(0 == ~E_6~0); 14021#L908-1 assume !(0 == ~E_7~0); 13903#L913-1 assume !(0 == ~E_8~0); 13189#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13190#L402 assume !(1 == ~m_pc~0); 13404#L402-2 is_master_triggered_~__retres1~0#1 := 0; 13321#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13322#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13574#L1035 assume !(0 != activate_threads_~tmp~1#1); 13575#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13629#L421 assume 1 == ~t1_pc~0; 14017#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14038#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13191#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13192#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 13683#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 14042#L440 assume 1 == ~t2_pc~0; 13160#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13161#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13522#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 13917#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13529#L459 assume !(1 == ~t3_pc~0); 13530#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 14015#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13149#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13150#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13316#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13325#L478 assume 1 == ~t4_pc~0; 13326#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13777#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13269#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13270#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 13232#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13233#L497 assume !(1 == ~t5_pc~0); 13280#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13281#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13848#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13954#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 14011#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14012#L516 assume 1 == ~t6_pc~0; 14058#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13802#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13505#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13371#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 13372#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13791#L535 assume !(1 == ~t7_pc~0); 13792#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13862#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13863#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13894#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 13885#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13886#L554 assume 1 == ~t8_pc~0; 13827#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13152#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13911#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13462#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 13463#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13138#L931 assume !(1 == ~M_E~0); 13139#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14030#L936-1 assume !(1 == ~T2_E~0); 14049#L941-1 assume !(1 == ~T3_E~0); 13627#L946-1 assume !(1 == ~T4_E~0); 13628#L951-1 assume !(1 == ~T5_E~0); 13386#L956-1 assume !(1 == ~T6_E~0); 13387#L961-1 assume !(1 == ~T7_E~0); 13772#L966-1 assume !(1 == ~T8_E~0); 13773#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 13887#L976-1 assume !(1 == ~E_2~0); 13852#L981-1 assume !(1 == ~E_3~0); 13632#L986-1 assume !(1 == ~E_4~0); 13413#L991-1 assume !(1 == ~E_5~0); 13414#L996-1 assume !(1 == ~E_6~0); 14039#L1001-1 assume !(1 == ~E_7~0); 13822#L1006-1 assume !(1 == ~E_8~0); 13823#L1011-1 assume { :end_inline_reset_delta_events } true; 13199#L1272-2 [2023-11-28 20:20:48,491 INFO L750 eck$LassoCheckResult]: Loop: 13199#L1272-2 assume !false; 13200#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13436#L813-1 assume !false; 13972#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13973#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13202#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13541#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13542#L696 assume !(0 != eval_~tmp~0#1); 13915#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13681#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13682#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13871#L838-5 assume !(0 == ~T1_E~0); 13872#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13725#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 13726#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13774#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13841#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13831#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13832#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 13440#L878-3 assume !(0 == ~E_1~0); 13163#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13164#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13165#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 13166#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13658#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13974#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13666#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13204#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13205#L402-27 assume 1 == ~m_pc~0; 13153#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13154#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13864#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 13865#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 13991#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13992#L421-27 assume !(1 == ~t1_pc~0); 13430#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 13431#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13750#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13751#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14040#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13794#L440-27 assume !(1 == ~t2_pc~0); 13795#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 13968#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13836#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13701#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 13702#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13416#L459-27 assume 1 == ~t3_pc~0; 13417#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13857#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13678#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13679#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13790#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 14033#L478-27 assume 1 == ~t4_pc~0; 14052#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13406#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13589#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13590#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13939#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13975#L497-27 assume 1 == ~t5_pc~0; 13976#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13449#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13450#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13392#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13393#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13660#L516-27 assume !(1 == ~t6_pc~0); 13661#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 13513#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13514#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13813#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13814#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13593#L535-27 assume 1 == ~t7_pc~0; 13594#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13923#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13473#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13474#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13544#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13545#L554-27 assume 1 == ~t8_pc~0; 13747#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13179#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13330#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13710#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13437#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13438#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13312#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 13313#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 13543#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 13677#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13453#L951-3 assume !(1 == ~T5_E~0); 13454#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13748#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13553#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13554#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 13801#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13197#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 13198#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13186#L991-3 assume !(1 == ~E_5~0); 13187#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13877#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13527#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13528#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13225#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13226#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13479#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 13480#L1291 assume !(0 == start_simulation_~tmp~3#1); 13745#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 13648#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 13131#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 13132#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 13188#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13614#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13615#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 13700#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 13199#L1272-2 [2023-11-28 20:20:48,492 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:48,492 INFO L85 PathProgramCache]: Analyzing trace with hash -1281590756, now seen corresponding path program 1 times [2023-11-28 20:20:48,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:48,492 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [709194206] [2023-11-28 20:20:48,493 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:48,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:48,505 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:48,531 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:48,532 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:48,532 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [709194206] [2023-11-28 20:20:48,532 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [709194206] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:48,532 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:48,532 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:48,533 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1581531743] [2023-11-28 20:20:48,533 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:48,533 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:48,533 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:48,534 INFO L85 PathProgramCache]: Analyzing trace with hash -567599280, now seen corresponding path program 2 times [2023-11-28 20:20:48,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:48,534 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1552118389] [2023-11-28 20:20:48,534 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:48,534 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:48,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:48,587 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:48,588 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:48,588 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1552118389] [2023-11-28 20:20:48,588 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1552118389] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:48,588 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:48,588 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:48,589 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1710506864] [2023-11-28 20:20:48,589 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:48,589 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:48,589 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:48,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:48,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:48,590 INFO L87 Difference]: Start difference. First operand 933 states and 1382 transitions. cyclomatic complexity: 450 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:48,617 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:48,617 INFO L93 Difference]: Finished difference Result 933 states and 1381 transitions. [2023-11-28 20:20:48,617 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1381 transitions. [2023-11-28 20:20:48,625 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:48,632 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1381 transitions. [2023-11-28 20:20:48,632 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-28 20:20:48,633 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-28 20:20:48,633 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1381 transitions. [2023-11-28 20:20:48,635 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:48,635 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1381 transitions. [2023-11-28 20:20:48,637 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1381 transitions. [2023-11-28 20:20:48,687 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-28 20:20:48,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.480171489817792) internal successors, (1381), 932 states have internal predecessors, (1381), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:48,694 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1381 transitions. [2023-11-28 20:20:48,695 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1381 transitions. [2023-11-28 20:20:48,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:48,696 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1381 transitions. [2023-11-28 20:20:48,696 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-28 20:20:48,696 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1381 transitions. [2023-11-28 20:20:48,702 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:48,703 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:48,703 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:48,705 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:48,705 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:48,706 INFO L748 eck$LassoCheckResult]: Stem: 15250#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 15251#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 15877#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 15878#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 15879#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 15369#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 15370#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 15875#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15871#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15441#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 15442#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 15676#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 15677#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 15525#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15526#L838 assume !(0 == ~M_E~0); 15685#L838-2 assume !(0 == ~T1_E~0); 15049#L843-1 assume !(0 == ~T2_E~0); 15050#L848-1 assume !(0 == ~T3_E~0); 15170#L853-1 assume !(0 == ~T4_E~0); 15514#L858-1 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15002#L863-1 assume !(0 == ~T6_E~0); 15003#L868-1 assume !(0 == ~T7_E~0); 15907#L873-1 assume !(0 == ~T8_E~0); 15905#L878-1 assume !(0 == ~E_1~0); 15896#L883-1 assume !(0 == ~E_2~0); 15897#L888-1 assume !(0 == ~E_3~0); 15645#L893-1 assume !(0 == ~E_4~0); 15646#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 15917#L903-1 assume !(0 == ~E_6~0); 15894#L908-1 assume !(0 == ~E_7~0); 15776#L913-1 assume !(0 == ~E_8~0); 15062#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15063#L402 assume !(1 == ~m_pc~0); 15277#L402-2 is_master_triggered_~__retres1~0#1 := 0; 15194#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15195#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15447#L1035 assume !(0 != activate_threads_~tmp~1#1); 15448#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15500#L421 assume 1 == ~t1_pc~0; 15890#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15911#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15064#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15065#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 15554#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15915#L440 assume 1 == ~t2_pc~0; 15033#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 15034#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15204#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15395#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 15790#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15402#L459 assume !(1 == ~t3_pc~0); 15403#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 15888#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15022#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15023#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15189#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15198#L478 assume 1 == ~t4_pc~0; 15199#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15650#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15142#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15143#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 15105#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15106#L497 assume !(1 == ~t5_pc~0); 15153#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15154#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15721#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15827#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 15884#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15885#L516 assume 1 == ~t6_pc~0; 15931#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15675#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15378#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15244#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 15245#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15664#L535 assume !(1 == ~t7_pc~0); 15665#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15735#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15736#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15767#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 15758#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15759#L554 assume 1 == ~t8_pc~0; 15700#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15025#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15783#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15335#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 15336#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15011#L931 assume !(1 == ~M_E~0); 15012#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15903#L936-1 assume !(1 == ~T2_E~0); 15922#L941-1 assume !(1 == ~T3_E~0); 15501#L946-1 assume !(1 == ~T4_E~0); 15502#L951-1 assume !(1 == ~T5_E~0); 15259#L956-1 assume !(1 == ~T6_E~0); 15260#L961-1 assume !(1 == ~T7_E~0); 15647#L966-1 assume !(1 == ~T8_E~0); 15648#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 15761#L976-1 assume !(1 == ~E_2~0); 15725#L981-1 assume !(1 == ~E_3~0); 15505#L986-1 assume !(1 == ~E_4~0); 15286#L991-1 assume !(1 == ~E_5~0); 15287#L996-1 assume !(1 == ~E_6~0); 15912#L1001-1 assume !(1 == ~E_7~0); 15695#L1006-1 assume !(1 == ~E_8~0); 15696#L1011-1 assume { :end_inline_reset_delta_events } true; 15072#L1272-2 [2023-11-28 20:20:48,706 INFO L750 eck$LassoCheckResult]: Loop: 15072#L1272-2 assume !false; 15073#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 15311#L813-1 assume !false; 15845#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15846#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15075#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15414#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 15415#L696 assume !(0 != eval_~tmp~0#1); 15788#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 15555#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 15556#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 15744#L838-5 assume !(0 == ~T1_E~0); 15745#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15599#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 15600#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15649#L858-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15714#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 15705#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 15706#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 15315#L878-3 assume !(0 == ~E_1~0); 15038#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15039#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15036#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 15037#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15531#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 15847#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15539#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15077#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15078#L402-27 assume 1 == ~m_pc~0; 15026#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15027#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 15737#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 15738#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 15864#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15865#L421-27 assume !(1 == ~t1_pc~0); 15303#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 15304#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15623#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15624#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15913#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15667#L440-27 assume !(1 == ~t2_pc~0); 15668#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 15841#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15709#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15574#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 15575#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 15289#L459-27 assume 1 == ~t3_pc~0; 15290#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15730#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15551#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15552#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 15663#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15906#L478-27 assume 1 == ~t4_pc~0; 15925#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15279#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15462#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15463#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 15812#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15848#L497-27 assume !(1 == ~t5_pc~0); 15456#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 15322#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15323#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15265#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15266#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15532#L516-27 assume !(1 == ~t6_pc~0); 15533#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 15383#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15384#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15686#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15687#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15466#L535-27 assume 1 == ~t7_pc~0; 15467#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15796#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 15346#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15347#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15417#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15418#L554-27 assume 1 == ~t8_pc~0; 15620#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 15052#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15203#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15580#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 15308#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15309#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 15185#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 15186#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 15416#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 15550#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15326#L951-3 assume !(1 == ~T5_E~0); 15327#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 15621#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15426#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15427#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 15674#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 15070#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 15071#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15059#L991-3 assume !(1 == ~E_5~0); 15060#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15750#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15400#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 15401#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15098#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15099#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15348#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 15349#L1291 assume !(0 == start_simulation_~tmp~3#1); 15618#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 15521#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 15004#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 15005#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 15061#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15487#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 15488#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 15573#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 15072#L1272-2 [2023-11-28 20:20:48,707 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:48,708 INFO L85 PathProgramCache]: Analyzing trace with hash -1253090466, now seen corresponding path program 1 times [2023-11-28 20:20:48,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:48,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [250964542] [2023-11-28 20:20:48,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:48,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:48,731 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:48,789 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:48,790 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:48,790 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [250964542] [2023-11-28 20:20:48,790 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [250964542] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:48,790 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:48,790 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:20:48,791 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [945495509] [2023-11-28 20:20:48,791 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:48,791 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:48,791 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:48,792 INFO L85 PathProgramCache]: Analyzing trace with hash -464798033, now seen corresponding path program 1 times [2023-11-28 20:20:48,792 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:48,792 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [213596042] [2023-11-28 20:20:48,792 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:48,792 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:48,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:48,855 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:48,855 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:48,856 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [213596042] [2023-11-28 20:20:48,856 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [213596042] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:48,856 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:48,856 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:48,856 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [410764313] [2023-11-28 20:20:48,856 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:48,857 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:48,857 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:48,857 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:48,858 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:48,858 INFO L87 Difference]: Start difference. First operand 933 states and 1381 transitions. cyclomatic complexity: 449 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:48,909 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:48,909 INFO L93 Difference]: Finished difference Result 933 states and 1376 transitions. [2023-11-28 20:20:48,910 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 933 states and 1376 transitions. [2023-11-28 20:20:48,917 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:48,924 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 933 states to 933 states and 1376 transitions. [2023-11-28 20:20:48,924 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 933 [2023-11-28 20:20:48,925 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 933 [2023-11-28 20:20:48,925 INFO L73 IsDeterministic]: Start isDeterministic. Operand 933 states and 1376 transitions. [2023-11-28 20:20:48,927 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:48,927 INFO L218 hiAutomatonCegarLoop]: Abstraction has 933 states and 1376 transitions. [2023-11-28 20:20:48,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 933 states and 1376 transitions. [2023-11-28 20:20:48,942 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 933 to 933. [2023-11-28 20:20:48,944 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 933 states, 933 states have (on average 1.47481243301179) internal successors, (1376), 932 states have internal predecessors, (1376), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:48,948 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 933 states to 933 states and 1376 transitions. [2023-11-28 20:20:48,948 INFO L240 hiAutomatonCegarLoop]: Abstraction has 933 states and 1376 transitions. [2023-11-28 20:20:48,949 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:48,949 INFO L428 stractBuchiCegarLoop]: Abstraction has 933 states and 1376 transitions. [2023-11-28 20:20:48,950 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-28 20:20:48,950 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 933 states and 1376 transitions. [2023-11-28 20:20:48,955 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 820 [2023-11-28 20:20:48,955 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:48,955 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:48,957 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:48,957 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:48,958 INFO L748 eck$LassoCheckResult]: Stem: 17123#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 17124#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 17750#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 17751#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 17752#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 17242#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 17243#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 17748#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 17744#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 17314#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 17315#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 17549#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 17550#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 17398#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 17399#L838 assume !(0 == ~M_E~0); 17558#L838-2 assume !(0 == ~T1_E~0); 16922#L843-1 assume !(0 == ~T2_E~0); 16923#L848-1 assume !(0 == ~T3_E~0); 17043#L853-1 assume !(0 == ~T4_E~0); 17387#L858-1 assume !(0 == ~T5_E~0); 16873#L863-1 assume !(0 == ~T6_E~0); 16874#L868-1 assume !(0 == ~T7_E~0); 17780#L873-1 assume !(0 == ~T8_E~0); 17778#L878-1 assume !(0 == ~E_1~0); 17769#L883-1 assume !(0 == ~E_2~0); 17770#L888-1 assume !(0 == ~E_3~0); 17518#L893-1 assume !(0 == ~E_4~0); 17519#L898-1 assume 0 == ~E_5~0;~E_5~0 := 1; 17790#L903-1 assume !(0 == ~E_6~0); 17767#L908-1 assume !(0 == ~E_7~0); 17648#L913-1 assume !(0 == ~E_8~0); 16935#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16936#L402 assume !(1 == ~m_pc~0); 17148#L402-2 is_master_triggered_~__retres1~0#1 := 0; 17067#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17068#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17320#L1035 assume !(0 != activate_threads_~tmp~1#1); 17321#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17373#L421 assume 1 == ~t1_pc~0; 17763#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 17784#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16937#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16938#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 17427#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17788#L440 assume 1 == ~t2_pc~0; 16906#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 16907#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17077#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17268#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 17663#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17275#L459 assume !(1 == ~t3_pc~0); 17276#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 17761#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16895#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 16896#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17062#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17071#L478 assume 1 == ~t4_pc~0; 17072#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17523#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17015#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17016#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 16978#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16979#L497 assume !(1 == ~t5_pc~0); 17026#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17027#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17594#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17700#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 17757#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17758#L516 assume 1 == ~t6_pc~0; 17804#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17548#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17251#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17117#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 17118#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17537#L535 assume !(1 == ~t7_pc~0); 17538#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 17608#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17609#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17640#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 17630#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17631#L554 assume 1 == ~t8_pc~0; 17573#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16898#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17656#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17208#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 17209#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16884#L931 assume !(1 == ~M_E~0); 16885#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17776#L936-1 assume !(1 == ~T2_E~0); 17795#L941-1 assume !(1 == ~T3_E~0); 17374#L946-1 assume !(1 == ~T4_E~0); 17375#L951-1 assume !(1 == ~T5_E~0); 17132#L956-1 assume !(1 == ~T6_E~0); 17133#L961-1 assume !(1 == ~T7_E~0); 17520#L966-1 assume !(1 == ~T8_E~0); 17521#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 17633#L976-1 assume !(1 == ~E_2~0); 17598#L981-1 assume !(1 == ~E_3~0); 17378#L986-1 assume !(1 == ~E_4~0); 17159#L991-1 assume !(1 == ~E_5~0); 17160#L996-1 assume !(1 == ~E_6~0); 17785#L1001-1 assume !(1 == ~E_7~0); 17568#L1006-1 assume !(1 == ~E_8~0); 17569#L1011-1 assume { :end_inline_reset_delta_events } true; 16945#L1272-2 [2023-11-28 20:20:48,958 INFO L750 eck$LassoCheckResult]: Loop: 16945#L1272-2 assume !false; 16946#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 17184#L813-1 assume !false; 17718#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17719#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16948#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17287#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 17288#L696 assume !(0 != eval_~tmp~0#1); 17661#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 17428#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 17429#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 17617#L838-5 assume !(0 == ~T1_E~0); 17618#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 17471#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 17472#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17522#L858-3 assume !(0 == ~T5_E~0); 17587#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 17578#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 17579#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 17188#L878-3 assume !(0 == ~E_1~0); 16909#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 16910#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16911#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16912#L898-3 assume 0 == ~E_5~0;~E_5~0 := 1; 17404#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 17722#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 17412#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 16950#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16951#L402-27 assume 1 == ~m_pc~0; 16899#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 16900#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 17610#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 17611#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 17737#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17738#L421-27 assume !(1 == ~t1_pc~0); 17176#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 17177#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17496#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 17497#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 17786#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 17540#L440-27 assume !(1 == ~t2_pc~0); 17541#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 17714#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 17582#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17447#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 17448#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 17162#L459-27 assume 1 == ~t3_pc~0; 17163#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 17603#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17424#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 17425#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 17536#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17779#L478-27 assume 1 == ~t4_pc~0; 17798#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 17152#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17335#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17336#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 17685#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17720#L497-27 assume 1 == ~t5_pc~0; 17721#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17195#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17196#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17138#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 17139#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 17405#L516-27 assume !(1 == ~t6_pc~0); 17406#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 17252#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17253#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 17559#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 17560#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 17339#L535-27 assume 1 == ~t7_pc~0; 17340#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 17667#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 17219#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17220#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 17290#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 17291#L554-27 assume 1 == ~t8_pc~0; 17493#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16925#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 17076#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 17453#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 17181#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 17182#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 17058#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 17059#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 17289#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 17423#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 17199#L951-3 assume !(1 == ~T5_E~0); 17200#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 17494#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17299#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17300#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 17547#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16943#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16944#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16932#L991-3 assume !(1 == ~E_5~0); 16933#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 17623#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 17273#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 17274#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 16971#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16972#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 17221#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 17222#L1291 assume !(0 == start_simulation_~tmp~3#1); 17491#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 17392#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 16877#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 16878#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 16934#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 17359#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 17360#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 17446#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 16945#L1272-2 [2023-11-28 20:20:48,958 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:48,958 INFO L85 PathProgramCache]: Analyzing trace with hash 623392352, now seen corresponding path program 1 times [2023-11-28 20:20:48,959 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:48,959 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [696003660] [2023-11-28 20:20:48,959 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:48,959 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:48,971 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:49,035 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:49,036 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:49,036 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [696003660] [2023-11-28 20:20:49,036 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [696003660] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:49,036 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:49,036 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:49,037 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [196397714] [2023-11-28 20:20:49,037 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:49,037 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:49,037 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:49,038 INFO L85 PathProgramCache]: Analyzing trace with hash 1033471826, now seen corresponding path program 1 times [2023-11-28 20:20:49,038 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:49,038 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1609548900] [2023-11-28 20:20:49,038 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:49,038 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:49,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:49,088 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:49,089 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:49,089 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1609548900] [2023-11-28 20:20:49,089 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1609548900] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:49,089 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:49,089 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:49,089 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1927148409] [2023-11-28 20:20:49,090 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:49,090 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:49,090 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:49,090 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-28 20:20:49,091 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-28 20:20:49,091 INFO L87 Difference]: Start difference. First operand 933 states and 1376 transitions. cyclomatic complexity: 444 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:49,284 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:49,284 INFO L93 Difference]: Finished difference Result 1704 states and 2511 transitions. [2023-11-28 20:20:49,284 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1704 states and 2511 transitions. [2023-11-28 20:20:49,296 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1575 [2023-11-28 20:20:49,309 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1704 states to 1704 states and 2511 transitions. [2023-11-28 20:20:49,310 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1704 [2023-11-28 20:20:49,312 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1704 [2023-11-28 20:20:49,312 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1704 states and 2511 transitions. [2023-11-28 20:20:49,315 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:49,315 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1704 states and 2511 transitions. [2023-11-28 20:20:49,318 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1704 states and 2511 transitions. [2023-11-28 20:20:49,380 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1704 to 1703. [2023-11-28 20:20:49,384 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1703 states, 1703 states have (on average 1.473869641808573) internal successors, (2510), 1702 states have internal predecessors, (2510), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:49,393 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1703 states to 1703 states and 2510 transitions. [2023-11-28 20:20:49,393 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1703 states and 2510 transitions. [2023-11-28 20:20:49,393 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-28 20:20:49,394 INFO L428 stractBuchiCegarLoop]: Abstraction has 1703 states and 2510 transitions. [2023-11-28 20:20:49,394 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-28 20:20:49,394 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1703 states and 2510 transitions. [2023-11-28 20:20:49,402 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1575 [2023-11-28 20:20:49,402 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:49,402 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:49,404 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:49,404 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:49,404 INFO L748 eck$LassoCheckResult]: Stem: 19770#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 19771#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 20417#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 20418#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 20419#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 19889#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19890#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 20415#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20409#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 19963#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19964#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 20207#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 20208#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 20048#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 20049#L838 assume !(0 == ~M_E~0); 20215#L838-2 assume !(0 == ~T1_E~0); 19569#L843-1 assume !(0 == ~T2_E~0); 19570#L848-1 assume !(0 == ~T3_E~0); 19690#L853-1 assume !(0 == ~T4_E~0); 20035#L858-1 assume !(0 == ~T5_E~0); 19520#L863-1 assume !(0 == ~T6_E~0); 19521#L868-1 assume !(0 == ~T7_E~0); 20452#L873-1 assume !(0 == ~T8_E~0); 20450#L878-1 assume !(0 == ~E_1~0); 20438#L883-1 assume !(0 == ~E_2~0); 20439#L888-1 assume !(0 == ~E_3~0); 20175#L893-1 assume !(0 == ~E_4~0); 20176#L898-1 assume !(0 == ~E_5~0); 20464#L903-1 assume !(0 == ~E_6~0); 20436#L908-1 assume !(0 == ~E_7~0); 20306#L913-1 assume !(0 == ~E_8~0); 19581#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19582#L402 assume !(1 == ~m_pc~0); 19793#L402-2 is_master_triggered_~__retres1~0#1 := 0; 19714#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 19715#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 19969#L1035 assume !(0 != activate_threads_~tmp~1#1); 19970#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20023#L421 assume 1 == ~t1_pc~0; 20432#L422 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 20453#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19584#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 19585#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 20079#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20462#L440 assume 1 == ~t2_pc~0; 19553#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 19554#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 19724#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19915#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 20325#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19918#L459 assume !(1 == ~t3_pc~0); 19919#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 20428#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 19542#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 19543#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 19709#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19718#L478 assume 1 == ~t4_pc~0; 19719#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20180#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19662#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19663#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 19623#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 19624#L497 assume !(1 == ~t5_pc~0); 19673#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 19674#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20252#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20363#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 20424#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20425#L516 assume 1 == ~t6_pc~0; 20486#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 20206#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19898#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19764#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 19765#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 20195#L535 assume !(1 == ~t7_pc~0); 20196#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 20266#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 20267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 20298#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 20288#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20289#L554 assume 1 == ~t8_pc~0; 20231#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19545#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 20316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 19852#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 19853#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19531#L931 assume !(1 == ~M_E~0); 19532#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 20447#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 20473#L941-1 assume !(1 == ~T3_E~0); 20024#L946-1 assume !(1 == ~T4_E~0); 20025#L951-1 assume !(1 == ~T5_E~0); 19779#L956-1 assume !(1 == ~T6_E~0); 19780#L961-1 assume !(1 == ~T7_E~0); 20177#L966-1 assume !(1 == ~T8_E~0); 20178#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 20291#L976-1 assume !(1 == ~E_2~0); 20256#L981-1 assume !(1 == ~E_3~0); 20028#L986-1 assume !(1 == ~E_4~0); 19806#L991-1 assume !(1 == ~E_5~0); 19807#L996-1 assume !(1 == ~E_6~0); 20457#L1001-1 assume !(1 == ~E_7~0); 20226#L1006-1 assume !(1 == ~E_8~0); 20227#L1011-1 assume { :end_inline_reset_delta_events } true; 20505#L1272-2 [2023-11-28 20:20:49,405 INFO L750 eck$LassoCheckResult]: Loop: 20505#L1272-2 assume !false; 20501#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 20476#L813-1 assume !false; 20477#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20499#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20172#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 19934#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 19935#L696 assume !(0 != eval_~tmp~0#1); 20322#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 20323#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 20412#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 20413#L838-5 assume !(0 == ~T1_E~0); 20489#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 20123#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 20124#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 20179#L858-3 assume !(0 == ~T5_E~0); 20245#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 20235#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 20236#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 19833#L878-3 assume !(0 == ~E_1~0); 19556#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 19557#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 19558#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19559#L898-3 assume !(0 == ~E_5~0); 20054#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 20383#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20063#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 19597#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 19598#L402-27 assume 1 == ~m_pc~0; 19546#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 19547#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 20268#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 20269#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 20402#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 20403#L421-27 assume 1 == ~t1_pc~0; 20304#L422-9 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19824#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20151#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 20152#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 20458#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20198#L440-27 assume !(1 == ~t2_pc~0); 20199#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 20378#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20240#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20099#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 20100#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19809#L459-27 assume 1 == ~t3_pc~0; 19810#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20261#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20075#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20076#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 20194#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20451#L478-27 assume !(1 == ~t4_pc~0); 19798#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 19799#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 19984#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19985#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 20347#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20384#L497-27 assume 1 == ~t5_pc~0; 20385#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 19842#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19843#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 19785#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19786#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 20056#L516-27 assume !(1 == ~t6_pc~0); 20057#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 19906#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 19907#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20217#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 20218#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19988#L535-27 assume 1 == ~t7_pc~0; 19989#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 20331#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19866#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19867#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19938#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 19939#L554-27 assume !(1 == ~t8_pc~0); 19571#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 19572#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19723#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 20108#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19830#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19831#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19705#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19706#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19937#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 20074#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 19846#L951-3 assume !(1 == ~T5_E~0); 19847#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 20149#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 19948#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19949#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 20205#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 19590#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19591#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 19579#L991-3 assume !(1 == ~E_5~0); 19580#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 20281#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 19923#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 19924#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 19618#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 19619#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20078#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 20537#L1291 assume !(0 == start_simulation_~tmp~3#1); 20535#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 20534#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 20524#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 20523#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 20442#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 20009#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 20010#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 20098#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 20505#L1272-2 [2023-11-28 20:20:49,405 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:49,405 INFO L85 PathProgramCache]: Analyzing trace with hash 1671526308, now seen corresponding path program 1 times [2023-11-28 20:20:49,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:49,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1574629901] [2023-11-28 20:20:49,406 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:49,406 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:49,419 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:49,457 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:49,457 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:49,458 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1574629901] [2023-11-28 20:20:49,458 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1574629901] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:49,458 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:49,458 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:20:49,458 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1114715732] [2023-11-28 20:20:49,458 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:49,459 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:49,459 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:49,459 INFO L85 PathProgramCache]: Analyzing trace with hash -2131409869, now seen corresponding path program 1 times [2023-11-28 20:20:49,459 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:49,459 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1636923388] [2023-11-28 20:20:49,460 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:49,460 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:49,474 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:49,503 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:49,503 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:49,503 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1636923388] [2023-11-28 20:20:49,503 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1636923388] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:49,503 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:49,503 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:49,504 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [23291925] [2023-11-28 20:20:49,504 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:49,504 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:49,504 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:49,505 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:49,505 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:49,505 INFO L87 Difference]: Start difference. First operand 1703 states and 2510 transitions. cyclomatic complexity: 809 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:49,606 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:49,606 INFO L93 Difference]: Finished difference Result 3128 states and 4579 transitions. [2023-11-28 20:20:49,607 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3128 states and 4579 transitions. [2023-11-28 20:20:49,627 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2997 [2023-11-28 20:20:49,651 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3128 states to 3128 states and 4579 transitions. [2023-11-28 20:20:49,651 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3128 [2023-11-28 20:20:49,655 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3128 [2023-11-28 20:20:49,655 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3128 states and 4579 transitions. [2023-11-28 20:20:49,661 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:49,661 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3128 states and 4579 transitions. [2023-11-28 20:20:49,665 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3128 states and 4579 transitions. [2023-11-28 20:20:49,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3128 to 3124. [2023-11-28 20:20:49,732 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3124 states, 3124 states have (on average 1.4644686299615877) internal successors, (4575), 3123 states have internal predecessors, (4575), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:49,747 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3124 states to 3124 states and 4575 transitions. [2023-11-28 20:20:49,747 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3124 states and 4575 transitions. [2023-11-28 20:20:49,748 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:49,748 INFO L428 stractBuchiCegarLoop]: Abstraction has 3124 states and 4575 transitions. [2023-11-28 20:20:49,748 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-28 20:20:49,749 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3124 states and 4575 transitions. [2023-11-28 20:20:49,763 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 2993 [2023-11-28 20:20:49,763 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:49,763 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:49,765 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:49,765 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:49,765 INFO L748 eck$LassoCheckResult]: Stem: 24613#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 24614#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 25349#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 25350#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 25351#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 24735#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24736#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 25341#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 25335#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 24819#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24820#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 25079#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 25080#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24911#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 24912#L838 assume !(0 == ~M_E~0); 25087#L838-2 assume !(0 == ~T1_E~0); 24407#L843-1 assume !(0 == ~T2_E~0); 24408#L848-1 assume !(0 == ~T3_E~0); 24530#L853-1 assume !(0 == ~T4_E~0); 24898#L858-1 assume !(0 == ~T5_E~0); 24358#L863-1 assume !(0 == ~T6_E~0); 24359#L868-1 assume !(0 == ~T7_E~0); 25407#L873-1 assume !(0 == ~T8_E~0); 25404#L878-1 assume !(0 == ~E_1~0); 25379#L883-1 assume !(0 == ~E_2~0); 25380#L888-1 assume !(0 == ~E_3~0); 25047#L893-1 assume !(0 == ~E_4~0); 25048#L898-1 assume !(0 == ~E_5~0); 25422#L903-1 assume !(0 == ~E_6~0); 25375#L908-1 assume !(0 == ~E_7~0); 25197#L913-1 assume !(0 == ~E_8~0); 24420#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24421#L402 assume !(1 == ~m_pc~0); 24636#L402-2 is_master_triggered_~__retres1~0#1 := 0; 24554#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24555#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 24826#L1035 assume !(0 != activate_threads_~tmp~1#1); 24827#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24885#L421 assume !(1 == ~t1_pc~0); 25371#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 25408#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24424#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 24425#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 24941#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 25419#L440 assume 1 == ~t2_pc~0; 24391#L441 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 24392#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 24564#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24762#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 25215#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24765#L459 assume !(1 == ~t3_pc~0); 24766#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 25362#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 24380#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 24381#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24549#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24558#L478 assume 1 == ~t4_pc~0; 24559#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 25052#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 24502#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24503#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 24462#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 24463#L497 assume !(1 == ~t5_pc~0); 24513#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 24514#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 25131#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 25265#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 25357#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 25358#L516 assume 1 == ~t6_pc~0; 25454#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 25078#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 24745#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24607#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 24608#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 25067#L535 assume !(1 == ~t7_pc~0); 25068#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 25146#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 25147#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 25186#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 25174#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 25175#L554 assume 1 == ~t8_pc~0; 25105#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24383#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 25207#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 24695#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 24696#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24369#L931 assume !(1 == ~M_E~0); 24370#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 25397#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 25430#L941-1 assume !(1 == ~T3_E~0); 24886#L946-1 assume !(1 == ~T4_E~0); 24887#L951-1 assume !(1 == ~T5_E~0); 24622#L956-1 assume !(1 == ~T6_E~0); 24623#L961-1 assume !(1 == ~T7_E~0); 25049#L966-1 assume !(1 == ~T8_E~0); 25050#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 25178#L976-1 assume !(1 == ~E_2~0); 25135#L981-1 assume !(1 == ~E_3~0); 25136#L986-1 assume !(1 == ~E_4~0); 24649#L991-1 assume !(1 == ~E_5~0); 24650#L996-1 assume !(1 == ~E_6~0); 25412#L1001-1 assume !(1 == ~E_7~0); 25413#L1006-1 assume !(1 == ~E_8~0); 25369#L1011-1 assume { :end_inline_reset_delta_events } true; 25243#L1272-2 [2023-11-28 20:20:49,766 INFO L750 eck$LassoCheckResult]: Loop: 25243#L1272-2 assume !false; 25093#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24670#L813-1 assume !false; 25433#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 26690#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 25044#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24783#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 24784#L696 assume !(0 != eval_~tmp~0#1); 26680#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 26679#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 26678#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 26677#L838-5 assume !(0 == ~T1_E~0); 26674#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 26675#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 27404#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27403#L858-3 assume !(0 == ~T5_E~0); 27402#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27401#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27400#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 27399#L878-3 assume !(0 == ~E_1~0); 27398#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27397#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27396#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 27395#L898-3 assume !(0 == ~E_5~0); 27394#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27393#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27392#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27391#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27390#L402-27 assume 1 == ~m_pc~0; 27388#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 27387#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27386#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 27385#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 27384#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27383#L421-27 assume !(1 == ~t1_pc~0); 27382#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 27381#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27380#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27379#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 27378#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27377#L440-27 assume !(1 == ~t2_pc~0); 27376#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 27374#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27373#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27372#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 27371#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27370#L459-27 assume 1 == ~t3_pc~0; 27368#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27367#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27366#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27365#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27364#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27363#L478-27 assume 1 == ~t4_pc~0; 27361#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27360#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27359#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27358#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27357#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27356#L497-27 assume 1 == ~t5_pc~0; 27354#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27353#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27352#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27351#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27350#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27349#L516-27 assume !(1 == ~t6_pc~0); 27347#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 27346#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27345#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27344#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 27343#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27342#L535-27 assume 1 == ~t7_pc~0; 27340#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 27339#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27338#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27337#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27336#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27335#L554-27 assume !(1 == ~t8_pc~0); 27333#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 27332#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27331#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27330#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 27329#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27328#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 27327#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 27326#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24787#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 27325#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 27324#L951-3 assume !(1 == ~T5_E~0); 27323#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 27322#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 27321#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 27320#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 27319#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 27318#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 27317#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27316#L991-3 assume !(1 == ~E_5~0); 26009#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27315#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27314#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27313#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 27311#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 27303#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 27302#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 27300#L1291 assume !(0 == start_simulation_~tmp~3#1); 27298#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 24907#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 24482#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 24422#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 24423#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 24867#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24868#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 25242#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 25243#L1272-2 [2023-11-28 20:20:49,766 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:49,766 INFO L85 PathProgramCache]: Analyzing trace with hash 493551747, now seen corresponding path program 1 times [2023-11-28 20:20:49,766 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:49,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1254768350] [2023-11-28 20:20:49,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:49,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:49,780 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:49,820 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:49,820 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:49,820 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1254768350] [2023-11-28 20:20:49,821 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1254768350] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:49,821 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:49,821 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:20:49,821 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1453007082] [2023-11-28 20:20:49,821 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:49,822 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:49,822 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:49,822 INFO L85 PathProgramCache]: Analyzing trace with hash -1502078349, now seen corresponding path program 1 times [2023-11-28 20:20:49,822 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:49,822 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [998903081] [2023-11-28 20:20:49,823 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:49,823 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:49,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:49,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:49,868 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:49,868 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [998903081] [2023-11-28 20:20:49,868 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [998903081] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:49,868 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:49,868 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:49,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1979987227] [2023-11-28 20:20:49,869 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:49,869 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:49,869 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:49,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:49,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:49,870 INFO L87 Difference]: Start difference. First operand 3124 states and 4575 transitions. cyclomatic complexity: 1455 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:50,014 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:50,014 INFO L93 Difference]: Finished difference Result 5826 states and 8485 transitions. [2023-11-28 20:20:50,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 5826 states and 8485 transitions. [2023-11-28 20:20:50,047 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5684 [2023-11-28 20:20:50,089 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 5826 states to 5826 states and 8485 transitions. [2023-11-28 20:20:50,089 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 5826 [2023-11-28 20:20:50,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 5826 [2023-11-28 20:20:50,097 INFO L73 IsDeterministic]: Start isDeterministic. Operand 5826 states and 8485 transitions. [2023-11-28 20:20:50,107 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:50,107 INFO L218 hiAutomatonCegarLoop]: Abstraction has 5826 states and 8485 transitions. [2023-11-28 20:20:50,115 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 5826 states and 8485 transitions. [2023-11-28 20:20:50,219 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 5826 to 5818. [2023-11-28 20:20:50,232 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5818 states, 5818 states have (on average 1.4570299071845996) internal successors, (8477), 5817 states have internal predecessors, (8477), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:50,250 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 5818 states to 5818 states and 8477 transitions. [2023-11-28 20:20:50,250 INFO L240 hiAutomatonCegarLoop]: Abstraction has 5818 states and 8477 transitions. [2023-11-28 20:20:50,250 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:50,251 INFO L428 stractBuchiCegarLoop]: Abstraction has 5818 states and 8477 transitions. [2023-11-28 20:20:50,251 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-28 20:20:50,251 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 5818 states and 8477 transitions. [2023-11-28 20:20:50,278 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5676 [2023-11-28 20:20:50,278 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:50,278 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:50,280 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:50,281 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:50,281 INFO L748 eck$LassoCheckResult]: Stem: 33564#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 33565#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 34233#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 34234#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 34235#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 33682#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 33683#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34231#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34225#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 33758#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 33759#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 33999#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 34000#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 33843#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 33844#L838 assume !(0 == ~M_E~0); 34007#L838-2 assume !(0 == ~T1_E~0); 33363#L843-1 assume !(0 == ~T2_E~0); 33364#L848-1 assume !(0 == ~T3_E~0); 33482#L853-1 assume !(0 == ~T4_E~0); 33830#L858-1 assume !(0 == ~T5_E~0); 33315#L863-1 assume !(0 == ~T6_E~0); 33316#L868-1 assume !(0 == ~T7_E~0); 34277#L873-1 assume !(0 == ~T8_E~0); 34274#L878-1 assume !(0 == ~E_1~0); 34256#L883-1 assume !(0 == ~E_2~0); 34257#L888-1 assume !(0 == ~E_3~0); 33968#L893-1 assume !(0 == ~E_4~0); 33969#L898-1 assume !(0 == ~E_5~0); 34293#L903-1 assume !(0 == ~E_6~0); 34254#L908-1 assume !(0 == ~E_7~0); 34109#L913-1 assume !(0 == ~E_8~0); 33375#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33376#L402 assume !(1 == ~m_pc~0); 33589#L402-2 is_master_triggered_~__retres1~0#1 := 0; 33507#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 33508#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 33764#L1035 assume !(0 != activate_threads_~tmp~1#1); 33765#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 33818#L421 assume !(1 == ~t1_pc~0); 34251#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 34278#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33378#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33379#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 33872#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34290#L440 assume !(1 == ~t2_pc~0); 34326#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 33517#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 33518#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33708#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 34126#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33711#L459 assume !(1 == ~t3_pc~0); 33712#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 34246#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33337#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33338#L1059 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33501#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 33511#L478 assume 1 == ~t4_pc~0; 33512#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33973#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33454#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33455#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 33416#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 33417#L497 assume !(1 == ~t5_pc~0); 33465#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 33466#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34049#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34170#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 34241#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 34242#L516 assume 1 == ~t6_pc~0; 34320#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 33998#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33692#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 33558#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 33559#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33988#L535 assume !(1 == ~t7_pc~0); 33989#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34063#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 34064#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 34100#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 34090#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34091#L554 assume 1 == ~t8_pc~0; 34024#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 33340#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 34118#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33644#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 33645#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33326#L931 assume !(1 == ~M_E~0); 33327#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 34268#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34301#L941-1 assume !(1 == ~T3_E~0); 33819#L946-1 assume !(1 == ~T4_E~0); 33820#L951-1 assume !(1 == ~T5_E~0); 33573#L956-1 assume !(1 == ~T6_E~0); 33574#L961-1 assume !(1 == ~T7_E~0); 33970#L966-1 assume !(1 == ~T8_E~0); 33971#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 34093#L976-1 assume !(1 == ~E_2~0); 34053#L981-1 assume !(1 == ~E_3~0); 33823#L986-1 assume !(1 == ~E_4~0); 33600#L991-1 assume !(1 == ~E_5~0); 33601#L996-1 assume !(1 == ~E_6~0); 34285#L1001-1 assume !(1 == ~E_7~0); 34018#L1006-1 assume !(1 == ~E_8~0); 34019#L1011-1 assume { :end_inline_reset_delta_events } true; 34249#L1272-2 [2023-11-28 20:20:50,281 INFO L750 eck$LassoCheckResult]: Loop: 34249#L1272-2 assume !false; 38515#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 38514#L813-1 assume !false; 34192#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 34193#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 33389#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 33727#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 33728#L696 assume !(0 != eval_~tmp~0#1); 34203#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 36825#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 36826#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 37071#L838-5 assume !(0 == ~T1_E~0); 34296#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 33918#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 33919#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 33972#L858-3 assume !(0 == ~T5_E~0); 34041#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 34029#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 34030#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 33625#L878-3 assume !(0 == ~E_1~0); 33350#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 33351#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 33352#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 33353#L898-3 assume !(0 == ~E_5~0); 33849#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 34194#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 33857#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 33391#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 33392#L402-27 assume 1 == ~m_pc~0; 33341#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 33342#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 34065#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 34066#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 34217#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 34218#L421-27 assume !(1 == ~t1_pc~0); 33615#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 33616#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 33945#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 33946#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 34286#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 33991#L440-27 assume !(1 == ~t2_pc~0); 33992#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 34189#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34036#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 33894#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 33895#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 33603#L459-27 assume 1 == ~t3_pc~0; 33604#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34058#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 33869#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 33870#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 33987#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 34276#L478-27 assume 1 == ~t4_pc~0; 34306#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 33593#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 33779#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 33780#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 34154#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34195#L497-27 assume 1 == ~t5_pc~0; 34196#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 33635#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 33636#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 33579#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 33580#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 33851#L516-27 assume !(1 == ~t6_pc~0); 33852#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 33699#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 33700#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34009#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 34010#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 33783#L535-27 assume 1 == ~t7_pc~0; 33784#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 34132#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 33660#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 33661#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 33731#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 33732#L554-27 assume !(1 == ~t8_pc~0); 33365#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 33366#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 33516#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 33903#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 33622#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 33623#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 33497#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 33498#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 33729#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 33868#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 33638#L951-3 assume !(1 == ~T5_E~0); 33639#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 33942#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 33743#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 33744#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 33997#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 33384#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 33385#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 33373#L991-3 assume !(1 == ~E_5~0); 33374#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 34079#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 33716#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 33717#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 33411#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 33412#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 33666#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 33667#L1291 assume !(0 == start_simulation_~tmp~3#1); 34291#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 38631#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 38621#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 38620#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 38619#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 38616#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 38614#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 38612#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 34249#L1272-2 [2023-11-28 20:20:50,282 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:50,282 INFO L85 PathProgramCache]: Analyzing trace with hash -1412932446, now seen corresponding path program 1 times [2023-11-28 20:20:50,282 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:50,282 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1640552060] [2023-11-28 20:20:50,282 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:50,282 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:50,296 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:50,345 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:50,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:50,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1640552060] [2023-11-28 20:20:50,346 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1640552060] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:50,346 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:50,346 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:20:50,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [467533683] [2023-11-28 20:20:50,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:50,346 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:50,347 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:50,347 INFO L85 PathProgramCache]: Analyzing trace with hash -1502078349, now seen corresponding path program 2 times [2023-11-28 20:20:50,347 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:50,347 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [785221628] [2023-11-28 20:20:50,347 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:50,348 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:50,361 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:50,389 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:50,389 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:50,389 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [785221628] [2023-11-28 20:20:50,389 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [785221628] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:50,389 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:50,390 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:50,390 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [904692658] [2023-11-28 20:20:50,390 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:50,390 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:50,390 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:50,391 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 20:20:50,391 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 20:20:50,391 INFO L87 Difference]: Start difference. First operand 5818 states and 8477 transitions. cyclomatic complexity: 2667 Second operand has 5 states, 5 states have (on average 20.8) internal successors, (104), 5 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:50,753 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:50,753 INFO L93 Difference]: Finished difference Result 13862 states and 19988 transitions. [2023-11-28 20:20:50,753 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13862 states and 19988 transitions. [2023-11-28 20:20:50,838 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 13596 [2023-11-28 20:20:50,909 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13862 states to 13862 states and 19988 transitions. [2023-11-28 20:20:50,909 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13862 [2023-11-28 20:20:50,924 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13862 [2023-11-28 20:20:50,924 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13862 states and 19988 transitions. [2023-11-28 20:20:50,946 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:50,946 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13862 states and 19988 transitions. [2023-11-28 20:20:50,963 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13862 states and 19988 transitions. [2023-11-28 20:20:51,178 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13862 to 6025. [2023-11-28 20:20:51,193 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 6025 states, 6025 states have (on average 1.4413278008298755) internal successors, (8684), 6024 states have internal predecessors, (8684), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:51,215 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 6025 states to 6025 states and 8684 transitions. [2023-11-28 20:20:51,215 INFO L240 hiAutomatonCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2023-11-28 20:20:51,216 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-28 20:20:51,216 INFO L428 stractBuchiCegarLoop]: Abstraction has 6025 states and 8684 transitions. [2023-11-28 20:20:51,216 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-28 20:20:51,217 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 6025 states and 8684 transitions. [2023-11-28 20:20:51,249 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 5880 [2023-11-28 20:20:51,250 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:51,250 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:51,252 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:51,252 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:51,253 INFO L748 eck$LassoCheckResult]: Stem: 53261#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 53262#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 54014#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 54015#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 54016#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 53384#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 53385#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 54008#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 53993#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 53466#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 53467#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 53737#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 53738#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 53557#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 53558#L838 assume !(0 == ~M_E~0); 53748#L838-2 assume !(0 == ~T1_E~0); 53054#L843-1 assume !(0 == ~T2_E~0); 53055#L848-1 assume !(0 == ~T3_E~0); 53176#L853-1 assume !(0 == ~T4_E~0); 53544#L858-1 assume !(0 == ~T5_E~0); 53008#L863-1 assume !(0 == ~T6_E~0); 53009#L868-1 assume !(0 == ~T7_E~0); 54073#L873-1 assume !(0 == ~T8_E~0); 54070#L878-1 assume !(0 == ~E_1~0); 54044#L883-1 assume !(0 == ~E_2~0); 54045#L888-1 assume !(0 == ~E_3~0); 53700#L893-1 assume !(0 == ~E_4~0); 53701#L898-1 assume !(0 == ~E_5~0); 54097#L903-1 assume !(0 == ~E_6~0); 54041#L908-1 assume !(0 == ~E_7~0); 53862#L913-1 assume !(0 == ~E_8~0); 53066#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 53067#L402 assume !(1 == ~m_pc~0); 53284#L402-2 is_master_triggered_~__retres1~0#1 := 0; 53202#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 53203#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 53473#L1035 assume !(0 != activate_threads_~tmp~1#1); 53474#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 53531#L421 assume !(1 == ~t1_pc~0); 54037#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 54074#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 53069#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 53070#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 53589#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 54088#L440 assume !(1 == ~t2_pc~0); 54160#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 53212#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 53213#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 53412#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 53882#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 53416#L459 assume !(1 == ~t3_pc~0); 53417#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 54034#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 54087#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 53195#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 53196#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 53206#L478 assume 1 == ~t4_pc~0; 53207#L479 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 53705#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 53147#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 53148#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 53107#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 53108#L497 assume !(1 == ~t5_pc~0); 53158#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 53159#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 53797#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 53931#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 54028#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 54029#L516 assume 1 == ~t6_pc~0; 54148#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 53736#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 53394#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 53254#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 53255#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 53724#L535 assume !(1 == ~t7_pc~0); 53725#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 53815#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 53816#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 53852#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 53841#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 53842#L554 assume 1 == ~t8_pc~0; 53768#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 53033#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 53873#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 53346#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 53347#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 53019#L931 assume !(1 == ~M_E~0); 53020#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 54057#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 54109#L941-1 assume !(1 == ~T3_E~0); 53532#L946-1 assume !(1 == ~T4_E~0); 53533#L951-1 assume !(1 == ~T5_E~0); 53270#L956-1 assume !(1 == ~T6_E~0); 53271#L961-1 assume !(1 == ~T7_E~0); 53702#L966-1 assume !(1 == ~T8_E~0); 53703#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 53844#L976-1 assume !(1 == ~E_2~0); 53802#L981-1 assume !(1 == ~E_3~0); 53537#L986-1 assume !(1 == ~E_4~0); 53299#L991-1 assume !(1 == ~E_5~0); 53300#L996-1 assume !(1 == ~E_6~0); 54081#L1001-1 assume !(1 == ~E_7~0); 54082#L1006-1 assume !(1 == ~E_8~0); 54035#L1011-1 assume { :end_inline_reset_delta_events } true; 53077#L1272-2 [2023-11-28 20:20:51,253 INFO L750 eck$LassoCheckResult]: Loop: 53077#L1272-2 assume !false; 53078#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 53322#L813-1 assume !false; 56713#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 56710#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 56701#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 56699#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 56696#L696 assume !(0 != eval_~tmp~0#1); 56697#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 57168#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 57167#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 57166#L838-5 assume !(0 == ~T1_E~0); 57165#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 57164#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 57163#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 57162#L858-3 assume !(0 == ~T5_E~0); 57161#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 57160#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 57159#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 57158#L878-3 assume !(0 == ~E_1~0); 57157#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 57156#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 57155#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 57154#L898-3 assume !(0 == ~E_5~0); 57153#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 57152#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 57151#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 57150#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 57149#L402-27 assume 1 == ~m_pc~0; 57147#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 57146#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 57145#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 57144#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 57143#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 57142#L421-27 assume !(1 == ~t1_pc~0); 57141#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 57140#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 57139#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 57138#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 57137#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 57136#L440-27 assume !(1 == ~t2_pc~0); 57135#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 57134#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 57133#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 57132#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 57131#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 57130#L459-27 assume 1 == ~t3_pc~0; 57128#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 57126#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 57124#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 57122#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 57119#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 57116#L478-27 assume 1 == ~t4_pc~0; 57110#L479-9 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 57108#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 57078#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 57075#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 56938#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 56936#L497-27 assume 1 == ~t5_pc~0; 56933#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 56932#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 56929#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 56927#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 56925#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 56923#L516-27 assume !(1 == ~t6_pc~0); 56920#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 56918#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 56915#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 56913#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 56911#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 56909#L535-27 assume 1 == ~t7_pc~0; 56906#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 56904#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 56901#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 56899#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 56897#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 56895#L554-27 assume !(1 == ~t8_pc~0); 56877#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 56874#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 56872#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 56847#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 56842#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 56841#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 56840#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 56839#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 53434#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 56837#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 56835#L951-3 assume !(1 == ~T5_E~0); 56833#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 56831#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 56830#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 56828#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 53735#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 53075#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 53076#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 53064#L991-3 assume !(1 == ~E_5~0); 53065#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 53832#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 53421#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 53422#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 53102#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 53103#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 53367#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 53368#L1291 assume !(0 == start_simulation_~tmp~3#1); 56793#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 56792#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 53012#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 53013#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 53068#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 53517#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 53518#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 53609#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 53077#L1272-2 [2023-11-28 20:20:51,254 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:51,254 INFO L85 PathProgramCache]: Analyzing trace with hash -1894012704, now seen corresponding path program 1 times [2023-11-28 20:20:51,254 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:51,254 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [414280890] [2023-11-28 20:20:51,254 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:51,254 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:51,271 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:51,314 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:51,314 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:51,314 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [414280890] [2023-11-28 20:20:51,314 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [414280890] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:51,314 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:51,315 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:20:51,315 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1248588973] [2023-11-28 20:20:51,315 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:51,315 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:51,316 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:51,316 INFO L85 PathProgramCache]: Analyzing trace with hash -1502078349, now seen corresponding path program 3 times [2023-11-28 20:20:51,316 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:51,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [976094712] [2023-11-28 20:20:51,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:51,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:51,334 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:51,366 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:51,367 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:51,367 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [976094712] [2023-11-28 20:20:51,367 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [976094712] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:51,367 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:51,367 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:51,368 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1458956246] [2023-11-28 20:20:51,368 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:51,368 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:51,369 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:51,369 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:51,369 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:51,370 INFO L87 Difference]: Start difference. First operand 6025 states and 8684 transitions. cyclomatic complexity: 2667 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:51,508 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:51,508 INFO L93 Difference]: Finished difference Result 11580 states and 16593 transitions. [2023-11-28 20:20:51,508 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 11580 states and 16593 transitions. [2023-11-28 20:20:51,564 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11404 [2023-11-28 20:20:51,608 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 11580 states to 11580 states and 16593 transitions. [2023-11-28 20:20:51,609 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 11580 [2023-11-28 20:20:51,622 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 11580 [2023-11-28 20:20:51,622 INFO L73 IsDeterministic]: Start isDeterministic. Operand 11580 states and 16593 transitions. [2023-11-28 20:20:51,688 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:51,688 INFO L218 hiAutomatonCegarLoop]: Abstraction has 11580 states and 16593 transitions. [2023-11-28 20:20:51,702 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 11580 states and 16593 transitions. [2023-11-28 20:20:51,804 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 11580 to 11564. [2023-11-28 20:20:51,819 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 11564 states, 11564 states have (on average 1.4335005188516083) internal successors, (16577), 11563 states have internal predecessors, (16577), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:51,841 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 11564 states to 11564 states and 16577 transitions. [2023-11-28 20:20:51,841 INFO L240 hiAutomatonCegarLoop]: Abstraction has 11564 states and 16577 transitions. [2023-11-28 20:20:51,842 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:51,842 INFO L428 stractBuchiCegarLoop]: Abstraction has 11564 states and 16577 transitions. [2023-11-28 20:20:51,842 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-28 20:20:51,842 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 11564 states and 16577 transitions. [2023-11-28 20:20:51,873 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 11388 [2023-11-28 20:20:51,873 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:51,874 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:51,875 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:51,875 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:51,876 INFO L748 eck$LassoCheckResult]: Stem: 70868#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 70869#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 71568#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 71569#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 71570#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 70988#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 70989#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 71562#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 71554#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 71069#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 71070#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 71312#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 71313#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 71154#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 71155#L838 assume !(0 == ~M_E~0); 71322#L838-2 assume !(0 == ~T1_E~0); 70666#L843-1 assume !(0 == ~T2_E~0); 70667#L848-1 assume !(0 == ~T3_E~0); 70787#L853-1 assume !(0 == ~T4_E~0); 71143#L858-1 assume !(0 == ~T5_E~0); 70620#L863-1 assume !(0 == ~T6_E~0); 70621#L868-1 assume !(0 == ~T7_E~0); 71612#L873-1 assume !(0 == ~T8_E~0); 71610#L878-1 assume !(0 == ~E_1~0); 71597#L883-1 assume !(0 == ~E_2~0); 71598#L888-1 assume !(0 == ~E_3~0); 71281#L893-1 assume !(0 == ~E_4~0); 71282#L898-1 assume !(0 == ~E_5~0); 71640#L903-1 assume !(0 == ~E_6~0); 71595#L908-1 assume !(0 == ~E_7~0); 71421#L913-1 assume !(0 == ~E_8~0); 70680#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 70681#L402 assume !(1 == ~m_pc~0); 70894#L402-2 is_master_triggered_~__retres1~0#1 := 0; 70813#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 70814#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 71076#L1035 assume !(0 != activate_threads_~tmp~1#1); 71077#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 71129#L421 assume !(1 == ~t1_pc~0); 71590#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 71616#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 70682#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 70683#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 71183#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 71631#L440 assume !(1 == ~t2_pc~0); 71683#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 70822#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 70823#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 71014#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 71443#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 71021#L459 assume !(1 == ~t3_pc~0); 71022#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 71585#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 70642#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 70643#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 70808#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 70817#L478 assume !(1 == ~t4_pc~0); 70818#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 71502#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 70758#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 70759#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 70722#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 70723#L497 assume !(1 == ~t5_pc~0); 70769#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 70770#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 71361#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 71498#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 71578#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 71579#L516 assume 1 == ~t6_pc~0; 71676#L517 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 71311#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 70997#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 70862#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 70863#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 71299#L535 assume !(1 == ~t7_pc~0); 71300#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 71376#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 71377#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 71413#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 71403#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 71404#L554 assume 1 == ~t8_pc~0; 71339#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 70645#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 71432#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 70954#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 70955#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 70631#L931 assume !(1 == ~M_E~0); 70632#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 71604#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 71648#L941-1 assume !(1 == ~T3_E~0); 74948#L946-1 assume !(1 == ~T4_E~0); 74946#L951-1 assume !(1 == ~T5_E~0); 74944#L956-1 assume !(1 == ~T6_E~0); 74942#L961-1 assume !(1 == ~T7_E~0); 74939#L966-1 assume !(1 == ~T8_E~0); 74937#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 74935#L976-1 assume !(1 == ~E_2~0); 74933#L981-1 assume !(1 == ~E_3~0); 71134#L986-1 assume !(1 == ~E_4~0); 70905#L991-1 assume !(1 == ~E_5~0); 70906#L996-1 assume !(1 == ~E_6~0); 71621#L1001-1 assume !(1 == ~E_7~0); 71622#L1006-1 assume !(1 == ~E_8~0); 71586#L1011-1 assume { :end_inline_reset_delta_events } true; 71587#L1272-2 [2023-11-28 20:20:51,876 INFO L750 eck$LassoCheckResult]: Loop: 71587#L1272-2 assume !false; 75589#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 75587#L813-1 assume !false; 75585#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 75576#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 75565#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 75563#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 75560#L696 assume !(0 != eval_~tmp~0#1); 75561#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 76153#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 76152#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 76151#L838-5 assume !(0 == ~T1_E~0); 76150#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 76149#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 76148#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 76147#L858-3 assume !(0 == ~T5_E~0); 76146#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 76145#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 76144#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 76143#L878-3 assume !(0 == ~E_1~0); 76142#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 76141#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 76140#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 76139#L898-3 assume !(0 == ~E_5~0); 76138#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 76137#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 76136#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 76135#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 76134#L402-27 assume !(1 == ~m_pc~0); 76133#L402-29 is_master_triggered_~__retres1~0#1 := 0; 76131#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 76130#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 76129#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 76128#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 76127#L421-27 assume !(1 == ~t1_pc~0); 76126#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 76125#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 76124#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 76123#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 76122#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 76121#L440-27 assume !(1 == ~t2_pc~0); 76120#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 76119#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 76118#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 76117#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 76116#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 76115#L459-27 assume 1 == ~t3_pc~0; 76113#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 76111#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 76109#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 76107#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 76106#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 76105#L478-27 assume !(1 == ~t4_pc~0); 76104#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 76102#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 76099#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 76097#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 76095#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 76093#L497-27 assume !(1 == ~t5_pc~0); 76091#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 76088#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 76086#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 76084#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 76082#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 76080#L516-27 assume !(1 == ~t6_pc~0); 76077#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 76075#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 76073#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 76071#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 76069#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 76067#L535-27 assume !(1 == ~t7_pc~0); 76065#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 76062#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 76059#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 76056#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 76053#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 76050#L554-27 assume 1 == ~t8_pc~0; 76048#L555-9 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 76045#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 76043#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 76041#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 76039#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 76037#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 76034#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 76030#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 75169#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 76024#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 76021#L951-3 assume !(1 == ~T5_E~0); 76017#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 76013#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 76008#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 76003#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 75999#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 75995#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 75991#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 75987#L991-3 assume !(1 == ~E_5~0); 75106#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 75979#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 75975#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 75972#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 75905#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 75894#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 75889#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 75883#L1291 assume !(0 == start_simulation_~tmp~3#1); 75879#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 75809#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 75796#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 75789#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 75782#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 75778#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 75620#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 75600#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 71587#L1272-2 [2023-11-28 20:20:51,876 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:51,876 INFO L85 PathProgramCache]: Analyzing trace with hash -461177985, now seen corresponding path program 1 times [2023-11-28 20:20:51,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:51,877 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [977525187] [2023-11-28 20:20:51,877 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:51,877 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:51,890 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:51,972 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:51,972 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:51,972 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [977525187] [2023-11-28 20:20:51,972 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [977525187] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:51,972 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:51,973 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:20:51,973 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [974525993] [2023-11-28 20:20:51,973 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:51,973 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:51,973 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:51,974 INFO L85 PathProgramCache]: Analyzing trace with hash 143602128, now seen corresponding path program 1 times [2023-11-28 20:20:51,974 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:51,974 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1283393825] [2023-11-28 20:20:51,974 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:51,974 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:51,985 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:52,028 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:52,028 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:52,028 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1283393825] [2023-11-28 20:20:52,028 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1283393825] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:52,028 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:52,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:20:52,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1765361683] [2023-11-28 20:20:52,029 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:52,029 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:52,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:52,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:52,030 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:52,030 INFO L87 Difference]: Start difference. First operand 11564 states and 16577 transitions. cyclomatic complexity: 5029 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:52,153 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:52,154 INFO L93 Difference]: Finished difference Result 21803 states and 31130 transitions. [2023-11-28 20:20:52,154 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 21803 states and 31130 transitions. [2023-11-28 20:20:52,289 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21548 [2023-11-28 20:20:52,337 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 21803 states to 21803 states and 31130 transitions. [2023-11-28 20:20:52,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 21803 [2023-11-28 20:20:52,347 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 21803 [2023-11-28 20:20:52,348 INFO L73 IsDeterministic]: Start isDeterministic. Operand 21803 states and 31130 transitions. [2023-11-28 20:20:52,359 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:52,359 INFO L218 hiAutomatonCegarLoop]: Abstraction has 21803 states and 31130 transitions. [2023-11-28 20:20:52,434 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 21803 states and 31130 transitions. [2023-11-28 20:20:52,778 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 21803 to 21771. [2023-11-28 20:20:52,820 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 21771 states, 21771 states have (on average 1.4284139451564006) internal successors, (31098), 21770 states have internal predecessors, (31098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:52,875 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 21771 states to 21771 states and 31098 transitions. [2023-11-28 20:20:52,875 INFO L240 hiAutomatonCegarLoop]: Abstraction has 21771 states and 31098 transitions. [2023-11-28 20:20:52,876 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:52,876 INFO L428 stractBuchiCegarLoop]: Abstraction has 21771 states and 31098 transitions. [2023-11-28 20:20:52,877 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-28 20:20:52,877 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 21771 states and 31098 transitions. [2023-11-28 20:20:53,006 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21516 [2023-11-28 20:20:53,007 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:53,007 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:53,019 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:53,019 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:53,020 INFO L748 eck$LassoCheckResult]: Stem: 104247#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 104248#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 104982#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 104983#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 104985#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 104372#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 104373#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 104980#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 104966#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 104460#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 104461#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 104716#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 104717#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 104549#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 104550#L838 assume !(0 == ~M_E~0); 104725#L838-2 assume !(0 == ~T1_E~0); 104044#L843-1 assume !(0 == ~T2_E~0); 104045#L848-1 assume !(0 == ~T3_E~0); 104163#L853-1 assume !(0 == ~T4_E~0); 104538#L858-1 assume !(0 == ~T5_E~0); 103996#L863-1 assume !(0 == ~T6_E~0); 103997#L868-1 assume !(0 == ~T7_E~0); 105036#L873-1 assume !(0 == ~T8_E~0); 105034#L878-1 assume !(0 == ~E_1~0); 105012#L883-1 assume !(0 == ~E_2~0); 105013#L888-1 assume !(0 == ~E_3~0); 104684#L893-1 assume !(0 == ~E_4~0); 104685#L898-1 assume !(0 == ~E_5~0); 105060#L903-1 assume !(0 == ~E_6~0); 105009#L908-1 assume !(0 == ~E_7~0); 104831#L913-1 assume !(0 == ~E_8~0); 104057#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 104058#L402 assume !(1 == ~m_pc~0); 104273#L402-2 is_master_triggered_~__retres1~0#1 := 0; 104190#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 104191#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 104468#L1035 assume !(0 != activate_threads_~tmp~1#1); 104469#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 104524#L421 assume !(1 == ~t1_pc~0); 105004#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 105037#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 104059#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 104060#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 104578#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 105052#L440 assume !(1 == ~t2_pc~0); 105108#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 104199#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 104200#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 104401#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 104855#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 104411#L459 assume !(1 == ~t3_pc~0); 104412#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 105000#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 104018#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 104019#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 104184#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 104194#L478 assume !(1 == ~t4_pc~0); 104195#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 104914#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 104135#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 104136#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 104099#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 104100#L497 assume !(1 == ~t5_pc~0); 104146#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 104147#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 104770#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 104909#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 104994#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 104995#L516 assume !(1 == ~t6_pc~0); 104929#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 104715#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 104382#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 104241#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 104242#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 104704#L535 assume !(1 == ~t7_pc~0); 104705#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 104785#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 104786#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 104821#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 104811#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 104812#L554 assume 1 == ~t8_pc~0; 104744#L555 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 104021#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 104842#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 104337#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 104338#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 104007#L931 assume !(1 == ~M_E~0); 104008#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 105027#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 105074#L941-1 assume !(1 == ~T3_E~0); 108908#L946-1 assume !(1 == ~T4_E~0); 108907#L951-1 assume !(1 == ~T5_E~0); 108906#L956-1 assume !(1 == ~T6_E~0); 108905#L961-1 assume !(1 == ~T7_E~0); 108904#L966-1 assume !(1 == ~T8_E~0); 108903#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 108902#L976-1 assume !(1 == ~E_2~0); 108901#L981-1 assume !(1 == ~E_3~0); 108900#L986-1 assume !(1 == ~E_4~0); 108899#L991-1 assume !(1 == ~E_5~0); 104287#L996-1 assume !(1 == ~E_6~0); 108897#L1001-1 assume !(1 == ~E_7~0); 108895#L1006-1 assume !(1 == ~E_8~0); 108893#L1011-1 assume { :end_inline_reset_delta_events } true; 108891#L1272-2 [2023-11-28 20:20:53,022 INFO L750 eck$LassoCheckResult]: Loop: 108891#L1272-2 assume !false; 108603#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 108601#L813-1 assume !false; 108599#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 108590#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 108582#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 108579#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 108577#L696 assume !(0 != eval_~tmp~0#1); 108578#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 114106#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 114101#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 114096#L838-5 assume !(0 == ~T1_E~0); 114090#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 114085#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 114079#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 114073#L858-3 assume !(0 == ~T5_E~0); 114068#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 114063#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 114056#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 114051#L878-3 assume !(0 == ~E_1~0); 114045#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 114039#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 114034#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 114027#L898-3 assume !(0 == ~E_5~0); 114005#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 109181#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 109180#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 109178#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 109176#L402-27 assume 1 == ~m_pc~0; 109173#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 109172#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 109171#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 109170#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 109169#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 109167#L421-27 assume !(1 == ~t1_pc~0); 109165#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 109164#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 109163#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 109161#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 109151#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 109149#L440-27 assume !(1 == ~t2_pc~0); 109147#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 109144#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 109142#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 109140#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 109138#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 109136#L459-27 assume !(1 == ~t3_pc~0); 109132#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 109130#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 109128#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 109126#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 109123#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 109121#L478-27 assume !(1 == ~t4_pc~0); 109119#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 109117#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 109115#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 109113#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 109111#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 109109#L497-27 assume !(1 == ~t5_pc~0); 109107#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 109104#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 109102#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 109100#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 109098#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 109095#L516-27 assume !(1 == ~t6_pc~0); 109093#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 109091#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 109089#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 109087#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 109085#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 109083#L535-27 assume !(1 == ~t7_pc~0); 109081#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 109078#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 109076#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 109074#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 109072#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 109070#L554-27 assume !(1 == ~t8_pc~0); 109067#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 109065#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 109063#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 109061#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 109057#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 109055#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 109053#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 109051#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 108985#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 109047#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 109045#L951-3 assume !(1 == ~T5_E~0); 109043#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 109041#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 109039#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 109037#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 109035#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 109033#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 109030#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 108959#L991-3 assume !(1 == ~E_5~0); 108957#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 108955#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 108953#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 108951#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 108944#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 108935#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 108933#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 108929#L1291 assume !(0 == start_simulation_~tmp~3#1); 108926#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 108922#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 108913#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 108912#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 108911#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 108910#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 108909#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 108892#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 108891#L1272-2 [2023-11-28 20:20:53,023 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:53,023 INFO L85 PathProgramCache]: Analyzing trace with hash 2068972702, now seen corresponding path program 1 times [2023-11-28 20:20:53,023 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:53,024 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [334174612] [2023-11-28 20:20:53,024 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:53,024 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:53,034 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:53,066 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:53,066 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:53,066 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [334174612] [2023-11-28 20:20:53,066 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [334174612] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:53,066 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:53,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:20:53,067 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1618041754] [2023-11-28 20:20:53,067 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:53,067 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:53,067 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:53,067 INFO L85 PathProgramCache]: Analyzing trace with hash -1665010707, now seen corresponding path program 1 times [2023-11-28 20:20:53,068 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:53,068 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1915131273] [2023-11-28 20:20:53,068 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:53,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:53,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:53,116 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:53,116 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:53,116 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1915131273] [2023-11-28 20:20:53,116 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1915131273] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:53,117 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:53,117 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:20:53,117 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1074202582] [2023-11-28 20:20:53,117 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:53,117 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:53,118 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:53,118 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:53,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:53,118 INFO L87 Difference]: Start difference. First operand 21771 states and 31098 transitions. cyclomatic complexity: 9359 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:53,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:53,290 INFO L93 Difference]: Finished difference Result 43134 states and 61227 transitions. [2023-11-28 20:20:53,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43134 states and 61227 transitions. [2023-11-28 20:20:53,557 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42688 [2023-11-28 20:20:53,711 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43134 states to 43134 states and 61227 transitions. [2023-11-28 20:20:53,712 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43134 [2023-11-28 20:20:53,741 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43134 [2023-11-28 20:20:53,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43134 states and 61227 transitions. [2023-11-28 20:20:53,849 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:53,849 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43134 states and 61227 transitions. [2023-11-28 20:20:53,878 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43134 states and 61227 transitions. [2023-11-28 20:20:54,209 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43134 to 43006. [2023-11-28 20:20:54,250 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43006 states, 43006 states have (on average 1.4199646560944985) internal successors, (61067), 43005 states have internal predecessors, (61067), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:54,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43006 states to 43006 states and 61067 transitions. [2023-11-28 20:20:54,347 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43006 states and 61067 transitions. [2023-11-28 20:20:54,348 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:54,348 INFO L428 stractBuchiCegarLoop]: Abstraction has 43006 states and 61067 transitions. [2023-11-28 20:20:54,349 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-28 20:20:54,349 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43006 states and 61067 transitions. [2023-11-28 20:20:54,476 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2023-11-28 20:20:54,476 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:54,477 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:54,478 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:54,479 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:54,479 INFO L748 eck$LassoCheckResult]: Stem: 169159#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 169160#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 169850#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 169851#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 169853#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 169279#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 169280#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 169846#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 169840#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 169353#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 169354#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 169604#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 169605#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 169441#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 169442#L838 assume !(0 == ~M_E~0); 169616#L838-2 assume !(0 == ~T1_E~0); 168956#L843-1 assume !(0 == ~T2_E~0); 168957#L848-1 assume !(0 == ~T3_E~0); 169076#L853-1 assume !(0 == ~T4_E~0); 169430#L858-1 assume !(0 == ~T5_E~0); 168912#L863-1 assume !(0 == ~T6_E~0); 168913#L868-1 assume !(0 == ~T7_E~0); 169896#L873-1 assume !(0 == ~T8_E~0); 169894#L878-1 assume !(0 == ~E_1~0); 169879#L883-1 assume !(0 == ~E_2~0); 169880#L888-1 assume !(0 == ~E_3~0); 169574#L893-1 assume !(0 == ~E_4~0); 169575#L898-1 assume !(0 == ~E_5~0); 169910#L903-1 assume !(0 == ~E_6~0); 169876#L908-1 assume !(0 == ~E_7~0); 169713#L913-1 assume !(0 == ~E_8~0); 168969#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 168970#L402 assume !(1 == ~m_pc~0); 169187#L402-2 is_master_triggered_~__retres1~0#1 := 0; 169100#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 169101#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 169360#L1035 assume !(0 != activate_threads_~tmp~1#1); 169361#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 169416#L421 assume !(1 == ~t1_pc~0); 169872#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 169899#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 168971#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 168972#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 169473#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 169908#L440 assume !(1 == ~t2_pc~0); 169956#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 169111#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 169112#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 169305#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 169728#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 169313#L459 assume !(1 == ~t3_pc~0); 169314#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 169866#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 168932#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 168933#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 169095#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 169104#L478 assume !(1 == ~t4_pc~0); 169105#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 169778#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 169048#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 169049#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 169011#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 169012#L497 assume !(1 == ~t5_pc~0); 169059#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 169060#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 169651#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 169774#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 169861#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 169862#L516 assume !(1 == ~t6_pc~0); 169793#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 169603#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 169289#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 169153#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 169154#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 169592#L535 assume !(1 == ~t7_pc~0); 169593#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 169666#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 169667#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 169703#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 169691#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 169692#L554 assume !(1 == ~t8_pc~0); 168934#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 168935#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 169722#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 169244#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 169245#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 168921#L931 assume !(1 == ~M_E~0); 168922#L931-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 169889#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 169918#L941-1 assume !(1 == ~T3_E~0); 169417#L946-1 assume !(1 == ~T4_E~0); 169418#L951-1 assume !(1 == ~T5_E~0); 169169#L956-1 assume !(1 == ~T6_E~0); 169170#L961-1 assume !(1 == ~T7_E~0); 169576#L966-1 assume !(1 == ~T8_E~0); 169577#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 169930#L976-1 assume !(1 == ~E_2~0); 169655#L981-1 assume !(1 == ~E_3~0); 169656#L986-1 assume !(1 == ~E_4~0); 175401#L991-1 assume !(1 == ~E_5~0); 169197#L996-1 assume !(1 == ~E_6~0); 169901#L1001-1 assume !(1 == ~E_7~0); 169902#L1006-1 assume !(1 == ~E_8~0); 169869#L1011-1 assume { :end_inline_reset_delta_events } true; 169870#L1272-2 [2023-11-28 20:20:54,479 INFO L750 eck$LassoCheckResult]: Loop: 169870#L1272-2 assume !false; 179174#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 179171#L813-1 assume !false; 179166#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 179160#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 179150#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 179147#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 179142#L696 assume !(0 != eval_~tmp~0#1); 179143#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 181135#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 181129#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 181123#L838-5 assume !(0 == ~T1_E~0); 181117#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 181111#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 181106#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 181100#L858-3 assume !(0 == ~T5_E~0); 181094#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 181089#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 181083#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 181078#L878-3 assume !(0 == ~E_1~0); 181073#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 181067#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 181060#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 181055#L898-3 assume !(0 == ~E_5~0); 181049#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 181044#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 181039#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 181033#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 181027#L402-27 assume !(1 == ~m_pc~0); 181022#L402-29 is_master_triggered_~__retres1~0#1 := 0; 181014#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 181007#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 181001#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 180995#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 180988#L421-27 assume !(1 == ~t1_pc~0); 180982#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 180976#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 180970#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 180962#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 180954#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 180946#L440-27 assume !(1 == ~t2_pc~0); 180935#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 180926#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 180916#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 180907#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 180901#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 180898#L459-27 assume 1 == ~t3_pc~0; 180894#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 180889#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 180884#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 180879#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 180874#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 180868#L478-27 assume !(1 == ~t4_pc~0); 180863#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 180858#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 180852#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 180847#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 180842#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 180836#L497-27 assume !(1 == ~t5_pc~0); 180830#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 180822#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 180816#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 180811#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 180806#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 180800#L516-27 assume !(1 == ~t6_pc~0); 180795#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 180790#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 180784#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 180779#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 180773#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 180765#L535-27 assume 1 == ~t7_pc~0; 180759#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 180752#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 180745#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 180739#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 180732#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 180726#L554-27 assume !(1 == ~t8_pc~0); 180721#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 180716#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 180711#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 180706#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 180701#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 180694#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 180689#L931-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 180683#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 175660#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 180675#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 180670#L951-3 assume !(1 == ~T5_E~0); 180665#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 180660#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 180654#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 180649#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 180644#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 180640#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 180637#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 180634#L991-3 assume !(1 == ~E_5~0); 175625#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 180627#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 180626#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 180625#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 180620#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 180608#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 180604#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 180602#L1291 assume !(0 == start_simulation_~tmp~3#1); 180510#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 179401#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 179391#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 179389#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 179386#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 179384#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 179382#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 179379#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 169870#L1272-2 [2023-11-28 20:20:54,480 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:54,480 INFO L85 PathProgramCache]: Analyzing trace with hash 478577725, now seen corresponding path program 1 times [2023-11-28 20:20:54,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:54,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488198717] [2023-11-28 20:20:54,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:54,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:54,495 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:54,535 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:54,535 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:54,535 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488198717] [2023-11-28 20:20:54,535 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1488198717] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:54,535 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:54,536 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:20:54,536 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [641629084] [2023-11-28 20:20:54,536 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:54,536 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:54,536 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:54,537 INFO L85 PathProgramCache]: Analyzing trace with hash 534299920, now seen corresponding path program 1 times [2023-11-28 20:20:54,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:54,537 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194726286] [2023-11-28 20:20:54,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:54,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:54,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:54,685 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:54,686 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:54,686 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194726286] [2023-11-28 20:20:54,686 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [194726286] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:54,686 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:54,686 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:20:54,687 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1166427395] [2023-11-28 20:20:54,687 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:54,687 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:54,687 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:54,688 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:54,688 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:54,688 INFO L87 Difference]: Start difference. First operand 43006 states and 61067 transitions. cyclomatic complexity: 18125 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:54,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:54,833 INFO L93 Difference]: Finished difference Result 43006 states and 60873 transitions. [2023-11-28 20:20:54,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 43006 states and 60873 transitions. [2023-11-28 20:20:55,130 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2023-11-28 20:20:55,225 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 43006 states to 43006 states and 60873 transitions. [2023-11-28 20:20:55,225 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 43006 [2023-11-28 20:20:55,245 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 43006 [2023-11-28 20:20:55,245 INFO L73 IsDeterministic]: Start isDeterministic. Operand 43006 states and 60873 transitions. [2023-11-28 20:20:55,277 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:55,277 INFO L218 hiAutomatonCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2023-11-28 20:20:55,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 43006 states and 60873 transitions. [2023-11-28 20:20:55,603 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 43006 to 43006. [2023-11-28 20:20:55,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 43006 states, 43006 states have (on average 1.415453657629168) internal successors, (60873), 43005 states have internal predecessors, (60873), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:55,703 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 43006 states to 43006 states and 60873 transitions. [2023-11-28 20:20:55,703 INFO L240 hiAutomatonCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2023-11-28 20:20:55,704 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:55,704 INFO L428 stractBuchiCegarLoop]: Abstraction has 43006 states and 60873 transitions. [2023-11-28 20:20:55,704 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-28 20:20:55,705 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 43006 states and 60873 transitions. [2023-11-28 20:20:55,836 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2023-11-28 20:20:55,837 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:55,837 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:55,839 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:55,839 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:55,839 INFO L748 eck$LassoCheckResult]: Stem: 255176#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 255177#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 255903#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 255904#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 255906#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 255298#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 255299#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 255898#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 255888#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 255374#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 255375#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 255630#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 255631#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 255467#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 255468#L838 assume !(0 == ~M_E~0); 255642#L838-2 assume !(0 == ~T1_E~0); 254979#L843-1 assume !(0 == ~T2_E~0); 254980#L848-1 assume !(0 == ~T3_E~0); 255098#L853-1 assume !(0 == ~T4_E~0); 255453#L858-1 assume !(0 == ~T5_E~0); 254931#L863-1 assume !(0 == ~T6_E~0); 254932#L868-1 assume !(0 == ~T7_E~0); 255956#L873-1 assume !(0 == ~T8_E~0); 255954#L878-1 assume !(0 == ~E_1~0); 255932#L883-1 assume !(0 == ~E_2~0); 255933#L888-1 assume !(0 == ~E_3~0); 255597#L893-1 assume !(0 == ~E_4~0); 255598#L898-1 assume !(0 == ~E_5~0); 255970#L903-1 assume !(0 == ~E_6~0); 255929#L908-1 assume !(0 == ~E_7~0); 255749#L913-1 assume !(0 == ~E_8~0); 254991#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 254992#L402 assume !(1 == ~m_pc~0); 255201#L402-2 is_master_triggered_~__retres1~0#1 := 0; 255122#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 255123#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 255381#L1035 assume !(0 != activate_threads_~tmp~1#1); 255382#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 255439#L421 assume !(1 == ~t1_pc~0); 255922#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 255957#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 254994#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 254995#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 255497#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 255966#L440 assume !(1 == ~t2_pc~0); 256014#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 255131#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 255132#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 255325#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 255767#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 255328#L459 assume !(1 == ~t3_pc~0); 255329#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 255917#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 254953#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 254954#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 255117#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 255126#L478 assume !(1 == ~t4_pc~0); 255127#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 255828#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 255070#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 255071#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 255032#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 255033#L497 assume !(1 == ~t5_pc~0); 255081#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 255082#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 255682#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 255823#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 255912#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 255913#L516 assume !(1 == ~t6_pc~0); 255844#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 255629#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 255308#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 255170#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 255171#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 255618#L535 assume !(1 == ~t7_pc~0); 255619#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 255697#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 255698#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 255739#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 255726#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 255727#L554 assume !(1 == ~t8_pc~0); 254955#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 254956#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 255759#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 255261#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 255262#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 254942#L931 assume !(1 == ~M_E~0); 254943#L931-2 assume !(1 == ~T1_E~0); 255948#L936-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 255978#L941-1 assume !(1 == ~T3_E~0); 255440#L946-1 assume !(1 == ~T4_E~0); 255441#L951-1 assume !(1 == ~T5_E~0); 255186#L956-1 assume !(1 == ~T6_E~0); 255187#L961-1 assume !(1 == ~T7_E~0); 255599#L966-1 assume !(1 == ~T8_E~0); 255600#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 255730#L976-1 assume !(1 == ~E_2~0); 255686#L981-1 assume !(1 == ~E_3~0); 255446#L986-1 assume !(1 == ~E_4~0); 255214#L991-1 assume !(1 == ~E_5~0); 255215#L996-1 assume !(1 == ~E_6~0); 255960#L1001-1 assume !(1 == ~E_7~0); 255653#L1006-1 assume !(1 == ~E_8~0); 255654#L1011-1 assume { :end_inline_reset_delta_events } true; 255920#L1272-2 [2023-11-28 20:20:55,840 INFO L750 eck$LassoCheckResult]: Loop: 255920#L1272-2 assume !false; 275876#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 275625#L813-1 assume !false; 275624#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 261512#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 261503#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 261501#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 261498#L696 assume !(0 != eval_~tmp~0#1); 261499#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 282032#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282030#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 282028#L838-5 assume !(0 == ~T1_E~0); 282026#L843-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 282024#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 282022#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 282020#L858-3 assume !(0 == ~T5_E~0); 282018#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 282016#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 282014#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 282012#L878-3 assume !(0 == ~E_1~0); 282010#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 282008#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 282006#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 282004#L898-3 assume !(0 == ~E_5~0); 282002#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 282000#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 281996#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 281994#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 281992#L402-27 assume 1 == ~m_pc~0; 281989#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 281986#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 281984#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 281982#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 281980#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 281978#L421-27 assume !(1 == ~t1_pc~0); 281976#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 281974#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 281972#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 281970#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 281967#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 281965#L440-27 assume !(1 == ~t2_pc~0); 281963#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 281961#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 281959#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 281957#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 281955#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 281953#L459-27 assume !(1 == ~t3_pc~0); 281949#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 281947#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 281945#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 281943#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 281939#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 281937#L478-27 assume !(1 == ~t4_pc~0); 281935#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 281933#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 281931#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 281929#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 281926#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 281924#L497-27 assume 1 == ~t5_pc~0; 281921#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 281919#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 281917#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 281915#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 281913#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 281911#L516-27 assume !(1 == ~t6_pc~0); 281910#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 281908#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 281906#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 281904#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 281902#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 281900#L535-27 assume 1 == ~t7_pc~0; 281897#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 281895#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 281893#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 281891#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 281889#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 281888#L554-27 assume !(1 == ~t8_pc~0); 281086#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 281083#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 281081#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 281079#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 281066#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 281057#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 281052#L931-5 assume !(1 == ~T1_E~0); 280858#L936-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 265595#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 280847#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 280845#L951-3 assume !(1 == ~T5_E~0); 280834#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 276759#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 276758#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 276757#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 276756#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 276755#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 276753#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 276752#L991-3 assume !(1 == ~E_5~0); 265571#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 276751#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 276750#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 276748#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 275935#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 275926#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 275923#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 275920#L1291 assume !(0 == start_simulation_~tmp~3#1); 275917#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 275913#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 275903#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 275901#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 275899#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 275897#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 275895#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 275894#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 255920#L1272-2 [2023-11-28 20:20:55,840 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:55,840 INFO L85 PathProgramCache]: Analyzing trace with hash -1109770177, now seen corresponding path program 1 times [2023-11-28 20:20:55,840 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:55,840 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [604728114] [2023-11-28 20:20:55,841 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:55,841 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:55,855 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:55,901 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:55,902 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:55,902 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [604728114] [2023-11-28 20:20:55,902 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [604728114] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:55,902 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:55,902 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:20:55,902 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [353663754] [2023-11-28 20:20:55,903 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:55,903 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:55,903 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:55,903 INFO L85 PathProgramCache]: Analyzing trace with hash 1773905841, now seen corresponding path program 1 times [2023-11-28 20:20:55,904 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:55,904 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1961391012] [2023-11-28 20:20:55,904 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:55,904 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:55,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:55,946 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:55,946 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:55,947 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1961391012] [2023-11-28 20:20:55,947 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1961391012] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:55,947 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:55,947 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:55,947 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1081633478] [2023-11-28 20:20:55,947 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:55,947 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:55,948 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:55,948 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:20:55,948 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:20:55,948 INFO L87 Difference]: Start difference. First operand 43006 states and 60873 transitions. cyclomatic complexity: 17931 Second operand has 3 states, 3 states have (on average 34.666666666666664) internal successors, (104), 2 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:56,252 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:56,252 INFO L93 Difference]: Finished difference Result 42995 states and 60691 transitions. [2023-11-28 20:20:56,252 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 42995 states and 60691 transitions. [2023-11-28 20:20:56,415 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 42624 [2023-11-28 20:20:56,611 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 42995 states to 42995 states and 60691 transitions. [2023-11-28 20:20:56,611 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 42995 [2023-11-28 20:20:56,625 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 42995 [2023-11-28 20:20:56,625 INFO L73 IsDeterministic]: Start isDeterministic. Operand 42995 states and 60691 transitions. [2023-11-28 20:20:56,638 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:56,638 INFO L218 hiAutomatonCegarLoop]: Abstraction has 42995 states and 60691 transitions. [2023-11-28 20:20:56,657 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 42995 states and 60691 transitions. [2023-11-28 20:20:56,837 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 42995 to 22079. [2023-11-28 20:20:56,853 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22079 states, 22079 states have (on average 1.4100276280628652) internal successors, (31132), 22078 states have internal predecessors, (31132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:56,896 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22079 states to 22079 states and 31132 transitions. [2023-11-28 20:20:56,896 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22079 states and 31132 transitions. [2023-11-28 20:20:56,897 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:20:56,897 INFO L428 stractBuchiCegarLoop]: Abstraction has 22079 states and 31132 transitions. [2023-11-28 20:20:56,897 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-28 20:20:56,898 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22079 states and 31132 transitions. [2023-11-28 20:20:56,958 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2023-11-28 20:20:56,958 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:56,959 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:56,961 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:56,961 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:56,961 INFO L748 eck$LassoCheckResult]: Stem: 341188#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 341189#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 341904#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 341905#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 341906#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 341308#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 341309#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 341895#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 341883#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 341386#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 341387#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 341633#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 341634#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 341475#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 341476#L838 assume !(0 == ~M_E~0); 341645#L838-2 assume !(0 == ~T1_E~0); 340985#L843-1 assume !(0 == ~T2_E~0); 340986#L848-1 assume !(0 == ~T3_E~0); 341104#L853-1 assume !(0 == ~T4_E~0); 341464#L858-1 assume !(0 == ~T5_E~0); 340939#L863-1 assume !(0 == ~T6_E~0); 340940#L868-1 assume !(0 == ~T7_E~0); 341954#L873-1 assume !(0 == ~T8_E~0); 341950#L878-1 assume !(0 == ~E_1~0); 341930#L883-1 assume !(0 == ~E_2~0); 341931#L888-1 assume !(0 == ~E_3~0); 341602#L893-1 assume !(0 == ~E_4~0); 341603#L898-1 assume !(0 == ~E_5~0); 341969#L903-1 assume !(0 == ~E_6~0); 341928#L908-1 assume !(0 == ~E_7~0); 341745#L913-1 assume !(0 == ~E_8~0); 340998#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 340999#L402 assume !(1 == ~m_pc~0); 341214#L402-2 is_master_triggered_~__retres1~0#1 := 0; 341131#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 341132#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 341393#L1035 assume !(0 != activate_threads_~tmp~1#1); 341394#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 341450#L421 assume !(1 == ~t1_pc~0); 341923#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 341956#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 341000#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 341001#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 341502#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 341963#L440 assume !(1 == ~t2_pc~0); 342023#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 341140#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 341141#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 341335#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 341763#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 341343#L459 assume !(1 == ~t3_pc~0); 341344#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 341920#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 340961#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 340962#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 341125#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 341135#L478 assume !(1 == ~t4_pc~0); 341136#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 341821#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 341076#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 341077#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 341040#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 341041#L497 assume !(1 == ~t5_pc~0); 341087#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 341088#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 341682#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 341816#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 341913#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 341914#L516 assume !(1 == ~t6_pc~0); 341837#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 341632#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 341318#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 341182#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 341183#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 341621#L535 assume !(1 == ~t7_pc~0); 341622#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 341696#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 341697#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 341734#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 341723#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 341724#L554 assume !(1 == ~t8_pc~0); 340963#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 340964#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 341755#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 341272#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 341273#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 340950#L931 assume !(1 == ~M_E~0); 340951#L931-2 assume !(1 == ~T1_E~0); 341942#L936-1 assume !(1 == ~T2_E~0); 341978#L941-1 assume !(1 == ~T3_E~0); 341451#L946-1 assume !(1 == ~T4_E~0); 341452#L951-1 assume !(1 == ~T5_E~0); 341198#L956-1 assume !(1 == ~T6_E~0); 341199#L961-1 assume !(1 == ~T7_E~0); 341604#L966-1 assume !(1 == ~T8_E~0); 341605#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 341726#L976-1 assume !(1 == ~E_2~0); 341686#L981-1 assume !(1 == ~E_3~0); 341455#L986-1 assume !(1 == ~E_4~0); 341225#L991-1 assume !(1 == ~E_5~0); 341226#L996-1 assume !(1 == ~E_6~0); 341958#L1001-1 assume !(1 == ~E_7~0); 341654#L1006-1 assume !(1 == ~E_8~0); 341655#L1011-1 assume { :end_inline_reset_delta_events } true; 341921#L1272-2 [2023-11-28 20:20:56,962 INFO L750 eck$LassoCheckResult]: Loop: 341921#L1272-2 assume !false; 347957#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 347955#L813-1 assume !false; 347953#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 347947#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 347937#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 347935#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 347827#L696 assume !(0 != eval_~tmp~0#1); 347828#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 348380#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 348378#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 348376#L838-5 assume !(0 == ~T1_E~0); 348374#L843-3 assume !(0 == ~T2_E~0); 348372#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 348370#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 348368#L858-3 assume !(0 == ~T5_E~0); 348366#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 348364#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 348361#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 348359#L878-3 assume !(0 == ~E_1~0); 348357#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 348355#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 348353#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 348351#L898-3 assume !(0 == ~E_5~0); 348349#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 348347#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 348345#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 348343#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 348341#L402-27 assume !(1 == ~m_pc~0); 348339#L402-29 is_master_triggered_~__retres1~0#1 := 0; 348336#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 348334#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 348332#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 348330#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 348328#L421-27 assume !(1 == ~t1_pc~0); 348326#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 348324#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 348322#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 348320#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 348318#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 348316#L440-27 assume !(1 == ~t2_pc~0); 348314#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 348312#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 348310#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 348308#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 348306#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 348305#L459-27 assume 1 == ~t3_pc~0; 348304#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 348302#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 348300#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 348297#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 348296#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 348295#L478-27 assume !(1 == ~t4_pc~0); 348294#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 348293#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 348292#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 348291#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 348290#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 348289#L497-27 assume !(1 == ~t5_pc~0); 348287#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 348285#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 348284#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 348283#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 348282#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 348280#L516-27 assume !(1 == ~t6_pc~0); 348277#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 348275#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 348273#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 348271#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 348269#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 348267#L535-27 assume !(1 == ~t7_pc~0); 348265#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 348262#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 348260#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 348258#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 348256#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 348254#L554-27 assume !(1 == ~t8_pc~0); 348252#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 348250#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 348248#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 348246#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 348244#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 348243#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 348239#L931-5 assume !(1 == ~T1_E~0); 348237#L936-3 assume !(1 == ~T2_E~0); 348235#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 348233#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 348230#L951-3 assume !(1 == ~T5_E~0); 348228#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 348226#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 348224#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 348222#L971-3 assume 1 == ~E_1~0;~E_1~0 := 2; 348220#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 348218#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 348216#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 348214#L991-3 assume !(1 == ~E_5~0); 348211#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 348209#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 348207#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 348205#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 348199#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 348190#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 348188#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 348185#L1291 assume !(0 == start_simulation_~tmp~3#1); 348182#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 348177#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 348167#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 348165#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 348163#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 348161#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 348159#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 348157#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 341921#L1272-2 [2023-11-28 20:20:56,962 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:56,963 INFO L85 PathProgramCache]: Analyzing trace with hash -2130838531, now seen corresponding path program 1 times [2023-11-28 20:20:56,963 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:56,963 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844490214] [2023-11-28 20:20:56,963 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:56,963 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:56,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:57,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:57,105 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:57,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844490214] [2023-11-28 20:20:57,106 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844490214] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:57,106 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:57,106 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:57,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1213375476] [2023-11-28 20:20:57,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:57,106 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:57,107 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:57,107 INFO L85 PathProgramCache]: Analyzing trace with hash 1153012589, now seen corresponding path program 1 times [2023-11-28 20:20:57,107 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:57,107 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [552448887] [2023-11-28 20:20:57,107 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:57,108 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:57,119 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:57,156 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:57,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:57,157 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [552448887] [2023-11-28 20:20:57,157 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [552448887] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:57,157 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:57,157 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:20:57,157 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [897280777] [2023-11-28 20:20:57,157 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:57,158 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:57,158 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:57,158 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-28 20:20:57,158 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-28 20:20:57,159 INFO L87 Difference]: Start difference. First operand 22079 states and 31132 transitions. cyclomatic complexity: 9085 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:57,368 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:57,368 INFO L93 Difference]: Finished difference Result 45574 states and 64007 transitions. [2023-11-28 20:20:57,368 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 45574 states and 64007 transitions. [2023-11-28 20:20:57,520 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 45056 [2023-11-28 20:20:57,726 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 45574 states to 45574 states and 64007 transitions. [2023-11-28 20:20:57,726 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 45574 [2023-11-28 20:20:57,740 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 45574 [2023-11-28 20:20:57,740 INFO L73 IsDeterministic]: Start isDeterministic. Operand 45574 states and 64007 transitions. [2023-11-28 20:20:57,751 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:57,751 INFO L218 hiAutomatonCegarLoop]: Abstraction has 45574 states and 64007 transitions. [2023-11-28 20:20:57,776 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 45574 states and 64007 transitions. [2023-11-28 20:20:57,988 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 45574 to 24766. [2023-11-28 20:20:58,002 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 24766 states, 24766 states have (on average 1.4045061778244368) internal successors, (34784), 24765 states have internal predecessors, (34784), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:58,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 24766 states to 24766 states and 34784 transitions. [2023-11-28 20:20:58,163 INFO L240 hiAutomatonCegarLoop]: Abstraction has 24766 states and 34784 transitions. [2023-11-28 20:20:58,164 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-28 20:20:58,164 INFO L428 stractBuchiCegarLoop]: Abstraction has 24766 states and 34784 transitions. [2023-11-28 20:20:58,164 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-28 20:20:58,164 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 24766 states and 34784 transitions. [2023-11-28 20:20:58,224 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 24448 [2023-11-28 20:20:58,224 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:58,225 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:58,226 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:58,226 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:58,226 INFO L748 eck$LassoCheckResult]: Stem: 408856#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 408857#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 409553#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 409554#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 409556#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 408974#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 408975#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 409549#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 409541#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 409052#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 409053#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 409301#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 409302#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 409139#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 409140#L838 assume !(0 == ~M_E~0); 409313#L838-2 assume !(0 == ~T1_E~0); 408650#L843-1 assume !(0 == ~T2_E~0); 408651#L848-1 assume !(0 == ~T3_E~0); 408771#L853-1 assume !(0 == ~T4_E~0); 409128#L858-1 assume !(0 == ~T5_E~0); 408604#L863-1 assume !(0 == ~T6_E~0); 408605#L868-1 assume !(0 == ~T7_E~0); 409614#L873-1 assume !(0 == ~T8_E~0); 409611#L878-1 assume 0 == ~E_1~0;~E_1~0 := 1; 409612#L883-1 assume !(0 == ~E_2~0); 409642#L888-1 assume !(0 == ~E_3~0); 409643#L893-1 assume !(0 == ~E_4~0); 409640#L898-1 assume !(0 == ~E_5~0); 409641#L903-1 assume !(0 == ~E_6~0); 409700#L908-1 assume !(0 == ~E_7~0); 409731#L913-1 assume !(0 == ~E_8~0); 409730#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 409432#L402 assume !(1 == ~m_pc~0); 409433#L402-2 is_master_triggered_~__retres1~0#1 := 0; 408799#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 408800#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 409729#L1035 assume !(0 != activate_threads_~tmp~1#1); 409113#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 409114#L421 assume !(1 == ~t1_pc~0); 409616#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 409617#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 409728#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 409169#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 409170#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 409697#L440 assume !(1 == ~t2_pc~0); 409698#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 408809#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 408810#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 409658#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 409659#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 409012#L459 assume !(1 == ~t3_pc~0); 409013#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 409726#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 409724#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 409722#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 409721#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 408803#L478 assume !(1 == ~t4_pc~0); 408804#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 409547#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 409548#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 408984#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 408985#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 409324#L497 assume !(1 == ~t5_pc~0); 409325#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 409355#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 409356#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 409629#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 409630#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 409685#L516 assume !(1 == ~t6_pc~0); 409686#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 409299#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 409300#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 409720#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 409719#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 409287#L535 assume !(1 == ~t7_pc~0); 409288#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 409718#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 409680#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 409404#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 409394#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 409395#L554 assume !(1 == ~t8_pc~0); 408626#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 408627#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 409715#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 408941#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 408942#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 408614#L931 assume !(1 == ~M_E~0); 408615#L931-2 assume !(1 == ~T1_E~0); 409652#L936-1 assume !(1 == ~T2_E~0); 409653#L941-1 assume !(1 == ~T3_E~0); 409694#L946-1 assume !(1 == ~T4_E~0); 409575#L951-1 assume !(1 == ~T5_E~0); 408865#L956-1 assume !(1 == ~T6_E~0); 408866#L961-1 assume !(1 == ~T7_E~0); 409687#L966-1 assume !(1 == ~T8_E~0); 409709#L971-1 assume 1 == ~E_1~0;~E_1~0 := 2; 409397#L976-1 assume !(1 == ~E_2~0); 409360#L981-1 assume !(1 == ~E_3~0); 409119#L986-1 assume !(1 == ~E_4~0); 408893#L991-1 assume !(1 == ~E_5~0); 408894#L996-1 assume !(1 == ~E_6~0); 409621#L1001-1 assume !(1 == ~E_7~0); 409322#L1006-1 assume !(1 == ~E_8~0); 409323#L1011-1 assume { :end_inline_reset_delta_events } true; 409576#L1272-2 [2023-11-28 20:20:58,227 INFO L750 eck$LassoCheckResult]: Loop: 409576#L1272-2 assume !false; 414762#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 414760#L813-1 assume !false; 414758#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 414451#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 414442#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 414440#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 414437#L696 assume !(0 != eval_~tmp~0#1); 414438#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 420265#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 420258#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 420253#L838-5 assume !(0 == ~T1_E~0); 420248#L843-3 assume !(0 == ~T2_E~0); 420244#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 420240#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 420232#L858-3 assume !(0 == ~T5_E~0); 420226#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 420221#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 420215#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 420208#L878-3 assume !(0 == ~E_1~0); 420209#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 420467#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 420465#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 420463#L898-3 assume !(0 == ~E_5~0); 420462#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 420461#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 420460#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 420459#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 420458#L402-27 assume 1 == ~m_pc~0; 420455#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 420454#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 420453#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 420451#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 420450#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 420449#L421-27 assume !(1 == ~t1_pc~0); 420448#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 420447#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 420445#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 420442#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 420440#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 420438#L440-27 assume !(1 == ~t2_pc~0); 420436#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 420434#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 420432#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 420430#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 420428#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 420426#L459-27 assume !(1 == ~t3_pc~0); 420422#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 420420#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 420418#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 420416#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 420413#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 420411#L478-27 assume !(1 == ~t4_pc~0); 420409#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 420407#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 420406#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 420405#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 420404#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 420403#L497-27 assume 1 == ~t5_pc~0; 420400#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 420396#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 420394#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 420392#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 420390#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 420387#L516-27 assume !(1 == ~t6_pc~0); 420385#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 420383#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 420380#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 420378#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 420376#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 420374#L535-27 assume 1 == ~t7_pc~0; 420342#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 420306#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 420305#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 420304#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 420302#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 420300#L554-27 assume !(1 == ~t8_pc~0); 420289#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 420275#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 420272#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 420269#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 420264#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 420257#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 420252#L931-5 assume !(1 == ~T1_E~0); 420247#L936-3 assume !(1 == ~T2_E~0); 420243#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 420239#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 420231#L951-3 assume !(1 == ~T5_E~0); 420225#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 420220#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 420214#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 420129#L971-3 assume !(1 == ~E_1~0); 420125#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 420122#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 420118#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 420114#L991-3 assume !(1 == ~E_5~0); 420111#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 420108#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 420105#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 420103#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 416315#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 416306#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 416304#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 415154#L1291 assume !(0 == start_simulation_~tmp~3#1); 415151#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 414904#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 414894#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 414892#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 414890#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 414888#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 414886#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 414880#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 409576#L1272-2 [2023-11-28 20:20:58,227 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:58,227 INFO L85 PathProgramCache]: Analyzing trace with hash -1073000453, now seen corresponding path program 1 times [2023-11-28 20:20:58,227 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:58,228 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [514809403] [2023-11-28 20:20:58,228 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:58,228 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:58,241 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:58,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:58,295 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:58,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [514809403] [2023-11-28 20:20:58,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [514809403] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:58,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:58,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:58,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [556767437] [2023-11-28 20:20:58,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:58,297 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:20:58,297 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:58,298 INFO L85 PathProgramCache]: Analyzing trace with hash -710335953, now seen corresponding path program 1 times [2023-11-28 20:20:58,298 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:58,298 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1816304471] [2023-11-28 20:20:58,298 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:58,298 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:58,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:58,344 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:58,345 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:58,345 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1816304471] [2023-11-28 20:20:58,345 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1816304471] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:58,345 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:58,346 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:20:58,346 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742466348] [2023-11-28 20:20:58,346 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:58,346 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:58,347 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:58,347 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-28 20:20:58,347 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-28 20:20:58,347 INFO L87 Difference]: Start difference. First operand 24766 states and 34784 transitions. cyclomatic complexity: 10050 Second operand has 4 states, 4 states have (on average 26.0) internal successors, (104), 3 states have internal predecessors, (104), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:58,560 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:58,561 INFO L93 Difference]: Finished difference Result 41983 states and 58906 transitions. [2023-11-28 20:20:58,561 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 41983 states and 58906 transitions. [2023-11-28 20:20:58,715 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 41552 [2023-11-28 20:20:58,811 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 41983 states to 41983 states and 58906 transitions. [2023-11-28 20:20:58,812 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 41983 [2023-11-28 20:20:58,833 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 41983 [2023-11-28 20:20:58,833 INFO L73 IsDeterministic]: Start isDeterministic. Operand 41983 states and 58906 transitions. [2023-11-28 20:20:58,853 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:58,853 INFO L218 hiAutomatonCegarLoop]: Abstraction has 41983 states and 58906 transitions. [2023-11-28 20:20:58,877 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 41983 states and 58906 transitions. [2023-11-28 20:20:59,215 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 41983 to 22079. [2023-11-28 20:20:59,229 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22079 states, 22079 states have (on average 1.4001539924815436) internal successors, (30914), 22078 states have internal predecessors, (30914), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:59,262 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22079 states to 22079 states and 30914 transitions. [2023-11-28 20:20:59,262 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22079 states and 30914 transitions. [2023-11-28 20:20:59,262 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-28 20:20:59,263 INFO L428 stractBuchiCegarLoop]: Abstraction has 22079 states and 30914 transitions. [2023-11-28 20:20:59,263 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-28 20:20:59,263 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22079 states and 30914 transitions. [2023-11-28 20:20:59,306 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21840 [2023-11-28 20:20:59,307 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:20:59,307 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:20:59,308 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:59,308 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:20:59,308 INFO L748 eck$LassoCheckResult]: Stem: 475608#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 475609#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 476288#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 476289#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 476291#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 475724#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 475725#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 476281#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 476274#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 475799#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 475800#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 476045#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 476046#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 475885#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 475886#L838 assume !(0 == ~M_E~0); 476056#L838-2 assume !(0 == ~T1_E~0); 475409#L843-1 assume !(0 == ~T2_E~0); 475410#L848-1 assume !(0 == ~T3_E~0); 475530#L853-1 assume !(0 == ~T4_E~0); 475873#L858-1 assume !(0 == ~T5_E~0); 475365#L863-1 assume !(0 == ~T6_E~0); 475366#L868-1 assume !(0 == ~T7_E~0); 476340#L873-1 assume !(0 == ~T8_E~0); 476338#L878-1 assume !(0 == ~E_1~0); 476321#L883-1 assume !(0 == ~E_2~0); 476322#L888-1 assume !(0 == ~E_3~0); 476012#L893-1 assume !(0 == ~E_4~0); 476013#L898-1 assume !(0 == ~E_5~0); 476360#L903-1 assume !(0 == ~E_6~0); 476319#L908-1 assume !(0 == ~E_7~0); 476157#L913-1 assume !(0 == ~E_8~0); 475422#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 475423#L402 assume !(1 == ~m_pc~0); 475633#L402-2 is_master_triggered_~__retres1~0#1 := 0; 475555#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 475556#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 475806#L1035 assume !(0 != activate_threads_~tmp~1#1); 475807#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 475859#L421 assume !(1 == ~t1_pc~0); 476309#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 476342#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 475424#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 475425#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 475914#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 476354#L440 assume !(1 == ~t2_pc~0); 476395#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 475564#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 475565#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 475751#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 476172#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 475758#L459 assume !(1 == ~t3_pc~0); 475759#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 476306#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 475383#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 475384#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 475549#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 475559#L478 assume !(1 == ~t4_pc~0); 475560#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 476227#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 475501#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 475502#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 475465#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 475466#L497 assume !(1 == ~t5_pc~0); 475512#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 475513#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 476095#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 476223#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 476301#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 476302#L516 assume !(1 == ~t6_pc~0); 476242#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 476044#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 475734#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 475602#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 475603#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 476031#L535 assume !(1 == ~t7_pc~0); 476032#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 476110#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 476111#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 476148#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 476138#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 476139#L554 assume !(1 == ~t8_pc~0); 475385#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 475386#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 476166#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 475691#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 475692#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 475373#L931 assume !(1 == ~M_E~0); 475374#L931-2 assume !(1 == ~T1_E~0); 476332#L936-1 assume !(1 == ~T2_E~0); 476367#L941-1 assume !(1 == ~T3_E~0); 475860#L946-1 assume !(1 == ~T4_E~0); 475861#L951-1 assume !(1 == ~T5_E~0); 475617#L956-1 assume !(1 == ~T6_E~0); 475618#L961-1 assume !(1 == ~T7_E~0); 476014#L966-1 assume !(1 == ~T8_E~0); 476015#L971-1 assume !(1 == ~E_1~0); 476141#L976-1 assume !(1 == ~E_2~0); 476099#L981-1 assume !(1 == ~E_3~0); 475864#L986-1 assume !(1 == ~E_4~0); 475644#L991-1 assume !(1 == ~E_5~0); 475645#L996-1 assume !(1 == ~E_6~0); 476348#L1001-1 assume !(1 == ~E_7~0); 476066#L1006-1 assume !(1 == ~E_8~0); 476067#L1011-1 assume { :end_inline_reset_delta_events } true; 476307#L1272-2 [2023-11-28 20:20:59,308 INFO L750 eck$LassoCheckResult]: Loop: 476307#L1272-2 assume !false; 481549#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 481547#L813-1 assume !false; 481545#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 481417#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 481405#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 481400#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 481395#L696 assume !(0 != eval_~tmp~0#1); 481396#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 482464#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 482461#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 482459#L838-5 assume !(0 == ~T1_E~0); 482457#L843-3 assume !(0 == ~T2_E~0); 482455#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 482453#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 482449#L858-3 assume !(0 == ~T5_E~0); 482447#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 482445#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 482443#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 482440#L878-3 assume !(0 == ~E_1~0); 482438#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 482436#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 482434#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 482432#L898-3 assume !(0 == ~E_5~0); 482430#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 482428#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 482426#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 482424#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 482421#L402-27 assume !(1 == ~m_pc~0); 482419#L402-29 is_master_triggered_~__retres1~0#1 := 0; 482416#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 482414#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 482413#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 482412#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 482411#L421-27 assume !(1 == ~t1_pc~0); 482410#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 482408#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 482406#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 482405#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 482404#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 482403#L440-27 assume !(1 == ~t2_pc~0); 482401#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 482400#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 482399#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 482398#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 482397#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 482395#L459-27 assume !(1 == ~t3_pc~0); 482390#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 482388#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 482386#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 482384#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 482381#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 482379#L478-27 assume !(1 == ~t4_pc~0); 482377#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 482375#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 482373#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 482371#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 482369#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 482367#L497-27 assume !(1 == ~t5_pc~0); 482365#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 482362#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 482360#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 482358#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 482356#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 482354#L516-27 assume !(1 == ~t6_pc~0); 482351#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 482349#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 482347#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 482344#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 482342#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 482340#L535-27 assume !(1 == ~t7_pc~0); 482338#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 482335#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 482333#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 482331#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 482329#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 482327#L554-27 assume !(1 == ~t8_pc~0); 482324#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 482322#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 482320#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 482318#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 482316#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 482314#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 482136#L931-5 assume !(1 == ~T1_E~0); 482130#L936-3 assume !(1 == ~T2_E~0); 482123#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 482117#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 482111#L951-3 assume !(1 == ~T5_E~0); 482105#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 482098#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 482092#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 482075#L971-3 assume !(1 == ~E_1~0); 481961#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 481956#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 481950#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 481944#L991-3 assume !(1 == ~E_5~0); 481937#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 481931#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 481925#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 481919#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 481694#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 481686#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 481684#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 481680#L1291 assume !(0 == start_simulation_~tmp~3#1); 481677#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 481673#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 481663#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 481661#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 481659#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 481657#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 481655#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 481653#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 476307#L1272-2 [2023-11-28 20:20:59,308 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:59,309 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 1 times [2023-11-28 20:20:59,309 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:59,309 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892459382] [2023-11-28 20:20:59,309 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:59,309 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:59,319 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:20:59,319 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:20:59,326 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:20:59,374 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:20:59,375 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:20:59,375 INFO L85 PathProgramCache]: Analyzing trace with hash 1077012108, now seen corresponding path program 1 times [2023-11-28 20:20:59,375 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:20:59,375 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2099203467] [2023-11-28 20:20:59,375 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:20:59,376 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:20:59,388 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:20:59,423 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:20:59,423 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:20:59,424 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2099203467] [2023-11-28 20:20:59,424 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2099203467] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:20:59,424 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:20:59,424 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:20:59,424 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1978686350] [2023-11-28 20:20:59,424 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:20:59,424 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:20:59,425 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:20:59,425 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 20:20:59,425 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 20:20:59,425 INFO L87 Difference]: Start difference. First operand 22079 states and 30914 transitions. cyclomatic complexity: 8867 Second operand has 5 states, 5 states have (on average 22.4) internal successors, (112), 5 states have internal predecessors, (112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:20:59,624 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:20:59,624 INFO L93 Difference]: Finished difference Result 40415 states and 55946 transitions. [2023-11-28 20:20:59,624 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40415 states and 55946 transitions. [2023-11-28 20:20:59,770 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40048 [2023-11-28 20:20:59,876 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40415 states to 40415 states and 55946 transitions. [2023-11-28 20:20:59,876 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40415 [2023-11-28 20:20:59,899 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40415 [2023-11-28 20:20:59,899 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40415 states and 55946 transitions. [2023-11-28 20:20:59,916 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:20:59,916 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40415 states and 55946 transitions. [2023-11-28 20:20:59,935 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40415 states and 55946 transitions. [2023-11-28 20:21:00,268 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40415 to 22175. [2023-11-28 20:21:00,280 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 22175 states, 22175 states have (on average 1.3984216459977452) internal successors, (31010), 22174 states have internal predecessors, (31010), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:00,312 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 22175 states to 22175 states and 31010 transitions. [2023-11-28 20:21:00,312 INFO L240 hiAutomatonCegarLoop]: Abstraction has 22175 states and 31010 transitions. [2023-11-28 20:21:00,313 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-28 20:21:00,313 INFO L428 stractBuchiCegarLoop]: Abstraction has 22175 states and 31010 transitions. [2023-11-28 20:21:00,314 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-28 20:21:00,314 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 22175 states and 31010 transitions. [2023-11-28 20:21:00,361 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 21936 [2023-11-28 20:21:00,361 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:00,361 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:00,362 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:00,362 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:00,363 INFO L748 eck$LassoCheckResult]: Stem: 538121#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 538122#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 538826#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 538827#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 538828#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 538236#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 538237#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 538819#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 538810#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 538314#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 538315#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 538565#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 538566#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 538399#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 538400#L838 assume !(0 == ~M_E~0); 538580#L838-2 assume !(0 == ~T1_E~0); 537920#L843-1 assume !(0 == ~T2_E~0); 537921#L848-1 assume !(0 == ~T3_E~0); 538039#L853-1 assume !(0 == ~T4_E~0); 538388#L858-1 assume !(0 == ~T5_E~0); 537874#L863-1 assume !(0 == ~T6_E~0); 537875#L868-1 assume !(0 == ~T7_E~0); 538880#L873-1 assume !(0 == ~T8_E~0); 538875#L878-1 assume !(0 == ~E_1~0); 538857#L883-1 assume !(0 == ~E_2~0); 538858#L888-1 assume !(0 == ~E_3~0); 538532#L893-1 assume !(0 == ~E_4~0); 538533#L898-1 assume !(0 == ~E_5~0); 538903#L903-1 assume !(0 == ~E_6~0); 538854#L908-1 assume !(0 == ~E_7~0); 538681#L913-1 assume !(0 == ~E_8~0); 537933#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 537934#L402 assume !(1 == ~m_pc~0); 538146#L402-2 is_master_triggered_~__retres1~0#1 := 0; 538066#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 538067#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 538321#L1035 assume !(0 != activate_threads_~tmp~1#1); 538322#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 538374#L421 assume !(1 == ~t1_pc~0); 538847#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 538883#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 537935#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 537936#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 538429#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 538896#L440 assume !(1 == ~t2_pc~0); 538945#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 538076#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 538077#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 538263#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 538699#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 538270#L459 assume !(1 == ~t3_pc~0); 538271#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 538844#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 537894#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 537895#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 538060#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 538070#L478 assume !(1 == ~t4_pc~0); 538071#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 538756#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 538011#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 538012#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 537975#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 537976#L497 assume !(1 == ~t5_pc~0); 538022#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 538023#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 538622#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 538751#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 538835#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 538836#L516 assume !(1 == ~t6_pc~0); 538770#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 538563#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 538246#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 538115#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 538116#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 538552#L535 assume !(1 == ~t7_pc~0); 538553#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 538637#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 538638#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 538672#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 538662#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 538663#L554 assume !(1 == ~t8_pc~0); 537896#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 537897#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 538692#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 538203#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 538204#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 537884#L931 assume !(1 == ~M_E~0); 537885#L931-2 assume !(1 == ~T1_E~0); 538866#L936-1 assume !(1 == ~T2_E~0); 538912#L941-1 assume !(1 == ~T3_E~0); 538375#L946-1 assume !(1 == ~T4_E~0); 538376#L951-1 assume !(1 == ~T5_E~0); 538130#L956-1 assume !(1 == ~T6_E~0); 538131#L961-1 assume !(1 == ~T7_E~0); 538534#L966-1 assume !(1 == ~T8_E~0); 538535#L971-1 assume !(1 == ~E_1~0); 538665#L976-1 assume !(1 == ~E_2~0); 538627#L981-1 assume !(1 == ~E_3~0); 538379#L986-1 assume !(1 == ~E_4~0); 538157#L991-1 assume !(1 == ~E_5~0); 538158#L996-1 assume !(1 == ~E_6~0); 538888#L1001-1 assume !(1 == ~E_7~0); 538590#L1006-1 assume !(1 == ~E_8~0); 538591#L1011-1 assume { :end_inline_reset_delta_events } true; 538845#L1272-2 [2023-11-28 20:21:00,363 INFO L750 eck$LassoCheckResult]: Loop: 538845#L1272-2 assume !false; 544041#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 543992#L813-1 assume !false; 543983#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 543977#L634 assume !(0 == ~m_st~0); 543978#L638 assume !(0 == ~t1_st~0); 543971#L642 assume !(0 == ~t2_st~0); 543972#L646 assume !(0 == ~t3_st~0); 543976#L650 assume !(0 == ~t4_st~0); 543969#L654 assume !(0 == ~t5_st~0); 543970#L658 assume !(0 == ~t6_st~0); 543975#L662 assume !(0 == ~t7_st~0); 543973#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 543974#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 540856#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 540857#L696 assume !(0 != eval_~tmp~0#1); 547350#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 547349#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 547348#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 547347#L838-5 assume !(0 == ~T1_E~0); 547346#L843-3 assume !(0 == ~T2_E~0); 547345#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 547344#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 547343#L858-3 assume !(0 == ~T5_E~0); 547342#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 547341#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 547340#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 547339#L878-3 assume !(0 == ~E_1~0); 547338#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 547337#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 547336#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 547335#L898-3 assume !(0 == ~E_5~0); 547334#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 547333#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 547332#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 547331#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 547330#L402-27 assume 1 == ~m_pc~0; 547328#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 547327#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 547326#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 547325#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 547324#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 547323#L421-27 assume !(1 == ~t1_pc~0); 547322#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 547321#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 547320#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 547319#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 547318#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 547317#L440-27 assume !(1 == ~t2_pc~0); 547316#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 547315#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 547314#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 547313#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 547312#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 547311#L459-27 assume 1 == ~t3_pc~0; 547309#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 547307#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 547305#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 547303#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 547302#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 547301#L478-27 assume !(1 == ~t4_pc~0); 547300#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 547299#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 547298#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 547297#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 547296#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 547295#L497-27 assume 1 == ~t5_pc~0; 547293#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 547292#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 547291#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 547290#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 547289#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 547288#L516-27 assume !(1 == ~t6_pc~0); 547287#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 547286#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 547285#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 547284#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 547283#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 547282#L535-27 assume 1 == ~t7_pc~0; 547280#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 547279#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 547278#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 547277#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 547276#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 547275#L554-27 assume !(1 == ~t8_pc~0); 547274#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 547273#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 547272#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 547271#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 547270#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 547269#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 547268#L931-5 assume !(1 == ~T1_E~0); 547267#L936-3 assume !(1 == ~T2_E~0); 547266#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 547265#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 547264#L951-3 assume !(1 == ~T5_E~0); 547263#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 547262#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 547261#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 547260#L971-3 assume !(1 == ~E_1~0); 547259#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 547258#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 547257#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 547256#L991-3 assume !(1 == ~E_5~0); 547255#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 547254#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 547253#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 547252#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 547250#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 547231#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 547226#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 547221#L1291 assume !(0 == start_simulation_~tmp~3#1); 547160#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 547159#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 547147#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 547143#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 547140#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 547137#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 547133#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 545280#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 538845#L1272-2 [2023-11-28 20:21:00,363 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:00,363 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 2 times [2023-11-28 20:21:00,363 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:00,363 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [273966266] [2023-11-28 20:21:00,364 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:00,364 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:00,379 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:00,379 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:00,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:00,421 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:00,421 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:00,421 INFO L85 PathProgramCache]: Analyzing trace with hash -342395588, now seen corresponding path program 1 times [2023-11-28 20:21:00,422 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:00,422 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1198397980] [2023-11-28 20:21:00,422 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:00,422 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:00,434 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:00,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:00,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:00,462 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1198397980] [2023-11-28 20:21:00,462 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1198397980] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:00,462 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:00,463 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:21:00,463 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1962104786] [2023-11-28 20:21:00,463 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:00,463 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:00,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:00,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:21:00,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:21:00,464 INFO L87 Difference]: Start difference. First operand 22175 states and 31010 transitions. cyclomatic complexity: 8867 Second operand has 3 states, 3 states have (on average 40.0) internal successors, (120), 3 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:00,612 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:00,612 INFO L93 Difference]: Finished difference Result 40724 states and 56454 transitions. [2023-11-28 20:21:00,612 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 40724 states and 56454 transitions. [2023-11-28 20:21:00,729 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40320 [2023-11-28 20:21:00,803 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 40724 states to 40724 states and 56454 transitions. [2023-11-28 20:21:00,803 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 40724 [2023-11-28 20:21:00,821 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 40724 [2023-11-28 20:21:00,821 INFO L73 IsDeterministic]: Start isDeterministic. Operand 40724 states and 56454 transitions. [2023-11-28 20:21:00,998 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:00,998 INFO L218 hiAutomatonCegarLoop]: Abstraction has 40724 states and 56454 transitions. [2023-11-28 20:21:01,017 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 40724 states and 56454 transitions. [2023-11-28 20:21:01,213 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 40724 to 40708. [2023-11-28 20:21:01,237 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40708 states, 40708 states have (on average 1.3864105335560577) internal successors, (56438), 40707 states have internal predecessors, (56438), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:01,299 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40708 states to 40708 states and 56438 transitions. [2023-11-28 20:21:01,299 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40708 states and 56438 transitions. [2023-11-28 20:21:01,300 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:21:01,300 INFO L428 stractBuchiCegarLoop]: Abstraction has 40708 states and 56438 transitions. [2023-11-28 20:21:01,300 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-28 20:21:01,300 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40708 states and 56438 transitions. [2023-11-28 20:21:01,391 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40304 [2023-11-28 20:21:01,391 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:01,392 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:01,393 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:01,393 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:01,393 INFO L748 eck$LassoCheckResult]: Stem: 601030#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 601031#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 601802#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 601803#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 601805#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 601157#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 601158#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 601796#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 601775#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 601241#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 601242#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 601502#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 601503#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 601330#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 601331#L838 assume !(0 == ~M_E~0); 601511#L838-2 assume !(0 == ~T1_E~0); 600825#L843-1 assume !(0 == ~T2_E~0); 600826#L848-1 assume !(0 == ~T3_E~0); 600946#L853-1 assume !(0 == ~T4_E~0); 601315#L858-1 assume !(0 == ~T5_E~0); 600781#L863-1 assume !(0 == ~T6_E~0); 600782#L868-1 assume !(0 == ~T7_E~0); 601870#L873-1 assume !(0 == ~T8_E~0); 601868#L878-1 assume !(0 == ~E_1~0); 601841#L883-1 assume !(0 == ~E_2~0); 601842#L888-1 assume !(0 == ~E_3~0); 601466#L893-1 assume !(0 == ~E_4~0); 601467#L898-1 assume !(0 == ~E_5~0); 601888#L903-1 assume !(0 == ~E_6~0); 601837#L908-1 assume !(0 == ~E_7~0); 601623#L913-1 assume !(0 == ~E_8~0); 600838#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 600839#L402 assume !(1 == ~m_pc~0); 601058#L402-2 is_master_triggered_~__retres1~0#1 := 0; 600974#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 600975#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 601249#L1035 assume !(0 != activate_threads_~tmp~1#1); 601250#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 601303#L421 assume !(1 == ~t1_pc~0); 601829#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 601872#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 600840#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 600841#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 601360#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 601882#L440 assume !(1 == ~t2_pc~0); 601949#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 600983#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 600984#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 601186#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 601640#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 601195#L459 assume !(1 == ~t3_pc~0); 601196#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 601823#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 601881#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 600967#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 600968#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 600978#L478 assume !(1 == ~t4_pc~0); 600979#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 601701#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 600917#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 600918#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 600878#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 600879#L497 assume !(1 == ~t5_pc~0); 600928#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 601421#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 601695#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 601696#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 601817#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 601818#L516 assume !(1 == ~t6_pc~0); 601720#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 601721#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 601167#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 601168#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 601574#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 601575#L535 assume !(1 == ~t7_pc~0); 601752#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 601751#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 601927#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 601613#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 601603#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 601604#L554 assume !(1 == ~t8_pc~0); 600801#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 600802#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 601970#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 601116#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 601117#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 600789#L931 assume !(1 == ~M_E~0); 600790#L931-2 assume !(1 == ~T1_E~0); 601899#L936-1 assume !(1 == ~T2_E~0); 601900#L941-1 assume !(1 == ~T3_E~0); 601948#L946-1 assume !(1 == ~T4_E~0); 601826#L951-1 assume !(1 == ~T5_E~0); 601039#L956-1 assume !(1 == ~T6_E~0); 601040#L961-1 assume !(1 == ~T7_E~0); 601468#L966-1 assume !(1 == ~T8_E~0); 601469#L971-1 assume !(1 == ~E_1~0); 601607#L976-1 assume !(1 == ~E_2~0); 601964#L981-1 assume !(1 == ~E_3~0); 601963#L986-1 assume !(1 == ~E_4~0); 601962#L991-1 assume !(1 == ~E_5~0); 601068#L996-1 assume !(1 == ~E_6~0); 601876#L1001-1 assume !(1 == ~E_7~0); 601523#L1006-1 assume !(1 == ~E_8~0); 601524#L1011-1 assume { :end_inline_reset_delta_events } true; 601827#L1272-2 [2023-11-28 20:21:01,394 INFO L750 eck$LassoCheckResult]: Loop: 601827#L1272-2 assume !false; 609944#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 609942#L813-1 assume !false; 609940#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 608147#L634 assume !(0 == ~m_st~0); 608148#L638 assume !(0 == ~t1_st~0); 608143#L642 assume !(0 == ~t2_st~0); 608144#L646 assume !(0 == ~t3_st~0); 608146#L650 assume !(0 == ~t4_st~0); 608139#L654 assume !(0 == ~t5_st~0); 608140#L658 assume !(0 == ~t6_st~0); 608145#L662 assume !(0 == ~t7_st~0); 608141#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 608142#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 610476#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 610474#L696 assume !(0 != eval_~tmp~0#1); 610472#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 610470#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 610468#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 610466#L838-5 assume !(0 == ~T1_E~0); 610464#L843-3 assume !(0 == ~T2_E~0); 610462#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 610459#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 610457#L858-3 assume !(0 == ~T5_E~0); 610455#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 610453#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 610451#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 610449#L878-3 assume !(0 == ~E_1~0); 610447#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 610445#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 610443#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 610441#L898-3 assume !(0 == ~E_5~0); 610439#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 610437#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 610434#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 610432#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 610430#L402-27 assume 1 == ~m_pc~0; 610427#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 610425#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 610423#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 610421#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 610419#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 610417#L421-27 assume !(1 == ~t1_pc~0); 610415#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 610413#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 610412#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 610408#L1043-27 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 610406#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 610404#L440-27 assume !(1 == ~t2_pc~0); 610403#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 610400#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 610399#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 610398#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 610395#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 610391#L459-27 assume !(1 == ~t3_pc~0); 610385#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 610381#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 610379#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 610377#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 610375#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 610374#L478-27 assume !(1 == ~t4_pc~0); 610373#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 610372#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 610371#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 610370#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 610369#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 610217#L497-27 assume 1 == ~t5_pc~0; 610216#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 610210#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 610207#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 610204#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 610201#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 610198#L516-27 assume !(1 == ~t6_pc~0); 610194#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 610190#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 610185#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 610180#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 610175#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 610170#L535-27 assume 1 == ~t7_pc~0; 610165#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 610160#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 610156#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 610152#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 610148#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 610143#L554-27 assume !(1 == ~t8_pc~0); 610139#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 610135#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 610130#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 610126#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 610122#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 610118#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 610114#L931-5 assume !(1 == ~T1_E~0); 610110#L936-3 assume !(1 == ~T2_E~0); 610106#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 610102#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 610098#L951-3 assume !(1 == ~T5_E~0); 610094#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 610090#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 610085#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 610079#L971-3 assume !(1 == ~E_1~0); 610074#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 610069#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 610064#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 610059#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 610054#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 610050#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 610046#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 610043#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 610003#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 609992#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 609988#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 609983#L1291 assume !(0 == start_simulation_~tmp~3#1); 609979#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 609975#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 609964#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 609961#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 609958#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 609956#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 609953#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 609950#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 601827#L1272-2 [2023-11-28 20:21:01,394 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:01,394 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 3 times [2023-11-28 20:21:01,394 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:01,394 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2120049973] [2023-11-28 20:21:01,395 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:01,395 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:01,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:01,406 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:01,412 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:01,435 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:01,435 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:01,435 INFO L85 PathProgramCache]: Analyzing trace with hash 747250007, now seen corresponding path program 1 times [2023-11-28 20:21:01,435 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:01,435 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1272315474] [2023-11-28 20:21:01,436 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:01,436 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:01,447 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:01,500 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:01,501 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:01,501 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1272315474] [2023-11-28 20:21:01,501 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1272315474] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:01,501 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:01,501 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:21:01,501 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1624933800] [2023-11-28 20:21:01,501 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:01,502 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:01,502 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:01,502 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 20:21:01,502 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 20:21:01,502 INFO L87 Difference]: Start difference. First operand 40708 states and 56438 transitions. cyclomatic complexity: 15762 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:01,992 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:01,992 INFO L93 Difference]: Finished difference Result 49220 states and 68029 transitions. [2023-11-28 20:21:01,992 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 49220 states and 68029 transitions. [2023-11-28 20:21:02,204 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 48720 [2023-11-28 20:21:02,329 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 49220 states to 49220 states and 68029 transitions. [2023-11-28 20:21:02,329 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 49220 [2023-11-28 20:21:02,356 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 49220 [2023-11-28 20:21:02,356 INFO L73 IsDeterministic]: Start isDeterministic. Operand 49220 states and 68029 transitions. [2023-11-28 20:21:02,381 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:02,382 INFO L218 hiAutomatonCegarLoop]: Abstraction has 49220 states and 68029 transitions. [2023-11-28 20:21:02,410 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 49220 states and 68029 transitions. [2023-11-28 20:21:02,730 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 49220 to 40804. [2023-11-28 20:21:02,755 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40804 states, 40804 states have (on average 1.3748897166944418) internal successors, (56101), 40803 states have internal predecessors, (56101), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:02,835 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40804 states to 40804 states and 56101 transitions. [2023-11-28 20:21:02,835 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40804 states and 56101 transitions. [2023-11-28 20:21:02,835 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-28 20:21:02,836 INFO L428 stractBuchiCegarLoop]: Abstraction has 40804 states and 56101 transitions. [2023-11-28 20:21:02,836 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-28 20:21:02,836 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40804 states and 56101 transitions. [2023-11-28 20:21:03,051 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 40400 [2023-11-28 20:21:03,052 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:03,052 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:03,053 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:03,053 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:03,053 INFO L748 eck$LassoCheckResult]: Stem: 690970#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 690971#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 691701#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 691702#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 691703#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 691093#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 691094#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 691696#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 691688#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 691174#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 691175#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 691431#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 691432#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 691263#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 691264#L838 assume !(0 == ~M_E~0); 691445#L838-2 assume !(0 == ~T1_E~0); 690764#L843-1 assume !(0 == ~T2_E~0); 690765#L848-1 assume !(0 == ~T3_E~0); 690884#L853-1 assume !(0 == ~T4_E~0); 691252#L858-1 assume !(0 == ~T5_E~0); 690721#L863-1 assume !(0 == ~T6_E~0); 690722#L868-1 assume !(0 == ~T7_E~0); 691763#L873-1 assume !(0 == ~T8_E~0); 691759#L878-1 assume !(0 == ~E_1~0); 691736#L883-1 assume !(0 == ~E_2~0); 691737#L888-1 assume !(0 == ~E_3~0); 691398#L893-1 assume !(0 == ~E_4~0); 691399#L898-1 assume !(0 == ~E_5~0); 691786#L903-1 assume !(0 == ~E_6~0); 691734#L908-1 assume !(0 == ~E_7~0); 691551#L913-1 assume !(0 == ~E_8~0); 690777#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 690778#L402 assume !(1 == ~m_pc~0); 690998#L402-2 is_master_triggered_~__retres1~0#1 := 0; 690912#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 690913#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 691181#L1035 assume !(0 != activate_threads_~tmp~1#1); 691182#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 691236#L421 assume !(1 == ~t1_pc~0); 691723#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 691767#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 690779#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 690780#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 691296#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 691777#L440 assume !(1 == ~t2_pc~0); 691850#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 690922#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 690923#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 691122#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 691570#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 691129#L459 assume !(1 == ~t3_pc~0); 691130#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 691718#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 691774#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 690905#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 690906#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 690916#L478 assume !(1 == ~t4_pc~0); 690917#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 691632#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 690855#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 690856#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 690819#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 690820#L497 assume !(1 == ~t5_pc~0); 690866#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 691359#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 691489#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 691778#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 691779#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 691838#L516 assume !(1 == ~t6_pc~0); 691839#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 691429#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 691430#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 690964#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 690965#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 691417#L535 assume !(1 == ~t7_pc~0); 691418#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 691504#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 691505#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 691872#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 691871#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 691704#L554 assume !(1 == ~t8_pc~0); 691705#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 691802#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 691803#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 691054#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 691055#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 690729#L931 assume !(1 == ~M_E~0); 690730#L931-2 assume !(1 == ~T1_E~0); 691798#L936-1 assume !(1 == ~T2_E~0); 691799#L941-1 assume !(1 == ~T3_E~0); 691849#L946-1 assume !(1 == ~T4_E~0); 691720#L951-1 assume !(1 == ~T5_E~0); 690979#L956-1 assume !(1 == ~T6_E~0); 690980#L961-1 assume !(1 == ~T7_E~0); 691400#L966-1 assume !(1 == ~T8_E~0); 691401#L971-1 assume !(1 == ~E_1~0); 691536#L976-1 assume !(1 == ~E_2~0); 691865#L981-1 assume !(1 == ~E_3~0); 691864#L986-1 assume !(1 == ~E_4~0); 691863#L991-1 assume !(1 == ~E_5~0); 691008#L996-1 assume !(1 == ~E_6~0); 691770#L1001-1 assume !(1 == ~E_7~0); 691456#L1006-1 assume !(1 == ~E_8~0); 691457#L1011-1 assume { :end_inline_reset_delta_events } true; 691721#L1272-2 [2023-11-28 20:21:03,053 INFO L750 eck$LassoCheckResult]: Loop: 691721#L1272-2 assume !false; 708299#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 708298#L813-1 assume !false; 708297#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 708295#L634 assume !(0 == ~m_st~0); 708296#L638 assume !(0 == ~t1_st~0); 708291#L642 assume !(0 == ~t2_st~0); 708292#L646 assume !(0 == ~t3_st~0); 708294#L650 assume !(0 == ~t4_st~0); 708287#L654 assume !(0 == ~t5_st~0); 708289#L658 assume !(0 == ~t6_st~0); 708293#L662 assume !(0 == ~t7_st~0); 708290#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 708282#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 703002#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 703003#L696 assume !(0 != eval_~tmp~0#1); 708756#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 708754#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 708752#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 708750#L838-5 assume !(0 == ~T1_E~0); 708748#L843-3 assume !(0 == ~T2_E~0); 708745#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 708743#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 708741#L858-3 assume !(0 == ~T5_E~0); 708739#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 708737#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 708735#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 708732#L878-3 assume !(0 == ~E_1~0); 708730#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 708728#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 708726#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 708724#L898-3 assume !(0 == ~E_5~0); 708722#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 708721#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 708718#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 708716#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 708714#L402-27 assume !(1 == ~m_pc~0); 708712#L402-29 is_master_triggered_~__retres1~0#1 := 0; 708701#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 708699#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 708698#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 708697#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 708696#L421-27 assume !(1 == ~t1_pc~0); 708695#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 708693#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 708692#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 708691#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 708689#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 708688#L440-27 assume !(1 == ~t2_pc~0); 708686#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 708684#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 708682#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 708680#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 708678#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 708676#L459-27 assume !(1 == ~t3_pc~0); 708674#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 708690#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 708658#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 708652#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 708646#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 708640#L478-27 assume !(1 == ~t4_pc~0); 708634#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 708629#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 708623#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 708619#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 708549#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 708526#L497-27 assume !(1 == ~t5_pc~0); 708521#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 708518#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 708515#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 708512#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 708509#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 708505#L516-27 assume !(1 == ~t6_pc~0); 708501#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 708497#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 708493#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 708489#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 708485#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 708481#L535-27 assume 1 == ~t7_pc~0; 708475#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 708471#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 708467#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 708463#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 708459#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 708454#L554-27 assume !(1 == ~t8_pc~0); 708449#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 708445#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 708441#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 708437#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 708433#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 708429#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 708425#L931-5 assume !(1 == ~T1_E~0); 708421#L936-3 assume !(1 == ~T2_E~0); 708417#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 708413#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 708409#L951-3 assume !(1 == ~T5_E~0); 708405#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 708400#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 708395#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 708390#L971-3 assume !(1 == ~E_1~0); 708385#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 708380#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 708375#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 708370#L991-3 assume !(1 == ~E_5~0); 708366#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 708362#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 708358#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 708354#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 708345#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 708335#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 708332#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 708328#L1291 assume !(0 == start_simulation_~tmp~3#1); 708325#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 708322#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 708312#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 708310#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 708308#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 708307#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 708305#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 708303#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 691721#L1272-2 [2023-11-28 20:21:03,054 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:03,054 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 4 times [2023-11-28 20:21:03,054 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:03,054 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780643458] [2023-11-28 20:21:03,054 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:03,054 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:03,067 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:03,067 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:03,074 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:03,102 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:03,103 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:03,103 INFO L85 PathProgramCache]: Analyzing trace with hash -305979883, now seen corresponding path program 1 times [2023-11-28 20:21:03,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:03,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1472866234] [2023-11-28 20:21:03,104 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:03,104 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:03,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:03,176 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:03,176 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:03,176 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1472866234] [2023-11-28 20:21:03,176 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1472866234] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:03,176 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:03,177 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:21:03,177 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1715926098] [2023-11-28 20:21:03,177 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:03,177 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:03,177 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:03,177 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 20:21:03,178 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 20:21:03,178 INFO L87 Difference]: Start difference. First operand 40804 states and 56101 transitions. cyclomatic complexity: 15329 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:03,593 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:03,593 INFO L93 Difference]: Finished difference Result 107859 states and 145376 transitions. [2023-11-28 20:21:03,593 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 107859 states and 145376 transitions. [2023-11-28 20:21:03,958 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 107008 [2023-11-28 20:21:04,391 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 107859 states to 107859 states and 145376 transitions. [2023-11-28 20:21:04,391 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 107859 [2023-11-28 20:21:04,426 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 107859 [2023-11-28 20:21:04,426 INFO L73 IsDeterministic]: Start isDeterministic. Operand 107859 states and 145376 transitions. [2023-11-28 20:21:04,462 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:04,462 INFO L218 hiAutomatonCegarLoop]: Abstraction has 107859 states and 145376 transitions. [2023-11-28 20:21:04,501 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 107859 states and 145376 transitions. [2023-11-28 20:21:04,829 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 107859 to 42199. [2023-11-28 20:21:04,854 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 42199 states, 42199 states have (on average 1.3624967416289486) internal successors, (57496), 42198 states have internal predecessors, (57496), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:04,917 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 42199 states to 42199 states and 57496 transitions. [2023-11-28 20:21:04,917 INFO L240 hiAutomatonCegarLoop]: Abstraction has 42199 states and 57496 transitions. [2023-11-28 20:21:04,918 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-28 20:21:04,918 INFO L428 stractBuchiCegarLoop]: Abstraction has 42199 states and 57496 transitions. [2023-11-28 20:21:04,918 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-28 20:21:04,918 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 42199 states and 57496 transitions. [2023-11-28 20:21:05,012 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 41792 [2023-11-28 20:21:05,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:05,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:05,013 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:05,013 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:05,013 INFO L748 eck$LassoCheckResult]: Stem: 839638#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 839639#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 840367#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 840368#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 840370#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 839757#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 839758#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 840360#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 840352#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 839840#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 839841#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 840102#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 840103#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 839927#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 839928#L838 assume !(0 == ~M_E~0); 840112#L838-2 assume !(0 == ~T1_E~0); 839439#L843-1 assume !(0 == ~T2_E~0); 839440#L848-1 assume !(0 == ~T3_E~0); 839557#L853-1 assume !(0 == ~T4_E~0); 839916#L858-1 assume !(0 == ~T5_E~0); 839396#L863-1 assume !(0 == ~T6_E~0); 839397#L868-1 assume !(0 == ~T7_E~0); 840429#L873-1 assume !(0 == ~T8_E~0); 840421#L878-1 assume !(0 == ~E_1~0); 840405#L883-1 assume !(0 == ~E_2~0); 840406#L888-1 assume !(0 == ~E_3~0); 840069#L893-1 assume !(0 == ~E_4~0); 840070#L898-1 assume !(0 == ~E_5~0); 840459#L903-1 assume !(0 == ~E_6~0); 840401#L908-1 assume !(0 == ~E_7~0); 840221#L913-1 assume !(0 == ~E_8~0); 839452#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 839453#L402 assume !(1 == ~m_pc~0); 839666#L402-2 is_master_triggered_~__retres1~0#1 := 0; 839585#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 839586#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 839847#L1035 assume !(0 != activate_threads_~tmp~1#1); 839848#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 839902#L421 assume !(1 == ~t1_pc~0); 840390#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 840431#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 839454#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 839455#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 839963#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 840444#L440 assume !(1 == ~t2_pc~0); 840514#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 839594#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 839595#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 839784#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 840244#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 839793#L459 assume !(1 == ~t3_pc~0); 839794#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 840387#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 840443#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 839578#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 839579#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 839589#L478 assume !(1 == ~t4_pc~0); 839590#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 840302#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 839529#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 839530#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 839494#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 839495#L497 assume !(1 == ~t5_pc~0); 839540#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 840025#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 840155#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 840445#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 840446#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 840503#L516 assume !(1 == ~t6_pc~0); 840504#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 840100#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 840101#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 840551#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 840550#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 840088#L535 assume !(1 == ~t7_pc~0); 840089#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 840170#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 840171#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 840546#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 840545#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 840544#L554 assume !(1 == ~t8_pc~0); 839416#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 839417#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 840234#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 840235#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 840543#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 840542#L931 assume !(1 == ~M_E~0); 840541#L931-2 assume !(1 == ~T1_E~0); 840540#L936-1 assume !(1 == ~T2_E~0); 840539#L941-1 assume !(1 == ~T3_E~0); 840538#L946-1 assume !(1 == ~T4_E~0); 840537#L951-1 assume !(1 == ~T5_E~0); 840536#L956-1 assume !(1 == ~T6_E~0); 840535#L961-1 assume !(1 == ~T7_E~0); 840534#L966-1 assume !(1 == ~T8_E~0); 840533#L971-1 assume !(1 == ~E_1~0); 840532#L976-1 assume !(1 == ~E_2~0); 840531#L981-1 assume !(1 == ~E_3~0); 840530#L986-1 assume !(1 == ~E_4~0); 840529#L991-1 assume !(1 == ~E_5~0); 839676#L996-1 assume !(1 == ~E_6~0); 840439#L1001-1 assume !(1 == ~E_7~0); 840124#L1006-1 assume !(1 == ~E_8~0); 840125#L1011-1 assume { :end_inline_reset_delta_events } true; 840388#L1272-2 [2023-11-28 20:21:05,014 INFO L750 eck$LassoCheckResult]: Loop: 840388#L1272-2 assume !false; 854239#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 854238#L813-1 assume !false; 854237#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 854235#L634 assume !(0 == ~m_st~0); 854236#L638 assume !(0 == ~t1_st~0); 854229#L642 assume !(0 == ~t2_st~0); 854230#L646 assume !(0 == ~t3_st~0); 854234#L650 assume !(0 == ~t4_st~0); 854227#L654 assume !(0 == ~t5_st~0); 854228#L658 assume !(0 == ~t6_st~0); 854233#L662 assume !(0 == ~t7_st~0); 854231#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 854232#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 854218#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 854219#L696 assume !(0 != eval_~tmp~0#1); 854704#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 854703#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 854702#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 854701#L838-5 assume !(0 == ~T1_E~0); 854700#L843-3 assume !(0 == ~T2_E~0); 854699#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 854698#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 854697#L858-3 assume !(0 == ~T5_E~0); 854696#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 854695#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 854694#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 854693#L878-3 assume !(0 == ~E_1~0); 854692#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 854691#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 854690#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 854689#L898-3 assume !(0 == ~E_5~0); 854688#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 854687#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 854686#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 854685#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 854684#L402-27 assume !(1 == ~m_pc~0); 854683#L402-29 is_master_triggered_~__retres1~0#1 := 0; 854681#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 854679#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 854677#L1035-27 assume !(0 != activate_threads_~tmp~1#1); 854670#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 854664#L421-27 assume !(1 == ~t1_pc~0); 854658#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 854649#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 854641#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 854633#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 854625#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 854620#L440-27 assume !(1 == ~t2_pc~0); 854615#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 854610#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 854605#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 854600#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 854594#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 854590#L459-27 assume !(1 == ~t3_pc~0); 854583#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 854576#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 854569#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 854562#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 854555#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 854540#L478-27 assume !(1 == ~t4_pc~0); 854533#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 854526#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 854519#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 854512#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 854504#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 854481#L497-27 assume !(1 == ~t5_pc~0); 854477#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 854475#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 854473#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 854471#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 854469#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 854467#L516-27 assume !(1 == ~t6_pc~0); 854465#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 854463#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 854461#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 854459#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 854457#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 854455#L535-27 assume !(1 == ~t7_pc~0); 854453#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 854441#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 854433#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 854425#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 854416#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 854407#L554-27 assume !(1 == ~t8_pc~0); 854399#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 854391#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 854382#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 854373#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 854364#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 854362#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 854360#L931-5 assume !(1 == ~T1_E~0); 854358#L936-3 assume !(1 == ~T2_E~0); 854356#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 854353#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 854349#L951-3 assume !(1 == ~T5_E~0); 854345#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 854341#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 854337#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 854333#L971-3 assume !(1 == ~E_1~0); 854329#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 854325#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 854321#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 854317#L991-3 assume !(1 == ~E_5~0); 854314#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 854311#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 854308#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 854305#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 854300#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 854291#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 854289#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 854286#L1291 assume !(0 == start_simulation_~tmp~3#1); 854284#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 854282#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 854270#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 854267#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 854262#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 854258#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 854253#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 854247#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 840388#L1272-2 [2023-11-28 20:21:05,014 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:05,014 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 5 times [2023-11-28 20:21:05,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:05,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2039248541] [2023-11-28 20:21:05,014 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:05,014 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:05,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:05,025 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:05,032 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:05,049 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:05,049 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:05,049 INFO L85 PathProgramCache]: Analyzing trace with hash 690970546, now seen corresponding path program 1 times [2023-11-28 20:21:05,049 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:05,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [818486029] [2023-11-28 20:21:05,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:05,050 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:05,058 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:05,079 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:05,079 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:05,079 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [818486029] [2023-11-28 20:21:05,079 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [818486029] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:05,079 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:05,079 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:21:05,080 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1608882792] [2023-11-28 20:21:05,080 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:05,080 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:05,080 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:05,080 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:21:05,081 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:21:05,081 INFO L87 Difference]: Start difference. First operand 42199 states and 57496 transitions. cyclomatic complexity: 15329 Second operand has 3 states, 3 states have (on average 40.0) internal successors, (120), 3 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:05,552 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:05,552 INFO L93 Difference]: Finished difference Result 80215 states and 108128 transitions. [2023-11-28 20:21:05,552 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 80215 states and 108128 transitions. [2023-11-28 20:21:05,793 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79552 [2023-11-28 20:21:05,941 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 80215 states to 80215 states and 108128 transitions. [2023-11-28 20:21:05,941 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 80215 [2023-11-28 20:21:05,976 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 80215 [2023-11-28 20:21:05,976 INFO L73 IsDeterministic]: Start isDeterministic. Operand 80215 states and 108128 transitions. [2023-11-28 20:21:06,005 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:06,005 INFO L218 hiAutomatonCegarLoop]: Abstraction has 80215 states and 108128 transitions. [2023-11-28 20:21:06,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 80215 states and 108128 transitions. [2023-11-28 20:21:06,708 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 80215 to 76247. [2023-11-28 20:21:06,753 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76247 states, 76247 states have (on average 1.350977743386625) internal successors, (103008), 76246 states have internal predecessors, (103008), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:06,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76247 states to 76247 states and 103008 transitions. [2023-11-28 20:21:06,906 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76247 states and 103008 transitions. [2023-11-28 20:21:06,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:21:06,907 INFO L428 stractBuchiCegarLoop]: Abstraction has 76247 states and 103008 transitions. [2023-11-28 20:21:06,907 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-28 20:21:06,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76247 states and 103008 transitions. [2023-11-28 20:21:07,129 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75584 [2023-11-28 20:21:07,129 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:07,129 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:07,131 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:07,131 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:07,132 INFO L748 eck$LassoCheckResult]: Stem: 962066#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 962067#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 962836#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 962837#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 962839#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 962191#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 962192#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 962828#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 962813#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 962269#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 962270#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 962539#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 962540#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 962355#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 962356#L838 assume !(0 == ~M_E~0); 962552#L838-2 assume !(0 == ~T1_E~0); 961860#L843-1 assume !(0 == ~T2_E~0); 961861#L848-1 assume !(0 == ~T3_E~0); 961979#L853-1 assume !(0 == ~T4_E~0); 962344#L858-1 assume !(0 == ~T5_E~0); 961816#L863-1 assume !(0 == ~T6_E~0); 961817#L868-1 assume !(0 == ~T7_E~0); 962906#L873-1 assume !(0 == ~T8_E~0); 962902#L878-1 assume !(0 == ~E_1~0); 962870#L883-1 assume !(0 == ~E_2~0); 962871#L888-1 assume !(0 == ~E_3~0); 962506#L893-1 assume !(0 == ~E_4~0); 962507#L898-1 assume !(0 == ~E_5~0); 962930#L903-1 assume !(0 == ~E_6~0); 962867#L908-1 assume !(0 == ~E_7~0); 962666#L913-1 assume !(0 == ~E_8~0); 961873#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 961874#L402 assume !(1 == ~m_pc~0); 962096#L402-2 is_master_triggered_~__retres1~0#1 := 0; 962007#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 962008#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 962275#L1035 assume !(0 != activate_threads_~tmp~1#1); 962276#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 962330#L421 assume !(1 == ~t1_pc~0); 962860#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 962911#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 961875#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 961876#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 962387#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 962922#L440 assume !(1 == ~t2_pc~0); 963012#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 962017#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 962018#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 962219#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 962683#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 962227#L459 assume !(1 == ~t3_pc~0); 962228#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 962855#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 962921#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 962000#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 962001#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 962011#L478 assume !(1 == ~t4_pc~0); 962012#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 962740#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 961950#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 961951#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 961914#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 961915#L497 assume !(1 == ~t5_pc~0); 961961#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 962459#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 962734#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 962735#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 962849#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 962850#L516 assume !(1 == ~t6_pc~0); 962760#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 962761#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 962201#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 962202#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 962618#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 962619#L535 assume !(1 == ~t7_pc~0); 962795#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 962794#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 962974#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 962657#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 962646#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 962647#L554 assume !(1 == ~t8_pc~0); 961836#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 961837#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 962674#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 962675#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 963037#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 963036#L931 assume !(1 == ~M_E~0); 962890#L931-2 assume !(1 == ~T1_E~0); 962891#L936-1 assume !(1 == ~T2_E~0); 963010#L941-1 assume !(1 == ~T3_E~0); 963011#L946-1 assume !(1 == ~T4_E~0); 962857#L951-1 assume !(1 == ~T5_E~0); 962076#L956-1 assume !(1 == ~T6_E~0); 962077#L961-1 assume !(1 == ~T7_E~0); 962508#L966-1 assume !(1 == ~T8_E~0); 962509#L971-1 assume !(1 == ~E_1~0); 962650#L976-1 assume !(1 == ~E_2~0); 963032#L981-1 assume !(1 == ~E_3~0); 963031#L986-1 assume !(1 == ~E_4~0); 963030#L991-1 assume !(1 == ~E_5~0); 962107#L996-1 assume !(1 == ~E_6~0); 962915#L1001-1 assume !(1 == ~E_7~0); 962565#L1006-1 assume !(1 == ~E_8~0); 962566#L1011-1 assume { :end_inline_reset_delta_events } true; 962858#L1272-2 [2023-11-28 20:21:07,132 INFO L750 eck$LassoCheckResult]: Loop: 962858#L1272-2 assume !false; 978892#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 978890#L813-1 assume !false; 978888#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 978885#L634 assume !(0 == ~m_st~0); 978886#L638 assume !(0 == ~t1_st~0); 984672#L642 assume !(0 == ~t2_st~0); 984670#L646 assume !(0 == ~t3_st~0); 984668#L650 assume !(0 == ~t4_st~0); 984666#L654 assume !(0 == ~t5_st~0); 984664#L658 assume !(0 == ~t6_st~0); 984662#L662 assume !(0 == ~t7_st~0); 984659#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 984657#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 984655#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 984653#L696 assume !(0 != eval_~tmp~0#1); 984651#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 984648#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 984646#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 984644#L838-5 assume !(0 == ~T1_E~0); 984642#L843-3 assume !(0 == ~T2_E~0); 984641#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 984640#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 984639#L858-3 assume !(0 == ~T5_E~0); 984638#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 984637#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 984635#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 984634#L878-3 assume !(0 == ~E_1~0); 984633#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 984632#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 984630#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 984629#L898-3 assume !(0 == ~E_5~0); 984628#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 984627#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 984625#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 984622#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 984620#L402-27 assume 1 == ~m_pc~0; 984616#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 984614#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 984612#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 984608#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 984606#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 984604#L421-27 assume !(1 == ~t1_pc~0); 984603#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 984602#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 984600#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 984599#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 984598#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 984597#L440-27 assume !(1 == ~t2_pc~0); 984593#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 984591#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 984589#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 984587#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 984582#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 984580#L459-27 assume 1 == ~t3_pc~0; 984578#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 984579#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 984631#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 984569#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 984567#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 984565#L478-27 assume !(1 == ~t4_pc~0); 984563#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 984561#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 984559#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 984557#L1067-27 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 984555#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 984553#L497-27 assume 1 == ~t5_pc~0; 984552#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 979183#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 979181#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 979179#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 979177#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 979175#L516-27 assume !(1 == ~t6_pc~0); 979173#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 979171#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 979168#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 979166#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 979164#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 979162#L535-27 assume !(1 == ~t7_pc~0); 979160#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 979157#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 979154#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 979152#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 979150#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 979148#L554-27 assume !(1 == ~t8_pc~0); 979146#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 979145#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 979141#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 979139#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 979137#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 979136#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 979133#L931-5 assume !(1 == ~T1_E~0); 979132#L936-3 assume !(1 == ~T2_E~0); 979130#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 979129#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 979128#L951-3 assume !(1 == ~T5_E~0); 979125#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 979121#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 979117#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 979113#L971-3 assume !(1 == ~E_1~0); 979109#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 979105#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 979101#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 979099#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 979096#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 979093#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 979091#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 979089#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 979086#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 979083#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 979080#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 979077#L1291 assume !(0 == start_simulation_~tmp~3#1); 979073#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 979069#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 979067#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 979064#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 979061#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 979057#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 979053#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 979049#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 962858#L1272-2 [2023-11-28 20:21:07,132 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:07,133 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 6 times [2023-11-28 20:21:07,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:07,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [598736979] [2023-11-28 20:21:07,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:07,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:07,147 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:07,147 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:07,155 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:07,177 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:07,177 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:07,178 INFO L85 PathProgramCache]: Analyzing trace with hash -22339241, now seen corresponding path program 1 times [2023-11-28 20:21:07,178 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:07,178 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1945585067] [2023-11-28 20:21:07,178 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:07,178 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:07,192 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:07,247 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:07,247 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:07,247 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1945585067] [2023-11-28 20:21:07,248 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1945585067] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:07,248 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:07,248 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:21:07,248 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1547451375] [2023-11-28 20:21:07,248 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:07,248 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:07,248 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:07,249 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 20:21:07,249 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 20:21:07,249 INFO L87 Difference]: Start difference. First operand 76247 states and 103008 transitions. cyclomatic complexity: 26793 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:08,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:08,056 INFO L93 Difference]: Finished difference Result 127687 states and 171359 transitions. [2023-11-28 20:21:08,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127687 states and 171359 transitions. [2023-11-28 20:21:08,435 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 126832 [2023-11-28 20:21:08,634 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127687 states to 127687 states and 171359 transitions. [2023-11-28 20:21:08,634 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127687 [2023-11-28 20:21:08,673 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127687 [2023-11-28 20:21:08,673 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127687 states and 171359 transitions. [2023-11-28 20:21:08,707 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:08,707 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127687 states and 171359 transitions. [2023-11-28 20:21:08,753 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127687 states and 171359 transitions. [2023-11-28 20:21:09,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127687 to 77591. [2023-11-28 20:21:09,608 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77591 states, 77591 states have (on average 1.3395239138559885) internal successors, (103935), 77590 states have internal predecessors, (103935), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:09,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77591 states to 77591 states and 103935 transitions. [2023-11-28 20:21:09,728 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77591 states and 103935 transitions. [2023-11-28 20:21:09,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-28 20:21:09,729 INFO L428 stractBuchiCegarLoop]: Abstraction has 77591 states and 103935 transitions. [2023-11-28 20:21:09,729 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-28 20:21:09,729 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77591 states and 103935 transitions. [2023-11-28 20:21:09,910 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 76928 [2023-11-28 20:21:09,910 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:09,911 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:09,912 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:09,912 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:09,912 INFO L748 eck$LassoCheckResult]: Stem: 1166009#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1166010#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1166739#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1166740#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1166742#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1166128#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1166129#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1166735#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1166724#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1166207#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1166208#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1166469#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1166470#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1166296#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1166297#L838 assume !(0 == ~M_E~0); 1166481#L838-2 assume !(0 == ~T1_E~0); 1165805#L843-1 assume !(0 == ~T2_E~0); 1165806#L848-1 assume !(0 == ~T3_E~0); 1165924#L853-1 assume !(0 == ~T4_E~0); 1166285#L858-1 assume !(0 == ~T5_E~0); 1165762#L863-1 assume !(0 == ~T6_E~0); 1165763#L868-1 assume !(0 == ~T7_E~0); 1166801#L873-1 assume !(0 == ~T8_E~0); 1166798#L878-1 assume !(0 == ~E_1~0); 1166772#L883-1 assume !(0 == ~E_2~0); 1166773#L888-1 assume !(0 == ~E_3~0); 1166436#L893-1 assume !(0 == ~E_4~0); 1166437#L898-1 assume !(0 == ~E_5~0); 1166825#L903-1 assume !(0 == ~E_6~0); 1166770#L908-1 assume !(0 == ~E_7~0); 1166585#L913-1 assume !(0 == ~E_8~0); 1165818#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1165819#L402 assume !(1 == ~m_pc~0); 1166037#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1165952#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1165953#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1166215#L1035 assume !(0 != activate_threads_~tmp~1#1); 1166216#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1166271#L421 assume !(1 == ~t1_pc~0); 1166763#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1166806#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1165820#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1165821#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1166329#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1166815#L440 assume !(1 == ~t2_pc~0); 1166889#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1165962#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1165963#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1166157#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1166602#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1166166#L459 assume !(1 == ~t3_pc~0); 1166167#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1166758#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1166814#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1165945#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1165946#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1165956#L478 assume !(1 == ~t4_pc~0); 1165957#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1166658#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1165895#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1165896#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1165859#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1165860#L497 assume !(1 == ~t5_pc~0); 1165906#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1166393#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1166652#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1166653#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1166752#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1166753#L516 assume !(1 == ~t6_pc~0); 1166674#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1166675#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1166138#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1166139#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1166540#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1166541#L535 assume !(1 == ~t7_pc~0); 1166707#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1166706#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1166865#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1166576#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1166567#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1166568#L554 assume !(1 == ~t8_pc~0); 1165782#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1165783#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1166595#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1166596#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1166910#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1166909#L931 assume !(1 == ~M_E~0); 1166785#L931-2 assume !(1 == ~T1_E~0); 1166786#L936-1 assume !(1 == ~T2_E~0); 1166887#L941-1 assume !(1 == ~T3_E~0); 1166888#L946-1 assume !(1 == ~T4_E~0); 1166760#L951-1 assume !(1 == ~T5_E~0); 1166018#L956-1 assume !(1 == ~T6_E~0); 1166019#L961-1 assume !(1 == ~T7_E~0); 1166438#L966-1 assume !(1 == ~T8_E~0); 1166439#L971-1 assume !(1 == ~E_1~0); 1166570#L976-1 assume !(1 == ~E_2~0); 1166905#L981-1 assume !(1 == ~E_3~0); 1166904#L986-1 assume !(1 == ~E_4~0); 1166903#L991-1 assume !(1 == ~E_5~0); 1166048#L996-1 assume !(1 == ~E_6~0); 1166809#L1001-1 assume !(1 == ~E_7~0); 1166493#L1006-1 assume !(1 == ~E_8~0); 1166494#L1011-1 assume { :end_inline_reset_delta_events } true; 1166761#L1272-2 [2023-11-28 20:21:09,912 INFO L750 eck$LassoCheckResult]: Loop: 1166761#L1272-2 assume !false; 1174285#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1170002#L813-1 assume !false; 1174280#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1174281#L634 assume !(0 == ~m_st~0); 1174278#L638 assume !(0 == ~t1_st~0); 1174274#L642 assume !(0 == ~t2_st~0); 1174275#L646 assume !(0 == ~t3_st~0); 1174277#L650 assume !(0 == ~t4_st~0); 1174270#L654 assume !(0 == ~t5_st~0); 1174271#L658 assume !(0 == ~t6_st~0); 1174276#L662 assume !(0 == ~t7_st~0); 1174272#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1174273#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1174546#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1174544#L696 assume !(0 != eval_~tmp~0#1); 1174542#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1174540#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1174538#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1174536#L838-5 assume !(0 == ~T1_E~0); 1174534#L843-3 assume !(0 == ~T2_E~0); 1174532#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1174530#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1174528#L858-3 assume !(0 == ~T5_E~0); 1174526#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1174524#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1174522#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1174520#L878-3 assume !(0 == ~E_1~0); 1174518#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1174516#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1174514#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1174512#L898-3 assume !(0 == ~E_5~0); 1174510#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1174508#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1174506#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1174504#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1174502#L402-27 assume 1 == ~m_pc~0; 1174499#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1174496#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1174494#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1174491#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1174488#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1174486#L421-27 assume !(1 == ~t1_pc~0); 1174484#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1174482#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1174480#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1174478#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1174476#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1174474#L440-27 assume !(1 == ~t2_pc~0); 1174472#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1174470#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1174468#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1174466#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1174464#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1174462#L459-27 assume !(1 == ~t3_pc~0); 1174456#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1174454#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1174452#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1174450#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1174446#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1174444#L478-27 assume !(1 == ~t4_pc~0); 1174442#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1174440#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1174438#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1174436#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1174434#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1174430#L497-27 assume !(1 == ~t5_pc~0); 1174432#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1174637#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1174635#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1174632#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1174630#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1174628#L516-27 assume !(1 == ~t6_pc~0); 1174626#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1174624#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1174622#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1174620#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1174618#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1174616#L535-27 assume !(1 == ~t7_pc~0); 1174613#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1174611#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1174609#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1174607#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1174605#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1174603#L554-27 assume !(1 == ~t8_pc~0); 1174601#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1174599#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1174597#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1174595#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1174593#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1174591#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1174588#L931-5 assume !(1 == ~T1_E~0); 1174586#L936-3 assume !(1 == ~T2_E~0); 1174584#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1174582#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1174580#L951-3 assume !(1 == ~T5_E~0); 1174578#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1174576#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1174574#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1174572#L971-3 assume !(1 == ~E_1~0); 1174570#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1174568#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1174566#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1174354#L991-3 assume !(1 == ~E_5~0); 1174352#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1174350#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1174348#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1174346#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1174343#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1174341#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1174339#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1174336#L1291 assume !(0 == start_simulation_~tmp~3#1); 1174333#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1174326#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1174327#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1174312#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1174313#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1174306#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1174307#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1174301#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1166761#L1272-2 [2023-11-28 20:21:09,913 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:09,913 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 7 times [2023-11-28 20:21:09,913 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:09,913 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [561398563] [2023-11-28 20:21:09,913 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:09,913 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:09,923 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:09,924 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:09,929 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:09,948 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:09,948 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:09,949 INFO L85 PathProgramCache]: Analyzing trace with hash -1965913453, now seen corresponding path program 1 times [2023-11-28 20:21:09,949 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:09,949 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1882931207] [2023-11-28 20:21:09,949 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:09,949 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:09,959 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:10,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:10,003 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:10,004 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1882931207] [2023-11-28 20:21:10,004 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1882931207] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:10,004 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:10,004 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:21:10,004 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1373962741] [2023-11-28 20:21:10,004 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:10,004 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:10,004 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:10,005 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 20:21:10,005 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 20:21:10,005 INFO L87 Difference]: Start difference. First operand 77591 states and 103935 transitions. cyclomatic complexity: 26376 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:10,779 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:10,779 INFO L93 Difference]: Finished difference Result 147247 states and 195118 transitions. [2023-11-28 20:21:10,779 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 147247 states and 195118 transitions. [2023-11-28 20:21:11,236 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 146048 [2023-11-28 20:21:11,507 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 147247 states to 147247 states and 195118 transitions. [2023-11-28 20:21:11,507 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 147247 [2023-11-28 20:21:11,571 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 147247 [2023-11-28 20:21:11,571 INFO L73 IsDeterministic]: Start isDeterministic. Operand 147247 states and 195118 transitions. [2023-11-28 20:21:11,622 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:11,623 INFO L218 hiAutomatonCegarLoop]: Abstraction has 147247 states and 195118 transitions. [2023-11-28 20:21:11,693 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 147247 states and 195118 transitions. [2023-11-28 20:21:12,763 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 147247 to 78839. [2023-11-28 20:21:12,811 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 78839 states, 78839 states have (on average 1.3284541914534684) internal successors, (104734), 78838 states have internal predecessors, (104734), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:12,967 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 78839 states to 78839 states and 104734 transitions. [2023-11-28 20:21:12,967 INFO L240 hiAutomatonCegarLoop]: Abstraction has 78839 states and 104734 transitions. [2023-11-28 20:21:12,968 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-28 20:21:12,968 INFO L428 stractBuchiCegarLoop]: Abstraction has 78839 states and 104734 transitions. [2023-11-28 20:21:12,968 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-28 20:21:12,969 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 78839 states and 104734 transitions. [2023-11-28 20:21:13,196 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 78176 [2023-11-28 20:21:13,196 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:13,196 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:13,197 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:13,198 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:13,198 INFO L748 eck$LassoCheckResult]: Stem: 1390858#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1390859#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1391591#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1391592#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1391593#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1390978#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1390979#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1391582#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1391573#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1391054#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1391055#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1391314#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1391315#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1391141#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1391142#L838 assume !(0 == ~M_E~0); 1391324#L838-2 assume !(0 == ~T1_E~0); 1390655#L843-1 assume !(0 == ~T2_E~0); 1390656#L848-1 assume !(0 == ~T3_E~0); 1390774#L853-1 assume !(0 == ~T4_E~0); 1391130#L858-1 assume !(0 == ~T5_E~0); 1390612#L863-1 assume !(0 == ~T6_E~0); 1390613#L868-1 assume !(0 == ~T7_E~0); 1391650#L873-1 assume !(0 == ~T8_E~0); 1391647#L878-1 assume !(0 == ~E_1~0); 1391627#L883-1 assume !(0 == ~E_2~0); 1391628#L888-1 assume !(0 == ~E_3~0); 1391280#L893-1 assume !(0 == ~E_4~0); 1391281#L898-1 assume !(0 == ~E_5~0); 1391669#L903-1 assume !(0 == ~E_6~0); 1391622#L908-1 assume !(0 == ~E_7~0); 1391436#L913-1 assume !(0 == ~E_8~0); 1390668#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1390669#L402 assume !(1 == ~m_pc~0); 1390887#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1390801#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1390802#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1391060#L1035 assume !(0 != activate_threads_~tmp~1#1); 1391061#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1391114#L421 assume !(1 == ~t1_pc~0); 1391615#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1391653#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1390670#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1390671#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1391175#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1391659#L440 assume !(1 == ~t2_pc~0); 1391725#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1390810#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1390811#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1391005#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1391457#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1391014#L459 assume !(1 == ~t3_pc~0); 1391015#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1391609#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1390630#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1390631#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1390795#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1390805#L478 assume !(1 == ~t4_pc~0); 1390806#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1391509#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1390745#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1390746#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1390709#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1390710#L497 assume !(1 == ~t5_pc~0); 1390756#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1391238#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1391504#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1391505#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1391765#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1391764#L516 assume !(1 == ~t6_pc~0); 1391763#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1391762#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1391761#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1391760#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1391759#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1391758#L535 assume !(1 == ~t7_pc~0); 1391756#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1391755#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1391754#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1391753#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1391752#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1391751#L554 assume !(1 == ~t8_pc~0); 1391750#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1391749#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1391447#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1390944#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1390945#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1391427#L931 assume !(1 == ~M_E~0); 1391637#L931-2 assume !(1 == ~T1_E~0); 1391638#L936-1 assume !(1 == ~T2_E~0); 1391723#L941-1 assume !(1 == ~T3_E~0); 1391724#L946-1 assume !(1 == ~T4_E~0); 1391612#L951-1 assume !(1 == ~T5_E~0); 1390868#L956-1 assume !(1 == ~T6_E~0); 1390869#L961-1 assume !(1 == ~T7_E~0); 1391282#L966-1 assume !(1 == ~T8_E~0); 1391283#L971-1 assume !(1 == ~E_1~0); 1391419#L976-1 assume !(1 == ~E_2~0); 1391744#L981-1 assume !(1 == ~E_3~0); 1391120#L986-1 assume !(1 == ~E_4~0); 1391121#L991-1 assume !(1 == ~E_5~0); 1390897#L996-1 assume !(1 == ~E_6~0); 1391655#L1001-1 assume !(1 == ~E_7~0); 1391338#L1006-1 assume !(1 == ~E_8~0); 1391339#L1011-1 assume { :end_inline_reset_delta_events } true; 1391613#L1272-2 [2023-11-28 20:21:13,198 INFO L750 eck$LassoCheckResult]: Loop: 1391613#L1272-2 assume !false; 1396029#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1394901#L813-1 assume !false; 1396024#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1396021#L634 assume !(0 == ~m_st~0); 1396022#L638 assume !(0 == ~t1_st~0); 1397185#L642 assume !(0 == ~t2_st~0); 1397184#L646 assume !(0 == ~t3_st~0); 1397183#L650 assume !(0 == ~t4_st~0); 1397182#L654 assume !(0 == ~t5_st~0); 1397180#L658 assume !(0 == ~t6_st~0); 1397178#L662 assume !(0 == ~t7_st~0); 1397175#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1397174#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1397172#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1397170#L696 assume !(0 != eval_~tmp~0#1); 1397168#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1397166#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1397164#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1397162#L838-5 assume !(0 == ~T1_E~0); 1397160#L843-3 assume !(0 == ~T2_E~0); 1397158#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1397156#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1397154#L858-3 assume !(0 == ~T5_E~0); 1397152#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1397150#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1397149#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1397148#L878-3 assume !(0 == ~E_1~0); 1397147#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1397146#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1397145#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1397143#L898-3 assume !(0 == ~E_5~0); 1397142#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1397141#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1397140#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1397138#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1397137#L402-27 assume 1 == ~m_pc~0; 1396690#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1396655#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1396645#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1396637#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1396629#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1396615#L421-27 assume !(1 == ~t1_pc~0); 1396604#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1396596#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1396588#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1396558#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1396552#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1396547#L440-27 assume !(1 == ~t2_pc~0); 1396545#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1396543#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1396541#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1396539#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1396537#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1396535#L459-27 assume !(1 == ~t3_pc~0); 1396533#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1396553#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1396480#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1396471#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1396463#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1396454#L478-27 assume !(1 == ~t4_pc~0); 1396443#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1396399#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1396398#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1396397#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1396395#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1396394#L497-27 assume !(1 == ~t5_pc~0); 1396391#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1396390#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1396389#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1396388#L1075-27 assume !(0 != activate_threads_~tmp___4~0#1); 1396387#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1396386#L516-27 assume !(1 == ~t6_pc~0); 1396385#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1396384#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1396383#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1396382#L1083-27 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1396381#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1396380#L535-27 assume !(1 == ~t7_pc~0); 1396379#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1396377#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1396376#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1396375#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1396374#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1396373#L554-27 assume !(1 == ~t8_pc~0); 1396372#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1396371#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1396370#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1396369#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1396368#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1396367#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1396366#L931-5 assume !(1 == ~T1_E~0); 1396365#L936-3 assume !(1 == ~T2_E~0); 1396364#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1396363#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1396362#L951-3 assume !(1 == ~T5_E~0); 1396361#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1396360#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1396359#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1396358#L971-3 assume !(1 == ~E_1~0); 1396357#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1396356#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1396355#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1396353#L991-3 assume !(1 == ~E_5~0); 1396352#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1396351#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1396138#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1396136#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1396133#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1396131#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1396130#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1396128#L1291 assume !(0 == start_simulation_~tmp~3#1); 1396125#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1396123#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1396049#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1396047#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1396045#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1396043#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1396041#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1396039#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1391613#L1272-2 [2023-11-28 20:21:13,199 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:13,199 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 8 times [2023-11-28 20:21:13,199 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:13,199 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [417725189] [2023-11-28 20:21:13,199 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:13,199 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:13,210 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:13,210 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:13,218 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:13,239 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:13,240 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:13,240 INFO L85 PathProgramCache]: Analyzing trace with hash 1847973585, now seen corresponding path program 1 times [2023-11-28 20:21:13,240 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:13,241 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331472965] [2023-11-28 20:21:13,241 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:13,241 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:13,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:13,309 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:13,310 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:13,310 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1331472965] [2023-11-28 20:21:13,310 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1331472965] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:13,310 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:13,310 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:21:13,310 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [686496187] [2023-11-28 20:21:13,310 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:13,311 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:13,311 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:13,311 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 20:21:13,311 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 20:21:13,312 INFO L87 Difference]: Start difference. First operand 78839 states and 104734 transitions. cyclomatic complexity: 25927 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:14,070 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:14,071 INFO L93 Difference]: Finished difference Result 126503 states and 166980 transitions. [2023-11-28 20:21:14,071 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126503 states and 166980 transitions. [2023-11-28 20:21:14,486 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 125648 [2023-11-28 20:21:14,741 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126503 states to 126503 states and 166980 transitions. [2023-11-28 20:21:14,741 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126503 [2023-11-28 20:21:14,799 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126503 [2023-11-28 20:21:14,800 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126503 states and 166980 transitions. [2023-11-28 20:21:14,845 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:14,845 INFO L218 hiAutomatonCegarLoop]: Abstraction has 126503 states and 166980 transitions. [2023-11-28 20:21:14,904 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126503 states and 166980 transitions. [2023-11-28 20:21:15,758 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126503 to 80327. [2023-11-28 20:21:15,803 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 80327 states, 80327 states have (on average 1.3169668978052211) internal successors, (105788), 80326 states have internal predecessors, (105788), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:15,927 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 80327 states to 80327 states and 105788 transitions. [2023-11-28 20:21:15,928 INFO L240 hiAutomatonCegarLoop]: Abstraction has 80327 states and 105788 transitions. [2023-11-28 20:21:15,928 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-28 20:21:15,929 INFO L428 stractBuchiCegarLoop]: Abstraction has 80327 states and 105788 transitions. [2023-11-28 20:21:15,929 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-28 20:21:15,929 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 80327 states and 105788 transitions. [2023-11-28 20:21:16,114 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 79664 [2023-11-28 20:21:16,114 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:16,114 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:16,115 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:16,115 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:16,115 INFO L748 eck$LassoCheckResult]: Stem: 1596210#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1596211#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1596966#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1596967#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1596969#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1596330#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1596331#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1596958#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1596948#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1596410#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1596411#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1596678#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1596679#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1596500#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1596501#L838 assume !(0 == ~M_E~0); 1596688#L838-2 assume !(0 == ~T1_E~0); 1596010#L843-1 assume !(0 == ~T2_E~0); 1596011#L848-1 assume !(0 == ~T3_E~0); 1596128#L853-1 assume !(0 == ~T4_E~0); 1596486#L858-1 assume !(0 == ~T5_E~0); 1595964#L863-1 assume !(0 == ~T6_E~0); 1595965#L868-1 assume !(0 == ~T7_E~0); 1597024#L873-1 assume !(0 == ~T8_E~0); 1597022#L878-1 assume !(0 == ~E_1~0); 1596995#L883-1 assume !(0 == ~E_2~0); 1596996#L888-1 assume !(0 == ~E_3~0); 1596643#L893-1 assume !(0 == ~E_4~0); 1596644#L898-1 assume !(0 == ~E_5~0); 1597048#L903-1 assume !(0 == ~E_6~0); 1596993#L908-1 assume !(0 == ~E_7~0); 1596796#L913-1 assume !(0 == ~E_8~0); 1596023#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1596024#L402 assume !(1 == ~m_pc~0); 1596237#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1596154#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1596155#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1596417#L1035 assume !(0 != activate_threads_~tmp~1#1); 1596418#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1596473#L421 assume !(1 == ~t1_pc~0); 1596988#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1597026#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1596025#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1596026#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1596536#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1597040#L440 assume !(1 == ~t2_pc~0); 1597101#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1596163#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1596164#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1596359#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1596817#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1596365#L459 assume !(1 == ~t3_pc~0); 1596366#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1596984#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1595984#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1595985#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1596148#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1596158#L478 assume !(1 == ~t4_pc~0); 1596159#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1596881#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1596099#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1596100#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1596062#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1596063#L497 assume !(1 == ~t5_pc~0); 1596110#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1596603#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1596874#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1596875#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1596978#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1596979#L516 assume !(1 == ~t6_pc~0); 1596898#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1596899#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1596340#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1596341#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1596748#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1596749#L535 assume !(1 == ~t7_pc~0); 1596931#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1596930#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1597077#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1596788#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1596777#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1596778#L554 assume !(1 == ~t8_pc~0); 1595986#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1595987#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1597126#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1596291#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1596292#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1595974#L931 assume !(1 == ~M_E~0); 1595975#L931-2 assume !(1 == ~T1_E~0); 1597055#L936-1 assume !(1 == ~T2_E~0); 1597056#L941-1 assume !(1 == ~T3_E~0); 1596474#L946-1 assume !(1 == ~T4_E~0); 1596475#L951-1 assume !(1 == ~T5_E~0); 1597123#L956-1 assume !(1 == ~T6_E~0); 1597122#L961-1 assume !(1 == ~T7_E~0); 1596645#L966-1 assume !(1 == ~T8_E~0); 1596646#L971-1 assume !(1 == ~E_1~0); 1596780#L976-1 assume !(1 == ~E_2~0); 1596734#L981-1 assume !(1 == ~E_3~0); 1596478#L986-1 assume !(1 == ~E_4~0); 1596479#L991-1 assume !(1 == ~E_5~0); 1596249#L996-1 assume !(1 == ~E_6~0); 1597033#L1001-1 assume !(1 == ~E_7~0); 1596702#L1006-1 assume !(1 == ~E_8~0); 1596703#L1011-1 assume { :end_inline_reset_delta_events } true; 1596986#L1272-2 [2023-11-28 20:21:16,116 INFO L750 eck$LassoCheckResult]: Loop: 1596986#L1272-2 assume !false; 1602973#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1602918#L813-1 assume !false; 1602970#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1602967#L634 assume !(0 == ~m_st~0); 1602968#L638 assume !(0 == ~t1_st~0); 1620247#L642 assume !(0 == ~t2_st~0); 1620245#L646 assume !(0 == ~t3_st~0); 1620241#L650 assume !(0 == ~t4_st~0); 1620239#L654 assume !(0 == ~t5_st~0); 1620237#L658 assume !(0 == ~t6_st~0); 1620235#L662 assume !(0 == ~t7_st~0); 1620231#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1620229#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1620226#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1620224#L696 assume !(0 != eval_~tmp~0#1); 1620222#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1620220#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1620217#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1620215#L838-5 assume !(0 == ~T1_E~0); 1620213#L843-3 assume !(0 == ~T2_E~0); 1620211#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1620209#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1620207#L858-3 assume !(0 == ~T5_E~0); 1620205#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1620203#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1620201#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1620198#L878-3 assume !(0 == ~E_1~0); 1620196#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1620194#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1620192#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1620190#L898-3 assume !(0 == ~E_5~0); 1620188#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1620186#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1620184#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1620182#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1620180#L402-27 assume 1 == ~m_pc~0; 1620177#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1620161#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1620133#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1620083#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1620077#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1620070#L421-27 assume !(1 == ~t1_pc~0); 1620061#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1620053#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1620028#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1620004#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1619999#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1619992#L440-27 assume !(1 == ~t2_pc~0); 1613457#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1613455#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1613453#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1613451#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1603330#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1603327#L459-27 assume !(1 == ~t3_pc~0); 1603323#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 1603321#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1603319#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1603317#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 1603314#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1603312#L478-27 assume !(1 == ~t4_pc~0); 1603309#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1603307#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1603305#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1603303#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1603301#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1603297#L497-27 assume !(1 == ~t5_pc~0); 1603294#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1603292#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1603290#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1603287#L1075-27 assume !(0 != activate_threads_~tmp___4~0#1); 1603285#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1603283#L516-27 assume !(1 == ~t6_pc~0); 1603280#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1603278#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1603276#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1603273#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1603271#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1603268#L535-27 assume 1 == ~t7_pc~0; 1603265#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1603263#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1603261#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1603258#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1603256#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1603254#L554-27 assume !(1 == ~t8_pc~0); 1603252#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1603250#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1603248#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1603246#L1099-27 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1603244#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1603242#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1603239#L931-5 assume !(1 == ~T1_E~0); 1603237#L936-3 assume !(1 == ~T2_E~0); 1603235#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1603233#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1603231#L951-3 assume !(1 == ~T5_E~0); 1603229#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1603227#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1603225#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1603223#L971-3 assume !(1 == ~E_1~0); 1603221#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1603219#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1603217#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1603015#L991-3 assume !(1 == ~E_5~0); 1603012#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1603010#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1603008#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1603006#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1603003#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1603001#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1602998#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1602995#L1291 assume !(0 == start_simulation_~tmp~3#1); 1602992#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1602989#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1602987#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1602985#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1602983#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1602981#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1602979#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1602977#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1596986#L1272-2 [2023-11-28 20:21:16,116 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:16,116 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 9 times [2023-11-28 20:21:16,116 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:16,116 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [465651208] [2023-11-28 20:21:16,116 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:16,116 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:16,129 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:16,129 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:16,137 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:16,165 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:16,166 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:16,166 INFO L85 PathProgramCache]: Analyzing trace with hash 1954100144, now seen corresponding path program 1 times [2023-11-28 20:21:16,166 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:16,166 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [748638821] [2023-11-28 20:21:16,166 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:16,166 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:16,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:16,243 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:16,243 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:16,243 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [748638821] [2023-11-28 20:21:16,243 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [748638821] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:16,243 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:16,243 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:21:16,243 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [759476537] [2023-11-28 20:21:16,243 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:16,244 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:16,244 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:16,244 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 20:21:16,244 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 20:21:16,244 INFO L87 Difference]: Start difference. First operand 80327 states and 105788 transitions. cyclomatic complexity: 25493 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:16,996 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:16,996 INFO L93 Difference]: Finished difference Result 119879 states and 156682 transitions. [2023-11-28 20:21:16,996 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 119879 states and 156682 transitions. [2023-11-28 20:21:17,378 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 118960 [2023-11-28 20:21:17,605 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 119879 states to 119879 states and 156682 transitions. [2023-11-28 20:21:17,606 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 119879 [2023-11-28 20:21:17,659 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 119879 [2023-11-28 20:21:17,659 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119879 states and 156682 transitions. [2023-11-28 20:21:17,701 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:17,701 INFO L218 hiAutomatonCegarLoop]: Abstraction has 119879 states and 156682 transitions. [2023-11-28 20:21:17,756 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119879 states and 156682 transitions. [2023-11-28 20:21:18,602 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119879 to 81719. [2023-11-28 20:21:18,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 81719 states, 81719 states have (on average 1.3058652210624213) internal successors, (106714), 81718 states have internal predecessors, (106714), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:18,810 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 81719 states to 81719 states and 106714 transitions. [2023-11-28 20:21:18,811 INFO L240 hiAutomatonCegarLoop]: Abstraction has 81719 states and 106714 transitions. [2023-11-28 20:21:18,811 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-28 20:21:18,812 INFO L428 stractBuchiCegarLoop]: Abstraction has 81719 states and 106714 transitions. [2023-11-28 20:21:18,812 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-28 20:21:18,812 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 81719 states and 106714 transitions. [2023-11-28 20:21:19,044 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 81056 [2023-11-28 20:21:19,044 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:19,045 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:19,046 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:19,046 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:19,047 INFO L748 eck$LassoCheckResult]: Stem: 1796434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 1796435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 1797202#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1797203#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1797205#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 1796555#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1796556#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1797198#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1797182#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1796637#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1796638#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1796912#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1796913#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1796727#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1796728#L838 assume !(0 == ~M_E~0); 1796923#L838-2 assume !(0 == ~T1_E~0); 1796228#L843-1 assume !(0 == ~T2_E~0); 1796229#L848-1 assume !(0 == ~T3_E~0); 1796347#L853-1 assume !(0 == ~T4_E~0); 1796713#L858-1 assume !(0 == ~T5_E~0); 1796182#L863-1 assume !(0 == ~T6_E~0); 1796183#L868-1 assume !(0 == ~T7_E~0); 1797270#L873-1 assume !(0 == ~T8_E~0); 1797266#L878-1 assume !(0 == ~E_1~0); 1797239#L883-1 assume !(0 == ~E_2~0); 1797240#L888-1 assume !(0 == ~E_3~0); 1796875#L893-1 assume !(0 == ~E_4~0); 1796876#L898-1 assume !(0 == ~E_5~0); 1797292#L903-1 assume !(0 == ~E_6~0); 1797237#L908-1 assume !(0 == ~E_7~0); 1797033#L913-1 assume !(0 == ~E_8~0); 1796240#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1796241#L402 assume !(1 == ~m_pc~0); 1796459#L402-2 is_master_triggered_~__retres1~0#1 := 0; 1796373#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1796374#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1796645#L1035 assume !(0 != activate_threads_~tmp~1#1); 1796646#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1796700#L421 assume !(1 == ~t1_pc~0); 1797228#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1797271#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1796243#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1796244#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 1796763#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1797283#L440 assume !(1 == ~t2_pc~0); 1797350#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1796383#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1796384#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1796584#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 1797056#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1796591#L459 assume !(1 == ~t3_pc~0); 1796592#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1797221#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1796202#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1796203#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 1796367#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1796377#L478 assume !(1 == ~t4_pc~0); 1796378#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1797116#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1796319#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1796320#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 1796280#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1796281#L497 assume !(1 == ~t5_pc~0); 1796330#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1796832#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1797110#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1797111#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 1797216#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1797217#L516 assume !(1 == ~t6_pc~0); 1797132#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1797133#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1796565#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1796566#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 1796987#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1796988#L535 assume !(1 == ~t7_pc~0); 1797165#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1797164#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1797328#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1797025#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 1797014#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1797015#L554 assume !(1 == ~t8_pc~0); 1796204#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1796205#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1797376#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1796516#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 1796517#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1796192#L931 assume !(1 == ~M_E~0); 1796193#L931-2 assume !(1 == ~T1_E~0); 1797300#L936-1 assume !(1 == ~T2_E~0); 1797301#L941-1 assume !(1 == ~T3_E~0); 1796701#L946-1 assume !(1 == ~T4_E~0); 1796702#L951-1 assume !(1 == ~T5_E~0); 1797373#L956-1 assume !(1 == ~T6_E~0); 1797372#L961-1 assume !(1 == ~T7_E~0); 1796877#L966-1 assume !(1 == ~T8_E~0); 1796878#L971-1 assume !(1 == ~E_1~0); 1797017#L976-1 assume !(1 == ~E_2~0); 1796973#L981-1 assume !(1 == ~E_3~0); 1796705#L986-1 assume !(1 == ~E_4~0); 1796706#L991-1 assume !(1 == ~E_5~0); 1796474#L996-1 assume !(1 == ~E_6~0); 1797275#L1001-1 assume !(1 == ~E_7~0); 1796937#L1006-1 assume !(1 == ~E_8~0); 1796938#L1011-1 assume { :end_inline_reset_delta_events } true; 1797226#L1272-2 [2023-11-28 20:21:19,047 INFO L750 eck$LassoCheckResult]: Loop: 1797226#L1272-2 assume !false; 1808688#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1808686#L813-1 assume !false; 1808684#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1808681#L634 assume !(0 == ~m_st~0); 1808682#L638 assume !(0 == ~t1_st~0); 1809418#L642 assume !(0 == ~t2_st~0); 1809416#L646 assume !(0 == ~t3_st~0); 1809414#L650 assume !(0 == ~t4_st~0); 1809412#L654 assume !(0 == ~t5_st~0); 1809410#L658 assume !(0 == ~t6_st~0); 1809408#L662 assume !(0 == ~t7_st~0); 1809405#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 1809403#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1809400#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1809398#L696 assume !(0 != eval_~tmp~0#1); 1809396#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1809393#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1809391#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1809389#L838-5 assume !(0 == ~T1_E~0); 1809387#L843-3 assume !(0 == ~T2_E~0); 1809385#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 1809383#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1809381#L858-3 assume !(0 == ~T5_E~0); 1809379#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1809376#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1809374#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1809372#L878-3 assume !(0 == ~E_1~0); 1809370#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1809368#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1809366#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1809364#L898-3 assume !(0 == ~E_5~0); 1809362#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1809360#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1809358#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1809356#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1809354#L402-27 assume 1 == ~m_pc~0; 1809351#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1809348#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1809346#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 1809343#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1809341#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1809339#L421-27 assume !(1 == ~t1_pc~0); 1809337#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 1809335#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1809333#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1809331#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 1809329#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1809327#L440-27 assume !(1 == ~t2_pc~0); 1809326#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 1809325#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1809323#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1809322#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 1809321#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1809320#L459-27 assume 1 == ~t3_pc~0; 1809318#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 1809319#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1809324#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1809307#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1809305#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1809303#L478-27 assume !(1 == ~t4_pc~0); 1809300#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 1809298#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1809296#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1809295#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 1809294#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1809293#L497-27 assume !(1 == ~t5_pc~0); 1809291#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 1809290#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1809288#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1809286#L1075-27 assume !(0 != activate_threads_~tmp___4~0#1); 1809284#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1809282#L516-27 assume !(1 == ~t6_pc~0); 1809280#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 1809278#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1809276#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1809274#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 1809272#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1809270#L535-27 assume !(1 == ~t7_pc~0); 1809267#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 1809264#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1809262#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1809260#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1809258#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1809256#L554-27 assume !(1 == ~t8_pc~0); 1809254#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 1809252#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1809250#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1809248#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 1809246#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1809244#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1809242#L931-5 assume !(1 == ~T1_E~0); 1809240#L936-3 assume !(1 == ~T2_E~0); 1809238#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1809236#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1809234#L951-3 assume !(1 == ~T5_E~0); 1809232#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1809230#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1809228#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1809226#L971-3 assume !(1 == ~E_1~0); 1809224#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1809222#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1809220#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1809032#L991-3 assume !(1 == ~E_5~0); 1809030#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1809028#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1809025#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1809023#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1809020#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1809018#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1809017#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 1809015#L1291 assume !(0 == start_simulation_~tmp~3#1); 1809012#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 1809010#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 1809009#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 1809008#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 1809004#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1809002#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1809000#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 1808998#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 1797226#L1272-2 [2023-11-28 20:21:19,047 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:19,048 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 10 times [2023-11-28 20:21:19,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:19,048 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [760692667] [2023-11-28 20:21:19,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:19,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:19,060 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:19,061 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:19,066 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:19,088 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:19,088 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:19,089 INFO L85 PathProgramCache]: Analyzing trace with hash 572047664, now seen corresponding path program 1 times [2023-11-28 20:21:19,089 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:19,089 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1297213005] [2023-11-28 20:21:19,089 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:19,089 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:19,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:19,157 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:19,157 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:19,158 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1297213005] [2023-11-28 20:21:19,158 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1297213005] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:19,158 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:19,158 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-28 20:21:19,158 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1195355555] [2023-11-28 20:21:19,158 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:19,158 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:19,159 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:19,159 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-28 20:21:19,159 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-28 20:21:19,159 INFO L87 Difference]: Start difference. First operand 81719 states and 106714 transitions. cyclomatic complexity: 25027 Second operand has 5 states, 5 states have (on average 24.0) internal successors, (120), 5 states have internal predecessors, (120), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:19,768 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:19,769 INFO L93 Difference]: Finished difference Result 168921 states and 217490 transitions. [2023-11-28 20:21:19,769 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 168921 states and 217490 transitions. [2023-11-28 20:21:20,635 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 167680 [2023-11-28 20:21:20,919 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 168921 states to 168921 states and 217490 transitions. [2023-11-28 20:21:20,919 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 168921 [2023-11-28 20:21:20,982 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 168921 [2023-11-28 20:21:20,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 168921 states and 217490 transitions. [2023-11-28 20:21:21,032 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:21,032 INFO L218 hiAutomatonCegarLoop]: Abstraction has 168921 states and 217490 transitions. [2023-11-28 20:21:21,100 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 168921 states and 217490 transitions. [2023-11-28 20:21:22,004 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 168921 to 84509. [2023-11-28 20:21:22,047 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 84509 states, 84509 states have (on average 1.2957673147238755) internal successors, (109504), 84508 states have internal predecessors, (109504), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:22,173 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 84509 states to 84509 states and 109504 transitions. [2023-11-28 20:21:22,173 INFO L240 hiAutomatonCegarLoop]: Abstraction has 84509 states and 109504 transitions. [2023-11-28 20:21:22,174 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-28 20:21:22,174 INFO L428 stractBuchiCegarLoop]: Abstraction has 84509 states and 109504 transitions. [2023-11-28 20:21:22,174 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-28 20:21:22,174 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 84509 states and 109504 transitions. [2023-11-28 20:21:22,365 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 83840 [2023-11-28 20:21:22,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:22,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:22,366 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:22,366 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:22,367 INFO L748 eck$LassoCheckResult]: Stem: 2047084#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2047085#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2047858#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2047859#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2047861#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2047203#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2047204#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2047851#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2047835#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2047283#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2047284#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2047548#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2047549#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2047372#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2047373#L838 assume !(0 == ~M_E~0); 2047558#L838-2 assume !(0 == ~T1_E~0); 2046880#L843-1 assume !(0 == ~T2_E~0); 2046881#L848-1 assume !(0 == ~T3_E~0); 2046999#L853-1 assume !(0 == ~T4_E~0); 2047358#L858-1 assume !(0 == ~T5_E~0); 2046834#L863-1 assume !(0 == ~T6_E~0); 2046835#L868-1 assume !(0 == ~T7_E~0); 2047928#L873-1 assume !(0 == ~T8_E~0); 2047926#L878-1 assume !(0 == ~E_1~0); 2047897#L883-1 assume !(0 == ~E_2~0); 2047898#L888-1 assume !(0 == ~E_3~0); 2047513#L893-1 assume !(0 == ~E_4~0); 2047514#L898-1 assume !(0 == ~E_5~0); 2047948#L903-1 assume !(0 == ~E_6~0); 2047895#L908-1 assume !(0 == ~E_7~0); 2047671#L913-1 assume !(0 == ~E_8~0); 2046892#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2046893#L402 assume !(1 == ~m_pc~0); 2047107#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2047336#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2047745#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2047290#L1035 assume !(0 != activate_threads_~tmp~1#1); 2047291#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2047345#L421 assume !(1 == ~t1_pc~0); 2047886#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2047929#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2046895#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2046896#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2047403#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2047942#L440 assume !(1 == ~t2_pc~0); 2048021#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2047035#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2047036#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2047231#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2047690#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2047235#L459 assume !(1 == ~t3_pc~0); 2047236#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2047878#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2046854#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2046855#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 2047019#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2047029#L478 assume !(1 == ~t4_pc~0); 2047030#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2047756#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2046970#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2046971#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 2046932#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2046933#L497 assume !(1 == ~t5_pc~0); 2046981#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2047468#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2047748#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2047749#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2047872#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2047873#L516 assume !(1 == ~t6_pc~0); 2047771#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2047772#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2047213#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2047214#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2047623#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2047624#L535 assume !(1 == ~t7_pc~0); 2047810#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2047619#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2047620#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2047662#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2047650#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2047651#L554 assume !(1 == ~t8_pc~0); 2046856#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2046857#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2048052#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2047164#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2047165#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2046844#L931 assume !(1 == ~M_E~0); 2046845#L931-2 assume !(1 == ~T1_E~0); 2047961#L936-1 assume !(1 == ~T2_E~0); 2047962#L941-1 assume !(1 == ~T3_E~0); 2047346#L946-1 assume !(1 == ~T4_E~0); 2047347#L951-1 assume !(1 == ~T5_E~0); 2048049#L956-1 assume !(1 == ~T6_E~0); 2048009#L961-1 assume !(1 == ~T7_E~0); 2048010#L966-1 assume !(1 == ~T8_E~0); 2048048#L971-1 assume !(1 == ~E_1~0); 2047978#L976-1 assume !(1 == ~E_2~0); 2047609#L981-1 assume !(1 == ~E_3~0); 2047350#L986-1 assume !(1 == ~E_4~0); 2047351#L991-1 assume !(1 == ~E_5~0); 2047121#L996-1 assume !(1 == ~E_6~0); 2047935#L1001-1 assume !(1 == ~E_7~0); 2047571#L1006-1 assume !(1 == ~E_8~0); 2047572#L1011-1 assume { :end_inline_reset_delta_events } true; 2047884#L1272-2 [2023-11-28 20:21:22,367 INFO L750 eck$LassoCheckResult]: Loop: 2047884#L1272-2 assume !false; 2082293#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2082287#L813-1 assume !false; 2082282#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2082274#L634 assume !(0 == ~m_st~0); 2082275#L638 assume !(0 == ~t1_st~0); 2083497#L642 assume !(0 == ~t2_st~0); 2083496#L646 assume !(0 == ~t3_st~0); 2083495#L650 assume !(0 == ~t4_st~0); 2083494#L654 assume !(0 == ~t5_st~0); 2083493#L658 assume !(0 == ~t6_st~0); 2083492#L662 assume !(0 == ~t7_st~0); 2083490#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 2083489#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2083488#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2083487#L696 assume !(0 != eval_~tmp~0#1); 2083486#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2083485#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2083484#L838-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2083483#L838-5 assume !(0 == ~T1_E~0); 2083482#L843-3 assume !(0 == ~T2_E~0); 2083481#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2083480#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2083479#L858-3 assume !(0 == ~T5_E~0); 2083478#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2083477#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2083476#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2083475#L878-3 assume !(0 == ~E_1~0); 2083474#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2083473#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2083472#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2083471#L898-3 assume !(0 == ~E_5~0); 2083470#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2083469#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2083468#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2083467#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2083466#L402-27 assume 1 == ~m_pc~0; 2083464#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2083463#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2083462#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2083460#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2083459#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2083458#L421-27 assume !(1 == ~t1_pc~0); 2083457#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2083456#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2083455#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2083454#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 2083453#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2083452#L440-27 assume !(1 == ~t2_pc~0); 2083451#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 2083450#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2083449#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2083448#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 2083447#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2083446#L459-27 assume !(1 == ~t3_pc~0); 2083445#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2083443#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2083441#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2083439#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 2083437#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2083436#L478-27 assume !(1 == ~t4_pc~0); 2083435#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2083434#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2083433#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2083432#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 2083431#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2083430#L497-27 assume 1 == ~t5_pc~0; 2083428#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2083429#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2084297#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2084295#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2084294#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2084293#L516-27 assume !(1 == ~t6_pc~0); 2084292#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2084291#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2084290#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2084289#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 2084288#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2084287#L535-27 assume !(1 == ~t7_pc~0); 2084286#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 2084284#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2084282#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2084280#L1091-27 assume !(0 != activate_threads_~tmp___6~0#1); 2084131#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2084109#L554-27 assume !(1 == ~t8_pc~0); 2084030#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 2083970#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2083962#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2083819#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 2082436#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2082434#L931-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2082432#L931-5 assume !(1 == ~T1_E~0); 2082430#L936-3 assume !(1 == ~T2_E~0); 2082428#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2082426#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2082424#L951-3 assume !(1 == ~T5_E~0); 2082422#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2082420#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2082418#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2082416#L971-3 assume !(1 == ~E_1~0); 2082414#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2082412#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2082410#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2082348#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2082345#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2082343#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2082340#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2082338#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2082335#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2082333#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2082332#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2082329#L1291 assume !(0 == start_simulation_~tmp~3#1); 2082327#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2082322#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2082320#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2082318#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2082317#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2082314#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2082313#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2082311#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 2047884#L1272-2 [2023-11-28 20:21:22,367 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:22,368 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 11 times [2023-11-28 20:21:22,368 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:22,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756824376] [2023-11-28 20:21:22,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:22,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:22,380 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:22,380 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:22,387 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:22,415 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:22,415 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:22,416 INFO L85 PathProgramCache]: Analyzing trace with hash 1010612972, now seen corresponding path program 1 times [2023-11-28 20:21:22,416 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:22,416 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1210641348] [2023-11-28 20:21:22,416 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:22,416 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:22,427 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:22,427 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:22,435 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:22,456 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:22,457 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:22,457 INFO L85 PathProgramCache]: Analyzing trace with hash 445027050, now seen corresponding path program 1 times [2023-11-28 20:21:22,457 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:22,457 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [234375611] [2023-11-28 20:21:22,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:22,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:22,473 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:22,515 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:22,515 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:22,515 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [234375611] [2023-11-28 20:21:22,515 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [234375611] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:22,515 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:22,515 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:21:22,515 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1924244280] [2023-11-28 20:21:22,516 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:24,657 INFO L210 LassoAnalysis]: Preferences: [2023-11-28 20:21:24,657 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-28 20:21:24,657 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-28 20:21:24,657 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-28 20:21:24,657 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-28 20:21:24,658 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:24,658 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-28 20:21:24,658 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-28 20:21:24,658 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.08.cil.c_Iteration31_Loop [2023-11-28 20:21:24,658 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-28 20:21:24,658 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-28 20:21:24,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,688 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,690 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,693 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,695 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,697 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,711 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,714 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,715 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,737 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,745 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,764 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,766 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,768 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,770 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,772 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,776 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,779 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,783 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,785 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,787 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,794 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,796 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,798 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,802 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,805 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,808 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,811 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,814 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,822 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,824 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,826 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,828 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,832 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,834 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,836 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,838 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,840 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,848 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,854 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,856 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,861 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,863 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,865 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,867 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,868 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,870 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,872 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,876 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,878 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,881 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,884 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,886 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,890 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,891 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,896 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,898 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,900 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,906 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,908 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,914 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,921 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,925 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,930 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,932 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,935 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:24,937 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,457 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-28 20:21:25,458 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-28 20:21:25,460 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:25,460 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:25,464 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:25,466 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-28 20:21:25,469 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-28 20:21:25,469 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-28 20:21:25,486 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-28 20:21:25,486 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret15#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-28 20:21:25,489 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-28 20:21:25,491 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:25,491 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:25,491 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:25,500 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-28 20:21:25,501 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-28 20:21:25,501 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-28 20:21:25,513 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-28 20:21:25,513 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-28 20:21:25,516 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2023-11-28 20:21:25,516 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:25,516 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:25,517 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:25,518 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-28 20:21:25,519 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-28 20:21:25,519 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-28 20:21:25,531 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-28 20:21:25,531 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-28 20:21:25,534 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2023-11-28 20:21:25,534 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:25,534 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:25,535 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:25,544 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-28 20:21:25,545 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-28 20:21:25,545 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-28 20:21:25,567 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-28 20:21:25,567 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-28 20:21:25,569 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2023-11-28 20:21:25,569 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:25,569 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:25,570 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:25,571 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-28 20:21:25,572 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-28 20:21:25,573 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-28 20:21:25,584 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-28 20:21:25,585 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-28 20:21:25,588 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Forceful destruction successful, exit code 0 [2023-11-28 20:21:25,588 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:25,588 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:25,589 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:25,592 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-28 20:21:25,593 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-28 20:21:25,593 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-28 20:21:25,612 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-28 20:21:25,612 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t8_st~0=4} Honda state: {~t8_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-28 20:21:25,615 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2023-11-28 20:21:25,616 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:25,616 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:25,617 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:25,618 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-28 20:21:25,619 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-28 20:21:25,619 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-28 20:21:25,630 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-28 20:21:25,631 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-28 20:21:25,633 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2023-11-28 20:21:25,633 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:25,633 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:25,634 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:25,635 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-28 20:21:25,636 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-28 20:21:25,636 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-28 20:21:25,650 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2023-11-28 20:21:25,650 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:25,650 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:25,651 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:25,652 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-28 20:21:25,653 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-28 20:21:25,653 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-28 20:21:25,666 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-28 20:21:25,669 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Forceful destruction successful, exit code 0 [2023-11-28 20:21:25,669 INFO L210 LassoAnalysis]: Preferences: [2023-11-28 20:21:25,670 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-28 20:21:25,670 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-28 20:21:25,670 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-28 20:21:25,670 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-28 20:21:25,670 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:25,670 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-28 20:21:25,670 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-28 20:21:25,670 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.08.cil.c_Iteration31_Loop [2023-11-28 20:21:25,670 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-28 20:21:25,670 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-28 20:21:25,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,681 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,707 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,718 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,722 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,725 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,727 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,745 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,748 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,752 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,754 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,756 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,766 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,767 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,771 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,773 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,774 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,777 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,779 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,781 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,783 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,787 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,789 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,793 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,796 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,799 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,801 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,807 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,817 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,818 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,823 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,826 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,828 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,841 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,849 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,853 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,857 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,859 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,860 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,867 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,872 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,873 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,877 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,879 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,881 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,900 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,912 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,918 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,920 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,926 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,928 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,934 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,937 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,942 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,945 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,947 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:25,950 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-28 20:21:26,460 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-28 20:21:26,465 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-28 20:21:26,466 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:26,466 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:26,467 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:26,468 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-28 20:21:26,469 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-28 20:21:26,479 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-28 20:21:26,479 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-28 20:21:26,480 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-28 20:21:26,480 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-28 20:21:26,480 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-28 20:21:26,481 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-28 20:21:26,481 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-28 20:21:26,483 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-28 20:21:26,485 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-28 20:21:26,485 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:26,486 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:26,486 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:26,488 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-28 20:21:26,489 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-28 20:21:26,498 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-28 20:21:26,498 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-28 20:21:26,498 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-28 20:21:26,498 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-28 20:21:26,499 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-28 20:21:26,499 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-28 20:21:26,499 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-28 20:21:26,501 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-28 20:21:26,503 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-28 20:21:26,503 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:26,503 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:26,504 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:26,505 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-28 20:21:26,506 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-28 20:21:26,516 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-28 20:21:26,516 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-28 20:21:26,516 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-28 20:21:26,516 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-28 20:21:26,516 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-28 20:21:26,517 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-28 20:21:26,517 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-28 20:21:26,518 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-28 20:21:26,520 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2023-11-28 20:21:26,520 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:26,521 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:26,521 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:26,522 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-28 20:21:26,524 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-28 20:21:26,533 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-28 20:21:26,533 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-28 20:21:26,533 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-28 20:21:26,533 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-28 20:21:26,534 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-28 20:21:26,534 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-28 20:21:26,534 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-28 20:21:26,536 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-28 20:21:26,538 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2023-11-28 20:21:26,538 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:26,539 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:26,539 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:26,540 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-28 20:21:26,542 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-28 20:21:26,551 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-28 20:21:26,551 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-28 20:21:26,551 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-28 20:21:26,551 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-28 20:21:26,552 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-28 20:21:26,552 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-28 20:21:26,552 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-28 20:21:26,553 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-28 20:21:26,555 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2023-11-28 20:21:26,555 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:26,556 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:26,556 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:26,559 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-28 20:21:26,559 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-28 20:21:26,569 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-28 20:21:26,569 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-28 20:21:26,569 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-28 20:21:26,569 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-28 20:21:26,569 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-28 20:21:26,570 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-28 20:21:26,570 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-28 20:21:26,572 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-28 20:21:26,574 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2023-11-28 20:21:26,574 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:26,574 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:26,575 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:26,577 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-28 20:21:26,578 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-28 20:21:26,587 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-28 20:21:26,587 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-28 20:21:26,587 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-28 20:21:26,588 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-28 20:21:26,588 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-28 20:21:26,588 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-28 20:21:26,588 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-28 20:21:26,590 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-28 20:21:26,592 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2023-11-28 20:21:26,592 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:26,592 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:26,593 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:26,595 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-28 20:21:26,596 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-28 20:21:26,605 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-28 20:21:26,605 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-28 20:21:26,606 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-28 20:21:26,606 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-28 20:21:26,606 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-28 20:21:26,607 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-28 20:21:26,607 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-28 20:21:26,609 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-28 20:21:26,612 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-28 20:21:26,612 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-28 20:21:26,613 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-28 20:21:26,613 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-28 20:21:26,629 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-28 20:21:26,630 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-28 20:21:26,631 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-28 20:21:26,631 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-28 20:21:26,631 INFO L513 LassoAnalysis]: Proved termination. [2023-11-28 20:21:26,631 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~M_E~0) = -1*~M_E~0 + 1 Supporting invariants [] [2023-11-28 20:21:26,634 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2023-11-28 20:21:26,636 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-28 20:21:26,654 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:26,708 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:26,710 INFO L262 TraceCheckSpWp]: Trace formula consists of 293 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-28 20:21:26,714 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-28 20:21:26,870 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:26,872 INFO L262 TraceCheckSpWp]: Trace formula consists of 264 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-28 20:21:26,876 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-28 20:21:27,140 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:27,146 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-28 20:21:27,147 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 84509 states and 109504 transitions. cyclomatic complexity: 25027 Second operand has 5 states, 5 states have (on average 44.8) internal successors, (224), 5 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:27,865 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_82560992-cfc1-407a-8526-0631dcbf5ba2/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2023-11-28 20:21:28,494 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 84509 states and 109504 transitions. cyclomatic complexity: 25027. Second operand has 5 states, 5 states have (on average 44.8) internal successors, (224), 5 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 236063 states and 304867 transitions. Complement of second has 5 states. [2023-11-28 20:21:28,496 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-28 20:21:28,497 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 44.8) internal successors, (224), 5 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:28,500 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1203 transitions. [2023-11-28 20:21:28,501 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1203 transitions. Stem has 104 letters. Loop has 120 letters. [2023-11-28 20:21:28,507 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-28 20:21:28,507 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1203 transitions. Stem has 224 letters. Loop has 120 letters. [2023-11-28 20:21:28,509 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-28 20:21:28,509 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1203 transitions. Stem has 104 letters. Loop has 240 letters. [2023-11-28 20:21:28,512 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-28 20:21:28,512 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 236063 states and 304867 transitions. [2023-11-28 20:21:29,429 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 158912 [2023-11-28 20:21:30,207 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 236063 states to 236063 states and 304867 transitions. [2023-11-28 20:21:30,207 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 160094 [2023-11-28 20:21:30,306 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 160287 [2023-11-28 20:21:30,306 INFO L73 IsDeterministic]: Start isDeterministic. Operand 236063 states and 304867 transitions. [2023-11-28 20:21:30,306 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-28 20:21:30,306 INFO L218 hiAutomatonCegarLoop]: Abstraction has 236063 states and 304867 transitions. [2023-11-28 20:21:30,398 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 236063 states and 304867 transitions. [2023-11-28 20:21:31,826 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 236063 to 235870. [2023-11-28 20:21:31,958 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 235870 states, 235870 states have (on average 1.291703056768559) internal successors, (304674), 235869 states have internal predecessors, (304674), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:32,347 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235870 states to 235870 states and 304674 transitions. [2023-11-28 20:21:32,347 INFO L240 hiAutomatonCegarLoop]: Abstraction has 235870 states and 304674 transitions. [2023-11-28 20:21:32,347 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:32,348 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:21:32,348 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:21:32,348 INFO L87 Difference]: Start difference. First operand 235870 states and 304674 transitions. Second operand has 3 states, 3 states have (on average 74.66666666666667) internal successors, (224), 3 states have internal predecessors, (224), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:33,877 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:33,877 INFO L93 Difference]: Finished difference Result 249502 states and 320802 transitions. [2023-11-28 20:21:33,877 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 249502 states and 320802 transitions. [2023-11-28 20:21:35,103 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 168000 [2023-11-28 20:21:35,580 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 249502 states to 249502 states and 320802 transitions. [2023-11-28 20:21:35,580 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 169182 [2023-11-28 20:21:35,642 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 169182 [2023-11-28 20:21:35,642 INFO L73 IsDeterministic]: Start isDeterministic. Operand 249502 states and 320802 transitions. [2023-11-28 20:21:35,646 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-28 20:21:35,646 INFO L218 hiAutomatonCegarLoop]: Abstraction has 249502 states and 320802 transitions. [2023-11-28 20:21:35,761 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 249502 states and 320802 transitions. [2023-11-28 20:21:37,340 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 249502 to 235870. [2023-11-28 20:21:37,473 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 235870 states, 235870 states have (on average 1.2892610336202146) internal successors, (304098), 235869 states have internal predecessors, (304098), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:38,358 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235870 states to 235870 states and 304098 transitions. [2023-11-28 20:21:38,358 INFO L240 hiAutomatonCegarLoop]: Abstraction has 235870 states and 304098 transitions. [2023-11-28 20:21:38,359 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:21:38,359 INFO L428 stractBuchiCegarLoop]: Abstraction has 235870 states and 304098 transitions. [2023-11-28 20:21:38,359 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-28 20:21:38,359 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 235870 states and 304098 transitions. [2023-11-28 20:21:38,786 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 158912 [2023-11-28 20:21:38,786 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:38,786 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:38,787 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:38,787 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:38,788 INFO L748 eck$LassoCheckResult]: Stem: 2853914#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 2853915#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 2855385#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2855386#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2855388#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 2854147#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2854148#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2855372#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2855342#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2854300#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2854301#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2854815#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2854816#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2854464#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2854465#L838 assume !(0 == ~M_E~0); 2854838#L838-2 assume !(0 == ~T1_E~0); 2853551#L843-1 assume !(0 == ~T2_E~0); 2853552#L848-1 assume !(0 == ~T3_E~0); 2853762#L853-1 assume !(0 == ~T4_E~0); 2854443#L858-1 assume !(0 == ~T5_E~0); 2853476#L863-1 assume !(0 == ~T6_E~0); 2853477#L868-1 assume !(0 == ~T7_E~0); 2855501#L873-1 assume !(0 == ~T8_E~0); 2855493#L878-1 assume !(0 == ~E_1~0); 2855447#L883-1 assume !(0 == ~E_2~0); 2855448#L888-1 assume !(0 == ~E_3~0); 2854758#L893-1 assume !(0 == ~E_4~0); 2854759#L898-1 assume !(0 == ~E_5~0); 2855540#L903-1 assume !(0 == ~E_6~0); 2855440#L908-1 assume !(0 == ~E_7~0); 2855039#L913-1 assume !(0 == ~E_8~0); 2853572#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2853573#L402 assume !(1 == ~m_pc~0); 2853966#L402-2 is_master_triggered_~__retres1~0#1 := 0; 2854397#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2855190#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2854313#L1035 assume !(0 != activate_threads_~tmp~1#1); 2854314#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2854417#L421 assume !(1 == ~t1_pc~0); 2855426#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2855508#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2853574#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2853575#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 2854535#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2855524#L440 assume !(1 == ~t2_pc~0); 2855678#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2853825#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2853826#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2854201#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 2855075#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2854217#L459 assume !(1 == ~t3_pc~0); 2854218#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2855417#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2853506#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2853507#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 2853798#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2853815#L478 assume !(1 == ~t4_pc~0); 2853816#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2855204#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2853713#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2853714#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 2853650#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2853651#L497 assume !(1 == ~t5_pc~0); 2853728#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2854668#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2854920#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2855525#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 2855526#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2855653#L516 assume !(1 == ~t6_pc~0); 2855654#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2854809#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2854810#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2853904#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 2853905#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2854791#L535 assume !(1 == ~t7_pc~0); 2854792#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2855726#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2855624#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2855625#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 2855005#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2855006#L554 assume !(1 == ~t8_pc~0); 2853508#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2853509#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2855724#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2854079#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 2854080#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2853488#L931 assume !(1 == ~M_E~0); 2853489#L931-2 assume !(1 == ~T1_E~0); 2855563#L936-1 assume !(1 == ~T2_E~0); 2855564#L941-1 assume !(1 == ~T3_E~0); 2855720#L946-1 assume !(1 == ~T4_E~0); 2855422#L951-1 assume !(1 == ~T5_E~0); 2853932#L956-1 assume !(1 == ~T6_E~0); 2853933#L961-1 assume !(1 == ~T7_E~0); 2854760#L966-1 assume !(1 == ~T8_E~0); 2854761#L971-1 assume !(1 == ~E_1~0); 2855011#L976-1 assume !(1 == ~E_2~0); 2855716#L981-1 assume !(1 == ~E_3~0); 2855714#L986-1 assume !(1 == ~E_4~0); 2855713#L991-1 assume !(1 == ~E_5~0); 2853987#L996-1 assume !(1 == ~E_6~0); 2855512#L1001-1 assume !(1 == ~E_7~0); 2854863#L1006-1 assume !(1 == ~E_8~0); 2854864#L1011-1 assume { :end_inline_reset_delta_events } true; 2855423#L1272-2 assume !false; 2864504#L1273 [2023-11-28 20:21:38,788 INFO L750 eck$LassoCheckResult]: Loop: 2864504#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2969058#L813-1 assume !false; 2969054#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2969052#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2969050#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2969049#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2969046#L696 assume 0 != eval_~tmp~0#1; 2969045#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 2969042#L704 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 2969043#L83 assume !(0 == ~m_pc~0); 2993114#L86 assume 1 == ~m_pc~0; 2993111#$Ultimate##322 assume !false; 2972497#L103 ~m_pc~0 := 1;~m_st~0 := 2; 2972495#master_returnLabel#1 assume { :end_inline_master } true; 2972486#L704-2 havoc eval_~tmp_ndt_1~0#1; 2972483#L701-1 assume !(0 == ~t1_st~0); 2972479#L715-1 assume !(0 == ~t2_st~0); 2972475#L729-1 assume !(0 == ~t3_st~0); 2972471#L743-1 assume !(0 == ~t4_st~0); 2972467#L757-1 assume !(0 == ~t5_st~0); 2972461#L771-1 assume !(0 == ~t6_st~0); 2972457#L785-1 assume !(0 == ~t7_st~0); 2972453#L799-1 assume !(0 == ~t8_st~0); 2972454#L813-1 assume !false; 2978779#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2978777#L634 assume !(0 == ~m_st~0); 2978775#L638 assume !(0 == ~t1_st~0); 2978773#L642 assume !(0 == ~t2_st~0); 2978771#L646 assume !(0 == ~t3_st~0); 2978769#L650 assume !(0 == ~t4_st~0); 2978767#L654 assume !(0 == ~t5_st~0); 2978765#L658 assume !(0 == ~t6_st~0); 2978763#L662 assume !(0 == ~t7_st~0); 2978759#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 2978757#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2978755#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2978752#L696 assume !(0 != eval_~tmp~0#1); 2978750#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2978746#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2978744#L838-3 assume !(0 == ~M_E~0); 2978742#L838-5 assume !(0 == ~T1_E~0); 2978740#L843-3 assume !(0 == ~T2_E~0); 2978737#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 2978735#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2978734#L858-3 assume !(0 == ~T5_E~0); 2978731#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2978730#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2978728#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2978726#L878-3 assume !(0 == ~E_1~0); 2978723#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2978721#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2978719#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2978718#L898-3 assume !(0 == ~E_5~0); 2978715#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2978714#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2978712#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2978711#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2978710#L402-27 assume 1 == ~m_pc~0; 2978707#L403-9 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2978705#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2978704#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 2978702#L1035-27 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2978700#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2978698#L421-27 assume !(1 == ~t1_pc~0); 2978696#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 2978692#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2978688#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2978684#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 2978680#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2978676#L440-27 assume !(1 == ~t2_pc~0); 2978672#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 2978668#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2978664#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2978662#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 2978660#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2978658#L459-27 assume !(1 == ~t3_pc~0); 2978654#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 2978652#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2978650#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2978648#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 2978645#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2978643#L478-27 assume !(1 == ~t4_pc~0); 2978641#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 2978638#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2978636#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2978634#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 2978631#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2978629#L497-27 assume 1 == ~t5_pc~0; 2978628#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2969224#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2969222#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2969180#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2969178#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2969176#L516-27 assume !(1 == ~t6_pc~0); 2969174#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 2969172#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2969170#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2969169#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 2969168#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2969166#L535-27 assume 1 == ~t7_pc~0; 2969164#L536-9 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2969165#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2969229#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2969155#L1091-27 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2969153#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2969151#L554-27 assume !(1 == ~t8_pc~0); 2969149#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 2969147#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2969145#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2969143#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 2969141#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2969140#L931-3 assume !(1 == ~M_E~0); 2969139#L931-5 assume !(1 == ~T1_E~0); 2969137#L936-3 assume !(1 == ~T2_E~0); 2969136#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2969135#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2969131#L951-3 assume !(1 == ~T5_E~0); 2969129#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2969127#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2969125#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2969122#L971-3 assume !(1 == ~E_1~0); 2969120#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2969116#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2969114#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2969112#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2969109#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2969106#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2969104#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2969103#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2969102#L634-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2969101#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2969100#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 2969098#L1291 assume !(0 == start_simulation_~tmp~3#1); 2969096#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 2969094#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 2969092#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 2969090#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 2969088#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2969086#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2969084#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 2969082#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 2969079#L1272-2 assume !false; 2864504#L1273 [2023-11-28 20:21:38,788 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:38,788 INFO L85 PathProgramCache]: Analyzing trace with hash -2024511544, now seen corresponding path program 1 times [2023-11-28 20:21:38,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:38,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [993363246] [2023-11-28 20:21:38,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:38,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:38,801 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:38,802 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:38,809 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:38,838 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:38,838 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:38,838 INFO L85 PathProgramCache]: Analyzing trace with hash 121105882, now seen corresponding path program 1 times [2023-11-28 20:21:38,839 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:38,839 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1505085999] [2023-11-28 20:21:38,839 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:38,839 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:38,852 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:38,882 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2023-11-28 20:21:38,882 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:38,882 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1505085999] [2023-11-28 20:21:38,882 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1505085999] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:38,882 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:38,882 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:21:38,882 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1465108467] [2023-11-28 20:21:38,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:38,883 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:38,883 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:38,883 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:21:38,883 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:21:38,883 INFO L87 Difference]: Start difference. First operand 235870 states and 304098 transitions. cyclomatic complexity: 68324 Second operand has 3 states, 3 states have (on average 46.0) internal successors, (138), 3 states have internal predecessors, (138), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:40,245 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:40,245 INFO L93 Difference]: Finished difference Result 433035 states and 552440 transitions. [2023-11-28 20:21:40,245 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 433035 states and 552440 transitions. [2023-11-28 20:21:42,110 INFO L131 ngComponentsAnalysis]: Automaton has 160 accepting balls. 272128 [2023-11-28 20:21:42,932 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 433035 states to 422539 states and 539128 transitions. [2023-11-28 20:21:42,932 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 281099 [2023-11-28 20:21:43,026 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 281099 [2023-11-28 20:21:43,026 INFO L73 IsDeterministic]: Start isDeterministic. Operand 422539 states and 539128 transitions. [2023-11-28 20:21:43,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-28 20:21:43,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 422539 states and 539128 transitions. [2023-11-28 20:21:43,621 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 422539 states and 539128 transitions. [2023-11-28 20:21:46,298 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 422539 to 422283. [2023-11-28 20:21:46,511 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 422283 states, 422283 states have (on average 1.2760920993741165) internal successors, (538872), 422282 states have internal predecessors, (538872), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:47,963 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 422283 states to 422283 states and 538872 transitions. [2023-11-28 20:21:47,963 INFO L240 hiAutomatonCegarLoop]: Abstraction has 422283 states and 538872 transitions. [2023-11-28 20:21:47,988 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:21:47,988 INFO L428 stractBuchiCegarLoop]: Abstraction has 422283 states and 538872 transitions. [2023-11-28 20:21:47,989 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2023-11-28 20:21:47,989 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 422283 states and 538872 transitions. [2023-11-28 20:21:48,978 INFO L131 ngComponentsAnalysis]: Automaton has 160 accepting balls. 271936 [2023-11-28 20:21:48,978 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:48,978 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:48,979 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:48,979 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:48,979 INFO L748 eck$LassoCheckResult]: Stem: 3522824#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 3522825#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 3524264#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3524265#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3524268#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 3523046#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3523047#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3524255#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3524222#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3523197#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3523198#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3523702#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3523703#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3523358#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3523359#L838 assume 0 == ~M_E~0;~M_E~0 := 1; 3524314#L838-2 assume !(0 == ~T1_E~0); 3522460#L843-1 assume !(0 == ~T2_E~0); 3522461#L848-1 assume !(0 == ~T3_E~0); 3523758#L853-1 assume !(0 == ~T4_E~0); 3523759#L858-1 assume !(0 == ~T5_E~0); 3522387#L863-1 assume !(0 == ~T6_E~0); 3522388#L868-1 assume !(0 == ~T7_E~0); 3524527#L873-1 assume !(0 == ~T8_E~0); 3524528#L878-1 assume !(0 == ~E_1~0); 3524329#L883-1 assume !(0 == ~E_2~0); 3524330#L888-1 assume !(0 == ~E_3~0); 3523640#L893-1 assume !(0 == ~E_4~0); 3523641#L898-1 assume !(0 == ~E_5~0); 3524580#L903-1 assume !(0 == ~E_6~0); 3524581#L908-1 assume !(0 == ~E_7~0); 3523922#L913-1 assume !(0 == ~E_8~0); 3523923#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3523953#L402 assume !(1 == ~m_pc~0); 3523291#L402-2 is_master_triggered_~__retres1~0#1 := 0; 3522718#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3522719#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 3523209#L1035 assume !(0 != activate_threads_~tmp~1#1); 3523210#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3523309#L421 assume !(1 == ~t1_pc~0); 3524393#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3524394#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3522483#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3522484#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 3524409#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3524410#L440 assume !(1 == ~t2_pc~0); 3524565#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3524566#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3523099#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3523100#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 3524695#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3523117#L459 assume !(1 == ~t3_pc~0); 3523118#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3524694#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3524692#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3524690#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 3524588#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3524589#L478 assume !(1 == ~t4_pc~0); 3524080#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3524081#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3524689#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3523064#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 3523065#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3523752#L497 assume !(1 == ~t5_pc~0); 3522637#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3523565#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3523810#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3524069#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 3524285#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3524286#L516 assume !(1 == ~t6_pc~0); 3524670#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3524667#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3524664#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3524661#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 3524658#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3524655#L535 assume !(1 == ~t7_pc~0); 3524652#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3524646#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3524640#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3524634#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 3524628#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3524625#L554 assume !(1 == ~t8_pc~0); 3524622#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3524619#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3524616#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3524613#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 3524610#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3524607#L931 assume 1 == ~M_E~0;~M_E~0 := 2; 3524358#L931-2 assume !(1 == ~T1_E~0); 3524359#L936-1 assume !(1 == ~T2_E~0); 3524564#L941-1 assume !(1 == ~T3_E~0); 3523310#L946-1 assume !(1 == ~T4_E~0); 3523311#L951-1 assume !(1 == ~T5_E~0); 3524604#L956-1 assume !(1 == ~T6_E~0); 3524537#L961-1 assume !(1 == ~T7_E~0); 3524538#L966-1 assume !(1 == ~T8_E~0); 3524603#L971-1 assume !(1 == ~E_1~0); 3524475#L976-1 assume !(1 == ~E_2~0); 3524476#L981-1 assume !(1 == ~E_3~0); 3524601#L986-1 assume !(1 == ~E_4~0); 3524600#L991-1 assume !(1 == ~E_5~0); 3522891#L996-1 assume !(1 == ~E_6~0); 3524398#L1001-1 assume !(1 == ~E_7~0); 3523750#L1006-1 assume !(1 == ~E_8~0); 3523751#L1011-1 assume { :end_inline_reset_delta_events } true; 3524307#L1272-2 assume !false; 3544195#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3706041#L813-1 [2023-11-28 20:21:48,979 INFO L750 eck$LassoCheckResult]: Loop: 3706041#L813-1 assume !false; 3706038#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 3706036#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 3706033#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 3706031#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3706029#L696 assume 0 != eval_~tmp~0#1; 3706027#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 3706024#L704 assume !(0 != eval_~tmp_ndt_1~0#1); 3706022#L704-2 havoc eval_~tmp_ndt_1~0#1; 3706017#L701-1 assume !(0 == ~t1_st~0); 3706013#L715-1 assume !(0 == ~t2_st~0); 3706009#L729-1 assume !(0 == ~t3_st~0); 3706005#L743-1 assume !(0 == ~t4_st~0); 3706006#L757-1 assume !(0 == ~t5_st~0); 3706052#L771-1 assume !(0 == ~t6_st~0); 3706048#L785-1 assume !(0 == ~t7_st~0); 3706044#L799-1 assume !(0 == ~t8_st~0); 3706041#L813-1 [2023-11-28 20:21:48,979 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:48,980 INFO L85 PathProgramCache]: Analyzing trace with hash -1784166491, now seen corresponding path program 1 times [2023-11-28 20:21:48,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:48,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2092491491] [2023-11-28 20:21:48,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:48,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:48,988 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:49,019 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:49,019 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:49,019 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2092491491] [2023-11-28 20:21:49,020 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2092491491] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:49,020 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:49,020 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:21:49,020 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1371164004] [2023-11-28 20:21:49,020 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:49,020 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:21:49,021 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:49,021 INFO L85 PathProgramCache]: Analyzing trace with hash -764442210, now seen corresponding path program 1 times [2023-11-28 20:21:49,021 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:49,021 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [624765177] [2023-11-28 20:21:49,021 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:49,022 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:49,025 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:49,026 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:49,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:49,030 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:49,140 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:49,140 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:21:49,141 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:21:49,141 INFO L87 Difference]: Start difference. First operand 422283 states and 538872 transitions. cyclomatic complexity: 116781 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 2 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:50,078 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:50,078 INFO L93 Difference]: Finished difference Result 211869 states and 269916 transitions. [2023-11-28 20:21:50,079 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 211869 states and 269916 transitions. [2023-11-28 20:21:50,754 INFO L131 ngComponentsAnalysis]: Automaton has 112 accepting balls. 137728 [2023-11-28 20:21:51,030 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 211869 states to 144220 states and 183882 transitions. [2023-11-28 20:21:51,031 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 144220 [2023-11-28 20:21:51,098 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 144220 [2023-11-28 20:21:51,098 INFO L73 IsDeterministic]: Start isDeterministic. Operand 144220 states and 183882 transitions. [2023-11-28 20:21:51,156 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:51,156 INFO L218 hiAutomatonCegarLoop]: Abstraction has 144220 states and 183882 transitions. [2023-11-28 20:21:51,231 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 144220 states and 183882 transitions. [2023-11-28 20:21:52,173 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 144220 to 76570. [2023-11-28 20:21:52,212 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76570 states, 76570 states have (on average 1.2774715946193027) internal successors, (97816), 76569 states have internal predecessors, (97816), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:52,323 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76570 states to 76570 states and 97816 transitions. [2023-11-28 20:21:52,324 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76570 states and 97816 transitions. [2023-11-28 20:21:52,324 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:21:52,324 INFO L428 stractBuchiCegarLoop]: Abstraction has 76570 states and 97816 transitions. [2023-11-28 20:21:52,324 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2023-11-28 20:21:52,324 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76570 states and 97816 transitions. [2023-11-28 20:21:52,489 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75904 [2023-11-28 20:21:52,489 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:52,489 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:52,491 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:52,491 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:52,491 INFO L748 eck$LassoCheckResult]: Stem: 4156784#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4156785#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4157525#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4157526#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4157528#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4156903#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4156904#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4157522#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4157511#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4156981#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4156982#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4157249#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4157250#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4157069#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4157070#L838 assume !(0 == ~M_E~0); 4157258#L838-2 assume !(0 == ~T1_E~0); 4156585#L843-1 assume !(0 == ~T2_E~0); 4156586#L848-1 assume !(0 == ~T3_E~0); 4156701#L853-1 assume !(0 == ~T4_E~0); 4157055#L858-1 assume !(0 == ~T5_E~0); 4156541#L863-1 assume !(0 == ~T6_E~0); 4156542#L868-1 assume !(0 == ~T7_E~0); 4157588#L873-1 assume !(0 == ~T8_E~0); 4157586#L878-1 assume !(0 == ~E_1~0); 4157562#L883-1 assume !(0 == ~E_2~0); 4157563#L888-1 assume !(0 == ~E_3~0); 4157212#L893-1 assume !(0 == ~E_4~0); 4157213#L898-1 assume !(0 == ~E_5~0); 4157610#L903-1 assume !(0 == ~E_6~0); 4157560#L908-1 assume !(0 == ~E_7~0); 4157367#L913-1 assume !(0 == ~E_8~0); 4156597#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4156598#L402 assume !(1 == ~m_pc~0); 4156808#L402-2 is_master_triggered_~__retres1~0#1 := 0; 4156728#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4156729#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4156988#L1035 assume !(0 != activate_threads_~tmp~1#1); 4156989#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4157042#L421 assume !(1 == ~t1_pc~0); 4157553#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4157589#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4156600#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4156601#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4157099#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4157601#L440 assume !(1 == ~t2_pc~0); 4157683#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4156737#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4156738#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4156930#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4157389#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4156935#L459 assume !(1 == ~t3_pc~0); 4156936#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4157548#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4157598#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4156721#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 4156722#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4156732#L478 assume !(1 == ~t4_pc~0); 4156733#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4157445#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4156673#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4156674#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 4156637#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4156638#L497 assume !(1 == ~t5_pc~0); 4156684#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4157171#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4157303#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4157599#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4157600#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4157668#L516 assume !(1 == ~t6_pc~0); 4157669#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4157247#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4157248#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4156778#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 4156779#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4157234#L535 assume !(1 == ~t7_pc~0); 4157235#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4157710#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4157708#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4157705#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4157346#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4157347#L554 assume !(1 == ~t8_pc~0); 4156563#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4156564#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4157703#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4156865#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4156866#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4156551#L931 assume !(1 == ~M_E~0); 4156552#L931-2 assume !(1 == ~T1_E~0); 4157628#L936-1 assume !(1 == ~T2_E~0); 4157629#L941-1 assume !(1 == ~T3_E~0); 4157043#L946-1 assume !(1 == ~T4_E~0); 4157044#L951-1 assume !(1 == ~T5_E~0); 4157700#L956-1 assume !(1 == ~T6_E~0); 4157670#L961-1 assume !(1 == ~T7_E~0); 4157671#L966-1 assume !(1 == ~T8_E~0); 4157699#L971-1 assume !(1 == ~E_1~0); 4157645#L976-1 assume !(1 == ~E_2~0); 4157308#L981-1 assume !(1 == ~E_3~0); 4157047#L986-1 assume !(1 == ~E_4~0); 4157048#L991-1 assume !(1 == ~E_5~0); 4156822#L996-1 assume !(1 == ~E_6~0); 4157594#L1001-1 assume !(1 == ~E_7~0); 4157271#L1006-1 assume !(1 == ~E_8~0); 4157272#L1011-1 assume { :end_inline_reset_delta_events } true; 4157550#L1272-2 [2023-11-28 20:21:52,491 INFO L750 eck$LassoCheckResult]: Loop: 4157550#L1272-2 assume !false; 4177488#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4173156#L813-1 assume !false; 4177484#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4177482#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4177480#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4177479#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4177476#L696 assume 0 != eval_~tmp~0#1; 4177475#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4177473#L704 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 4177474#L83 assume !(0 == ~m_pc~0); 4178984#L86 assume 1 == ~m_pc~0; 4178981#$Ultimate##322 assume !false; 4178980#L103 ~m_pc~0 := 1;~m_st~0 := 2; 4178977#master_returnLabel#1 assume { :end_inline_master } true; 4178974#L704-2 havoc eval_~tmp_ndt_1~0#1; 4178971#L701-1 assume !(0 == ~t1_st~0); 4178968#L715-1 assume !(0 == ~t2_st~0); 4178962#L729-1 assume !(0 == ~t3_st~0); 4178958#L743-1 assume !(0 == ~t4_st~0); 4178954#L757-1 assume !(0 == ~t5_st~0); 4178951#L771-1 assume !(0 == ~t6_st~0); 4178952#L785-1 assume !(0 == ~t7_st~0); 4186490#L799-1 assume !(0 == ~t8_st~0); 4186491#L813-1 assume !false; 4192243#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4192241#L634 assume !(0 == ~m_st~0); 4192239#L638 assume !(0 == ~t1_st~0); 4192237#L642 assume !(0 == ~t2_st~0); 4192235#L646 assume !(0 == ~t3_st~0); 4192233#L650 assume !(0 == ~t4_st~0); 4192231#L654 assume !(0 == ~t5_st~0); 4192229#L658 assume !(0 == ~t6_st~0); 4192227#L662 assume !(0 == ~t7_st~0); 4192224#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 4192222#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4192220#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4192218#L696 assume !(0 != eval_~tmp~0#1); 4192216#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4192214#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4192212#L838-3 assume !(0 == ~M_E~0); 4192210#L838-5 assume !(0 == ~T1_E~0); 4192208#L843-3 assume !(0 == ~T2_E~0); 4192206#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4192204#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4192202#L858-3 assume !(0 == ~T5_E~0); 4192200#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4192197#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4192195#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4192193#L878-3 assume !(0 == ~E_1~0); 4192191#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4192189#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4192187#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4192184#L898-3 assume !(0 == ~E_5~0); 4192182#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4192180#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4192178#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4192176#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4192174#L402-27 assume !(1 == ~m_pc~0); 4192171#L402-29 is_master_triggered_~__retres1~0#1 := 0; 4192168#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4192166#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4192164#L1035-27 assume !(0 != activate_threads_~tmp~1#1); 4192162#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4192160#L421-27 assume !(1 == ~t1_pc~0); 4192158#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 4192155#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4192153#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4192151#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 4192150#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4192149#L440-27 assume !(1 == ~t2_pc~0); 4192147#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 4192144#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4192142#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4192140#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 4192138#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4192136#L459-27 assume 1 == ~t3_pc~0; 4192134#L460-9 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4192135#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4192374#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4192124#L1059-27 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4192122#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4192120#L478-27 assume !(1 == ~t4_pc~0); 4192118#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 4190193#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4190190#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4190188#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 4190186#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4190184#L497-27 assume 1 == ~t5_pc~0; 4190182#L498-9 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4190183#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4192566#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4192557#L1075-27 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4192550#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4192543#L516-27 assume !(1 == ~t6_pc~0); 4192537#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 4192532#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4192526#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4192519#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 4192512#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4192505#L535-27 assume !(1 == ~t7_pc~0); 4192498#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 4192491#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4192482#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4192475#L1091-27 assume !(0 != activate_threads_~tmp___6~0#1); 4192469#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4192464#L554-27 assume !(1 == ~t8_pc~0); 4192459#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 4192455#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4192449#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4192445#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 4192442#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4192436#L931-3 assume !(1 == ~M_E~0); 4192433#L931-5 assume !(1 == ~T1_E~0); 4192429#L936-3 assume !(1 == ~T2_E~0); 4192425#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4192418#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4192413#L951-3 assume !(1 == ~T5_E~0); 4192408#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4192401#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4192396#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4192388#L971-3 assume !(1 == ~E_1~0); 4192383#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4192378#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4192114#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4190099#L991-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4190096#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4190093#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4190091#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4190089#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4189958#L634-1 assume !(0 == ~m_st~0); 4158057#L638-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4158048#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4158049#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 4177584#L1291 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 4177583#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4177582#L402-30 assume 1 == ~m_pc~0; 4177581#L403-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4177580#L413-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4177579#is_master_triggered_returnLabel#11 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4177578#L1035-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4177577#L1035-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4177576#L421-30 assume !(1 == ~t1_pc~0); 4177575#L421-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4177574#L432-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4177573#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4177572#L1043-30 assume !(0 != activate_threads_~tmp___0~0#1); 4177571#L1043-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4177570#L440-30 assume !(1 == ~t2_pc~0); 4177569#L440-32 is_transmit2_triggered_~__retres1~2#1 := 0; 4177568#L451-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4177567#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4177566#L1051-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4177565#L1051-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4177564#L459-30 assume !(1 == ~t3_pc~0); 4177563#L459-32 is_transmit3_triggered_~__retres1~3#1 := 0; 4177561#L470-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4177559#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4177557#L1059-30 assume !(0 != activate_threads_~tmp___2~0#1); 4177555#L1059-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4177554#L478-30 assume !(1 == ~t4_pc~0); 4177553#L478-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4177552#L489-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4177551#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4177550#L1067-30 assume !(0 != activate_threads_~tmp___3~0#1); 4177549#L1067-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4177548#L497-30 assume 1 == ~t5_pc~0; 4177546#L498-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4177547#L508-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4177623#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4177622#L1075-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4177621#L1075-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4177620#L516-30 assume !(1 == ~t6_pc~0); 4177619#L516-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4177618#L527-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4177617#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4177616#L1083-30 assume !(0 != activate_threads_~tmp___5~0#1); 4177615#L1083-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4177614#L535-30 assume !(1 == ~t7_pc~0); 4177613#L535-32 is_transmit7_triggered_~__retres1~7#1 := 0; 4177611#L546-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4177609#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4177607#L1091-30 assume !(0 != activate_threads_~tmp___6~0#1); 4177605#L1091-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4177604#L554-30 assume !(1 == ~t8_pc~0); 4177603#L554-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4177602#L565-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4177601#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4177600#L1099-30 assume !(0 != activate_threads_~tmp___7~0#1); 4177599#L1099-32 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 4177598#L1132 assume 1 == ~M_E~0;~M_E~0 := 2; 4177597#L1132-2 assume !(1 == ~T1_E~0); 4177596#L1137-1 assume !(1 == ~T2_E~0); 4177595#L1142-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4177594#L1147-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4177593#L1152-1 assume !(1 == ~T5_E~0); 4177592#L1157-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4177591#L1162-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4177590#L1167-1 assume !(1 == ~T8_E~0); 4177589#L1172-1 assume !(1 == ~E_1~0); 4177588#L1177-1 assume 1 == ~E_2~0;~E_2~0 := 2; 4177587#L1182-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4177586#L1187-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4177504#L1192-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4177503#L1197-1 assume 1 == ~E_6~0;~E_6~0 := 2; 4177502#L1202-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4177501#L1207-1 assume !(1 == ~E_8~0); 4177500#L1212-1 assume { :end_inline_reset_time_events } true; 4177499#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4177498#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4177497#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4177496#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 4177495#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4177494#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4177493#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4177492#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 4157550#L1272-2 [2023-11-28 20:21:52,492 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:52,492 INFO L85 PathProgramCache]: Analyzing trace with hash -1450780161, now seen corresponding path program 12 times [2023-11-28 20:21:52,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:52,492 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [889799540] [2023-11-28 20:21:52,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:52,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:52,501 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:52,501 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:52,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:52,543 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:52,543 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:52,544 INFO L85 PathProgramCache]: Analyzing trace with hash 616787509, now seen corresponding path program 1 times [2023-11-28 20:21:52,544 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:52,544 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1826643047] [2023-11-28 20:21:52,544 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:52,544 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:52,556 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:52,590 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:52,591 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:52,591 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1826643047] [2023-11-28 20:21:52,591 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1826643047] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:52,591 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:52,591 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:21:52,591 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2005521915] [2023-11-28 20:21:52,592 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:52,592 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:52,592 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:52,592 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:21:52,593 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:21:52,593 INFO L87 Difference]: Start difference. First operand 76570 states and 97816 transitions. cyclomatic complexity: 21278 Second operand has 3 states, 3 states have (on average 72.0) internal successors, (216), 3 states have internal predecessors, (216), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:52,961 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:52,961 INFO L93 Difference]: Finished difference Result 108116 states and 136587 transitions. [2023-11-28 20:21:52,961 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 108116 states and 136587 transitions. [2023-11-28 20:21:53,655 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 97216 [2023-11-28 20:21:53,818 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 108116 states to 108116 states and 136587 transitions. [2023-11-28 20:21:53,818 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 108116 [2023-11-28 20:21:53,854 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 108116 [2023-11-28 20:21:53,854 INFO L73 IsDeterministic]: Start isDeterministic. Operand 108116 states and 136587 transitions. [2023-11-28 20:21:53,886 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:53,886 INFO L218 hiAutomatonCegarLoop]: Abstraction has 108116 states and 136587 transitions. [2023-11-28 20:21:53,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 108116 states and 136587 transitions. [2023-11-28 20:21:54,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 108116 to 103316. [2023-11-28 20:21:54,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103316 states, 103316 states have (on average 1.2656606914708273) internal successors, (130763), 103315 states have internal predecessors, (130763), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:55,083 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103316 states to 103316 states and 130763 transitions. [2023-11-28 20:21:55,083 INFO L240 hiAutomatonCegarLoop]: Abstraction has 103316 states and 130763 transitions. [2023-11-28 20:21:55,084 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:21:55,084 INFO L428 stractBuchiCegarLoop]: Abstraction has 103316 states and 130763 transitions. [2023-11-28 20:21:55,084 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2023-11-28 20:21:55,085 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103316 states and 130763 transitions. [2023-11-28 20:21:55,322 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 97216 [2023-11-28 20:21:55,322 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:55,322 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:55,324 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:55,324 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:55,325 INFO L748 eck$LassoCheckResult]: Stem: 4341481#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4341482#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4342229#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4342230#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4342232#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4341600#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4341601#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4342225#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4342213#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4341677#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4341678#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4341950#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4341951#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4341767#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4341768#L838 assume !(0 == ~M_E~0); 4341960#L838-2 assume !(0 == ~T1_E~0); 4341278#L843-1 assume !(0 == ~T2_E~0); 4341279#L848-1 assume !(0 == ~T3_E~0); 4341397#L853-1 assume !(0 == ~T4_E~0); 4341751#L858-1 assume !(0 == ~T5_E~0); 4341233#L863-1 assume !(0 == ~T6_E~0); 4341234#L868-1 assume !(0 == ~T7_E~0); 4342294#L873-1 assume !(0 == ~T8_E~0); 4342291#L878-1 assume !(0 == ~E_1~0); 4342269#L883-1 assume !(0 == ~E_2~0); 4342270#L888-1 assume !(0 == ~E_3~0); 4341914#L893-1 assume !(0 == ~E_4~0); 4341915#L898-1 assume !(0 == ~E_5~0); 4342313#L903-1 assume !(0 == ~E_6~0); 4342266#L908-1 assume !(0 == ~E_7~0); 4342070#L913-1 assume !(0 == ~E_8~0); 4341290#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4341291#L402 assume 1 == ~m_pc~0; 4341503#L403 assume !(1 == ~M_E~0); 4341504#L402-2 is_master_triggered_~__retres1~0#1 := 0; 4341424#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4341425#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4341684#L1035 assume !(0 != activate_threads_~tmp~1#1); 4341685#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4341738#L421 assume !(1 == ~t1_pc~0); 4342258#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4342295#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4341293#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4341294#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4341798#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4342308#L440 assume !(1 == ~t2_pc~0); 4342385#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4341434#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4341435#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4341628#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4342090#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4341631#L459 assume !(1 == ~t3_pc~0); 4341632#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4342249#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4341253#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4341254#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 4341418#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4341428#L478 assume !(1 == ~t4_pc~0); 4341429#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4342143#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4341368#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4341369#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 4341330#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4341331#L497 assume !(1 == ~t5_pc~0); 4341380#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4349305#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4349304#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4349303#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4349302#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4349301#L516 assume !(1 == ~t6_pc~0); 4349300#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4349299#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4349298#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4349297#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 4349296#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4349245#L535 assume !(1 == ~t7_pc~0); 4349243#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4349241#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4349238#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4349236#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4349233#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4349231#L554 assume !(1 == ~t8_pc~0); 4349229#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4349227#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4342425#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4342426#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4342062#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4342063#L931 assume !(1 == ~M_E~0); 4342419#L931-2 assume !(1 == ~T1_E~0); 4342420#L936-1 assume !(1 == ~T2_E~0); 4342382#L941-1 assume !(1 == ~T3_E~0); 4342383#L946-1 assume !(1 == ~T4_E~0); 4342410#L951-1 assume !(1 == ~T5_E~0); 4342411#L956-1 assume !(1 == ~T6_E~0); 4342406#L961-1 assume !(1 == ~T7_E~0); 4342407#L966-1 assume !(1 == ~T8_E~0); 4342052#L971-1 assume !(1 == ~E_1~0); 4342053#L976-1 assume !(1 == ~E_2~0); 4342011#L981-1 assume !(1 == ~E_3~0); 4342012#L986-1 assume !(1 == ~E_4~0); 4342393#L991-1 assume !(1 == ~E_5~0); 4341519#L996-1 assume !(1 == ~E_6~0); 4342302#L1001-1 assume !(1 == ~E_7~0); 4342303#L1006-1 assume !(1 == ~E_8~0); 4342255#L1011-1 assume { :end_inline_reset_delta_events } true; 4342256#L1272-2 [2023-11-28 20:21:55,325 INFO L750 eck$LassoCheckResult]: Loop: 4342256#L1272-2 assume !false; 4375208#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4375206#L813-1 assume !false; 4375205#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4375204#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4375203#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4375201#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4375200#L696 assume 0 != eval_~tmp~0#1; 4375199#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4375196#L704 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 4375197#L83 assume !(0 == ~m_pc~0); 4397423#L86 assume 1 == ~m_pc~0; 4396067#$Ultimate##322 assume !false; 4375649#L103 ~m_pc~0 := 1;~m_st~0 := 2; 4375648#master_returnLabel#1 assume { :end_inline_master } true; 4375638#L704-2 havoc eval_~tmp_ndt_1~0#1; 4375635#L701-1 assume !(0 == ~t1_st~0); 4375636#L715-1 assume !(0 == ~t2_st~0); 4381928#L729-1 assume !(0 == ~t3_st~0); 4381925#L743-1 assume !(0 == ~t4_st~0); 4381921#L757-1 assume !(0 == ~t5_st~0); 4381918#L771-1 assume !(0 == ~t6_st~0); 4381914#L785-1 assume !(0 == ~t7_st~0); 4381911#L799-1 assume !(0 == ~t8_st~0); 4381908#L813-1 assume !false; 4381906#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4381905#L634 assume !(0 == ~m_st~0); 4381903#L638 assume !(0 == ~t1_st~0); 4381902#L642 assume !(0 == ~t2_st~0); 4381900#L646 assume !(0 == ~t3_st~0); 4381898#L650 assume !(0 == ~t4_st~0); 4381897#L654 assume !(0 == ~t5_st~0); 4381896#L658 assume !(0 == ~t6_st~0); 4381895#L662 assume !(0 == ~t7_st~0); 4381892#L666 assume !(0 == ~t8_st~0);exists_runnable_thread_~__retres1~9#1 := 0; 4381891#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4381890#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4381889#L696 assume !(0 != eval_~tmp~0#1); 4381887#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4381885#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4381884#L838-3 assume !(0 == ~M_E~0); 4381883#L838-5 assume !(0 == ~T1_E~0); 4381882#L843-3 assume !(0 == ~T2_E~0); 4381880#L848-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 4381878#L853-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4381876#L858-3 assume !(0 == ~T5_E~0); 4381875#L863-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4381873#L868-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4381871#L873-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 4381869#L878-3 assume !(0 == ~E_1~0); 4381867#L883-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4381865#L888-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4381862#L893-3 assume 0 == ~E_4~0;~E_4~0 := 1; 4381860#L898-3 assume !(0 == ~E_5~0); 4381858#L903-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4381856#L908-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4381854#L913-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4381852#L918-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4381850#L402-27 assume 1 == ~m_pc~0; 4381848#L403-9 assume !(1 == ~M_E~0); 4381846#L402-29 is_master_triggered_~__retres1~0#1 := 0; 4381844#L413-9 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4381842#is_master_triggered_returnLabel#10 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4381840#L1035-27 assume !(0 != activate_threads_~tmp~1#1); 4381838#L1035-29 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4381835#L421-27 assume !(1 == ~t1_pc~0); 4381833#L421-29 is_transmit1_triggered_~__retres1~1#1 := 0; 4381831#L432-9 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4381828#is_transmit1_triggered_returnLabel#10 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4381826#L1043-27 assume !(0 != activate_threads_~tmp___0~0#1); 4381822#L1043-29 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4381820#L440-27 assume !(1 == ~t2_pc~0); 4381818#L440-29 is_transmit2_triggered_~__retres1~2#1 := 0; 4381816#L451-9 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4381813#is_transmit2_triggered_returnLabel#10 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4381811#L1051-27 assume !(0 != activate_threads_~tmp___1~0#1); 4381808#L1051-29 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4381806#L459-27 assume !(1 == ~t3_pc~0); 4381802#L459-29 is_transmit3_triggered_~__retres1~3#1 := 0; 4381800#L470-9 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4381797#is_transmit3_triggered_returnLabel#10 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4381795#L1059-27 assume !(0 != activate_threads_~tmp___2~0#1); 4381790#L1059-29 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4381788#L478-27 assume !(1 == ~t4_pc~0); 4381786#L478-29 is_transmit4_triggered_~__retres1~4#1 := 0; 4381784#L489-9 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4381781#is_transmit4_triggered_returnLabel#10 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4381779#L1067-27 assume !(0 != activate_threads_~tmp___3~0#1); 4381775#L1067-29 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4381773#L497-27 assume !(1 == ~t5_pc~0); 4381770#L497-29 is_transmit5_triggered_~__retres1~5#1 := 0; 4381768#L508-9 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4381765#is_transmit5_triggered_returnLabel#10 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4381763#L1075-27 assume !(0 != activate_threads_~tmp___4~0#1); 4381761#L1075-29 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4381759#L516-27 assume !(1 == ~t6_pc~0); 4381757#L516-29 is_transmit6_triggered_~__retres1~6#1 := 0; 4381755#L527-9 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4381753#is_transmit6_triggered_returnLabel#10 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4381751#L1083-27 assume !(0 != activate_threads_~tmp___5~0#1); 4381747#L1083-29 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4375630#L535-27 assume !(1 == ~t7_pc~0); 4375626#L535-29 is_transmit7_triggered_~__retres1~7#1 := 0; 4375624#L546-9 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4375622#is_transmit7_triggered_returnLabel#10 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4375620#L1091-27 assume !(0 != activate_threads_~tmp___6~0#1); 4375615#L1091-29 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4375613#L554-27 assume !(1 == ~t8_pc~0); 4375611#L554-29 is_transmit8_triggered_~__retres1~8#1 := 0; 4375609#L565-9 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4375606#is_transmit8_triggered_returnLabel#10 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4375604#L1099-27 assume !(0 != activate_threads_~tmp___7~0#1); 4375602#L1099-29 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4375600#L931-3 assume !(1 == ~M_E~0); 4375598#L931-5 assume !(1 == ~T1_E~0); 4375596#L936-3 assume !(1 == ~T2_E~0); 4375594#L941-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4375592#L946-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4375589#L951-3 assume !(1 == ~T5_E~0); 4375587#L956-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4375585#L961-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4375583#L966-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4375580#L971-3 assume !(1 == ~E_1~0); 4375578#L976-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4375576#L981-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4375574#L986-3 assume 1 == ~E_4~0;~E_4~0 := 2; 4375516#L991-3 assume !(1 == ~E_5~0); 4375514#L996-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4375512#L1001-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4375510#L1006-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4375508#L1011-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4375506#L634-1 assume !(0 == ~m_st~0); 4375504#L638-1 assume 0 == ~t1_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4375495#L681-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4375493#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret24#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret24#1;havoc start_simulation_#t~ret24#1; 4375490#L1291 assume 0 == start_simulation_~tmp~3#1;start_simulation_~kernel_st~0#1 := 4;assume { :begin_inline_fire_time_events } true;~M_E~0 := 1; 4375488#fire_time_events_returnLabel#1 assume { :end_inline_fire_time_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4375486#L402-30 assume 1 == ~m_pc~0; 4375484#L403-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4375482#L413-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4375480#is_master_triggered_returnLabel#11 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4375477#L1035-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4375476#L1035-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4375475#L421-30 assume !(1 == ~t1_pc~0); 4375474#L421-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4375473#L432-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4375471#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4375470#L1043-30 assume !(0 != activate_threads_~tmp___0~0#1); 4375469#L1043-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4375467#L440-30 assume !(1 == ~t2_pc~0); 4375466#L440-32 is_transmit2_triggered_~__retres1~2#1 := 0; 4375465#L451-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4375464#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4375463#L1051-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4375462#L1051-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4375460#L459-30 assume 1 == ~t3_pc~0; 4375458#L460-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4375459#L470-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4375461#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4375452#L1059-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4375450#L1059-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4375448#L478-30 assume !(1 == ~t4_pc~0); 4375446#L478-32 is_transmit4_triggered_~__retres1~4#1 := 0; 4375444#L489-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4375442#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4375440#L1067-30 assume !(0 != activate_threads_~tmp___3~0#1); 4375438#L1067-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4375436#L497-30 assume 1 == ~t5_pc~0; 4375434#L498-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4375435#L508-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4375557#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4375555#L1075-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4375553#L1075-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4375551#L516-30 assume !(1 == ~t6_pc~0); 4375549#L516-32 is_transmit6_triggered_~__retres1~6#1 := 0; 4375547#L527-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4375545#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4375543#L1083-30 assume !(0 != activate_threads_~tmp___5~0#1); 4375541#L1083-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4375539#L535-30 assume 1 == ~t7_pc~0; 4375537#L536-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4375538#L546-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4375570#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4375528#L1091-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4375526#L1091-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4375524#L554-30 assume !(1 == ~t8_pc~0); 4375522#L554-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4375520#L565-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4375518#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4375515#L1099-30 assume !(0 != activate_threads_~tmp___7~0#1); 4375513#L1099-32 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_time_events } true; 4375511#L1132 assume 1 == ~M_E~0;~M_E~0 := 2; 4375509#L1132-2 assume !(1 == ~T1_E~0); 4375507#L1137-1 assume !(1 == ~T2_E~0); 4375505#L1142-1 assume 1 == ~T3_E~0;~T3_E~0 := 2; 4375496#L1147-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4375494#L1152-1 assume !(1 == ~T5_E~0); 4375492#L1157-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 4375489#L1162-1 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4375487#L1167-1 assume !(1 == ~T8_E~0); 4375485#L1172-1 assume !(1 == ~E_1~0); 4375483#L1177-1 assume 1 == ~E_2~0;~E_2~0 := 2; 4375481#L1182-1 assume 1 == ~E_3~0;~E_3~0 := 2; 4375479#L1187-1 assume 1 == ~E_4~0;~E_4~0 := 2; 4375350#L1192-1 assume 1 == ~E_5~0;~E_5~0 := 2; 4375348#L1197-1 assume 1 == ~E_6~0;~E_6~0 := 2; 4375345#L1202-1 assume 1 == ~E_7~0;~E_7~0 := 2; 4375343#L1207-1 assume !(1 == ~E_8~0); 4375341#L1212-1 assume { :end_inline_reset_time_events } true; 4375339#L1291-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4375337#L634-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4375335#L681-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4375333#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret23#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret23#1;havoc stop_simulation_#t~ret23#1; 4375331#L1246 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4375330#L1253 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4375329#stop_simulation_returnLabel#1 start_simulation_#t~ret25#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret23#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret25#1;havoc start_simulation_#t~ret25#1; 4375325#L1304 assume !(0 != start_simulation_~tmp___0~1#1); 4342256#L1272-2 [2023-11-28 20:21:55,326 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:55,326 INFO L85 PathProgramCache]: Analyzing trace with hash -1641920416, now seen corresponding path program 1 times [2023-11-28 20:21:55,326 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:55,326 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1861654466] [2023-11-28 20:21:55,326 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:55,326 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:55,338 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:55,376 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:55,376 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:55,377 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1861654466] [2023-11-28 20:21:55,377 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1861654466] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:55,377 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:55,377 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-28 20:21:55,377 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1742932833] [2023-11-28 20:21:55,377 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:55,378 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:21:55,378 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:55,378 INFO L85 PathProgramCache]: Analyzing trace with hash -1948710470, now seen corresponding path program 1 times [2023-11-28 20:21:55,379 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:55,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [416743084] [2023-11-28 20:21:55,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:55,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:55,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:55,459 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 6 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:55,459 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:55,459 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [416743084] [2023-11-28 20:21:55,459 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [416743084] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:55,459 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:55,460 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:21:55,460 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1775360808] [2023-11-28 20:21:55,460 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:55,460 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-28 20:21:55,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:55,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:21:55,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:21:55,461 INFO L87 Difference]: Start difference. First operand 103316 states and 130763 transitions. cyclomatic complexity: 27527 Second operand has 3 states, 3 states have (on average 35.0) internal successors, (105), 2 states have internal predecessors, (105), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:55,817 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:55,817 INFO L93 Difference]: Finished difference Result 103259 states and 130240 transitions. [2023-11-28 20:21:55,817 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 103259 states and 130240 transitions. [2023-11-28 20:21:56,165 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 97216 [2023-11-28 20:21:56,374 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 103259 states to 103259 states and 130240 transitions. [2023-11-28 20:21:56,375 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 103259 [2023-11-28 20:21:56,425 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 103259 [2023-11-28 20:21:56,425 INFO L73 IsDeterministic]: Start isDeterministic. Operand 103259 states and 130240 transitions. [2023-11-28 20:21:56,465 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:56,466 INFO L218 hiAutomatonCegarLoop]: Abstraction has 103259 states and 130240 transitions. [2023-11-28 20:21:56,518 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 103259 states and 130240 transitions. [2023-11-28 20:21:57,393 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 103259 to 103131. [2023-11-28 20:21:57,453 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 103131 states, 103131 states have (on average 1.2616187179412592) internal successors, (130112), 103130 states have internal predecessors, (130112), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:57,619 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 103131 states to 103131 states and 130112 transitions. [2023-11-28 20:21:57,619 INFO L240 hiAutomatonCegarLoop]: Abstraction has 103131 states and 130112 transitions. [2023-11-28 20:21:57,620 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:21:57,620 INFO L428 stractBuchiCegarLoop]: Abstraction has 103131 states and 130112 transitions. [2023-11-28 20:21:57,620 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2023-11-28 20:21:57,620 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 103131 states and 130112 transitions. [2023-11-28 20:21:57,867 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 97216 [2023-11-28 20:21:57,867 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:21:57,867 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:21:57,867 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:57,867 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:21:57,868 INFO L748 eck$LassoCheckResult]: Stem: 4548062#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4548063#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4548811#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4548812#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4548814#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4548178#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4548179#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4548807#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4548795#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4548256#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4548257#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4548525#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4548526#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4548343#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4548344#L838 assume !(0 == ~M_E~0); 4548537#L838-2 assume !(0 == ~T1_E~0); 4547860#L843-1 assume !(0 == ~T2_E~0); 4547861#L848-1 assume !(0 == ~T3_E~0); 4547981#L853-1 assume !(0 == ~T4_E~0); 4548333#L858-1 assume !(0 == ~T5_E~0); 4547817#L863-1 assume !(0 == ~T6_E~0); 4547818#L868-1 assume !(0 == ~T7_E~0); 4548877#L873-1 assume !(0 == ~T8_E~0); 4548873#L878-1 assume !(0 == ~E_1~0); 4548850#L883-1 assume !(0 == ~E_2~0); 4548851#L888-1 assume !(0 == ~E_3~0); 4548489#L893-1 assume !(0 == ~E_4~0); 4548490#L898-1 assume !(0 == ~E_5~0); 4548897#L903-1 assume !(0 == ~E_6~0); 4548847#L908-1 assume !(0 == ~E_7~0); 4548645#L913-1 assume !(0 == ~E_8~0); 4547873#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4547874#L402 assume !(1 == ~m_pc~0); 4548309#L402-2 is_master_triggered_~__retres1~0#1 := 0; 4548007#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4548008#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4548263#L1035 assume !(0 != activate_threads_~tmp~1#1); 4548264#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4548318#L421 assume !(1 == ~t1_pc~0); 4548837#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4548881#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4547875#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4547876#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4548375#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4548890#L440 assume !(1 == ~t2_pc~0); 4548957#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4548016#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4548017#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4548207#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4548666#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4548215#L459 assume !(1 == ~t3_pc~0); 4548216#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4548833#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4547835#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4547836#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 4548001#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4548011#L478 assume !(1 == ~t4_pc~0); 4548012#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4548724#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4547951#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4547952#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 4547914#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4547915#L497 assume !(1 == ~t5_pc~0); 4547963#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4548443#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4548579#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4548888#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4548889#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4548945#L516 assume !(1 == ~t6_pc~0); 4548946#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4548523#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4548524#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4548056#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 4548057#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4548510#L535 assume !(1 == ~t7_pc~0); 4548511#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4548982#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4548980#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4548977#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4548626#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4548627#L554 assume !(1 == ~t8_pc~0); 4547837#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4547838#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4548657#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4548658#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4548975#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4548974#L931 assume !(1 == ~M_E~0); 4548865#L931-2 assume !(1 == ~T1_E~0); 4548866#L936-1 assume !(1 == ~T2_E~0); 4548955#L941-1 assume !(1 == ~T3_E~0); 4548956#L946-1 assume !(1 == ~T4_E~0); 4548834#L951-1 assume !(1 == ~T5_E~0); 4548071#L956-1 assume !(1 == ~T6_E~0); 4548072#L961-1 assume !(1 == ~T7_E~0); 4548491#L966-1 assume !(1 == ~T8_E~0); 4548492#L971-1 assume !(1 == ~E_1~0); 4548629#L976-1 assume !(1 == ~E_2~0); 4548969#L981-1 assume !(1 == ~E_3~0); 4548968#L986-1 assume !(1 == ~E_4~0); 4548967#L991-1 assume !(1 == ~E_5~0); 4548098#L996-1 assume !(1 == ~E_6~0); 4548884#L1001-1 assume !(1 == ~E_7~0); 4548548#L1006-1 assume !(1 == ~E_8~0); 4548549#L1011-1 assume { :end_inline_reset_delta_events } true; 4548835#L1272-2 assume !false; 4555931#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4555929#L813-1 [2023-11-28 20:21:57,868 INFO L750 eck$LassoCheckResult]: Loop: 4555929#L813-1 assume !false; 4555925#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4555923#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4555921#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4555919#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4555916#L696 assume 0 != eval_~tmp~0#1; 4555914#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4555912#L704 assume !(0 != eval_~tmp_ndt_1~0#1); 4555910#L704-2 havoc eval_~tmp_ndt_1~0#1; 4555908#L701-1 assume !(0 == ~t1_st~0); 4555902#L715-1 assume !(0 == ~t2_st~0); 4555903#L729-1 assume !(0 == ~t3_st~0); 4555950#L743-1 assume !(0 == ~t4_st~0); 4555946#L757-1 assume !(0 == ~t5_st~0); 4555942#L771-1 assume !(0 == ~t6_st~0); 4555938#L785-1 assume !(0 == ~t7_st~0); 4555933#L799-1 assume !(0 == ~t8_st~0); 4555929#L813-1 [2023-11-28 20:21:57,868 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:57,868 INFO L85 PathProgramCache]: Analyzing trace with hash 1664652065, now seen corresponding path program 1 times [2023-11-28 20:21:57,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:57,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [264239070] [2023-11-28 20:21:57,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:57,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:57,876 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:57,877 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:57,882 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:57,901 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:57,902 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:57,902 INFO L85 PathProgramCache]: Analyzing trace with hash -764442210, now seen corresponding path program 2 times [2023-11-28 20:21:57,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:57,902 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1659190725] [2023-11-28 20:21:57,902 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:57,902 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:57,905 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:57,906 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:21:57,907 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:21:57,909 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:21:57,910 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:21:57,910 INFO L85 PathProgramCache]: Analyzing trace with hash -1655989634, now seen corresponding path program 1 times [2023-11-28 20:21:57,910 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:21:57,910 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1839004023] [2023-11-28 20:21:57,910 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:21:57,911 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:21:57,921 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:21:57,950 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:21:57,950 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:21:57,950 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1839004023] [2023-11-28 20:21:57,950 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1839004023] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:21:57,950 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:21:57,951 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:21:57,951 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2124767959] [2023-11-28 20:21:57,951 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:21:58,031 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:21:58,031 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:21:58,031 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:21:58,032 INFO L87 Difference]: Start difference. First operand 103131 states and 130112 transitions. cyclomatic complexity: 27061 Second operand has 3 states, 3 states have (on average 41.0) internal successors, (123), 3 states have internal predecessors, (123), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:21:58,756 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:21:58,756 INFO L93 Difference]: Finished difference Result 190032 states and 238441 transitions. [2023-11-28 20:21:58,756 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 190032 states and 238441 transitions. [2023-11-28 20:21:59,304 INFO L131 ngComponentsAnalysis]: Automaton has 152 accepting balls. 173680 [2023-11-28 20:21:59,616 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 190032 states to 190032 states and 238441 transitions. [2023-11-28 20:21:59,616 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 190032 [2023-11-28 20:21:59,688 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 190032 [2023-11-28 20:21:59,688 INFO L73 IsDeterministic]: Start isDeterministic. Operand 190032 states and 238441 transitions. [2023-11-28 20:21:59,753 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:21:59,753 INFO L218 hiAutomatonCegarLoop]: Abstraction has 190032 states and 238441 transitions. [2023-11-28 20:21:59,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 190032 states and 238441 transitions. [2023-11-28 20:22:01,151 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 190032 to 190032. [2023-11-28 20:22:01,258 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 190032 states, 190032 states have (on average 1.2547413067272881) internal successors, (238441), 190031 states have internal predecessors, (238441), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:02,045 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 190032 states to 190032 states and 238441 transitions. [2023-11-28 20:22:02,046 INFO L240 hiAutomatonCegarLoop]: Abstraction has 190032 states and 238441 transitions. [2023-11-28 20:22:02,046 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:22:02,046 INFO L428 stractBuchiCegarLoop]: Abstraction has 190032 states and 238441 transitions. [2023-11-28 20:22:02,046 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2023-11-28 20:22:02,047 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 190032 states and 238441 transitions. [2023-11-28 20:22:02,459 INFO L131 ngComponentsAnalysis]: Automaton has 152 accepting balls. 173680 [2023-11-28 20:22:02,459 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:22:02,459 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:22:02,460 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:02,460 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:02,460 INFO L748 eck$LassoCheckResult]: Stem: 4841232#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 4841233#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 4841981#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4841982#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4841984#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 4841346#L581-2 assume !(1 == ~t1_i~0);~t1_st~0 := 2; 4841347#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4841976#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4841960#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4841427#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4841428#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4841698#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4841699#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4841519#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4841520#L838 assume !(0 == ~M_E~0); 4841713#L838-2 assume !(0 == ~T1_E~0); 4841031#L843-1 assume !(0 == ~T2_E~0); 4841032#L848-1 assume !(0 == ~T3_E~0); 4841149#L853-1 assume !(0 == ~T4_E~0); 4841507#L858-1 assume !(0 == ~T5_E~0); 4840988#L863-1 assume !(0 == ~T6_E~0); 4840989#L868-1 assume !(0 == ~T7_E~0); 4842053#L873-1 assume !(0 == ~T8_E~0); 4842051#L878-1 assume !(0 == ~E_1~0); 4842026#L883-1 assume !(0 == ~E_2~0); 4842027#L888-1 assume !(0 == ~E_3~0); 4841660#L893-1 assume !(0 == ~E_4~0); 4841661#L898-1 assume !(0 == ~E_5~0); 4842076#L903-1 assume !(0 == ~E_6~0); 4842021#L908-1 assume !(0 == ~E_7~0); 4841824#L913-1 assume !(0 == ~E_8~0); 4841044#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4841045#L402 assume !(1 == ~m_pc~0); 4841482#L402-2 is_master_triggered_~__retres1~0#1 := 0; 4841176#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4841177#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 4841436#L1035 assume !(0 != activate_threads_~tmp~1#1); 4841437#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4841492#L421 assume !(1 == ~t1_pc~0); 4842011#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4842055#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4841046#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4841047#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 4841553#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4842071#L440 assume !(1 == ~t2_pc~0); 4842146#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4841186#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4841187#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4841375#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 4841843#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4841384#L459 assume !(1 == ~t3_pc~0); 4841385#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4842003#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4841006#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4841007#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 4841170#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4841180#L478 assume !(1 == ~t4_pc~0); 4841181#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4841902#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4841120#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4841121#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 4841086#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4841087#L497 assume !(1 == ~t5_pc~0); 4841132#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4849188#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4849187#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4849186#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 4849185#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4849184#L516 assume !(1 == ~t6_pc~0); 4849183#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4849182#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4849181#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4849180#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 4849179#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4849176#L535 assume !(1 == ~t7_pc~0); 4849175#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4849174#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4849173#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4849172#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 4849170#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4849169#L554 assume !(1 == ~t8_pc~0); 4849168#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4849167#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4849166#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4849165#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 4849164#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4849163#L931 assume !(1 == ~M_E~0); 4849162#L931-2 assume !(1 == ~T1_E~0); 4849161#L936-1 assume !(1 == ~T2_E~0); 4849160#L941-1 assume !(1 == ~T3_E~0); 4849159#L946-1 assume !(1 == ~T4_E~0); 4849158#L951-1 assume !(1 == ~T5_E~0); 4849157#L956-1 assume !(1 == ~T6_E~0); 4849156#L961-1 assume !(1 == ~T7_E~0); 4849155#L966-1 assume !(1 == ~T8_E~0); 4849154#L971-1 assume !(1 == ~E_1~0); 4849153#L976-1 assume !(1 == ~E_2~0); 4849152#L981-1 assume !(1 == ~E_3~0); 4849151#L986-1 assume !(1 == ~E_4~0); 4848609#L991-1 assume !(1 == ~E_5~0); 4848607#L996-1 assume !(1 == ~E_6~0); 4848605#L1001-1 assume !(1 == ~E_7~0); 4848603#L1006-1 assume !(1 == ~E_8~0); 4848600#L1011-1 assume { :end_inline_reset_delta_events } true; 4848598#L1272-2 assume !false; 4848456#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4848452#L813-1 [2023-11-28 20:22:02,460 INFO L750 eck$LassoCheckResult]: Loop: 4848452#L813-1 assume !false; 4848450#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 4848448#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 4848446#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 4848443#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4848441#L696 assume 0 != eval_~tmp~0#1; 4848440#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 4848435#L704 assume !(0 != eval_~tmp_ndt_1~0#1); 4848433#L704-2 havoc eval_~tmp_ndt_1~0#1; 4848430#L701-1 assume !(0 == ~t1_st~0); 4848427#L715-1 assume !(0 == ~t2_st~0); 4848422#L729-1 assume !(0 == ~t3_st~0); 4848418#L743-1 assume !(0 == ~t4_st~0); 4848419#L757-1 assume !(0 == ~t5_st~0); 4848466#L771-1 assume !(0 == ~t6_st~0); 4848462#L785-1 assume !(0 == ~t7_st~0); 4848458#L799-1 assume !(0 == ~t8_st~0); 4848452#L813-1 [2023-11-28 20:22:02,460 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:02,460 INFO L85 PathProgramCache]: Analyzing trace with hash 357509667, now seen corresponding path program 1 times [2023-11-28 20:22:02,460 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:02,461 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1059411473] [2023-11-28 20:22:02,461 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:02,461 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:02,468 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:22:02,487 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:22:02,487 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:22:02,487 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1059411473] [2023-11-28 20:22:02,488 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1059411473] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:22:02,488 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:22:02,488 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:22:02,488 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [764440513] [2023-11-28 20:22:02,488 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:22:02,488 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-28 20:22:02,489 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:02,489 INFO L85 PathProgramCache]: Analyzing trace with hash -764442210, now seen corresponding path program 3 times [2023-11-28 20:22:02,489 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:02,489 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1656941702] [2023-11-28 20:22:02,489 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:02,489 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:02,492 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:02,492 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:02,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:02,496 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:02,575 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:22:02,575 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:22:02,575 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:22:02,575 INFO L87 Difference]: Start difference. First operand 190032 states and 238441 transitions. cyclomatic complexity: 48561 Second operand has 3 states, 3 states have (on average 35.333333333333336) internal successors, (106), 3 states have internal predecessors, (106), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:02,855 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:22:02,855 INFO L93 Difference]: Finished difference Result 126067 states and 157919 transitions. [2023-11-28 20:22:02,855 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126067 states and 157919 transitions. [2023-11-28 20:22:03,629 INFO L131 ngComponentsAnalysis]: Automaton has 88 accepting balls. 117336 [2023-11-28 20:22:03,858 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126067 states to 126067 states and 157919 transitions. [2023-11-28 20:22:03,859 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126067 [2023-11-28 20:22:03,921 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126067 [2023-11-28 20:22:03,921 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126067 states and 157919 transitions. [2023-11-28 20:22:03,968 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:22:03,968 INFO L218 hiAutomatonCegarLoop]: Abstraction has 126067 states and 157919 transitions. [2023-11-28 20:22:04,036 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126067 states and 157919 transitions. [2023-11-28 20:22:05,044 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126067 to 126067. [2023-11-28 20:22:05,114 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 126067 states, 126067 states have (on average 1.2526593002133786) internal successors, (157919), 126066 states have internal predecessors, (157919), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:05,314 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 126067 states to 126067 states and 157919 transitions. [2023-11-28 20:22:05,314 INFO L240 hiAutomatonCegarLoop]: Abstraction has 126067 states and 157919 transitions. [2023-11-28 20:22:05,315 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:22:05,315 INFO L428 stractBuchiCegarLoop]: Abstraction has 126067 states and 157919 transitions. [2023-11-28 20:22:05,315 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2023-11-28 20:22:05,315 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 126067 states and 157919 transitions. [2023-11-28 20:22:05,577 INFO L131 ngComponentsAnalysis]: Automaton has 88 accepting balls. 117336 [2023-11-28 20:22:05,577 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:22:05,577 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:22:05,578 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:05,578 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:05,578 INFO L748 eck$LassoCheckResult]: Stem: 5157335#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 5157336#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5158091#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5158092#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5158094#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 5157454#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5157455#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5158087#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5158073#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5157537#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5157538#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5157799#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5157800#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5157625#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5157626#L838 assume !(0 == ~M_E~0); 5157813#L838-2 assume !(0 == ~T1_E~0); 5157135#L843-1 assume !(0 == ~T2_E~0); 5157136#L848-1 assume !(0 == ~T3_E~0); 5157254#L853-1 assume !(0 == ~T4_E~0); 5157612#L858-1 assume !(0 == ~T5_E~0); 5157091#L863-1 assume !(0 == ~T6_E~0); 5157092#L868-1 assume !(0 == ~T7_E~0); 5158155#L873-1 assume !(0 == ~T8_E~0); 5158152#L878-1 assume !(0 == ~E_1~0); 5158127#L883-1 assume !(0 == ~E_2~0); 5158128#L888-1 assume !(0 == ~E_3~0); 5157768#L893-1 assume !(0 == ~E_4~0); 5157769#L898-1 assume !(0 == ~E_5~0); 5158182#L903-1 assume !(0 == ~E_6~0); 5158125#L908-1 assume !(0 == ~E_7~0); 5157925#L913-1 assume !(0 == ~E_8~0); 5157147#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5157148#L402 assume !(1 == ~m_pc~0); 5157590#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5157280#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5157281#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5157544#L1035 assume !(0 != activate_threads_~tmp~1#1); 5157545#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5157600#L421 assume !(1 == ~t1_pc~0); 5158116#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5158157#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5157150#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5157151#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 5157656#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5158173#L440 assume !(1 == ~t2_pc~0); 5158243#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5157290#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5157291#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5157483#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 5157945#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5157487#L459 assume !(1 == ~t3_pc~0); 5157488#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5158111#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5157111#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5157112#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 5157274#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5157284#L478 assume !(1 == ~t4_pc~0); 5157285#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5158007#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5157225#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5157226#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5157188#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5157189#L497 assume !(1 == ~t5_pc~0); 5157237#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5157722#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5157860#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5158174#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 5158175#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5158228#L516 assume !(1 == ~t6_pc~0); 5158229#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5157797#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5157798#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5157329#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5157330#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5157785#L535 assume !(1 == ~t7_pc~0); 5157786#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5158269#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5158267#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5158264#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 5157905#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5157906#L554 assume !(1 == ~t8_pc~0); 5157113#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5157114#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5158262#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5157416#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5157417#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5157101#L931 assume !(1 == ~M_E~0); 5157102#L931-2 assume !(1 == ~T1_E~0); 5158195#L936-1 assume !(1 == ~T2_E~0); 5158196#L941-1 assume !(1 == ~T3_E~0); 5157598#L946-1 assume !(1 == ~T4_E~0); 5157599#L951-1 assume !(1 == ~T5_E~0); 5158259#L956-1 assume !(1 == ~T6_E~0); 5158230#L961-1 assume !(1 == ~T7_E~0); 5158231#L966-1 assume !(1 == ~T8_E~0); 5158258#L971-1 assume !(1 == ~E_1~0); 5158208#L976-1 assume !(1 == ~E_2~0); 5157864#L981-1 assume !(1 == ~E_3~0); 5157603#L986-1 assume !(1 == ~E_4~0); 5157604#L991-1 assume !(1 == ~E_5~0); 5157371#L996-1 assume !(1 == ~E_6~0); 5158166#L1001-1 assume !(1 == ~E_7~0); 5157826#L1006-1 assume !(1 == ~E_8~0); 5157827#L1011-1 assume { :end_inline_reset_delta_events } true; 5158113#L1272-2 assume !false; 5186963#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5186961#L813-1 [2023-11-28 20:22:05,578 INFO L750 eck$LassoCheckResult]: Loop: 5186961#L813-1 assume !false; 5186959#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5186956#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5186954#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5186952#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5186950#L696 assume 0 != eval_~tmp~0#1; 5186948#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5186943#L704 assume !(0 != eval_~tmp_ndt_1~0#1); 5186941#L704-2 havoc eval_~tmp_ndt_1~0#1; 5186939#L701-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5186936#L718 assume !(0 != eval_~tmp_ndt_2~0#1); 5186937#L718-2 havoc eval_~tmp_ndt_2~0#1; 5186989#L715-1 assume !(0 == ~t2_st~0); 5186986#L729-1 assume !(0 == ~t3_st~0); 5186981#L743-1 assume !(0 == ~t4_st~0); 5186977#L757-1 assume !(0 == ~t5_st~0); 5186973#L771-1 assume !(0 == ~t6_st~0); 5186969#L785-1 assume !(0 == ~t7_st~0); 5186965#L799-1 assume !(0 == ~t8_st~0); 5186961#L813-1 [2023-11-28 20:22:05,579 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:05,579 INFO L85 PathProgramCache]: Analyzing trace with hash 1664652065, now seen corresponding path program 2 times [2023-11-28 20:22:05,579 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:05,579 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585036843] [2023-11-28 20:22:05,579 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:05,579 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:05,589 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:05,589 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:05,594 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:05,605 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:05,605 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:05,605 INFO L85 PathProgramCache]: Analyzing trace with hash -575001325, now seen corresponding path program 1 times [2023-11-28 20:22:05,606 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:05,606 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905358753] [2023-11-28 20:22:05,606 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:05,606 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:05,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:05,609 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:05,610 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:05,612 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:05,613 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:05,613 INFO L85 PathProgramCache]: Analyzing trace with hash 1641383411, now seen corresponding path program 1 times [2023-11-28 20:22:05,613 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:05,613 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2063388846] [2023-11-28 20:22:05,613 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:05,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:05,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:22:05,645 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:22:05,645 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:22:05,645 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2063388846] [2023-11-28 20:22:05,645 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2063388846] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:22:05,646 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:22:05,646 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:22:05,646 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1489712950] [2023-11-28 20:22:05,646 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:22:05,733 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:22:05,733 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:22:05,733 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:22:05,733 INFO L87 Difference]: Start difference. First operand 126067 states and 157919 transitions. cyclomatic complexity: 31940 Second operand has 3 states, 3 states have (on average 41.666666666666664) internal successors, (125), 3 states have internal predecessors, (125), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:06,120 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:22:06,120 INFO L93 Difference]: Finished difference Result 171543 states and 214355 transitions. [2023-11-28 20:22:06,120 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 171543 states and 214355 transitions. [2023-11-28 20:22:07,000 INFO L131 ngComponentsAnalysis]: Automaton has 92 accepting balls. 158628 [2023-11-28 20:22:07,237 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 171543 states to 171543 states and 214355 transitions. [2023-11-28 20:22:07,237 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 171543 [2023-11-28 20:22:07,290 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 171543 [2023-11-28 20:22:07,290 INFO L73 IsDeterministic]: Start isDeterministic. Operand 171543 states and 214355 transitions. [2023-11-28 20:22:07,337 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:22:07,337 INFO L218 hiAutomatonCegarLoop]: Abstraction has 171543 states and 214355 transitions. [2023-11-28 20:22:07,406 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 171543 states and 214355 transitions. [2023-11-28 20:22:08,558 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 171543 to 164311. [2023-11-28 20:22:08,650 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 164311 states, 164311 states have (on average 1.2508170481586747) internal successors, (205523), 164310 states have internal predecessors, (205523), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:08,914 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 164311 states to 164311 states and 205523 transitions. [2023-11-28 20:22:08,914 INFO L240 hiAutomatonCegarLoop]: Abstraction has 164311 states and 205523 transitions. [2023-11-28 20:22:08,914 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:22:08,914 INFO L428 stractBuchiCegarLoop]: Abstraction has 164311 states and 205523 transitions. [2023-11-28 20:22:08,915 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2023-11-28 20:22:08,915 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 164311 states and 205523 transitions. [2023-11-28 20:22:09,297 INFO L131 ngComponentsAnalysis]: Automaton has 92 accepting balls. 151396 [2023-11-28 20:22:09,297 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:22:09,297 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:22:09,298 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:09,298 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:09,299 INFO L748 eck$LassoCheckResult]: Stem: 5454956#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 5454957#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5455730#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5455731#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5455733#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 5455074#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5455075#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5455725#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5455712#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5455156#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5455157#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5455430#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5455431#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5455248#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5455249#L838 assume !(0 == ~M_E~0); 5455442#L838-2 assume !(0 == ~T1_E~0); 5454754#L843-1 assume !(0 == ~T2_E~0); 5454755#L848-1 assume !(0 == ~T3_E~0); 5454875#L853-1 assume !(0 == ~T4_E~0); 5455235#L858-1 assume !(0 == ~T5_E~0); 5454709#L863-1 assume !(0 == ~T6_E~0); 5454710#L868-1 assume !(0 == ~T7_E~0); 5455802#L873-1 assume !(0 == ~T8_E~0); 5455796#L878-1 assume !(0 == ~E_1~0); 5455769#L883-1 assume !(0 == ~E_2~0); 5455770#L888-1 assume !(0 == ~E_3~0); 5455393#L893-1 assume !(0 == ~E_4~0); 5455394#L898-1 assume !(0 == ~E_5~0); 5455832#L903-1 assume !(0 == ~E_6~0); 5455767#L908-1 assume !(0 == ~E_7~0); 5455552#L913-1 assume !(0 == ~E_8~0); 5454766#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5454767#L402 assume !(1 == ~m_pc~0); 5455210#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5454901#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5454902#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5455163#L1035 assume !(0 != activate_threads_~tmp~1#1); 5455164#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5455224#L421 assume !(1 == ~t1_pc~0); 5455760#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5455804#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5454769#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5454770#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 5455280#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5455823#L440 assume !(1 == ~t2_pc~0); 5455916#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5454910#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5454911#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5455102#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 5455576#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5455107#L459 assume !(1 == ~t3_pc~0); 5455108#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5455752#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5454729#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5454730#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 5454895#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5454905#L478 assume !(1 == ~t4_pc~0); 5454906#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5455639#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5454845#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5454846#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5454806#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5454807#L497 assume !(1 == ~t5_pc~0); 5454857#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5455349#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5455487#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5455824#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 5455825#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5455899#L516 assume !(1 == ~t6_pc~0); 5455900#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5455428#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5455429#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5454949#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5454950#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5455416#L535 assume !(1 == ~t7_pc~0); 5455417#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5455945#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5455943#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5455940#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 5455532#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5455533#L554 assume !(1 == ~t8_pc~0); 5454731#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5454732#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5455938#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5455037#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5455038#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5454719#L931 assume !(1 == ~M_E~0); 5454720#L931-2 assume !(1 == ~T1_E~0); 5455850#L936-1 assume !(1 == ~T2_E~0); 5455851#L941-1 assume !(1 == ~T3_E~0); 5455222#L946-1 assume !(1 == ~T4_E~0); 5455223#L951-1 assume !(1 == ~T5_E~0); 5455935#L956-1 assume !(1 == ~T6_E~0); 5455901#L961-1 assume !(1 == ~T7_E~0); 5455902#L966-1 assume !(1 == ~T8_E~0); 5455934#L971-1 assume !(1 == ~E_1~0); 5455871#L976-1 assume !(1 == ~E_2~0); 5455493#L981-1 assume !(1 == ~E_3~0); 5455227#L986-1 assume !(1 == ~E_4~0); 5455228#L991-1 assume !(1 == ~E_5~0); 5454992#L996-1 assume !(1 == ~E_6~0); 5455814#L1001-1 assume !(1 == ~E_7~0); 5455454#L1006-1 assume !(1 == ~E_8~0); 5455455#L1011-1 assume { :end_inline_reset_delta_events } true; 5455757#L1272-2 assume !false; 5495370#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5495368#L813-1 [2023-11-28 20:22:09,299 INFO L750 eck$LassoCheckResult]: Loop: 5495368#L813-1 assume !false; 5495366#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5495364#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5495362#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5495360#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5495358#L696 assume 0 != eval_~tmp~0#1; 5495356#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5495352#L704 assume !(0 != eval_~tmp_ndt_1~0#1); 5495353#L704-2 havoc eval_~tmp_ndt_1~0#1; 5497103#L701-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5497100#L718 assume !(0 != eval_~tmp_ndt_2~0#1); 5497098#L718-2 havoc eval_~tmp_ndt_2~0#1; 5497096#L715-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5497093#L732 assume !(0 != eval_~tmp_ndt_3~0#1); 5497091#L732-2 havoc eval_~tmp_ndt_3~0#1; 5497088#L729-1 assume !(0 == ~t3_st~0); 5497084#L743-1 assume !(0 == ~t4_st~0); 5497085#L757-1 assume !(0 == ~t5_st~0); 5497246#L771-1 assume !(0 == ~t6_st~0); 5495376#L785-1 assume !(0 == ~t7_st~0); 5495372#L799-1 assume !(0 == ~t8_st~0); 5495368#L813-1 [2023-11-28 20:22:09,299 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:09,299 INFO L85 PathProgramCache]: Analyzing trace with hash 1664652065, now seen corresponding path program 3 times [2023-11-28 20:22:09,299 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:09,299 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1775115584] [2023-11-28 20:22:09,299 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:09,299 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:09,307 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:09,307 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:09,314 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:09,332 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:09,332 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:09,332 INFO L85 PathProgramCache]: Analyzing trace with hash 908169886, now seen corresponding path program 1 times [2023-11-28 20:22:09,332 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:09,332 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [328909563] [2023-11-28 20:22:09,332 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:09,332 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:09,335 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:09,335 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:09,336 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:09,338 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:09,338 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:09,338 INFO L85 PathProgramCache]: Analyzing trace with hash 550122366, now seen corresponding path program 1 times [2023-11-28 20:22:09,339 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:09,339 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [700665470] [2023-11-28 20:22:09,339 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:09,339 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:09,346 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:22:09,367 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:22:09,367 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:22:09,367 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [700665470] [2023-11-28 20:22:09,367 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [700665470] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:22:09,367 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:22:09,367 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:22:09,367 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1736368282] [2023-11-28 20:22:09,368 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:22:09,461 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:22:09,461 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:22:09,461 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:22:09,461 INFO L87 Difference]: Start difference. First operand 164311 states and 205523 transitions. cyclomatic complexity: 41304 Second operand has 3 states, 3 states have (on average 42.333333333333336) internal successors, (127), 3 states have internal predecessors, (127), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:10,535 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:22:10,535 INFO L93 Difference]: Finished difference Result 315315 states and 393567 transitions. [2023-11-28 20:22:10,535 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 315315 states and 393567 transitions. [2023-11-28 20:22:11,946 INFO L131 ngComponentsAnalysis]: Automaton has 92 accepting balls. 289640 [2023-11-28 20:22:12,526 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 315315 states to 315315 states and 393567 transitions. [2023-11-28 20:22:12,526 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 315315 [2023-11-28 20:22:12,666 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 315315 [2023-11-28 20:22:12,667 INFO L73 IsDeterministic]: Start isDeterministic. Operand 315315 states and 393567 transitions. [2023-11-28 20:22:12,776 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:22:12,776 INFO L218 hiAutomatonCegarLoop]: Abstraction has 315315 states and 393567 transitions. [2023-11-28 20:22:12,932 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 315315 states and 393567 transitions. [2023-11-28 20:22:15,105 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 315315 to 298947. [2023-11-28 20:22:15,241 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 298947 states, 298947 states have (on average 1.2505728440158288) internal successors, (373855), 298946 states have internal predecessors, (373855), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:15,763 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 298947 states to 298947 states and 373855 transitions. [2023-11-28 20:22:15,763 INFO L240 hiAutomatonCegarLoop]: Abstraction has 298947 states and 373855 transitions. [2023-11-28 20:22:15,764 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:22:15,764 INFO L428 stractBuchiCegarLoop]: Abstraction has 298947 states and 373855 transitions. [2023-11-28 20:22:15,764 INFO L335 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2023-11-28 20:22:15,764 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 298947 states and 373855 transitions. [2023-11-28 20:22:17,100 INFO L131 ngComponentsAnalysis]: Automaton has 92 accepting balls. 273272 [2023-11-28 20:22:17,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:22:17,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:22:17,101 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:17,101 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:17,102 INFO L748 eck$LassoCheckResult]: Stem: 5934591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 5934592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 5935374#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5935375#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5935377#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 5934715#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5934716#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5935368#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5935352#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5934797#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5934798#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5935072#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5935073#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5934885#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5934886#L838 assume !(0 == ~M_E~0); 5935086#L838-2 assume !(0 == ~T1_E~0); 5934387#L843-1 assume !(0 == ~T2_E~0); 5934388#L848-1 assume !(0 == ~T3_E~0); 5934507#L853-1 assume !(0 == ~T4_E~0); 5934874#L858-1 assume !(0 == ~T5_E~0); 5934345#L863-1 assume !(0 == ~T6_E~0); 5934346#L868-1 assume !(0 == ~T7_E~0); 5935455#L873-1 assume !(0 == ~T8_E~0); 5935453#L878-1 assume !(0 == ~E_1~0); 5935420#L883-1 assume !(0 == ~E_2~0); 5935421#L888-1 assume !(0 == ~E_3~0); 5935035#L893-1 assume !(0 == ~E_4~0); 5935036#L898-1 assume !(0 == ~E_5~0); 5935479#L903-1 assume !(0 == ~E_6~0); 5935415#L908-1 assume !(0 == ~E_7~0); 5935199#L913-1 assume !(0 == ~E_8~0); 5934400#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5934401#L402 assume !(1 == ~m_pc~0); 5934848#L402-2 is_master_triggered_~__retres1~0#1 := 0; 5934533#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5934534#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 5934804#L1035 assume !(0 != activate_threads_~tmp~1#1); 5934805#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5934858#L421 assume !(1 == ~t1_pc~0); 5935405#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5935457#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5934402#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5934403#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 5934919#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5935468#L440 assume !(1 == ~t2_pc~0); 5935567#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5934543#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5934544#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5934745#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 5935220#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5934755#L459 assume !(1 == ~t3_pc~0); 5934756#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5935397#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5934363#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5934364#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 5934527#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5934537#L478 assume !(1 == ~t4_pc~0); 5934538#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5935282#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5934477#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5934478#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 5934441#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5934442#L497 assume !(1 == ~t5_pc~0); 5934489#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5934989#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5935133#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5935469#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 5935470#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5935553#L516 assume !(1 == ~t6_pc~0); 5935554#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5935070#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5935071#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5934585#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 5934586#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5935057#L535 assume !(1 == ~t7_pc~0); 5935058#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5935603#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5935601#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5935598#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 5935178#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5935179#L554 assume !(1 == ~t8_pc~0); 5934365#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5934366#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5935211#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5935212#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 5935596#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5935595#L931 assume !(1 == ~M_E~0); 5935440#L931-2 assume !(1 == ~T1_E~0); 5935441#L936-1 assume !(1 == ~T2_E~0); 5935565#L941-1 assume !(1 == ~T3_E~0); 5935566#L946-1 assume !(1 == ~T4_E~0); 5935401#L951-1 assume !(1 == ~T5_E~0); 5934600#L956-1 assume !(1 == ~T6_E~0); 5934601#L961-1 assume !(1 == ~T7_E~0); 5935037#L966-1 assume !(1 == ~T8_E~0); 5935038#L971-1 assume !(1 == ~E_1~0); 5935181#L976-1 assume !(1 == ~E_2~0); 5935590#L981-1 assume !(1 == ~E_3~0); 5935589#L986-1 assume !(1 == ~E_4~0); 5935588#L991-1 assume !(1 == ~E_5~0); 5934628#L996-1 assume !(1 == ~E_6~0); 5935462#L1001-1 assume !(1 == ~E_7~0); 5935099#L1006-1 assume !(1 == ~E_8~0); 5935100#L1011-1 assume { :end_inline_reset_delta_events } true; 5935402#L1272-2 assume !false; 5979635#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5979633#L813-1 [2023-11-28 20:22:17,102 INFO L750 eck$LassoCheckResult]: Loop: 5979633#L813-1 assume !false; 5979630#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 5979628#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 5979626#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 5979624#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5979622#L696 assume 0 != eval_~tmp~0#1; 5979620#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5979618#L704 assume !(0 != eval_~tmp_ndt_1~0#1); 5979617#L704-2 havoc eval_~tmp_ndt_1~0#1; 5979615#L701-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 5979614#L718 assume !(0 != eval_~tmp_ndt_2~0#1); 5979613#L718-2 havoc eval_~tmp_ndt_2~0#1; 5979611#L715-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 5979608#L732 assume !(0 != eval_~tmp_ndt_3~0#1); 5979609#L732-2 havoc eval_~tmp_ndt_3~0#1; 6010563#L729-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 5974202#L746 assume !(0 != eval_~tmp_ndt_4~0#1); 5974521#L746-2 havoc eval_~tmp_ndt_4~0#1; 5979653#L743-1 assume !(0 == ~t4_st~0); 5979649#L757-1 assume !(0 == ~t5_st~0); 5979645#L771-1 assume !(0 == ~t6_st~0); 5979641#L785-1 assume !(0 == ~t7_st~0); 5979637#L799-1 assume !(0 == ~t8_st~0); 5979633#L813-1 [2023-11-28 20:22:17,102 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:17,103 INFO L85 PathProgramCache]: Analyzing trace with hash 1664652065, now seen corresponding path program 4 times [2023-11-28 20:22:17,103 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:17,103 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [395886295] [2023-11-28 20:22:17,103 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:17,103 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:17,113 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:17,113 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:17,118 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:17,128 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:17,129 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:17,129 INFO L85 PathProgramCache]: Analyzing trace with hash -807652525, now seen corresponding path program 1 times [2023-11-28 20:22:17,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:17,129 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [628205792] [2023-11-28 20:22:17,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:17,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:17,131 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:17,131 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:17,133 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:17,134 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:17,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:17,134 INFO L85 PathProgramCache]: Analyzing trace with hash -1293935565, now seen corresponding path program 1 times [2023-11-28 20:22:17,135 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:17,135 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658378604] [2023-11-28 20:22:17,135 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:17,135 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:17,144 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:22:17,177 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:22:17,178 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:22:17,178 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658378604] [2023-11-28 20:22:17,178 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658378604] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:22:17,178 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:22:17,178 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:22:17,179 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56940490] [2023-11-28 20:22:17,179 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:22:17,276 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:22:17,277 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:22:17,277 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:22:17,277 INFO L87 Difference]: Start difference. First operand 298947 states and 373855 transitions. cyclomatic complexity: 75000 Second operand has 3 states, 3 states have (on average 43.0) internal successors, (129), 3 states have internal predecessors, (129), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:18,295 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:22:18,296 INFO L93 Difference]: Finished difference Result 414971 states and 518535 transitions. [2023-11-28 20:22:18,296 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 414971 states and 518535 transitions. [2023-11-28 20:22:20,171 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 376536 [2023-11-28 20:22:21,402 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 414971 states to 414971 states and 518535 transitions. [2023-11-28 20:22:21,402 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 414971 [2023-11-28 20:22:21,523 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 414971 [2023-11-28 20:22:21,523 INFO L73 IsDeterministic]: Start isDeterministic. Operand 414971 states and 518535 transitions. [2023-11-28 20:22:21,627 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:22:21,627 INFO L218 hiAutomatonCegarLoop]: Abstraction has 414971 states and 518535 transitions. [2023-11-28 20:22:21,787 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 414971 states and 518535 transitions. [2023-11-28 20:22:24,428 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 414971 to 407931. [2023-11-28 20:22:24,657 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 407931 states, 407931 states have (on average 1.2504247041779124) internal successors, (510087), 407930 states have internal predecessors, (510087), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:25,926 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 407931 states to 407931 states and 510087 transitions. [2023-11-28 20:22:25,926 INFO L240 hiAutomatonCegarLoop]: Abstraction has 407931 states and 510087 transitions. [2023-11-28 20:22:25,927 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:22:25,928 INFO L428 stractBuchiCegarLoop]: Abstraction has 407931 states and 510087 transitions. [2023-11-28 20:22:25,928 INFO L335 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2023-11-28 20:22:25,928 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 407931 states and 510087 transitions. [2023-11-28 20:22:26,768 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 369496 [2023-11-28 20:22:26,768 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:22:26,768 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:22:26,769 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:26,769 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:26,769 INFO L748 eck$LassoCheckResult]: Stem: 6648510#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 6648511#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 6649322#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6649323#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6649325#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 6648628#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6648629#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6649314#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6649292#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6648710#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6648711#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6648993#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6648994#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6648807#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6648808#L838 assume !(0 == ~M_E~0); 6649009#L838-2 assume !(0 == ~T1_E~0); 6648313#L843-1 assume !(0 == ~T2_E~0); 6648314#L848-1 assume !(0 == ~T3_E~0); 6648430#L853-1 assume !(0 == ~T4_E~0); 6648795#L858-1 assume !(0 == ~T5_E~0); 6648271#L863-1 assume !(0 == ~T6_E~0); 6648272#L868-1 assume !(0 == ~T7_E~0); 6649404#L873-1 assume !(0 == ~T8_E~0); 6649399#L878-1 assume !(0 == ~E_1~0); 6649370#L883-1 assume !(0 == ~E_2~0); 6649371#L888-1 assume !(0 == ~E_3~0); 6648957#L893-1 assume !(0 == ~E_4~0); 6648958#L898-1 assume !(0 == ~E_5~0); 6649430#L903-1 assume !(0 == ~E_6~0); 6649364#L908-1 assume !(0 == ~E_7~0); 6649126#L913-1 assume !(0 == ~E_8~0); 6648326#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6648327#L402 assume !(1 == ~m_pc~0); 6648766#L402-2 is_master_triggered_~__retres1~0#1 := 0; 6648456#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6648457#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 6648718#L1035 assume !(0 != activate_threads_~tmp~1#1); 6648719#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6648779#L421 assume !(1 == ~t1_pc~0); 6649353#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6649408#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6648328#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 6648329#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 6648842#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6649418#L440 assume !(1 == ~t2_pc~0); 6649519#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6648465#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6648466#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6648657#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 6649147#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6648665#L459 assume !(1 == ~t3_pc~0); 6648666#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6649345#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6648289#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6648290#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 6648450#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6648460#L478 assume !(1 == ~t4_pc~0); 6648461#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6649214#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6648401#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6648402#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 6648366#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6648367#L497 assume !(1 == ~t5_pc~0); 6648413#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6648910#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6649058#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6649419#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 6649420#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6649502#L516 assume !(1 == ~t6_pc~0); 6649503#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6648991#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6648992#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6648504#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 6648505#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6648979#L535 assume !(1 == ~t7_pc~0); 6648980#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6649558#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6649556#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6649553#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 6649107#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6649108#L554 assume !(1 == ~t8_pc~0); 6648291#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6648292#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6649138#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6649139#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 6649551#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6649550#L931 assume !(1 == ~M_E~0); 6649383#L931-2 assume !(1 == ~T1_E~0); 6649384#L936-1 assume !(1 == ~T2_E~0); 6649517#L941-1 assume !(1 == ~T3_E~0); 6649518#L946-1 assume !(1 == ~T4_E~0); 6649349#L951-1 assume !(1 == ~T5_E~0); 6648519#L956-1 assume !(1 == ~T6_E~0); 6648520#L961-1 assume !(1 == ~T7_E~0); 6648959#L966-1 assume !(1 == ~T8_E~0); 6648960#L971-1 assume !(1 == ~E_1~0); 6649110#L976-1 assume !(1 == ~E_2~0); 6649545#L981-1 assume !(1 == ~E_3~0); 6649544#L986-1 assume !(1 == ~E_4~0); 6649543#L991-1 assume !(1 == ~E_5~0); 6648547#L996-1 assume !(1 == ~E_6~0); 6649414#L1001-1 assume !(1 == ~E_7~0); 6649021#L1006-1 assume !(1 == ~E_8~0); 6649022#L1011-1 assume { :end_inline_reset_delta_events } true; 6649350#L1272-2 assume !false; 6724646#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6724644#L813-1 [2023-11-28 20:22:26,769 INFO L750 eck$LassoCheckResult]: Loop: 6724644#L813-1 assume !false; 6724642#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 6724641#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 6724639#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 6724638#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6724637#L696 assume 0 != eval_~tmp~0#1; 6724636#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 6724634#L704 assume !(0 != eval_~tmp_ndt_1~0#1); 6724633#L704-2 havoc eval_~tmp_ndt_1~0#1; 6724631#L701-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 6724628#L718 assume !(0 != eval_~tmp_ndt_2~0#1); 6724626#L718-2 havoc eval_~tmp_ndt_2~0#1; 6724623#L715-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 6724620#L732 assume !(0 != eval_~tmp_ndt_3~0#1); 6724619#L732-2 havoc eval_~tmp_ndt_3~0#1; 6724618#L729-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 6723400#L746 assume !(0 != eval_~tmp_ndt_4~0#1); 6724616#L746-2 havoc eval_~tmp_ndt_4~0#1; 6724670#L743-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 6724667#L760 assume !(0 != eval_~tmp_ndt_5~0#1); 6724665#L760-2 havoc eval_~tmp_ndt_5~0#1; 6724661#L757-1 assume !(0 == ~t5_st~0); 6724657#L771-1 assume !(0 == ~t6_st~0); 6724653#L785-1 assume !(0 == ~t7_st~0); 6724648#L799-1 assume !(0 == ~t8_st~0); 6724644#L813-1 [2023-11-28 20:22:26,769 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:26,769 INFO L85 PathProgramCache]: Analyzing trace with hash 1664652065, now seen corresponding path program 5 times [2023-11-28 20:22:26,770 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:26,770 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1823025340] [2023-11-28 20:22:26,770 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:26,770 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:26,781 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:26,781 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:26,788 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:26,801 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:26,802 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:26,802 INFO L85 PathProgramCache]: Analyzing trace with hash 1873814430, now seen corresponding path program 1 times [2023-11-28 20:22:26,802 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:26,802 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1345796640] [2023-11-28 20:22:26,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:26,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:26,806 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:26,806 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:26,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:26,809 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:26,810 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:26,810 INFO L85 PathProgramCache]: Analyzing trace with hash -1587719042, now seen corresponding path program 1 times [2023-11-28 20:22:26,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:26,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221541353] [2023-11-28 20:22:26,810 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:26,810 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:26,820 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:22:26,849 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:22:26,849 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:22:26,849 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221541353] [2023-11-28 20:22:26,849 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221541353] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:22:26,849 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:22:26,850 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:22:26,850 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1242152422] [2023-11-28 20:22:26,850 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:22:26,940 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:22:26,940 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:22:26,940 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:22:26,941 INFO L87 Difference]: Start difference. First operand 407931 states and 510087 transitions. cyclomatic complexity: 102252 Second operand has 3 states, 3 states have (on average 43.666666666666664) internal successors, (131), 3 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:29,619 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:22:29,620 INFO L93 Difference]: Finished difference Result 747187 states and 933391 transitions. [2023-11-28 20:22:29,620 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 747187 states and 933391 transitions. [2023-11-28 20:22:32,462 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 670472 [2023-11-28 20:22:34,441 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 747187 states to 747187 states and 933391 transitions. [2023-11-28 20:22:34,442 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 747187 [2023-11-28 20:22:34,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 747187 [2023-11-28 20:22:34,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 747187 states and 933391 transitions. [2023-11-28 20:22:35,354 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:22:35,354 INFO L218 hiAutomatonCegarLoop]: Abstraction has 747187 states and 933391 transitions. [2023-11-28 20:22:35,727 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 747187 states and 933391 transitions. [2023-11-28 20:22:40,227 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 747187 to 732307. [2023-11-28 20:22:41,239 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 732307 states, 732307 states have (on average 1.2502065390608037) internal successors, (915535), 732306 states have internal predecessors, (915535), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:42,724 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 732307 states to 732307 states and 915535 transitions. [2023-11-28 20:22:42,724 INFO L240 hiAutomatonCegarLoop]: Abstraction has 732307 states and 915535 transitions. [2023-11-28 20:22:42,725 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:22:42,725 INFO L428 stractBuchiCegarLoop]: Abstraction has 732307 states and 915535 transitions. [2023-11-28 20:22:42,725 INFO L335 stractBuchiCegarLoop]: ======== Iteration 42 ============ [2023-11-28 20:22:42,725 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 732307 states and 915535 transitions. [2023-11-28 20:22:45,563 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 655592 [2023-11-28 20:22:45,563 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:22:45,563 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:22:45,564 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:45,564 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:22:45,564 INFO L748 eck$LassoCheckResult]: Stem: 7803641#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 7803642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 7804419#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7804420#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7804422#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 7803762#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7803763#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7804412#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7804398#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7803845#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7803846#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7804124#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7804125#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7803940#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7803941#L838 assume !(0 == ~M_E~0); 7804137#L838-2 assume !(0 == ~T1_E~0); 7803440#L843-1 assume !(0 == ~T2_E~0); 7803441#L848-1 assume !(0 == ~T3_E~0); 7803557#L853-1 assume !(0 == ~T4_E~0); 7803929#L858-1 assume !(0 == ~T5_E~0); 7803397#L863-1 assume !(0 == ~T6_E~0); 7803398#L868-1 assume !(0 == ~T7_E~0); 7804506#L873-1 assume !(0 == ~T8_E~0); 7804502#L878-1 assume !(0 == ~E_1~0); 7804470#L883-1 assume !(0 == ~E_2~0); 7804471#L888-1 assume !(0 == ~E_3~0); 7804086#L893-1 assume !(0 == ~E_4~0); 7804087#L898-1 assume !(0 == ~E_5~0); 7804532#L903-1 assume !(0 == ~E_6~0); 7804464#L908-1 assume !(0 == ~E_7~0); 7804247#L913-1 assume !(0 == ~E_8~0); 7803453#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7803454#L402 assume !(1 == ~m_pc~0); 7803901#L402-2 is_master_triggered_~__retres1~0#1 := 0; 7803583#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7803584#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 7803853#L1035 assume !(0 != activate_threads_~tmp~1#1); 7803854#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7803913#L421 assume !(1 == ~t1_pc~0); 7804456#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7804508#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7803455#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7803456#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 7803974#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7804523#L440 assume !(1 == ~t2_pc~0); 7804616#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7803594#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7803595#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7803790#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 7804266#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7803800#L459 assume !(1 == ~t3_pc~0); 7803801#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7804448#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7803415#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7803416#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 7803577#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7803587#L478 assume !(1 == ~t4_pc~0); 7803588#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7804326#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7803528#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7803529#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 7803493#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7803494#L497 assume !(1 == ~t5_pc~0); 7803540#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7804043#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7804181#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7804524#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 7804525#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7804603#L516 assume !(1 == ~t6_pc~0); 7804604#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7804122#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7804123#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7803634#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 7803635#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7804110#L535 assume !(1 == ~t7_pc~0); 7804111#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7804649#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7804647#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7804644#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 7804225#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7804226#L554 assume !(1 == ~t8_pc~0); 7803417#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7803418#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7804258#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7804259#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 7804642#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7804641#L931 assume !(1 == ~M_E~0); 7804487#L931-2 assume !(1 == ~T1_E~0); 7804488#L936-1 assume !(1 == ~T2_E~0); 7804614#L941-1 assume !(1 == ~T3_E~0); 7804615#L946-1 assume !(1 == ~T4_E~0); 7804452#L951-1 assume !(1 == ~T5_E~0); 7803650#L956-1 assume !(1 == ~T6_E~0); 7803651#L961-1 assume !(1 == ~T7_E~0); 7804088#L966-1 assume !(1 == ~T8_E~0); 7804089#L971-1 assume !(1 == ~E_1~0); 7804229#L976-1 assume !(1 == ~E_2~0); 7804636#L981-1 assume !(1 == ~E_3~0); 7804635#L986-1 assume !(1 == ~E_4~0); 7804634#L991-1 assume !(1 == ~E_5~0); 7803678#L996-1 assume !(1 == ~E_6~0); 7804514#L1001-1 assume !(1 == ~E_7~0); 7804149#L1006-1 assume !(1 == ~E_8~0); 7804150#L1011-1 assume { :end_inline_reset_delta_events } true; 7804453#L1272-2 assume !false; 7862367#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7862366#L813-1 [2023-11-28 20:22:45,564 INFO L750 eck$LassoCheckResult]: Loop: 7862366#L813-1 assume !false; 7862365#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 7862363#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 7862361#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 7862359#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7862357#L696 assume 0 != eval_~tmp~0#1; 7862355#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 7862352#L704 assume !(0 != eval_~tmp_ndt_1~0#1); 7862353#L704-2 havoc eval_~tmp_ndt_1~0#1; 7865150#L701-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 7865147#L718 assume !(0 != eval_~tmp_ndt_2~0#1); 7865148#L718-2 havoc eval_~tmp_ndt_2~0#1; 7870526#L715-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 7870523#L732 assume !(0 != eval_~tmp_ndt_3~0#1); 7870521#L732-2 havoc eval_~tmp_ndt_3~0#1; 7870519#L729-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 7869703#L746 assume !(0 != eval_~tmp_ndt_4~0#1); 7870513#L746-2 havoc eval_~tmp_ndt_4~0#1; 7870509#L743-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 7870506#L760 assume !(0 != eval_~tmp_ndt_5~0#1); 7870504#L760-2 havoc eval_~tmp_ndt_5~0#1; 7862382#L757-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 7862380#L774 assume !(0 != eval_~tmp_ndt_6~0#1); 7862378#L774-2 havoc eval_~tmp_ndt_6~0#1; 7862376#L771-1 assume !(0 == ~t6_st~0); 7862372#L785-1 assume !(0 == ~t7_st~0); 7862369#L799-1 assume !(0 == ~t8_st~0); 7862366#L813-1 [2023-11-28 20:22:45,564 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:45,565 INFO L85 PathProgramCache]: Analyzing trace with hash 1664652065, now seen corresponding path program 6 times [2023-11-28 20:22:45,565 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:45,565 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [903800733] [2023-11-28 20:22:45,565 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:45,565 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:45,573 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:45,573 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:45,577 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:45,593 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:45,594 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:45,594 INFO L85 PathProgramCache]: Analyzing trace with hash -1882779245, now seen corresponding path program 1 times [2023-11-28 20:22:45,594 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:45,594 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [825886847] [2023-11-28 20:22:45,594 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:45,594 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:45,597 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:45,597 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:22:45,599 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:22:45,601 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:22:45,602 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:22:45,602 INFO L85 PathProgramCache]: Analyzing trace with hash 183208563, now seen corresponding path program 1 times [2023-11-28 20:22:45,602 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:22:45,602 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2020567170] [2023-11-28 20:22:45,602 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:22:45,602 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:22:45,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:22:45,639 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:22:45,639 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:22:45,639 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2020567170] [2023-11-28 20:22:45,640 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2020567170] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:22:45,640 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:22:45,640 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:22:45,640 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [236279727] [2023-11-28 20:22:45,640 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:22:45,746 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:22:45,747 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:22:45,747 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:22:45,747 INFO L87 Difference]: Start difference. First operand 732307 states and 915535 transitions. cyclomatic complexity: 183324 Second operand has 3 states, 3 states have (on average 44.333333333333336) internal successors, (133), 3 states have internal predecessors, (133), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:22:48,543 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:22:48,543 INFO L93 Difference]: Finished difference Result 1024043 states and 1279035 transitions. [2023-11-28 20:22:48,543 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1024043 states and 1279035 transitions. [2023-11-28 20:22:53,204 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 908920 [2023-11-28 20:22:56,250 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1024043 states to 1024043 states and 1279035 transitions. [2023-11-28 20:22:56,251 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1024043 [2023-11-28 20:22:56,648 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1024043 [2023-11-28 20:22:56,648 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1024043 states and 1279035 transitions. [2023-11-28 20:22:57,091 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:22:57,091 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1024043 states and 1279035 transitions. [2023-11-28 20:22:57,634 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1024043 states and 1279035 transitions. [2023-11-28 20:23:05,103 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1024043 to 1002219. [2023-11-28 20:23:06,271 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1002219 states, 1002219 states have (on average 1.2499733092268257) internal successors, (1252747), 1002218 states have internal predecessors, (1252747), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:23:09,373 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1002219 states to 1002219 states and 1252747 transitions. [2023-11-28 20:23:09,373 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1002219 states and 1252747 transitions. [2023-11-28 20:23:09,373 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-28 20:23:09,374 INFO L428 stractBuchiCegarLoop]: Abstraction has 1002219 states and 1252747 transitions. [2023-11-28 20:23:09,374 INFO L335 stractBuchiCegarLoop]: ======== Iteration 43 ============ [2023-11-28 20:23:09,374 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1002219 states and 1252747 transitions. [2023-11-28 20:23:11,770 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 887096 [2023-11-28 20:23:11,770 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-28 20:23:11,770 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-28 20:23:11,771 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:23:11,771 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-28 20:23:11,771 INFO L748 eck$LassoCheckResult]: Stem: 9560001#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2; 9560002#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~10#1;havoc main_~__retres1~10#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1; 9560855#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret24#1, start_simulation_#t~ret25#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9560856#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9560858#L581 assume 1 == ~m_i~0;~m_st~0 := 0; 9560129#L581-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9560130#L586-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9560846#L591-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9560827#L596-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9560210#L601-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9560211#L606-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9560508#L611-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 9560509#L616-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 9560309#L621-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9560310#L838 assume !(0 == ~M_E~0); 9560520#L838-2 assume !(0 == ~T1_E~0); 9559797#L843-1 assume !(0 == ~T2_E~0); 9559798#L848-1 assume !(0 == ~T3_E~0); 9559918#L853-1 assume !(0 == ~T4_E~0); 9560296#L858-1 assume !(0 == ~T5_E~0); 9559753#L863-1 assume !(0 == ~T6_E~0); 9559754#L868-1 assume !(0 == ~T7_E~0); 9560938#L873-1 assume !(0 == ~T8_E~0); 9560933#L878-1 assume !(0 == ~E_1~0); 9560902#L883-1 assume !(0 == ~E_2~0); 9560903#L888-1 assume !(0 == ~E_3~0); 9560468#L893-1 assume !(0 == ~E_4~0); 9560469#L898-1 assume !(0 == ~E_5~0); 9560971#L903-1 assume !(0 == ~E_6~0); 9560898#L908-1 assume !(0 == ~E_7~0); 9560646#L913-1 assume !(0 == ~E_8~0); 9559809#L918-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9559810#L402 assume !(1 == ~m_pc~0); 9560270#L402-2 is_master_triggered_~__retres1~0#1 := 0; 9559945#L413 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9559946#is_master_triggered_returnLabel#1 activate_threads_#t~ret14#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret14#1;havoc activate_threads_#t~ret14#1; 9560218#L1035 assume !(0 != activate_threads_~tmp~1#1); 9560219#L1035-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9560282#L421 assume !(1 == ~t1_pc~0); 9560890#L421-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9560940#L432 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9559812#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9559813#L1043 assume !(0 != activate_threads_~tmp___0~0#1); 9560346#L1043-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9560960#L440 assume !(1 == ~t2_pc~0); 9561059#L440-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9559955#L451 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9559956#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9560157#L1051 assume !(0 != activate_threads_~tmp___1~0#1); 9560671#L1051-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9560162#L459 assume !(1 == ~t3_pc~0); 9560163#L459-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9560879#L470 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9559773#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9559774#L1059 assume !(0 != activate_threads_~tmp___2~0#1); 9559939#L1059-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9559949#L478 assume !(1 == ~t4_pc~0); 9559950#L478-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9560741#L489 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9559886#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9559887#L1067 assume !(0 != activate_threads_~tmp___3~0#1); 9559849#L1067-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9559850#L497 assume !(1 == ~t5_pc~0); 9559898#L497-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9560418#L508 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9560574#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9560961#L1075 assume !(0 != activate_threads_~tmp___4~0#1); 9560962#L1075-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9561043#L516 assume !(1 == ~t6_pc~0); 9561044#L516-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9560506#L527 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9560507#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9561121#L1083 assume !(0 != activate_threads_~tmp___5~0#1); 9561120#L1083-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9560494#L535 assume !(1 == ~t7_pc~0); 9560495#L535-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9561119#L546 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9561117#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9561115#L1091 assume !(0 != activate_threads_~tmp___6~0#1); 9561113#L1091-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9560859#L554 assume !(1 == ~t8_pc~0); 9560860#L554-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9560993#L565 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9560658#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9560659#L1099 assume !(0 != activate_threads_~tmp___7~0#1); 9561111#L1099-2 havoc activate_threads_#t~ret14#1, activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9561110#L931 assume !(1 == ~M_E~0); 9560920#L931-2 assume !(1 == ~T1_E~0); 9560921#L936-1 assume !(1 == ~T2_E~0); 9561104#L941-1 assume !(1 == ~T3_E~0); 9560283#L946-1 assume !(1 == ~T4_E~0); 9560284#L951-1 assume !(1 == ~T5_E~0); 9561100#L956-1 assume !(1 == ~T6_E~0); 9561099#L961-1 assume !(1 == ~T7_E~0); 9560470#L966-1 assume !(1 == ~T8_E~0); 9560471#L971-1 assume !(1 == ~E_1~0); 9560630#L976-1 assume !(1 == ~E_2~0); 9561080#L981-1 assume !(1 == ~E_3~0); 9561079#L986-1 assume !(1 == ~E_4~0); 9561078#L991-1 assume !(1 == ~E_5~0); 9560041#L996-1 assume !(1 == ~E_6~0); 9560951#L1001-1 assume !(1 == ~E_7~0); 9560535#L1006-1 assume !(1 == ~E_8~0); 9560536#L1011-1 assume { :end_inline_reset_delta_events } true; 9560887#L1272-2 assume !false; 9623540#L1273 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9623538#L813-1 [2023-11-28 20:23:11,771 INFO L750 eck$LassoCheckResult]: Loop: 9623538#L813-1 assume !false; 9623536#L692 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;havoc exists_runnable_thread_~__retres1~9#1; 9623534#L634 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~9#1 := 1; 9623532#L681 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~9#1; 9623529#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~9#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9623528#L696 assume 0 != eval_~tmp~0#1; 9623525#L696-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 9623522#L704 assume !(0 != eval_~tmp_ndt_1~0#1); 9623523#L704-2 havoc eval_~tmp_ndt_1~0#1; 9933732#L701-1 assume 0 == ~t1_st~0;havoc eval_~tmp_ndt_2~0#1;havoc eval_#t~nondet6#1;eval_~tmp_ndt_2~0#1 := eval_#t~nondet6#1;havoc eval_#t~nondet6#1; 9933729#L718 assume !(0 != eval_~tmp_ndt_2~0#1); 9933727#L718-2 havoc eval_~tmp_ndt_2~0#1; 9933725#L715-1 assume 0 == ~t2_st~0;havoc eval_~tmp_ndt_3~0#1;havoc eval_#t~nondet7#1;eval_~tmp_ndt_3~0#1 := eval_#t~nondet7#1;havoc eval_#t~nondet7#1; 9933723#L732 assume !(0 != eval_~tmp_ndt_3~0#1); 9933724#L732-2 havoc eval_~tmp_ndt_3~0#1; 9636381#L729-1 assume 0 == ~t3_st~0;havoc eval_~tmp_ndt_4~0#1;havoc eval_#t~nondet8#1;eval_~tmp_ndt_4~0#1 := eval_#t~nondet8#1;havoc eval_#t~nondet8#1; 9636378#L746 assume !(0 != eval_~tmp_ndt_4~0#1); 9636376#L746-2 havoc eval_~tmp_ndt_4~0#1; 9636374#L743-1 assume 0 == ~t4_st~0;havoc eval_~tmp_ndt_5~0#1;havoc eval_#t~nondet9#1;eval_~tmp_ndt_5~0#1 := eval_#t~nondet9#1;havoc eval_#t~nondet9#1; 9636370#L760 assume !(0 != eval_~tmp_ndt_5~0#1); 9636368#L760-2 havoc eval_~tmp_ndt_5~0#1; 9623562#L757-1 assume 0 == ~t5_st~0;havoc eval_~tmp_ndt_6~0#1;havoc eval_#t~nondet10#1;eval_~tmp_ndt_6~0#1 := eval_#t~nondet10#1;havoc eval_#t~nondet10#1; 9623559#L774 assume !(0 != eval_~tmp_ndt_6~0#1); 9623558#L774-2 havoc eval_~tmp_ndt_6~0#1; 9623556#L771-1 assume 0 == ~t6_st~0;havoc eval_~tmp_ndt_7~0#1;havoc eval_#t~nondet11#1;eval_~tmp_ndt_7~0#1 := eval_#t~nondet11#1;havoc eval_#t~nondet11#1; 9623551#L788 assume !(0 != eval_~tmp_ndt_7~0#1); 9623549#L788-2 havoc eval_~tmp_ndt_7~0#1; 9623546#L785-1 assume !(0 == ~t7_st~0); 9623542#L799-1 assume !(0 == ~t8_st~0); 9623538#L813-1 [2023-11-28 20:23:11,771 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:23:11,771 INFO L85 PathProgramCache]: Analyzing trace with hash 1664652065, now seen corresponding path program 7 times [2023-11-28 20:23:11,772 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:23:11,772 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1112650029] [2023-11-28 20:23:11,772 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:23:11,772 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:23:11,778 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:23:11,779 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:23:11,784 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:23:11,795 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:23:11,795 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:23:11,796 INFO L85 PathProgramCache]: Analyzing trace with hash -1405535074, now seen corresponding path program 1 times [2023-11-28 20:23:11,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:23:11,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [464075288] [2023-11-28 20:23:11,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:23:11,796 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:23:11,798 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:23:11,798 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-28 20:23:11,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-28 20:23:11,801 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-28 20:23:11,801 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-28 20:23:11,801 INFO L85 PathProgramCache]: Analyzing trace with hash -266142338, now seen corresponding path program 1 times [2023-11-28 20:23:11,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-28 20:23:11,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1621048431] [2023-11-28 20:23:11,801 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-28 20:23:11,801 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-28 20:23:11,807 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-28 20:23:11,828 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-28 20:23:11,828 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-28 20:23:11,828 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1621048431] [2023-11-28 20:23:11,828 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1621048431] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-28 20:23:11,828 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-28 20:23:11,828 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-28 20:23:11,828 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1411440619] [2023-11-28 20:23:11,828 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-28 20:23:11,939 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-28 20:23:11,939 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-28 20:23:11,939 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-28 20:23:11,939 INFO L87 Difference]: Start difference. First operand 1002219 states and 1252747 transitions. cyclomatic complexity: 250624 Second operand has 3 states, 3 states have (on average 45.0) internal successors, (135), 3 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-28 20:23:18,016 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-28 20:23:18,016 INFO L93 Difference]: Finished difference Result 1802759 states and 2248243 transitions. [2023-11-28 20:23:18,016 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1802759 states and 2248243 transitions. [2023-11-28 20:23:26,696 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 1572668 [2023-11-28 20:23:31,135 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1802759 states to 1802759 states and 2248243 transitions. [2023-11-28 20:23:31,135 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1802759 [2023-11-28 20:23:32,149 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1802759 [2023-11-28 20:23:32,149 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1802759 states and 2248243 transitions. [2023-11-28 20:23:32,861 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-28 20:23:32,861 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1802759 states and 2248243 transitions. [2023-11-28 20:23:33,639 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1802759 states and 2248243 transitions. [2023-11-28 20:23:47,717 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1802759 to 1768583. [2023-11-28 20:23:48,824 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1768583 states, 1768583 states have (on average 1.2494720349567987) internal successors, (2209795), 1768582 states have internal predecessors, (2209795), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0)