./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.09.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-11-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.09.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 04:11:39,440 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 04:11:39,502 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 04:11:39,507 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 04:11:39,507 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 04:11:39,530 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 04:11:39,530 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 04:11:39,531 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 04:11:39,532 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 04:11:39,532 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 04:11:39,533 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 04:11:39,534 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 04:11:39,534 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 04:11:39,535 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 04:11:39,535 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 04:11:39,536 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 04:11:39,536 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 04:11:39,537 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 04:11:39,537 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 04:11:39,538 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 04:11:39,538 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 04:11:39,539 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 04:11:39,540 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 04:11:39,540 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 04:11:39,540 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 04:11:39,541 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 04:11:39,541 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 04:11:39,542 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 04:11:39,542 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 04:11:39,543 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 04:11:39,543 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 04:11:39,543 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 04:11:39,544 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 04:11:39,544 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 04:11:39,544 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 04:11:39,544 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 04:11:39,545 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 04:11:39,545 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 04:11:39,545 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> 3945fa4b58cef50cb4b44b435a699812e99a1f6375664d08551274c6b50bee45 [2023-11-29 04:11:39,760 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 04:11:39,781 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 04:11:39,783 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 04:11:39,784 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 04:11:39,785 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 04:11:39,786 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/transmitter.09.cil.c [2023-11-29 04:11:42,542 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 04:11:42,750 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 04:11:42,750 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/sv-benchmarks/c/systemc/transmitter.09.cil.c [2023-11-29 04:11:42,763 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/data/cfc8a1a71/4cf1092c378b4ca3aff9d3c89b3b6281/FLAGa4e3dd508 [2023-11-29 04:11:42,774 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/data/cfc8a1a71/4cf1092c378b4ca3aff9d3c89b3b6281 [2023-11-29 04:11:42,775 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 04:11:42,777 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 04:11:42,777 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 04:11:42,778 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 04:11:42,781 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 04:11:42,782 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 04:11:42" (1/1) ... [2023-11-29 04:11:42,783 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@54ccfd81 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:42, skipping insertion in model container [2023-11-29 04:11:42,783 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 04:11:42" (1/1) ... [2023-11-29 04:11:42,831 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 04:11:43,057 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 04:11:43,073 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 04:11:43,124 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 04:11:43,146 INFO L206 MainTranslator]: Completed translation [2023-11-29 04:11:43,146 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43 WrapperNode [2023-11-29 04:11:43,146 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 04:11:43,147 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 04:11:43,147 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 04:11:43,148 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 04:11:43,155 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,167 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,239 INFO L138 Inliner]: procedures = 46, calls = 58, calls flagged for inlining = 53, calls inlined = 171, statements flattened = 2601 [2023-11-29 04:11:43,239 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 04:11:43,240 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 04:11:43,240 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 04:11:43,240 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 04:11:43,252 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,252 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,263 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,295 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 04:11:43,295 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,295 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,328 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,355 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,360 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,371 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,382 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 04:11:43,383 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 04:11:43,383 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 04:11:43,383 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 04:11:43,384 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (1/1) ... [2023-11-29 04:11:43,390 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:11:43,400 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:11:43,413 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:11:43,415 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 04:11:43,446 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 04:11:43,446 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 04:11:43,446 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 04:11:43,447 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 04:11:43,559 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 04:11:43,561 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 04:11:44,976 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 04:11:45,005 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 04:11:45,006 INFO L309 CfgBuilder]: Removed 13 assume(true) statements. [2023-11-29 04:11:45,008 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 04:11:45 BoogieIcfgContainer [2023-11-29 04:11:45,008 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 04:11:45,009 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 04:11:45,009 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 04:11:45,012 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 04:11:45,013 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 04:11:45,013 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 04:11:42" (1/3) ... [2023-11-29 04:11:45,014 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@345c3db5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 04:11:45, skipping insertion in model container [2023-11-29 04:11:45,014 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 04:11:45,014 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 04:11:43" (2/3) ... [2023-11-29 04:11:45,014 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@345c3db5 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 04:11:45, skipping insertion in model container [2023-11-29 04:11:45,015 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 04:11:45,015 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 04:11:45" (3/3) ... [2023-11-29 04:11:45,016 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.09.cil.c [2023-11-29 04:11:45,082 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 04:11:45,083 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 04:11:45,083 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 04:11:45,083 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 04:11:45,083 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 04:11:45,083 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 04:11:45,083 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 04:11:45,083 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 04:11:45,092 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:45,142 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 983 [2023-11-29 04:11:45,142 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:45,142 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:45,155 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:45,155 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:45,155 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 04:11:45,158 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:45,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 983 [2023-11-29 04:11:45,173 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:45,173 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:45,178 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:45,178 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:45,188 INFO L748 eck$LassoCheckResult]: Stem: 138#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1013#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 813#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1008#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 733#L641true assume !(1 == ~m_i~0);~m_st~0 := 2; 786#L641-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 705#L646-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 495#L651-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 988#L656-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 333#L661-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 945#L666-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 869#L671-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 684#L676-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 382#L681-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 221#L686-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1102#L922true assume !(0 == ~M_E~0); 1041#L922-2true assume !(0 == ~T1_E~0); 1058#L927-1true assume !(0 == ~T2_E~0); 552#L932-1true assume !(0 == ~T3_E~0); 437#L937-1true assume 0 == ~T4_E~0;~T4_E~0 := 1; 494#L942-1true assume !(0 == ~T5_E~0); 736#L947-1true assume !(0 == ~T6_E~0); 556#L952-1true assume !(0 == ~T7_E~0); 627#L957-1true assume !(0 == ~T8_E~0); 982#L962-1true assume !(0 == ~T9_E~0); 420#L967-1true assume !(0 == ~E_1~0); 954#L972-1true assume !(0 == ~E_2~0); 715#L977-1true assume 0 == ~E_3~0;~E_3~0 := 1; 1050#L982-1true assume !(0 == ~E_4~0); 104#L987-1true assume !(0 == ~E_5~0); 107#L992-1true assume !(0 == ~E_6~0); 363#L997-1true assume !(0 == ~E_7~0); 900#L1002-1true assume !(0 == ~E_8~0); 354#L1007-1true assume !(0 == ~E_9~0); 6#L1012-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 891#L443true assume !(1 == ~m_pc~0); 571#L443-2true is_master_triggered_~__retres1~0#1 := 0; 562#L454true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 693#is_master_triggered_returnLabel#1true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 187#L1140true assume !(0 != activate_threads_~tmp~1#1); 55#L1140-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 914#L462true assume 1 == ~t1_pc~0; 459#L463true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 961#L473true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 25#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 579#L1148true assume !(0 != activate_threads_~tmp___0~0#1); 318#L1148-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 995#L481true assume !(1 == ~t2_pc~0); 790#L481-2true is_transmit2_triggered_~__retres1~2#1 := 0; 543#L492true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 255#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 234#L1156true assume !(0 != activate_threads_~tmp___1~0#1); 299#L1156-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1094#L500true assume 1 == ~t3_pc~0; 474#L501true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 754#L511true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 781#L1164true assume !(0 != activate_threads_~tmp___2~0#1); 7#L1164-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 766#L519true assume 1 == ~t4_pc~0; 154#L520true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 298#L530true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 56#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 206#L1172true assume !(0 != activate_threads_~tmp___3~0#1); 515#L1172-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87#L538true assume !(1 == ~t5_pc~0); 845#L538-2true is_transmit5_triggered_~__retres1~5#1 := 0; 36#L549true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 697#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 176#L1180true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 611#L1180-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1113#L557true assume 1 == ~t6_pc~0; 410#L558true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 824#L568true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 244#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 207#L1188true assume !(0 != activate_threads_~tmp___5~0#1); 948#L1188-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1065#L576true assume !(1 == ~t7_pc~0); 303#L576-2true is_transmit7_triggered_~__retres1~7#1 := 0; 409#L587true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1030#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1059#L1196true assume !(0 != activate_threads_~tmp___6~0#1); 670#L1196-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 257#L595true assume 1 == ~t8_pc~0; 1015#L596true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 700#L606true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 616#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 517#L1204true assume !(0 != activate_threads_~tmp___7~0#1); 952#L1204-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 151#L614true assume !(1 == ~t9_pc~0); 460#L614-2true is_transmit9_triggered_~__retres1~9#1 := 0; 99#L625true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 282#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 682#L1212true assume !(0 != activate_threads_~tmp___8~0#1); 236#L1212-2true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 425#L1025true assume !(1 == ~M_E~0); 473#L1025-2true assume !(1 == ~T1_E~0); 603#L1030-1true assume 1 == ~T2_E~0;~T2_E~0 := 2; 761#L1035-1true assume !(1 == ~T3_E~0); 230#L1040-1true assume !(1 == ~T4_E~0); 740#L1045-1true assume !(1 == ~T5_E~0); 181#L1050-1true assume !(1 == ~T6_E~0); 292#L1055-1true assume !(1 == ~T7_E~0); 92#L1060-1true assume !(1 == ~T8_E~0); 123#L1065-1true assume !(1 == ~T9_E~0); 966#L1070-1true assume 1 == ~E_1~0;~E_1~0 := 2; 557#L1075-1true assume !(1 == ~E_2~0); 1098#L1080-1true assume !(1 == ~E_3~0); 549#L1085-1true assume !(1 == ~E_4~0); 858#L1090-1true assume !(1 == ~E_5~0); 980#L1095-1true assume !(1 == ~E_6~0); 586#L1100-1true assume !(1 == ~E_7~0); 591#L1105-1true assume !(1 == ~E_8~0); 79#L1110-1true assume 1 == ~E_9~0;~E_9~0 := 2; 262#L1115-1true assume { :end_inline_reset_delta_events } true; 202#L1396-2true [2023-11-29 04:11:45,191 INFO L750 eck$LassoCheckResult]: Loop: 202#L1396-2true assume !false; 967#L1397true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 946#L897-1true assume false; 621#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 387#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 349#L922-3true assume 0 == ~M_E~0;~M_E~0 := 1; 987#L922-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 172#L927-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 277#L932-3true assume !(0 == ~T3_E~0); 547#L937-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 75#L942-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 632#L947-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 278#L952-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 826#L957-3true assume 0 == ~T8_E~0;~T8_E~0 := 1; 850#L962-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 645#L967-3true assume 0 == ~E_1~0;~E_1~0 := 1; 875#L972-3true assume !(0 == ~E_2~0); 551#L977-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1101#L982-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1074#L987-3true assume 0 == ~E_5~0;~E_5~0 := 1; 243#L992-3true assume 0 == ~E_6~0;~E_6~0 := 1; 369#L997-3true assume 0 == ~E_7~0;~E_7~0 := 1; 241#L1002-3true assume 0 == ~E_8~0;~E_8~0 := 1; 507#L1007-3true assume 0 == ~E_9~0;~E_9~0 := 1; 93#L1012-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 269#L443-30true assume !(1 == ~m_pc~0); 691#L443-32true is_master_triggered_~__retres1~0#1 := 0; 260#L454-10true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 265#is_master_triggered_returnLabel#11true activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 964#L1140-30true assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 721#L1140-32true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 339#L462-30true assume 1 == ~t1_pc~0; 225#L463-10true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 711#L473-10true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 435#is_transmit1_triggered_returnLabel#11true activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 757#L1148-30true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1079#L1148-32true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 329#L481-30true assume !(1 == ~t2_pc~0); 726#L481-32true is_transmit2_triggered_~__retres1~2#1 := 0; 679#L492-10true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 204#is_transmit2_triggered_returnLabel#11true activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 140#L1156-30true assume !(0 != activate_threads_~tmp___1~0#1); 302#L1156-32true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 567#L500-30true assume !(1 == ~t3_pc~0); 1080#L500-32true is_transmit3_triggered_~__retres1~3#1 := 0; 371#L511-10true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 414#is_transmit3_triggered_returnLabel#11true activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1040#L1164-30true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 290#L1164-32true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 651#L519-30true assume !(1 == ~t4_pc~0); 433#L519-32true is_transmit4_triggered_~__retres1~4#1 := 0; 415#L530-10true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 919#is_transmit4_triggered_returnLabel#11true activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 422#L1172-30true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 533#L1172-32true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 943#L538-30true assume 1 == ~t5_pc~0; 98#L539-10true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 280#L549-10true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 522#is_transmit5_triggered_returnLabel#11true activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 674#L1180-30true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 137#L1180-32true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 143#L557-30true assume 1 == ~t6_pc~0; 2#L558-10true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 399#L568-10true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 58#is_transmit6_triggered_returnLabel#11true activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1056#L1188-30true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 150#L1188-32true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 525#L576-30true assume 1 == ~t7_pc~0; 1044#L577-10true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 393#L587-10true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 578#is_transmit7_triggered_returnLabel#11true activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 855#L1196-30true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 231#L1196-32true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 211#L595-30true assume !(1 == ~t8_pc~0); 772#L595-32true is_transmit8_triggered_~__retres1~8#1 := 0; 178#L606-10true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1071#is_transmit8_triggered_returnLabel#11true activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 856#L1204-30true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1104#L1204-32true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 958#L614-30true assume !(1 == ~t9_pc~0); 788#L614-32true is_transmit9_triggered_~__retres1~9#1 := 0; 653#L625-10true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 19#is_transmit9_triggered_returnLabel#11true activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 94#L1212-30true assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 625#L1212-32true havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 508#L1025-3true assume 1 == ~M_E~0;~M_E~0 := 2; 321#L1025-5true assume !(1 == ~T1_E~0); 476#L1030-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 876#L1035-3true assume 1 == ~T3_E~0;~T3_E~0 := 2; 1033#L1040-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 1052#L1045-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 864#L1050-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 698#L1055-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 40#L1060-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 732#L1065-3true assume !(1 == ~T9_E~0); 723#L1070-3true assume 1 == ~E_1~0;~E_1~0 := 2; 536#L1075-3true assume 1 == ~E_2~0;~E_2~0 := 2; 877#L1080-3true assume 1 == ~E_3~0;~E_3~0 := 2; 959#L1085-3true assume 1 == ~E_4~0;~E_4~0 := 2; 708#L1090-3true assume 1 == ~E_5~0;~E_5~0 := 2; 1019#L1095-3true assume 1 == ~E_6~0;~E_6~0 := 2; 738#L1100-3true assume 1 == ~E_7~0;~E_7~0 := 2; 932#L1105-3true assume !(1 == ~E_8~0); 116#L1110-3true assume 1 == ~E_9~0;~E_9~0 := 2; 793#L1115-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 769#L699-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 120#L751-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 222#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 720#L1415true assume !(0 == start_simulation_~tmp~3#1); 419#L1415-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 986#L699-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 423#L751-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 24#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1090#L1370true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1075#L1377true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 411#stop_simulation_returnLabel#1true start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 160#L1428true assume !(0 != start_simulation_~tmp___0~1#1); 202#L1396-2true [2023-11-29 04:11:45,198 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:45,199 INFO L85 PathProgramCache]: Analyzing trace with hash 1400170149, now seen corresponding path program 1 times [2023-11-29 04:11:45,208 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:45,208 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1981905312] [2023-11-29 04:11:45,209 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:45,209 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:45,312 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:45,481 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:45,481 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:45,482 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1981905312] [2023-11-29 04:11:45,482 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1981905312] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:45,483 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:45,483 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:45,485 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [93901289] [2023-11-29 04:11:45,486 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:45,490 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:45,491 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:45,492 INFO L85 PathProgramCache]: Analyzing trace with hash -541420616, now seen corresponding path program 1 times [2023-11-29 04:11:45,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:45,492 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1641729101] [2023-11-29 04:11:45,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:45,493 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:45,512 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:45,555 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:45,556 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:45,556 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1641729101] [2023-11-29 04:11:45,556 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1641729101] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:45,556 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:45,556 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:11:45,557 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1555901309] [2023-11-29 04:11:45,557 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:45,558 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:45,559 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:45,590 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:45,590 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:45,595 INFO L87 Difference]: Start difference. First operand has 1112 states, 1111 states have (on average 1.5085508550855085) internal successors, (1676), 1111 states have internal predecessors, (1676), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:45,671 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:45,671 INFO L93 Difference]: Finished difference Result 1110 states and 1646 transitions. [2023-11-29 04:11:45,673 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1110 states and 1646 transitions. [2023-11-29 04:11:45,685 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:45,717 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1110 states to 1104 states and 1640 transitions. [2023-11-29 04:11:45,718 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-29 04:11:45,720 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-29 04:11:45,720 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1640 transitions. [2023-11-29 04:11:45,728 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:45,728 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2023-11-29 04:11:45,748 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1640 transitions. [2023-11-29 04:11:45,791 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-29 04:11:45,794 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4855072463768115) internal successors, (1640), 1103 states have internal predecessors, (1640), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:45,800 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1640 transitions. [2023-11-29 04:11:45,801 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2023-11-29 04:11:45,802 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:45,806 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1640 transitions. [2023-11-29 04:11:45,806 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 04:11:45,806 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1640 transitions. [2023-11-29 04:11:45,814 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:45,814 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:45,814 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:45,817 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:45,817 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:45,818 INFO L748 eck$LassoCheckResult]: Stem: 2514#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2515#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3273#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3225#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3226#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3208#L646-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3030#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 3031#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2839#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 2840#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3294#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3200#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 2899#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2670#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2671#L922 assume !(0 == ~M_E~0); 3331#L922-2 assume !(0 == ~T1_E~0); 3332#L927-1 assume !(0 == ~T2_E~0); 3094#L932-1 assume !(0 == ~T3_E~0); 2969#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2970#L942-1 assume !(0 == ~T5_E~0); 3029#L947-1 assume !(0 == ~T6_E~0); 3098#L952-1 assume !(0 == ~T7_E~0); 3099#L957-1 assume !(0 == ~T8_E~0); 3156#L962-1 assume !(0 == ~T9_E~0); 2948#L967-1 assume !(0 == ~E_1~0); 2949#L972-1 assume !(0 == ~E_2~0); 3212#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 3213#L982-1 assume !(0 == ~E_4~0); 2447#L987-1 assume !(0 == ~E_5~0); 2448#L992-1 assume !(0 == ~E_6~0); 2454#L997-1 assume !(0 == ~E_7~0); 2875#L1002-1 assume !(0 == ~E_8~0); 2864#L1007-1 assume !(0 == ~E_9~0); 2241#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2242#L443 assume !(1 == ~m_pc~0); 3114#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3106#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3107#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2609#L1140 assume !(0 != activate_threads_~tmp~1#1); 2346#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2347#L462 assume 1 == ~t1_pc~0; 2995#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2961#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2283#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2284#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2818#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2819#L481 assume !(1 == ~t2_pc~0); 2603#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2602#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2729#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2693#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2694#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2786#L500 assume 1 == ~t3_pc~0; 3014#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3015#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2248#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2249#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2243#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2244#L519 assume 1 == ~t4_pc~0; 2546#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2547#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2348#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2349#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2643#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2410#L538 assume !(1 == ~t5_pc~0); 2411#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2308#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2309#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2589#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2590#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3141#L557 assume 1 == ~t6_pc~0; 2936#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2624#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2711#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2644#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2645#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3318#L576 assume !(1 == ~t7_pc~0); 2613#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2614#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2935#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3328#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3192#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2730#L595 assume 1 == ~t8_pc~0; 2731#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3205#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3146#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3053#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3054#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2539#L614 assume !(1 == ~t9_pc~0); 2540#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2436#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2437#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2762#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2696#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2697#L1025 assume !(1 == ~M_E~0); 2955#L1025-2 assume !(1 == ~T1_E~0); 3013#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3136#L1035-1 assume !(1 == ~T3_E~0); 2689#L1040-1 assume !(1 == ~T4_E~0); 2690#L1045-1 assume !(1 == ~T5_E~0); 2599#L1050-1 assume !(1 == ~T6_E~0); 2600#L1055-1 assume !(1 == ~T7_E~0); 2421#L1060-1 assume !(1 == ~T8_E~0); 2422#L1065-1 assume !(1 == ~T9_E~0); 2486#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 3100#L1075-1 assume !(1 == ~E_2~0); 3101#L1080-1 assume !(1 == ~E_3~0); 3089#L1085-1 assume !(1 == ~E_4~0); 3090#L1090-1 assume !(1 == ~E_5~0); 3289#L1095-1 assume !(1 == ~E_6~0); 3123#L1100-1 assume !(1 == ~E_7~0); 3124#L1105-1 assume !(1 == ~E_8~0); 2392#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 2393#L1115-1 assume { :end_inline_reset_delta_events } true; 2558#L1396-2 [2023-11-29 04:11:45,819 INFO L750 eck$LassoCheckResult]: Loop: 2558#L1396-2 assume !false; 2635#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3293#L897-1 assume !false; 3316#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3227#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2266#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2267#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2750#L766 assume !(0 != eval_~tmp~0#1); 3151#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2905#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2857#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2858#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2581#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 2582#L932-3 assume !(0 == ~T3_E~0); 2755#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2384#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2385#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2756#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2757#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3278#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3173#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 3174#L972-3 assume !(0 == ~E_2~0); 3092#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3093#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3333#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2709#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2710#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2704#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2705#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 2423#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2424#L443-30 assume 1 == ~m_pc~0; 2457#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2458#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2736#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2741#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3216#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2846#L462-30 assume 1 == ~t1_pc~0; 2678#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 2679#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2965#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2966#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3241#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2831#L481-30 assume 1 == ~t2_pc~0; 2549#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2550#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2639#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2518#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 2519#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2791#L500-30 assume 1 == ~t3_pc~0; 2554#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2555#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2884#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2940#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2775#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2776#L519-30 assume !(1 == ~t4_pc~0); 2964#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2941#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2942#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2952#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2953#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3072#L538-30 assume 1 == ~t5_pc~0; 2432#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2433#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2759#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3059#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2512#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2513#L557-30 assume 1 == ~t6_pc~0; 2231#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 2233#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2352#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2353#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2537#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2538#L576-30 assume !(1 == ~t7_pc~0); 2306#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2307#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2914#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3121#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2688#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2652#L595-30 assume !(1 == ~t8_pc~0); 2653#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2591#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2592#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3287#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3288#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3319#L614-30 assume 1 == ~t9_pc~0; 2595#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2596#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2270#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2271#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2425#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3046#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2820#L1025-5 assume !(1 == ~T1_E~0); 2821#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3018#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3297#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3329#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3292#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3204#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2316#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2317#L1065-3 assume !(1 == ~T9_E~0); 3218#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 3075#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3076#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3298#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3209#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3210#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3229#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3230#L1105-3 assume !(1 == ~E_8~0); 2471#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 2472#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3245#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2327#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2480#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2672#L1415 assume !(0 == start_simulation_~tmp~3#1); 2945#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2946#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2380#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2281#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2282#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3334#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2937#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2557#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2558#L1396-2 [2023-11-29 04:11:45,820 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:45,820 INFO L85 PathProgramCache]: Analyzing trace with hash -1247434205, now seen corresponding path program 1 times [2023-11-29 04:11:45,820 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:45,820 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [824522574] [2023-11-29 04:11:45,820 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:45,821 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:45,842 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:45,899 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:45,900 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:45,900 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [824522574] [2023-11-29 04:11:45,900 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [824522574] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:45,900 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:45,900 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:45,901 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [113941770] [2023-11-29 04:11:45,901 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:45,901 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:45,902 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:45,902 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 1 times [2023-11-29 04:11:45,902 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:45,902 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1852641125] [2023-11-29 04:11:45,903 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:45,903 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:45,930 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:46,008 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:46,008 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:46,008 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1852641125] [2023-11-29 04:11:46,009 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1852641125] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:46,009 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:46,009 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:46,009 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1509973385] [2023-11-29 04:11:46,009 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:46,010 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:46,010 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:46,011 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:46,011 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:46,011 INFO L87 Difference]: Start difference. First operand 1104 states and 1640 transitions. cyclomatic complexity: 537 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:46,043 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:46,043 INFO L93 Difference]: Finished difference Result 1104 states and 1639 transitions. [2023-11-29 04:11:46,043 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1639 transitions. [2023-11-29 04:11:46,052 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:46,061 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1639 transitions. [2023-11-29 04:11:46,061 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-29 04:11:46,063 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-29 04:11:46,063 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1639 transitions. [2023-11-29 04:11:46,065 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:46,065 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2023-11-29 04:11:46,068 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1639 transitions. [2023-11-29 04:11:46,084 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-29 04:11:46,087 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4846014492753623) internal successors, (1639), 1103 states have internal predecessors, (1639), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:46,091 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1639 transitions. [2023-11-29 04:11:46,092 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2023-11-29 04:11:46,092 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:46,093 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1639 transitions. [2023-11-29 04:11:46,093 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 04:11:46,093 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1639 transitions. [2023-11-29 04:11:46,100 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:46,100 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:46,100 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:46,103 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:46,103 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:46,103 INFO L748 eck$LassoCheckResult]: Stem: 4729#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 4730#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5488#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5489#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5440#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 5441#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5423#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5245#L651-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5246#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5054#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 5055#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 5509#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 5415#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 5114#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4885#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4886#L922 assume !(0 == ~M_E~0); 5546#L922-2 assume !(0 == ~T1_E~0); 5547#L927-1 assume !(0 == ~T2_E~0); 5309#L932-1 assume !(0 == ~T3_E~0); 5184#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5185#L942-1 assume !(0 == ~T5_E~0); 5244#L947-1 assume !(0 == ~T6_E~0); 5313#L952-1 assume !(0 == ~T7_E~0); 5314#L957-1 assume !(0 == ~T8_E~0); 5373#L962-1 assume !(0 == ~T9_E~0); 5163#L967-1 assume !(0 == ~E_1~0); 5164#L972-1 assume !(0 == ~E_2~0); 5427#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 5428#L982-1 assume !(0 == ~E_4~0); 4662#L987-1 assume !(0 == ~E_5~0); 4663#L992-1 assume !(0 == ~E_6~0); 4669#L997-1 assume !(0 == ~E_7~0); 5090#L1002-1 assume !(0 == ~E_8~0); 5079#L1007-1 assume !(0 == ~E_9~0); 4456#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4457#L443 assume !(1 == ~m_pc~0); 5329#L443-2 is_master_triggered_~__retres1~0#1 := 0; 5321#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5322#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4824#L1140 assume !(0 != activate_threads_~tmp~1#1); 4561#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4562#L462 assume 1 == ~t1_pc~0; 5210#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 5176#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4498#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4499#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 5033#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5034#L481 assume !(1 == ~t2_pc~0); 4818#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4817#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4944#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4908#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 4909#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5003#L500 assume 1 == ~t3_pc~0; 5229#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5230#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4463#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4464#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 4458#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4459#L519 assume 1 == ~t4_pc~0; 4761#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 4762#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4563#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4564#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 4860#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4625#L538 assume !(1 == ~t5_pc~0); 4626#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4523#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4524#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4804#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4805#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5358#L557 assume 1 == ~t6_pc~0; 5151#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4839#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4926#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4861#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 4862#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5533#L576 assume !(1 == ~t7_pc~0); 4828#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4829#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5150#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5543#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 5407#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4945#L595 assume 1 == ~t8_pc~0; 4946#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5420#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5361#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5268#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 5269#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4754#L614 assume !(1 == ~t9_pc~0); 4755#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4651#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4652#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4977#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 4911#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4912#L1025 assume !(1 == ~M_E~0); 5170#L1025-2 assume !(1 == ~T1_E~0); 5228#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5351#L1035-1 assume !(1 == ~T3_E~0); 4904#L1040-1 assume !(1 == ~T4_E~0); 4905#L1045-1 assume !(1 == ~T5_E~0); 4814#L1050-1 assume !(1 == ~T6_E~0); 4815#L1055-1 assume !(1 == ~T7_E~0); 4636#L1060-1 assume !(1 == ~T8_E~0); 4637#L1065-1 assume !(1 == ~T9_E~0); 4701#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 5315#L1075-1 assume !(1 == ~E_2~0); 5316#L1080-1 assume !(1 == ~E_3~0); 5304#L1085-1 assume !(1 == ~E_4~0); 5305#L1090-1 assume !(1 == ~E_5~0); 5504#L1095-1 assume !(1 == ~E_6~0); 5338#L1100-1 assume !(1 == ~E_7~0); 5339#L1105-1 assume !(1 == ~E_8~0); 4607#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 4608#L1115-1 assume { :end_inline_reset_delta_events } true; 4773#L1396-2 [2023-11-29 04:11:46,104 INFO L750 eck$LassoCheckResult]: Loop: 4773#L1396-2 assume !false; 4850#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5508#L897-1 assume !false; 5531#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5442#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4481#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4482#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4965#L766 assume !(0 != eval_~tmp~0#1); 5366#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5120#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5072#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 5073#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4796#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 4797#L932-3 assume !(0 == ~T3_E~0); 4970#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4599#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4600#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 4971#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4972#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 5493#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5388#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5389#L972-3 assume !(0 == ~E_2~0); 5307#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5308#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 5548#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4924#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 4925#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4922#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4923#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 4638#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4639#L443-30 assume 1 == ~m_pc~0; 4672#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4673#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4951#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 4956#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5431#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5061#L462-30 assume !(1 == ~t1_pc~0); 4897#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 4896#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5180#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5181#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5456#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5046#L481-30 assume 1 == ~t2_pc~0; 4764#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 4765#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4854#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4733#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 4734#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5006#L500-30 assume 1 == ~t3_pc~0; 4769#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 4770#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5099#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5155#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4991#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4992#L519-30 assume 1 == ~t4_pc~0; 5344#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5156#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5157#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5167#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5168#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5287#L538-30 assume 1 == ~t5_pc~0; 4647#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 4648#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4973#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5273#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4727#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4728#L557-30 assume 1 == ~t6_pc~0; 4446#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 4448#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4567#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4568#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4752#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4753#L576-30 assume !(1 == ~t7_pc~0); 4516#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 4517#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5129#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5335#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4903#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4867#L595-30 assume !(1 == ~t8_pc~0); 4868#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 4806#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4807#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5502#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5503#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5534#L614-30 assume 1 == ~t9_pc~0; 4810#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4811#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4485#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4486#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4640#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5261#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5035#L1025-5 assume !(1 == ~T1_E~0); 5036#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 5233#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 5512#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5544#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5507#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5419#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4531#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4532#L1065-3 assume !(1 == ~T9_E~0); 5433#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 5290#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5291#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5513#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5424#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5425#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5444#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5445#L1105-3 assume !(1 == ~E_8~0); 4686#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4687#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5461#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4542#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4695#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 4887#L1415 assume !(0 == start_simulation_~tmp~3#1); 5160#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5161#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 4595#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 4496#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 4497#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5549#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5152#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 4772#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 4773#L1396-2 [2023-11-29 04:11:46,104 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:46,105 INFO L85 PathProgramCache]: Analyzing trace with hash -208849631, now seen corresponding path program 1 times [2023-11-29 04:11:46,105 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:46,105 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1864582214] [2023-11-29 04:11:46,105 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:46,106 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:46,122 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:46,158 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:46,158 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:46,159 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1864582214] [2023-11-29 04:11:46,159 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1864582214] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:46,159 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:46,159 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:46,159 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2003936764] [2023-11-29 04:11:46,160 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:46,160 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:46,160 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:46,161 INFO L85 PathProgramCache]: Analyzing trace with hash 1344839060, now seen corresponding path program 1 times [2023-11-29 04:11:46,161 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:46,161 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [475148563] [2023-11-29 04:11:46,161 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:46,161 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:46,179 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:46,256 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:46,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:46,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [475148563] [2023-11-29 04:11:46,257 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [475148563] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:46,257 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:46,257 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:46,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [761306350] [2023-11-29 04:11:46,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:46,258 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:46,258 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:46,259 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:46,259 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:46,259 INFO L87 Difference]: Start difference. First operand 1104 states and 1639 transitions. cyclomatic complexity: 536 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:46,290 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:46,290 INFO L93 Difference]: Finished difference Result 1104 states and 1638 transitions. [2023-11-29 04:11:46,290 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1638 transitions. [2023-11-29 04:11:46,299 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:46,308 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1638 transitions. [2023-11-29 04:11:46,308 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-29 04:11:46,309 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-29 04:11:46,309 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1638 transitions. [2023-11-29 04:11:46,311 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:46,311 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2023-11-29 04:11:46,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1638 transitions. [2023-11-29 04:11:46,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-29 04:11:46,333 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.483695652173913) internal successors, (1638), 1103 states have internal predecessors, (1638), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:46,337 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1638 transitions. [2023-11-29 04:11:46,337 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2023-11-29 04:11:46,338 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:46,339 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1638 transitions. [2023-11-29 04:11:46,339 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 04:11:46,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1638 transitions. [2023-11-29 04:11:46,345 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:46,346 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:46,346 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:46,348 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:46,348 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:46,348 INFO L748 eck$LassoCheckResult]: Stem: 6946#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 6947#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 7703#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7704#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7655#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 7656#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7638#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7460#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7461#L656-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 7269#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 7270#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 7725#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 7630#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 7329#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7100#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7101#L922 assume !(0 == ~M_E~0); 7761#L922-2 assume !(0 == ~T1_E~0); 7762#L927-1 assume !(0 == ~T2_E~0); 7524#L932-1 assume !(0 == ~T3_E~0); 7399#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7400#L942-1 assume !(0 == ~T5_E~0); 7459#L947-1 assume !(0 == ~T6_E~0); 7528#L952-1 assume !(0 == ~T7_E~0); 7529#L957-1 assume !(0 == ~T8_E~0); 7588#L962-1 assume !(0 == ~T9_E~0); 7378#L967-1 assume !(0 == ~E_1~0); 7379#L972-1 assume !(0 == ~E_2~0); 7642#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 7643#L982-1 assume !(0 == ~E_4~0); 6877#L987-1 assume !(0 == ~E_5~0); 6878#L992-1 assume !(0 == ~E_6~0); 6884#L997-1 assume !(0 == ~E_7~0); 7307#L1002-1 assume !(0 == ~E_8~0); 7294#L1007-1 assume !(0 == ~E_9~0); 6671#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6672#L443 assume !(1 == ~m_pc~0); 7544#L443-2 is_master_triggered_~__retres1~0#1 := 0; 7536#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7537#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7039#L1140 assume !(0 != activate_threads_~tmp~1#1); 6776#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6777#L462 assume 1 == ~t1_pc~0; 7425#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7392#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6713#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6714#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 7248#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7249#L481 assume !(1 == ~t2_pc~0); 7033#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7032#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7159#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7123#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 7124#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7218#L500 assume 1 == ~t3_pc~0; 7444#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7445#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6678#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6679#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 6676#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6677#L519 assume 1 == ~t4_pc~0; 6976#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 6977#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6778#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6779#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 7075#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6840#L538 assume !(1 == ~t5_pc~0); 6841#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6738#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6739#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7019#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7020#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7573#L557 assume 1 == ~t6_pc~0; 7366#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 7054#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7141#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7076#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 7077#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7748#L576 assume !(1 == ~t7_pc~0); 7043#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7044#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7365#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7758#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 7622#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7160#L595 assume 1 == ~t8_pc~0; 7161#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 7635#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7576#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7483#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 7484#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6969#L614 assume !(1 == ~t9_pc~0); 6970#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6866#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6867#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7192#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 7126#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7127#L1025 assume !(1 == ~M_E~0); 7385#L1025-2 assume !(1 == ~T1_E~0); 7443#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7566#L1035-1 assume !(1 == ~T3_E~0); 7119#L1040-1 assume !(1 == ~T4_E~0); 7120#L1045-1 assume !(1 == ~T5_E~0); 7029#L1050-1 assume !(1 == ~T6_E~0); 7030#L1055-1 assume !(1 == ~T7_E~0); 6851#L1060-1 assume !(1 == ~T8_E~0); 6852#L1065-1 assume !(1 == ~T9_E~0); 6916#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 7531#L1075-1 assume !(1 == ~E_2~0); 7532#L1080-1 assume !(1 == ~E_3~0); 7519#L1085-1 assume !(1 == ~E_4~0); 7520#L1090-1 assume !(1 == ~E_5~0); 7719#L1095-1 assume !(1 == ~E_6~0); 7553#L1100-1 assume !(1 == ~E_7~0); 7554#L1105-1 assume !(1 == ~E_8~0); 6822#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 6823#L1115-1 assume { :end_inline_reset_delta_events } true; 6988#L1396-2 [2023-11-29 04:11:46,349 INFO L750 eck$LassoCheckResult]: Loop: 6988#L1396-2 assume !false; 7065#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7723#L897-1 assume !false; 7746#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7657#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6696#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6697#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7180#L766 assume !(0 != eval_~tmp~0#1); 7581#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7335#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7289#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 7290#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7011#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 7012#L932-3 assume !(0 == ~T3_E~0); 7185#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6814#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6815#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 7186#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7187#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 7708#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7603#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 7604#L972-3 assume !(0 == ~E_2~0); 7522#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7523#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 7763#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7139#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 7140#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7137#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7138#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6853#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6854#L443-30 assume 1 == ~m_pc~0; 6887#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6888#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7166#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 7171#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7647#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7276#L462-30 assume 1 == ~t1_pc~0; 7110#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 7111#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7395#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7396#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 7671#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7261#L481-30 assume 1 == ~t2_pc~0; 6979#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 6980#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7069#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6948#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 6949#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7221#L500-30 assume 1 == ~t3_pc~0; 6984#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 6985#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7314#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7370#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 7205#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7206#L519-30 assume 1 == ~t4_pc~0; 7558#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7371#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7372#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7382#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7383#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7502#L538-30 assume !(1 == ~t5_pc~0); 6864#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 6863#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7188#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7488#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6942#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6943#L557-30 assume 1 == ~t6_pc~0; 6661#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 6663#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6782#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6783#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6967#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6968#L576-30 assume 1 == ~t7_pc~0; 7492#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6735#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7344#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7550#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7118#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7082#L595-30 assume !(1 == ~t8_pc~0); 7083#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 7023#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7024#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7717#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7718#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7749#L614-30 assume 1 == ~t9_pc~0; 7026#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 7027#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6700#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6701#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6855#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7476#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7250#L1025-5 assume !(1 == ~T1_E~0); 7251#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 7448#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 7727#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7759#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7722#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 7634#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6746#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6747#L1065-3 assume !(1 == ~T9_E~0); 7648#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 7505#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7506#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7728#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7639#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7640#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7659#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7660#L1105-3 assume !(1 == ~E_8~0); 6901#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6902#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7676#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6757#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6910#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 7102#L1415 assume !(0 == start_simulation_~tmp~3#1); 7376#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 7377#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 6810#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 6711#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 6712#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7764#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7367#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 6987#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 6988#L1396-2 [2023-11-29 04:11:46,349 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:46,350 INFO L85 PathProgramCache]: Analyzing trace with hash 1764315747, now seen corresponding path program 1 times [2023-11-29 04:11:46,350 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:46,350 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1150989801] [2023-11-29 04:11:46,350 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:46,350 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:46,364 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:46,397 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:46,398 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:46,398 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1150989801] [2023-11-29 04:11:46,398 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1150989801] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:46,398 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:46,398 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:46,399 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [680566574] [2023-11-29 04:11:46,399 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:46,399 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:46,400 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:46,400 INFO L85 PathProgramCache]: Analyzing trace with hash -321985611, now seen corresponding path program 1 times [2023-11-29 04:11:46,400 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:46,400 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1804297892] [2023-11-29 04:11:46,400 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:46,401 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:46,417 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:46,461 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:46,461 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:46,461 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1804297892] [2023-11-29 04:11:46,461 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1804297892] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:46,462 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:46,462 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:46,462 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1843533181] [2023-11-29 04:11:46,462 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:46,463 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:46,463 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:46,463 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:46,463 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:46,463 INFO L87 Difference]: Start difference. First operand 1104 states and 1638 transitions. cyclomatic complexity: 535 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:46,492 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:46,492 INFO L93 Difference]: Finished difference Result 1104 states and 1637 transitions. [2023-11-29 04:11:46,492 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1637 transitions. [2023-11-29 04:11:46,501 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:46,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1637 transitions. [2023-11-29 04:11:46,509 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-29 04:11:46,510 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-29 04:11:46,510 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1637 transitions. [2023-11-29 04:11:46,512 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:46,512 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2023-11-29 04:11:46,514 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1637 transitions. [2023-11-29 04:11:46,531 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-29 04:11:46,533 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4827898550724639) internal successors, (1637), 1103 states have internal predecessors, (1637), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:46,537 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1637 transitions. [2023-11-29 04:11:46,537 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2023-11-29 04:11:46,537 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:46,538 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1637 transitions. [2023-11-29 04:11:46,538 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 04:11:46,538 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1637 transitions. [2023-11-29 04:11:46,543 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:46,543 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:46,543 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:46,545 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:46,545 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:46,545 INFO L748 eck$LassoCheckResult]: Stem: 9161#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 9162#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 9918#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9919#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9870#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 9871#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9853#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9675#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9676#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9484#L661-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 9485#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 9940#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 9845#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 9544#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9315#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9316#L922 assume !(0 == ~M_E~0); 9976#L922-2 assume !(0 == ~T1_E~0); 9977#L927-1 assume !(0 == ~T2_E~0); 9739#L932-1 assume !(0 == ~T3_E~0); 9614#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9615#L942-1 assume !(0 == ~T5_E~0); 9674#L947-1 assume !(0 == ~T6_E~0); 9743#L952-1 assume !(0 == ~T7_E~0); 9744#L957-1 assume !(0 == ~T8_E~0); 9803#L962-1 assume !(0 == ~T9_E~0); 9593#L967-1 assume !(0 == ~E_1~0); 9594#L972-1 assume !(0 == ~E_2~0); 9857#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 9858#L982-1 assume !(0 == ~E_4~0); 9092#L987-1 assume !(0 == ~E_5~0); 9093#L992-1 assume !(0 == ~E_6~0); 9099#L997-1 assume !(0 == ~E_7~0); 9522#L1002-1 assume !(0 == ~E_8~0); 9509#L1007-1 assume !(0 == ~E_9~0); 8886#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8887#L443 assume !(1 == ~m_pc~0); 9759#L443-2 is_master_triggered_~__retres1~0#1 := 0; 9751#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9752#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9254#L1140 assume !(0 != activate_threads_~tmp~1#1); 8991#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8992#L462 assume 1 == ~t1_pc~0; 9640#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9609#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8930#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8931#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 9463#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9464#L481 assume !(1 == ~t2_pc~0); 9248#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9247#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9374#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9338#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 9339#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9433#L500 assume 1 == ~t3_pc~0; 9659#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 9660#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8893#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8894#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 8891#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8892#L519 assume 1 == ~t4_pc~0; 9194#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 9195#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8993#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8994#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 9290#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9055#L538 assume !(1 == ~t5_pc~0); 9056#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8953#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8954#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9234#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9235#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9788#L557 assume 1 == ~t6_pc~0; 9581#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 9269#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9356#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9291#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 9292#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9963#L576 assume !(1 == ~t7_pc~0); 9258#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9259#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9580#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9973#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 9837#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9377#L595 assume 1 == ~t8_pc~0; 9378#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 9850#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9791#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9698#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 9699#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9184#L614 assume !(1 == ~t9_pc~0); 9185#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9081#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9082#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9407#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 9341#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9342#L1025 assume !(1 == ~M_E~0); 9600#L1025-2 assume !(1 == ~T1_E~0); 9658#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9781#L1035-1 assume !(1 == ~T3_E~0); 9334#L1040-1 assume !(1 == ~T4_E~0); 9335#L1045-1 assume !(1 == ~T5_E~0); 9244#L1050-1 assume !(1 == ~T6_E~0); 9245#L1055-1 assume !(1 == ~T7_E~0); 9066#L1060-1 assume !(1 == ~T8_E~0); 9067#L1065-1 assume !(1 == ~T9_E~0); 9131#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 9746#L1075-1 assume !(1 == ~E_2~0); 9747#L1080-1 assume !(1 == ~E_3~0); 9734#L1085-1 assume !(1 == ~E_4~0); 9735#L1090-1 assume !(1 == ~E_5~0); 9934#L1095-1 assume !(1 == ~E_6~0); 9768#L1100-1 assume !(1 == ~E_7~0); 9769#L1105-1 assume !(1 == ~E_8~0); 9037#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 9038#L1115-1 assume { :end_inline_reset_delta_events } true; 9203#L1396-2 [2023-11-29 04:11:46,546 INFO L750 eck$LassoCheckResult]: Loop: 9203#L1396-2 assume !false; 9283#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9938#L897-1 assume !false; 9961#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9872#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8911#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8912#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9395#L766 assume !(0 != eval_~tmp~0#1); 9797#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9552#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9504#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 9505#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9226#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 9227#L932-3 assume !(0 == ~T3_E~0); 9400#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9029#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9030#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 9401#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9402#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 9923#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9818#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 9819#L972-3 assume !(0 == ~E_2~0); 9737#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9738#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9978#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9354#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 9355#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9352#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9353#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 9068#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9069#L443-30 assume !(1 == ~m_pc~0); 9104#L443-32 is_master_triggered_~__retres1~0#1 := 0; 9103#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9381#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 9386#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9861#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9491#L462-30 assume 1 == ~t1_pc~0; 9323#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 9324#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9610#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9611#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 9886#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9476#L481-30 assume 1 == ~t2_pc~0; 9191#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9192#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9284#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9163#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 9164#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9436#L500-30 assume !(1 == ~t3_pc~0); 9201#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 9200#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9529#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9585#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 9420#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9421#L519-30 assume !(1 == ~t4_pc~0); 9607#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 9586#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9587#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9597#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 9598#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9717#L538-30 assume 1 == ~t5_pc~0; 9077#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 9078#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9403#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9703#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 9157#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9158#L557-30 assume 1 == ~t6_pc~0; 8876#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8878#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8997#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8998#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 9182#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9183#L576-30 assume !(1 == ~t7_pc~0); 8949#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 8950#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9559#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9766#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9333#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9297#L595-30 assume !(1 == ~t8_pc~0); 9298#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 9238#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9239#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9932#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9933#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9964#L614-30 assume 1 == ~t9_pc~0; 9241#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9242#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8915#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8916#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9070#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9691#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9465#L1025-5 assume !(1 == ~T1_E~0); 9466#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9663#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 9942#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9974#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9937#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 9849#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8961#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8962#L1065-3 assume !(1 == ~T9_E~0); 9863#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 9720#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9721#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9943#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 9854#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9855#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9874#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9875#L1105-3 assume !(1 == ~E_8~0); 9116#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9117#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9891#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 8972#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 9125#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 9317#L1415 assume !(0 == start_simulation_~tmp~3#1); 9591#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 9592#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 9025#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 8926#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 8927#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9979#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9582#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 9202#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 9203#L1396-2 [2023-11-29 04:11:46,546 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:46,546 INFO L85 PathProgramCache]: Analyzing trace with hash -388791071, now seen corresponding path program 1 times [2023-11-29 04:11:46,547 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:46,547 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [550607770] [2023-11-29 04:11:46,547 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:46,547 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:46,559 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:46,596 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:46,597 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:46,597 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [550607770] [2023-11-29 04:11:46,597 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [550607770] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:46,597 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:46,598 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:46,598 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [347773229] [2023-11-29 04:11:46,598 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:46,599 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:46,599 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:46,599 INFO L85 PathProgramCache]: Analyzing trace with hash -1993645742, now seen corresponding path program 1 times [2023-11-29 04:11:46,599 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:46,600 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [354445233] [2023-11-29 04:11:46,600 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:46,600 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:46,621 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:46,676 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:46,677 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:46,677 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [354445233] [2023-11-29 04:11:46,677 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [354445233] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:46,677 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:46,677 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:46,678 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [78789283] [2023-11-29 04:11:46,678 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:46,678 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:46,678 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:46,679 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:46,679 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:46,679 INFO L87 Difference]: Start difference. First operand 1104 states and 1637 transitions. cyclomatic complexity: 534 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:46,715 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:46,715 INFO L93 Difference]: Finished difference Result 1104 states and 1636 transitions. [2023-11-29 04:11:46,715 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1636 transitions. [2023-11-29 04:11:46,724 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:46,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1636 transitions. [2023-11-29 04:11:46,733 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-29 04:11:46,735 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-29 04:11:46,735 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1636 transitions. [2023-11-29 04:11:46,737 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:46,737 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2023-11-29 04:11:46,740 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1636 transitions. [2023-11-29 04:11:46,759 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-29 04:11:46,762 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4818840579710144) internal successors, (1636), 1103 states have internal predecessors, (1636), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:46,766 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1636 transitions. [2023-11-29 04:11:46,766 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2023-11-29 04:11:46,767 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:46,767 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1636 transitions. [2023-11-29 04:11:46,768 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 04:11:46,768 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1636 transitions. [2023-11-29 04:11:46,775 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:46,775 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:46,775 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:46,777 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:46,778 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:46,778 INFO L748 eck$LassoCheckResult]: Stem: 11376#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 11377#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 12133#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12134#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12085#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 12086#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12068#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 11890#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 11891#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 11699#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 11700#L666-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 12155#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 12060#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11759#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11530#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 11531#L922 assume !(0 == ~M_E~0); 12191#L922-2 assume !(0 == ~T1_E~0); 12192#L927-1 assume !(0 == ~T2_E~0); 11954#L932-1 assume !(0 == ~T3_E~0); 11829#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11830#L942-1 assume !(0 == ~T5_E~0); 11889#L947-1 assume !(0 == ~T6_E~0); 11958#L952-1 assume !(0 == ~T7_E~0); 11959#L957-1 assume !(0 == ~T8_E~0); 12019#L962-1 assume !(0 == ~T9_E~0); 11808#L967-1 assume !(0 == ~E_1~0); 11809#L972-1 assume !(0 == ~E_2~0); 12072#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 12073#L982-1 assume !(0 == ~E_4~0); 11309#L987-1 assume !(0 == ~E_5~0); 11310#L992-1 assume !(0 == ~E_6~0); 11314#L997-1 assume !(0 == ~E_7~0); 11737#L1002-1 assume !(0 == ~E_8~0); 11724#L1007-1 assume !(0 == ~E_9~0); 11101#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11102#L443 assume !(1 == ~m_pc~0); 11974#L443-2 is_master_triggered_~__retres1~0#1 := 0; 11966#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11967#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11469#L1140 assume !(0 != activate_threads_~tmp~1#1); 11206#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11207#L462 assume 1 == ~t1_pc~0; 11855#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11824#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11145#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11146#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 11678#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11679#L481 assume !(1 == ~t2_pc~0); 11463#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 11462#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11589#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11553#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 11554#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11648#L500 assume 1 == ~t3_pc~0; 11874#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11875#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11108#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11109#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 11106#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11107#L519 assume 1 == ~t4_pc~0; 11409#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11410#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11208#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11209#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 11505#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11270#L538 assume !(1 == ~t5_pc~0); 11271#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 11170#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11171#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11449#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11450#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12003#L557 assume 1 == ~t6_pc~0; 11796#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11484#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11571#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11506#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 11507#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12178#L576 assume !(1 == ~t7_pc~0); 11473#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 11474#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11795#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12188#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 12052#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11592#L595 assume 1 == ~t8_pc~0; 11593#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 12065#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12008#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11913#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 11914#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11399#L614 assume !(1 == ~t9_pc~0); 11400#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11296#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11297#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11622#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 11556#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11557#L1025 assume !(1 == ~M_E~0); 11815#L1025-2 assume !(1 == ~T1_E~0); 11873#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11997#L1035-1 assume !(1 == ~T3_E~0); 11549#L1040-1 assume !(1 == ~T4_E~0); 11550#L1045-1 assume !(1 == ~T5_E~0); 11459#L1050-1 assume !(1 == ~T6_E~0); 11460#L1055-1 assume !(1 == ~T7_E~0); 11281#L1060-1 assume !(1 == ~T8_E~0); 11282#L1065-1 assume !(1 == ~T9_E~0); 11346#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 11961#L1075-1 assume !(1 == ~E_2~0); 11962#L1080-1 assume !(1 == ~E_3~0); 11949#L1085-1 assume !(1 == ~E_4~0); 11950#L1090-1 assume !(1 == ~E_5~0); 12149#L1095-1 assume !(1 == ~E_6~0); 11983#L1100-1 assume !(1 == ~E_7~0); 11984#L1105-1 assume !(1 == ~E_8~0); 11252#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 11253#L1115-1 assume { :end_inline_reset_delta_events } true; 11418#L1396-2 [2023-11-29 04:11:46,779 INFO L750 eck$LassoCheckResult]: Loop: 11418#L1396-2 assume !false; 11498#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12153#L897-1 assume !false; 12176#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12087#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11126#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11127#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 11610#L766 assume !(0 != eval_~tmp~0#1); 12012#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11767#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 11719#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 11720#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11441#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11442#L932-3 assume !(0 == ~T3_E~0); 11615#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11244#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11245#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11616#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11617#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 12138#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12033#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 12034#L972-3 assume !(0 == ~E_2~0); 11952#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 11953#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 12193#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 11569#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 11570#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 11564#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 11565#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11283#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11284#L443-30 assume 1 == ~m_pc~0; 11317#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 11318#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11596#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 11601#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12076#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11706#L462-30 assume 1 == ~t1_pc~0; 11538#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11539#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11825#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11826#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 12101#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11691#L481-30 assume !(1 == ~t2_pc~0); 11408#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 11407#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 11499#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 11378#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 11379#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11651#L500-30 assume 1 == ~t3_pc~0; 11414#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 11415#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 11744#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11800#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11635#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11636#L519-30 assume 1 == ~t4_pc~0; 11988#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 11801#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 11802#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 11812#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11813#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 11932#L538-30 assume 1 == ~t5_pc~0; 11292#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 11293#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11619#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11919#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11372#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11373#L557-30 assume 1 == ~t6_pc~0; 11091#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 11093#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 11212#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11213#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 11397#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11398#L576-30 assume 1 == ~t7_pc~0; 11922#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 11167#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11774#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 11981#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11548#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 11512#L595-30 assume !(1 == ~t8_pc~0); 11513#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 11453#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11454#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12147#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 12148#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12179#L614-30 assume 1 == ~t9_pc~0; 11456#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 11457#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11130#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11131#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 11285#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11906#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11680#L1025-5 assume !(1 == ~T1_E~0); 11681#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11878#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 12157#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12189#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12152#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 12064#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11176#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11177#L1065-3 assume !(1 == ~T9_E~0); 12078#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 11935#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 11936#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12158#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 12069#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12070#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12089#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12090#L1105-3 assume !(1 == ~E_8~0); 11331#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 11332#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 12106#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11187#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11340#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 11532#L1415 assume !(0 == start_simulation_~tmp~3#1); 11806#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 11807#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 11240#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 11141#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 11142#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12194#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11797#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 11417#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 11418#L1396-2 [2023-11-29 04:11:46,779 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:46,780 INFO L85 PathProgramCache]: Analyzing trace with hash 234490531, now seen corresponding path program 1 times [2023-11-29 04:11:46,780 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:46,780 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [184249844] [2023-11-29 04:11:46,780 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:46,780 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:46,797 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:46,835 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:46,835 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:46,835 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [184249844] [2023-11-29 04:11:46,835 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [184249844] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:46,835 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:46,835 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:46,836 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [208883220] [2023-11-29 04:11:46,836 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:46,836 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:46,837 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:46,837 INFO L85 PathProgramCache]: Analyzing trace with hash -1124783627, now seen corresponding path program 1 times [2023-11-29 04:11:46,837 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:46,837 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [892379376] [2023-11-29 04:11:46,837 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:46,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:46,854 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:46,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:46,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:46,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [892379376] [2023-11-29 04:11:46,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [892379376] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:46,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:46,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:46,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [535514912] [2023-11-29 04:11:46,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:46,899 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:46,899 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:46,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:46,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:46,900 INFO L87 Difference]: Start difference. First operand 1104 states and 1636 transitions. cyclomatic complexity: 533 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:46,927 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:46,928 INFO L93 Difference]: Finished difference Result 1104 states and 1635 transitions. [2023-11-29 04:11:46,928 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1635 transitions. [2023-11-29 04:11:46,936 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:46,944 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1635 transitions. [2023-11-29 04:11:46,945 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-29 04:11:46,946 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-29 04:11:46,946 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1635 transitions. [2023-11-29 04:11:46,948 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:46,948 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2023-11-29 04:11:46,950 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1635 transitions. [2023-11-29 04:11:46,966 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-29 04:11:46,969 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4809782608695652) internal successors, (1635), 1103 states have internal predecessors, (1635), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:46,972 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1635 transitions. [2023-11-29 04:11:46,973 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2023-11-29 04:11:46,973 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:46,974 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1635 transitions. [2023-11-29 04:11:46,974 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 04:11:46,974 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1635 transitions. [2023-11-29 04:11:46,980 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:46,980 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:46,980 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:46,982 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:46,982 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:46,983 INFO L748 eck$LassoCheckResult]: Stem: 13591#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 13592#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 14348#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14349#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14300#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 14301#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14283#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 14105#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 14106#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13914#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 13915#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 14370#L671-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14275#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 13974#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 13745#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13746#L922 assume !(0 == ~M_E~0); 14406#L922-2 assume !(0 == ~T1_E~0); 14407#L927-1 assume !(0 == ~T2_E~0); 14169#L932-1 assume !(0 == ~T3_E~0); 14044#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 14045#L942-1 assume !(0 == ~T5_E~0); 14104#L947-1 assume !(0 == ~T6_E~0); 14173#L952-1 assume !(0 == ~T7_E~0); 14174#L957-1 assume !(0 == ~T8_E~0); 14234#L962-1 assume !(0 == ~T9_E~0); 14025#L967-1 assume !(0 == ~E_1~0); 14026#L972-1 assume !(0 == ~E_2~0); 14287#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 14288#L982-1 assume !(0 == ~E_4~0); 13524#L987-1 assume !(0 == ~E_5~0); 13525#L992-1 assume !(0 == ~E_6~0); 13529#L997-1 assume !(0 == ~E_7~0); 13952#L1002-1 assume !(0 == ~E_8~0); 13939#L1007-1 assume !(0 == ~E_9~0); 13316#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13317#L443 assume !(1 == ~m_pc~0); 14189#L443-2 is_master_triggered_~__retres1~0#1 := 0; 14181#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 14182#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13684#L1140 assume !(0 != activate_threads_~tmp~1#1); 13421#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13422#L462 assume 1 == ~t1_pc~0; 14070#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 14039#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13360#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 13361#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 13893#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13894#L481 assume !(1 == ~t2_pc~0); 13678#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13677#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13804#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13768#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 13769#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13863#L500 assume 1 == ~t3_pc~0; 14089#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 14090#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13323#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13324#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 13321#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13322#L519 assume 1 == ~t4_pc~0; 13624#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13625#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13423#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13424#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 13720#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13485#L538 assume !(1 == ~t5_pc~0); 13486#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 13385#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13386#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 13664#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13665#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14219#L557 assume 1 == ~t6_pc~0; 14011#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13699#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13786#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13721#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 13722#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14393#L576 assume !(1 == ~t7_pc~0); 13688#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13689#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14010#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14403#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 14267#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13805#L595 assume 1 == ~t8_pc~0; 13806#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 14280#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14221#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14128#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 14129#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13614#L614 assume !(1 == ~t9_pc~0); 13615#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13510#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13511#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13837#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 13771#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13772#L1025 assume !(1 == ~M_E~0); 14030#L1025-2 assume !(1 == ~T1_E~0); 14088#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14211#L1035-1 assume !(1 == ~T3_E~0); 13763#L1040-1 assume !(1 == ~T4_E~0); 13764#L1045-1 assume !(1 == ~T5_E~0); 13674#L1050-1 assume !(1 == ~T6_E~0); 13675#L1055-1 assume !(1 == ~T7_E~0); 13496#L1060-1 assume !(1 == ~T8_E~0); 13497#L1065-1 assume !(1 == ~T9_E~0); 13561#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 14175#L1075-1 assume !(1 == ~E_2~0); 14176#L1080-1 assume !(1 == ~E_3~0); 14164#L1085-1 assume !(1 == ~E_4~0); 14165#L1090-1 assume !(1 == ~E_5~0); 14364#L1095-1 assume !(1 == ~E_6~0); 14198#L1100-1 assume !(1 == ~E_7~0); 14199#L1105-1 assume !(1 == ~E_8~0); 13467#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 13468#L1115-1 assume { :end_inline_reset_delta_events } true; 13635#L1396-2 [2023-11-29 04:11:46,983 INFO L750 eck$LassoCheckResult]: Loop: 13635#L1396-2 assume !false; 13710#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 14368#L897-1 assume !false; 14391#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14302#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13339#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13340#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13825#L766 assume !(0 != eval_~tmp~0#1); 14226#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13979#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13931#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 13932#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 13656#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 13657#L932-3 assume !(0 == ~T3_E~0); 13830#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13459#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13460#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 13831#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 13832#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 14353#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14248#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 14249#L972-3 assume !(0 == ~E_2~0); 14167#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 14168#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14408#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13784#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 13785#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13779#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13780#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 13498#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13499#L443-30 assume 1 == ~m_pc~0; 13532#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 13533#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13811#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 13816#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 14291#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13921#L462-30 assume 1 == ~t1_pc~0; 13753#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13754#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 14040#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14041#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 14316#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13906#L481-30 assume 1 == ~t2_pc~0; 13621#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 13622#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13714#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13593#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 13594#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13866#L500-30 assume 1 == ~t3_pc~0; 13629#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13630#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 13959#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14015#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13850#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13851#L519-30 assume !(1 == ~t4_pc~0); 14037#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 14016#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 14017#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 14027#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 14028#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14147#L538-30 assume 1 == ~t5_pc~0; 13507#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13508#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13834#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14134#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13587#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13588#L557-30 assume 1 == ~t6_pc~0; 13306#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13308#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13427#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13428#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13612#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13613#L576-30 assume !(1 == ~t7_pc~0); 13381#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 13382#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 13989#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 14196#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13765#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13727#L595-30 assume !(1 == ~t8_pc~0); 13728#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 13668#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13669#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14362#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 14363#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 14394#L614-30 assume 1 == ~t9_pc~0; 13671#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 13672#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13345#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13346#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 13500#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14121#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 13895#L1025-5 assume !(1 == ~T1_E~0); 13896#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14093#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 14372#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 14404#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 14367#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 14279#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13391#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 13392#L1065-3 assume !(1 == ~T9_E~0); 14293#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 14150#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 14151#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14373#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 14284#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 14285#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 14304#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 14305#L1105-3 assume !(1 == ~E_8~0); 13546#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 13547#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14321#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13402#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13555#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 13747#L1415 assume !(0 == start_simulation_~tmp~3#1); 14021#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 14022#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 13455#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 13356#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 13357#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 14409#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 14012#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 13634#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 13635#L1396-2 [2023-11-29 04:11:46,984 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:46,984 INFO L85 PathProgramCache]: Analyzing trace with hash 116049057, now seen corresponding path program 1 times [2023-11-29 04:11:46,984 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:46,984 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1087785469] [2023-11-29 04:11:46,985 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:46,985 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:46,998 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:47,030 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:47,030 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:47,030 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1087785469] [2023-11-29 04:11:47,031 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1087785469] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:47,031 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:47,031 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:47,031 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [464256981] [2023-11-29 04:11:47,031 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:47,031 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:47,032 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:47,032 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 2 times [2023-11-29 04:11:47,032 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:47,032 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [239335662] [2023-11-29 04:11:47,032 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:47,033 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:47,049 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:47,092 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:47,092 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:47,093 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [239335662] [2023-11-29 04:11:47,093 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [239335662] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:47,093 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:47,093 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:47,093 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1680802770] [2023-11-29 04:11:47,093 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:47,094 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:47,094 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:47,094 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:47,094 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:47,094 INFO L87 Difference]: Start difference. First operand 1104 states and 1635 transitions. cyclomatic complexity: 532 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:47,122 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:47,122 INFO L93 Difference]: Finished difference Result 1104 states and 1634 transitions. [2023-11-29 04:11:47,123 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1634 transitions. [2023-11-29 04:11:47,130 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:47,138 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1634 transitions. [2023-11-29 04:11:47,139 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-29 04:11:47,140 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-29 04:11:47,140 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1634 transitions. [2023-11-29 04:11:47,142 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:47,142 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2023-11-29 04:11:47,144 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1634 transitions. [2023-11-29 04:11:47,160 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-29 04:11:47,162 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.480072463768116) internal successors, (1634), 1103 states have internal predecessors, (1634), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:47,166 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1634 transitions. [2023-11-29 04:11:47,166 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2023-11-29 04:11:47,167 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:47,167 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1634 transitions. [2023-11-29 04:11:47,167 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 04:11:47,167 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1634 transitions. [2023-11-29 04:11:47,173 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:47,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:47,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:47,176 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:47,176 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:47,176 INFO L748 eck$LassoCheckResult]: Stem: 15804#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 15805#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 16563#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16564#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16515#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 16516#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16498#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16320#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 16321#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 16128#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16129#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16584#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 16489#L676-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16189#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 15960#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15961#L922 assume !(0 == ~M_E~0); 16621#L922-2 assume !(0 == ~T1_E~0); 16622#L927-1 assume !(0 == ~T2_E~0); 16384#L932-1 assume !(0 == ~T3_E~0); 16259#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16260#L942-1 assume !(0 == ~T5_E~0); 16319#L947-1 assume !(0 == ~T6_E~0); 16388#L952-1 assume !(0 == ~T7_E~0); 16389#L957-1 assume !(0 == ~T8_E~0); 16446#L962-1 assume !(0 == ~T9_E~0); 16238#L967-1 assume !(0 == ~E_1~0); 16239#L972-1 assume !(0 == ~E_2~0); 16502#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 16503#L982-1 assume !(0 == ~E_4~0); 15737#L987-1 assume !(0 == ~E_5~0); 15738#L992-1 assume !(0 == ~E_6~0); 15744#L997-1 assume !(0 == ~E_7~0); 16165#L1002-1 assume !(0 == ~E_8~0); 16154#L1007-1 assume !(0 == ~E_9~0); 15531#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15532#L443 assume !(1 == ~m_pc~0); 16404#L443-2 is_master_triggered_~__retres1~0#1 := 0; 16396#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16397#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 15899#L1140 assume !(0 != activate_threads_~tmp~1#1); 15636#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 15637#L462 assume 1 == ~t1_pc~0; 16285#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16251#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15573#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15574#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 16106#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16107#L481 assume !(1 == ~t2_pc~0); 15893#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15892#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 16019#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15983#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 15984#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16076#L500 assume 1 == ~t3_pc~0; 16304#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16305#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15538#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 15539#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 15533#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 15534#L519 assume 1 == ~t4_pc~0; 15836#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15837#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15638#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15639#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 15933#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15700#L538 assume !(1 == ~t5_pc~0); 15701#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 15598#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15599#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15879#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15880#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16431#L557 assume 1 == ~t6_pc~0; 16226#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15914#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16001#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15934#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 15935#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16608#L576 assume !(1 == ~t7_pc~0); 15903#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15904#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16225#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16618#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 16482#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16020#L595 assume 1 == ~t8_pc~0; 16021#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16495#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16436#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16343#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 16344#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 15829#L614 assume !(1 == ~t9_pc~0); 15830#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 15725#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15726#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16052#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 15986#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 15987#L1025 assume !(1 == ~M_E~0); 16245#L1025-2 assume !(1 == ~T1_E~0); 16303#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16426#L1035-1 assume !(1 == ~T3_E~0); 15978#L1040-1 assume !(1 == ~T4_E~0); 15979#L1045-1 assume !(1 == ~T5_E~0); 15889#L1050-1 assume !(1 == ~T6_E~0); 15890#L1055-1 assume !(1 == ~T7_E~0); 15711#L1060-1 assume !(1 == ~T8_E~0); 15712#L1065-1 assume !(1 == ~T9_E~0); 15776#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 16390#L1075-1 assume !(1 == ~E_2~0); 16391#L1080-1 assume !(1 == ~E_3~0); 16379#L1085-1 assume !(1 == ~E_4~0); 16380#L1090-1 assume !(1 == ~E_5~0); 16579#L1095-1 assume !(1 == ~E_6~0); 16413#L1100-1 assume !(1 == ~E_7~0); 16414#L1105-1 assume !(1 == ~E_8~0); 15682#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 15683#L1115-1 assume { :end_inline_reset_delta_events } true; 15850#L1396-2 [2023-11-29 04:11:47,191 INFO L750 eck$LassoCheckResult]: Loop: 15850#L1396-2 assume !false; 15925#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16583#L897-1 assume !false; 16606#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16517#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15554#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15555#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16040#L766 assume !(0 != eval_~tmp~0#1); 16441#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16194#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16146#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 16147#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 15871#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 15872#L932-3 assume !(0 == ~T3_E~0); 16045#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 15674#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 15675#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16046#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16047#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 16568#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16463#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 16464#L972-3 assume !(0 == ~E_2~0); 16382#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 16383#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16623#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15999#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 16000#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15994#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15995#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 15713#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 15714#L443-30 assume 1 == ~m_pc~0; 15747#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 15748#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16026#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 16031#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 16506#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16136#L462-30 assume 1 == ~t1_pc~0; 15968#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 15969#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16255#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16256#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 16531#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16121#L481-30 assume !(1 == ~t2_pc~0); 15841#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 15840#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15929#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15808#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 15809#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16081#L500-30 assume 1 == ~t3_pc~0; 15844#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15845#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16174#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16230#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16065#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16066#L519-30 assume 1 == ~t4_pc~0; 16418#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 16231#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 16232#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 16242#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16243#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 16362#L538-30 assume 1 == ~t5_pc~0; 15722#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15723#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16049#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16349#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 15802#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 15803#L557-30 assume 1 == ~t6_pc~0; 15521#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15523#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 15642#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 15643#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15827#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 15828#L576-30 assume 1 == ~t7_pc~0; 16352#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 15597#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16204#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16411#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 15980#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15942#L595-30 assume !(1 == ~t8_pc~0); 15943#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 15883#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 15884#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16577#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16578#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16609#L614-30 assume !(1 == ~t9_pc~0); 15888#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 15887#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15560#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 15561#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 15715#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16336#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16110#L1025-5 assume !(1 == ~T1_E~0); 16111#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16308#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 16587#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 16619#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16582#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16494#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 15606#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 15607#L1065-3 assume !(1 == ~T9_E~0); 16508#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 16365#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16366#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16588#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 16499#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 16500#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 16519#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 16520#L1105-3 assume !(1 == ~E_8~0); 15761#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 15762#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16536#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15617#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15770#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 15962#L1415 assume !(0 == start_simulation_~tmp~3#1); 16236#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 16237#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 15670#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 15571#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 15572#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 16624#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16227#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 15849#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 15850#L1396-2 [2023-11-29 04:11:47,192 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:47,192 INFO L85 PathProgramCache]: Analyzing trace with hash -1273244957, now seen corresponding path program 1 times [2023-11-29 04:11:47,193 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:47,193 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095791686] [2023-11-29 04:11:47,193 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:47,193 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:47,206 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:47,235 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:47,235 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:47,236 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095791686] [2023-11-29 04:11:47,236 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095791686] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:47,236 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:47,236 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:47,236 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [366794218] [2023-11-29 04:11:47,236 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:47,237 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:47,237 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:47,237 INFO L85 PathProgramCache]: Analyzing trace with hash -601462956, now seen corresponding path program 1 times [2023-11-29 04:11:47,237 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:47,238 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1390659749] [2023-11-29 04:11:47,238 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:47,238 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:47,253 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:47,295 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:47,296 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:47,296 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1390659749] [2023-11-29 04:11:47,296 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1390659749] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:47,296 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:47,296 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:47,296 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1709990689] [2023-11-29 04:11:47,297 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:47,297 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:47,297 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:47,297 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:47,298 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:47,298 INFO L87 Difference]: Start difference. First operand 1104 states and 1634 transitions. cyclomatic complexity: 531 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:47,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:47,326 INFO L93 Difference]: Finished difference Result 1104 states and 1633 transitions. [2023-11-29 04:11:47,326 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1104 states and 1633 transitions. [2023-11-29 04:11:47,334 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:47,342 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1104 states to 1104 states and 1633 transitions. [2023-11-29 04:11:47,342 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1104 [2023-11-29 04:11:47,344 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1104 [2023-11-29 04:11:47,344 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1104 states and 1633 transitions. [2023-11-29 04:11:47,346 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:47,346 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2023-11-29 04:11:47,348 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1104 states and 1633 transitions. [2023-11-29 04:11:47,363 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1104 to 1104. [2023-11-29 04:11:47,365 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1104 states, 1104 states have (on average 1.4791666666666667) internal successors, (1633), 1103 states have internal predecessors, (1633), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:47,369 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1104 states to 1104 states and 1633 transitions. [2023-11-29 04:11:47,369 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2023-11-29 04:11:47,370 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:47,370 INFO L428 stractBuchiCegarLoop]: Abstraction has 1104 states and 1633 transitions. [2023-11-29 04:11:47,370 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 04:11:47,371 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1104 states and 1633 transitions. [2023-11-29 04:11:47,375 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 979 [2023-11-29 04:11:47,375 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:47,375 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:47,377 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:47,377 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:47,377 INFO L748 eck$LassoCheckResult]: Stem: 18019#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 18020#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 18778#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 18779#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 18730#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 18731#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 18713#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18535#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18536#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18343#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 18344#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 18799#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 18704#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 18404#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 18175#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18176#L922 assume !(0 == ~M_E~0); 18836#L922-2 assume !(0 == ~T1_E~0); 18837#L927-1 assume !(0 == ~T2_E~0); 18599#L932-1 assume !(0 == ~T3_E~0); 18474#L937-1 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18475#L942-1 assume !(0 == ~T5_E~0); 18534#L947-1 assume !(0 == ~T6_E~0); 18603#L952-1 assume !(0 == ~T7_E~0); 18604#L957-1 assume !(0 == ~T8_E~0); 18661#L962-1 assume !(0 == ~T9_E~0); 18453#L967-1 assume !(0 == ~E_1~0); 18454#L972-1 assume !(0 == ~E_2~0); 18717#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 18718#L982-1 assume !(0 == ~E_4~0); 17952#L987-1 assume !(0 == ~E_5~0); 17953#L992-1 assume !(0 == ~E_6~0); 17959#L997-1 assume !(0 == ~E_7~0); 18380#L1002-1 assume !(0 == ~E_8~0); 18369#L1007-1 assume !(0 == ~E_9~0); 17746#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17747#L443 assume !(1 == ~m_pc~0); 18619#L443-2 is_master_triggered_~__retres1~0#1 := 0; 18611#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18612#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18114#L1140 assume !(0 != activate_threads_~tmp~1#1); 17851#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 17852#L462 assume 1 == ~t1_pc~0; 18500#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18466#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 17788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 17789#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 18321#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18322#L481 assume !(1 == ~t2_pc~0); 18108#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18107#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18234#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18198#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 18199#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18291#L500 assume 1 == ~t3_pc~0; 18519#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18520#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 17753#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 17754#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 17748#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 17749#L519 assume 1 == ~t4_pc~0; 18051#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18052#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 17853#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 17854#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 18148#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 17915#L538 assume !(1 == ~t5_pc~0); 17916#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 17813#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 17814#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18094#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18095#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18646#L557 assume 1 == ~t6_pc~0; 18441#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18129#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18216#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 18149#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 18150#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18823#L576 assume !(1 == ~t7_pc~0); 18118#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18119#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18440#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18833#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 18697#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18235#L595 assume 1 == ~t8_pc~0; 18236#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18710#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18651#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18558#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 18559#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18044#L614 assume !(1 == ~t9_pc~0); 18045#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 17940#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17941#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 18267#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 18201#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18202#L1025 assume !(1 == ~M_E~0); 18460#L1025-2 assume !(1 == ~T1_E~0); 18518#L1030-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18641#L1035-1 assume !(1 == ~T3_E~0); 18193#L1040-1 assume !(1 == ~T4_E~0); 18194#L1045-1 assume !(1 == ~T5_E~0); 18104#L1050-1 assume !(1 == ~T6_E~0); 18105#L1055-1 assume !(1 == ~T7_E~0); 17926#L1060-1 assume !(1 == ~T8_E~0); 17927#L1065-1 assume !(1 == ~T9_E~0); 17991#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 18605#L1075-1 assume !(1 == ~E_2~0); 18606#L1080-1 assume !(1 == ~E_3~0); 18594#L1085-1 assume !(1 == ~E_4~0); 18595#L1090-1 assume !(1 == ~E_5~0); 18794#L1095-1 assume !(1 == ~E_6~0); 18628#L1100-1 assume !(1 == ~E_7~0); 18629#L1105-1 assume !(1 == ~E_8~0); 17897#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 17898#L1115-1 assume { :end_inline_reset_delta_events } true; 18065#L1396-2 [2023-11-29 04:11:47,378 INFO L750 eck$LassoCheckResult]: Loop: 18065#L1396-2 assume !false; 18140#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18798#L897-1 assume !false; 18821#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18732#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17769#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17770#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18255#L766 assume !(0 != eval_~tmp~0#1); 18656#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18409#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18361#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 18362#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 18086#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 18087#L932-3 assume !(0 == ~T3_E~0); 18260#L937-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 17889#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 17890#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 18261#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 18262#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 18783#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 18678#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18679#L972-3 assume !(0 == ~E_2~0); 18597#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18598#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 18838#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18214#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 18215#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18209#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18210#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 17928#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 17929#L443-30 assume 1 == ~m_pc~0; 17962#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 17963#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18241#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 18246#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 18721#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18351#L462-30 assume 1 == ~t1_pc~0; 18183#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 18184#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18470#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18471#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18746#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18336#L481-30 assume 1 == ~t2_pc~0; 18054#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 18055#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18144#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18023#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 18024#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 18296#L500-30 assume 1 == ~t3_pc~0; 18059#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18060#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18389#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18445#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18280#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 18281#L519-30 assume !(1 == ~t4_pc~0); 18469#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 18446#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18447#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18457#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 18458#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18577#L538-30 assume 1 == ~t5_pc~0; 17937#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 17938#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18264#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18564#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 18017#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 18018#L557-30 assume 1 == ~t6_pc~0; 17736#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 17738#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 17857#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 17858#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18042#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 18043#L576-30 assume !(1 == ~t7_pc~0); 17811#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 17812#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 18419#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18626#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18195#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18157#L595-30 assume !(1 == ~t8_pc~0); 18158#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 18098#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 18099#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 18792#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 18793#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18824#L614-30 assume 1 == ~t9_pc~0; 18101#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18102#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 17775#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 17776#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 17930#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18551#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 18325#L1025-5 assume !(1 == ~T1_E~0); 18326#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 18523#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 18802#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18834#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18797#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18709#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 17821#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 17822#L1065-3 assume !(1 == ~T9_E~0); 18723#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 18580#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18581#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 18803#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18714#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18715#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18734#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18735#L1105-3 assume !(1 == ~E_8~0); 17976#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 17977#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18751#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17832#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17985#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 18177#L1415 assume !(0 == start_simulation_~tmp~3#1); 18451#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 18452#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 17885#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 17786#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 17787#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18839#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18442#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 18064#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 18065#L1396-2 [2023-11-29 04:11:47,378 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:47,378 INFO L85 PathProgramCache]: Analyzing trace with hash 760149089, now seen corresponding path program 1 times [2023-11-29 04:11:47,378 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:47,379 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1886313870] [2023-11-29 04:11:47,379 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:47,379 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:47,395 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:47,466 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:47,466 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:47,466 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1886313870] [2023-11-29 04:11:47,466 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1886313870] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:47,467 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:47,467 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:47,467 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [128861595] [2023-11-29 04:11:47,467 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:47,467 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:47,468 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:47,468 INFO L85 PathProgramCache]: Analyzing trace with hash -2034235564, now seen corresponding path program 3 times [2023-11-29 04:11:47,468 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:47,468 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [367675620] [2023-11-29 04:11:47,468 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:47,468 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:47,484 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:47,524 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:47,525 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:47,525 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [367675620] [2023-11-29 04:11:47,525 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [367675620] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:47,525 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:47,525 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:47,525 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [60172335] [2023-11-29 04:11:47,525 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:47,526 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:47,526 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:47,526 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:11:47,526 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:11:47,526 INFO L87 Difference]: Start difference. First operand 1104 states and 1633 transitions. cyclomatic complexity: 530 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:47,656 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:47,656 INFO L93 Difference]: Finished difference Result 2100 states and 3099 transitions. [2023-11-29 04:11:47,656 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2100 states and 3099 transitions. [2023-11-29 04:11:47,669 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1958 [2023-11-29 04:11:47,684 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2100 states to 2100 states and 3099 transitions. [2023-11-29 04:11:47,684 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2100 [2023-11-29 04:11:47,687 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2100 [2023-11-29 04:11:47,687 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2100 states and 3099 transitions. [2023-11-29 04:11:47,691 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:47,691 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2023-11-29 04:11:47,694 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2100 states and 3099 transitions. [2023-11-29 04:11:47,729 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2100 to 2100. [2023-11-29 04:11:47,734 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2100 states, 2100 states have (on average 1.4757142857142858) internal successors, (3099), 2099 states have internal predecessors, (3099), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:47,741 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2100 states to 2100 states and 3099 transitions. [2023-11-29 04:11:47,741 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2023-11-29 04:11:47,741 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:11:47,742 INFO L428 stractBuchiCegarLoop]: Abstraction has 2100 states and 3099 transitions. [2023-11-29 04:11:47,742 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 04:11:47,742 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2100 states and 3099 transitions. [2023-11-29 04:11:47,751 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 1958 [2023-11-29 04:11:47,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:47,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:47,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:47,753 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:47,754 INFO L748 eck$LassoCheckResult]: Stem: 21234#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 21235#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 22035#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 22036#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21976#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 21977#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21954#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21757#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 21758#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 21561#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21562#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 22065#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21944#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21621#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21390#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21391#L922 assume !(0 == ~M_E~0); 22129#L922-2 assume !(0 == ~T1_E~0); 22130#L927-1 assume !(0 == ~T2_E~0); 21821#L932-1 assume !(0 == ~T3_E~0); 21695#L937-1 assume !(0 == ~T4_E~0); 21696#L942-1 assume !(0 == ~T5_E~0); 21756#L947-1 assume !(0 == ~T6_E~0); 21825#L952-1 assume !(0 == ~T7_E~0); 21826#L957-1 assume !(0 == ~T8_E~0); 21890#L962-1 assume !(0 == ~T9_E~0); 21673#L967-1 assume !(0 == ~E_1~0); 21674#L972-1 assume !(0 == ~E_2~0); 21959#L977-1 assume 0 == ~E_3~0;~E_3~0 := 1; 21960#L982-1 assume !(0 == ~E_4~0); 21166#L987-1 assume !(0 == ~E_5~0); 21167#L992-1 assume !(0 == ~E_6~0); 21173#L997-1 assume !(0 == ~E_7~0); 21597#L1002-1 assume !(0 == ~E_8~0); 21586#L1007-1 assume !(0 == ~E_9~0); 20960#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 20961#L443 assume !(1 == ~m_pc~0); 21841#L443-2 is_master_triggered_~__retres1~0#1 := 0; 21833#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21834#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21329#L1140 assume !(0 != activate_threads_~tmp~1#1); 21065#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21066#L462 assume 1 == ~t1_pc~0; 21721#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21687#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21002#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21003#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 21540#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21541#L481 assume !(1 == ~t2_pc~0); 21323#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 21322#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 21451#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21414#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 21415#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21508#L500 assume 1 == ~t3_pc~0; 21741#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21742#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20967#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 20968#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 20962#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 20963#L519 assume 1 == ~t4_pc~0; 21266#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 21267#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 21067#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 21068#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 21363#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21129#L538 assume !(1 == ~t5_pc~0); 21130#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 21027#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21028#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21309#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21310#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21872#L557 assume 1 == ~t6_pc~0; 21659#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21344#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21432#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21364#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 21365#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22101#L576 assume !(1 == ~t7_pc~0); 21333#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21334#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21658#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22126#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 21934#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21452#L595 assume 1 == ~t8_pc~0; 21453#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21951#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21878#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21780#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 21781#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21259#L614 assume !(1 == ~t9_pc~0); 21260#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21155#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21156#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21484#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 21417#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21418#L1025 assume !(1 == ~M_E~0); 21681#L1025-2 assume !(1 == ~T1_E~0); 21740#L1030-1 assume !(1 == ~T2_E~0); 21866#L1035-1 assume !(1 == ~T3_E~0); 21409#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21410#L1045-1 assume !(1 == ~T5_E~0); 21319#L1050-1 assume !(1 == ~T6_E~0); 21320#L1055-1 assume !(1 == ~T7_E~0); 21140#L1060-1 assume !(1 == ~T8_E~0); 21141#L1065-1 assume !(1 == ~T9_E~0); 21206#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 21827#L1075-1 assume !(1 == ~E_2~0); 21828#L1080-1 assume !(1 == ~E_3~0); 21816#L1085-1 assume !(1 == ~E_4~0); 21817#L1090-1 assume !(1 == ~E_5~0); 22060#L1095-1 assume !(1 == ~E_6~0); 21851#L1100-1 assume !(1 == ~E_7~0); 21852#L1105-1 assume !(1 == ~E_8~0); 21111#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 21112#L1115-1 assume { :end_inline_reset_delta_events } true; 21278#L1396-2 [2023-11-29 04:11:47,754 INFO L750 eck$LassoCheckResult]: Loop: 21278#L1396-2 assume !false; 21355#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 22155#L897-1 assume !false; 22154#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22153#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 22143#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 22142#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 22048#L766 assume !(0 != eval_~tmp~0#1); 22050#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 22141#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21579#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 21580#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 22139#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 22140#L932-3 assume !(0 == ~T3_E~0); 23023#L937-3 assume !(0 == ~T4_E~0); 23022#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 23021#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 23020#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 23019#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 23018#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 23017#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23016#L972-3 assume !(0 == ~E_2~0); 23015#L977-3 assume 0 == ~E_3~0;~E_3~0 := 1; 22138#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 22135#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 21430#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 21431#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 21425#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 21426#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21142#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21143#L443-30 assume 1 == ~m_pc~0; 21176#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 21177#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21458#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 21463#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 21966#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21568#L462-30 assume 1 == ~t1_pc~0; 21400#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21401#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21691#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21692#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 22770#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 22768#L481-30 assume 1 == ~t2_pc~0; 22764#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 22762#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 22760#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 22758#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 22756#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 22754#L500-30 assume 1 == ~t3_pc~0; 22750#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 22749#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 22748#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 22747#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 22746#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 22745#L519-30 assume 1 == ~t4_pc~0; 22743#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 22742#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 22741#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 22740#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 22739#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 22738#L538-30 assume 1 == ~t5_pc~0; 22736#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 22735#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 22734#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 22733#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 22732#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 22731#L557-30 assume !(1 == ~t6_pc~0); 22729#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 22728#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 22727#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 22726#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 22725#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 22724#L576-30 assume 1 == ~t7_pc~0; 22722#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 22721#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 22720#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 22719#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 22718#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 22717#L595-30 assume !(1 == ~t8_pc~0); 22714#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 22713#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 22711#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 22058#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 22059#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 22106#L614-30 assume 1 == ~t9_pc~0; 21315#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21316#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 20989#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 20990#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 21144#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21773#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21542#L1025-5 assume !(1 == ~T1_E~0); 21543#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21745#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 22068#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 22127#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 22063#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21950#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21035#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21036#L1065-3 assume !(1 == ~T9_E~0); 21969#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 21802#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21803#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 22069#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 21956#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 21957#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21980#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21981#L1105-3 assume !(1 == ~E_8~0); 21191#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 21192#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22000#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21046#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21200#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 21392#L1415 assume !(0 == start_simulation_~tmp~3#1); 22520#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 22115#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 21099#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 21000#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 21001#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 22136#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21660#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 21277#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 21278#L1396-2 [2023-11-29 04:11:47,754 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:47,755 INFO L85 PathProgramCache]: Analyzing trace with hash -1269658465, now seen corresponding path program 1 times [2023-11-29 04:11:47,755 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:47,755 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [194568909] [2023-11-29 04:11:47,755 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:47,755 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:47,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:47,850 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:47,851 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:47,851 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [194568909] [2023-11-29 04:11:47,851 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [194568909] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:47,851 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:47,851 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:47,851 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [479319437] [2023-11-29 04:11:47,851 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:47,852 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:47,852 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:47,852 INFO L85 PathProgramCache]: Analyzing trace with hash 187840947, now seen corresponding path program 1 times [2023-11-29 04:11:47,853 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:47,853 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1757620190] [2023-11-29 04:11:47,853 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:47,853 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:47,867 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:47,903 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:47,903 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:47,903 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1757620190] [2023-11-29 04:11:47,903 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1757620190] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:47,904 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:47,904 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:47,904 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375016574] [2023-11-29 04:11:47,904 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:47,904 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:47,904 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:47,905 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:11:47,905 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:11:47,905 INFO L87 Difference]: Start difference. First operand 2100 states and 3099 transitions. cyclomatic complexity: 1001 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:48,073 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:48,073 INFO L93 Difference]: Finished difference Result 3938 states and 5806 transitions. [2023-11-29 04:11:48,074 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 3938 states and 5806 transitions. [2023-11-29 04:11:48,091 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2023-11-29 04:11:48,112 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 3938 states to 3938 states and 5806 transitions. [2023-11-29 04:11:48,112 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 3938 [2023-11-29 04:11:48,115 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 3938 [2023-11-29 04:11:48,116 INFO L73 IsDeterministic]: Start isDeterministic. Operand 3938 states and 5806 transitions. [2023-11-29 04:11:48,120 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:48,120 INFO L218 hiAutomatonCegarLoop]: Abstraction has 3938 states and 5806 transitions. [2023-11-29 04:11:48,124 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 3938 states and 5806 transitions. [2023-11-29 04:11:48,172 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 3938 to 3936. [2023-11-29 04:11:48,180 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 3936 states, 3936 states have (on average 1.4745934959349594) internal successors, (5804), 3935 states have internal predecessors, (5804), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:48,190 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3936 states to 3936 states and 5804 transitions. [2023-11-29 04:11:48,190 INFO L240 hiAutomatonCegarLoop]: Abstraction has 3936 states and 5804 transitions. [2023-11-29 04:11:48,191 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:11:48,191 INFO L428 stractBuchiCegarLoop]: Abstraction has 3936 states and 5804 transitions. [2023-11-29 04:11:48,191 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 04:11:48,191 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 3936 states and 5804 transitions. [2023-11-29 04:11:48,202 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 3772 [2023-11-29 04:11:48,202 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:48,203 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:48,204 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:48,204 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:48,205 INFO L748 eck$LassoCheckResult]: Stem: 27284#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 27285#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 28099#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28100#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28044#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 28045#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28023#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27817#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27818#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27612#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 27613#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28135#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28012#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 27675#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 27439#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27440#L922 assume !(0 == ~M_E~0); 28186#L922-2 assume !(0 == ~T1_E~0); 28187#L927-1 assume !(0 == ~T2_E~0); 27888#L932-1 assume !(0 == ~T3_E~0); 27750#L937-1 assume !(0 == ~T4_E~0); 27751#L942-1 assume !(0 == ~T5_E~0); 27816#L947-1 assume !(0 == ~T6_E~0); 27892#L952-1 assume !(0 == ~T7_E~0); 27893#L957-1 assume !(0 == ~T8_E~0); 27963#L962-1 assume !(0 == ~T9_E~0); 27726#L967-1 assume !(0 == ~E_1~0); 27727#L972-1 assume !(0 == ~E_2~0); 28028#L977-1 assume !(0 == ~E_3~0); 28029#L982-1 assume !(0 == ~E_4~0); 27214#L987-1 assume !(0 == ~E_5~0); 27215#L992-1 assume !(0 == ~E_6~0); 27221#L997-1 assume !(0 == ~E_7~0); 27652#L1002-1 assume !(0 == ~E_8~0); 27637#L1007-1 assume !(0 == ~E_9~0); 27008#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27009#L443 assume !(1 == ~m_pc~0); 27909#L443-2 is_master_triggered_~__retres1~0#1 := 0; 27900#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27901#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 27377#L1140 assume !(0 != activate_threads_~tmp~1#1); 27113#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27114#L462 assume 1 == ~t1_pc~0; 27776#L463 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27745#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27052#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27053#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 27591#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27592#L481 assume !(1 == ~t2_pc~0); 27371#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27370#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27499#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27462#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 27463#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27561#L500 assume 1 == ~t3_pc~0; 27797#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27798#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27015#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27016#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 27013#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27014#L519 assume 1 == ~t4_pc~0; 27317#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27318#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27115#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27116#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 27414#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27177#L538 assume !(1 == ~t5_pc~0); 27178#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 27075#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27076#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27357#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27358#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 27944#L557 assume 1 == ~t6_pc~0; 27714#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27393#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27481#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27415#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 27416#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28162#L576 assume !(1 == ~t7_pc~0); 27381#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27382#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 27713#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28182#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 28004#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27500#L595 assume 1 == ~t8_pc~0; 27501#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 28019#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 27947#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 27841#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 27842#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27307#L614 assume !(1 == ~t9_pc~0); 27308#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27203#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27204#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 27534#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 27465#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27466#L1025 assume !(1 == ~M_E~0); 27734#L1025-2 assume !(1 == ~T1_E~0); 27796#L1030-1 assume !(1 == ~T2_E~0); 27935#L1035-1 assume !(1 == ~T3_E~0); 28360#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28050#L1045-1 assume !(1 == ~T5_E~0); 27367#L1050-1 assume !(1 == ~T6_E~0); 27368#L1055-1 assume !(1 == ~T7_E~0); 27188#L1060-1 assume !(1 == ~T8_E~0); 27189#L1065-1 assume !(1 == ~T9_E~0); 27254#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 28166#L1075-1 assume !(1 == ~E_2~0); 28350#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 28284#L1085-1 assume !(1 == ~E_4~0); 28262#L1090-1 assume !(1 == ~E_5~0); 28260#L1095-1 assume !(1 == ~E_6~0); 28258#L1100-1 assume !(1 == ~E_7~0); 28256#L1105-1 assume !(1 == ~E_8~0); 28246#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 28237#L1115-1 assume { :end_inline_reset_delta_events } true; 28230#L1396-2 [2023-11-29 04:11:48,205 INFO L750 eck$LassoCheckResult]: Loop: 28230#L1396-2 assume !false; 28224#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28220#L897-1 assume !false; 28219#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28218#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28208#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28207#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28205#L766 assume !(0 != eval_~tmp~0#1); 28204#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28203#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28202#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 28201#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28200#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 27526#L932-3 assume !(0 == ~T3_E~0); 27527#L937-3 assume !(0 == ~T4_E~0); 27151#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27152#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 27528#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 27529#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 28104#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 27981#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27982#L972-3 assume !(0 == ~E_2~0); 27886#L977-3 assume !(0 == ~E_3~0); 27887#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28191#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27479#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 27480#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 27477#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 27478#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 27190#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27191#L443-30 assume 1 == ~m_pc~0; 30699#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 30697#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 30695#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 30693#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 30692#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27619#L462-30 assume 1 == ~t1_pc~0; 27447#L463-10 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27448#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27746#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 27747#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 28062#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27604#L481-30 assume 1 == ~t2_pc~0; 27314#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 27315#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27408#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27286#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 27287#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 27564#L500-30 assume 1 == ~t3_pc~0; 27322#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27323#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27659#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27718#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 27547#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27548#L519-30 assume 1 == ~t4_pc~0; 27927#L520-10 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 27719#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27720#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27731#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 27732#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29313#L538-30 assume 1 == ~t5_pc~0; 29310#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 29307#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 29305#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29303#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 29302#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 29300#L557-30 assume !(1 == ~t6_pc~0); 29296#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 29294#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 29291#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 29289#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 29163#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 29161#L576-30 assume 1 == ~t7_pc~0; 29158#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 29155#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 29153#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 29151#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 29149#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 29147#L595-30 assume !(1 == ~t8_pc~0); 29143#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 29053#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 29050#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 29048#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28966#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28963#L614-30 assume 1 == ~t9_pc~0; 28960#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28854#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28735#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28732#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 28730#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28624#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28621#L1025-5 assume !(1 == ~T1_E~0); 28619#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27801#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 28616#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28183#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28541#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28539#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28537#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28535#L1065-3 assume !(1 == ~T9_E~0); 28534#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 28465#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28418#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28415#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 28413#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 28412#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 28410#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 28408#L1105-3 assume !(1 == ~E_8~0); 28406#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 28361#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28310#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28299#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28297#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 28289#L1415 assume !(0 == start_simulation_~tmp~3#1); 28287#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 28270#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 28263#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 28261#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 28259#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28257#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28247#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 28238#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 28230#L1396-2 [2023-11-29 04:11:48,205 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:48,205 INFO L85 PathProgramCache]: Analyzing trace with hash -1455005537, now seen corresponding path program 1 times [2023-11-29 04:11:48,205 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:48,206 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [971031580] [2023-11-29 04:11:48,206 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:48,206 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:48,217 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:48,257 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:48,257 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:48,257 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [971031580] [2023-11-29 04:11:48,258 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [971031580] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:48,258 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:48,258 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:11:48,258 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840241284] [2023-11-29 04:11:48,258 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:48,258 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:48,259 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:48,259 INFO L85 PathProgramCache]: Analyzing trace with hash 2085337713, now seen corresponding path program 1 times [2023-11-29 04:11:48,259 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:48,259 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1488714509] [2023-11-29 04:11:48,259 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:48,259 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:48,273 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:48,328 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:48,328 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:48,328 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1488714509] [2023-11-29 04:11:48,328 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1488714509] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:48,328 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:48,329 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:48,329 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [291901606] [2023-11-29 04:11:48,329 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:48,329 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:48,330 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:48,330 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:48,330 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:48,330 INFO L87 Difference]: Start difference. First operand 3936 states and 5804 transitions. cyclomatic complexity: 1872 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:48,469 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:48,469 INFO L93 Difference]: Finished difference Result 7377 states and 10808 transitions. [2023-11-29 04:11:48,469 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 7377 states and 10808 transitions. [2023-11-29 04:11:48,510 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7206 [2023-11-29 04:11:48,557 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 7377 states to 7377 states and 10808 transitions. [2023-11-29 04:11:48,558 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 7377 [2023-11-29 04:11:48,565 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 7377 [2023-11-29 04:11:48,565 INFO L73 IsDeterministic]: Start isDeterministic. Operand 7377 states and 10808 transitions. [2023-11-29 04:11:48,578 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:48,578 INFO L218 hiAutomatonCegarLoop]: Abstraction has 7377 states and 10808 transitions. [2023-11-29 04:11:48,588 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 7377 states and 10808 transitions. [2023-11-29 04:11:48,726 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 7377 to 7369. [2023-11-29 04:11:48,741 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 7369 states, 7369 states have (on average 1.4655991314968109) internal successors, (10800), 7368 states have internal predecessors, (10800), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:48,760 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 7369 states to 7369 states and 10800 transitions. [2023-11-29 04:11:48,760 INFO L240 hiAutomatonCegarLoop]: Abstraction has 7369 states and 10800 transitions. [2023-11-29 04:11:48,761 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:48,761 INFO L428 stractBuchiCegarLoop]: Abstraction has 7369 states and 10800 transitions. [2023-11-29 04:11:48,761 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 04:11:48,761 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 7369 states and 10800 transitions. [2023-11-29 04:11:48,792 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 7198 [2023-11-29 04:11:48,793 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:48,793 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:48,795 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:48,795 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:48,795 INFO L748 eck$LassoCheckResult]: Stem: 38605#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 38606#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 39496#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 39497#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 39427#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 39428#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 39399#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 39168#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 39169#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 38946#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 38947#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 39543#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 39387#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 39017#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 38763#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 38764#L922 assume !(0 == ~M_E~0); 39619#L922-2 assume !(0 == ~T1_E~0); 39620#L927-1 assume !(0 == ~T2_E~0); 39249#L932-1 assume !(0 == ~T3_E~0); 39099#L937-1 assume !(0 == ~T4_E~0); 39100#L942-1 assume !(0 == ~T5_E~0); 39167#L947-1 assume !(0 == ~T6_E~0); 39253#L952-1 assume !(0 == ~T7_E~0); 39254#L957-1 assume !(0 == ~T8_E~0); 39329#L962-1 assume !(0 == ~T9_E~0); 39072#L967-1 assume !(0 == ~E_1~0); 39073#L972-1 assume !(0 == ~E_2~0); 39407#L977-1 assume !(0 == ~E_3~0); 39408#L982-1 assume !(0 == ~E_4~0); 38534#L987-1 assume !(0 == ~E_5~0); 38535#L992-1 assume !(0 == ~E_6~0); 38541#L997-1 assume !(0 == ~E_7~0); 38991#L1002-1 assume !(0 == ~E_8~0); 38978#L1007-1 assume !(0 == ~E_9~0); 38328#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 38329#L443 assume !(1 == ~m_pc~0); 39272#L443-2 is_master_triggered_~__retres1~0#1 := 0; 39263#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 39264#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 38699#L1140 assume !(0 != activate_threads_~tmp~1#1); 38433#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 38434#L462 assume !(1 == ~t1_pc~0); 39092#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 39093#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 38372#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 38373#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 38920#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38921#L481 assume !(1 == ~t2_pc~0); 38693#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 38692#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 38824#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38787#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 38788#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 38887#L500 assume 1 == ~t3_pc~0; 39148#L501 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 39149#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 38335#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 38336#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 38333#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38334#L519 assume 1 == ~t4_pc~0; 38638#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 38639#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 38435#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 38436#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 38737#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 38497#L538 assume !(1 == ~t5_pc~0); 38498#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 38395#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38396#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 38679#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38680#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 39312#L557 assume 1 == ~t6_pc~0; 39059#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38715#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38806#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38738#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 38739#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 39575#L576 assume !(1 == ~t7_pc~0); 38703#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 38704#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39058#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39611#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 39373#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38827#L595 assume 1 == ~t8_pc~0; 38828#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 39395#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 39316#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39200#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 39201#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 38628#L614 assume !(1 == ~t9_pc~0); 38629#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 38523#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38524#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38859#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 38790#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 38791#L1025 assume !(1 == ~M_E~0); 39081#L1025-2 assume !(1 == ~T1_E~0); 39147#L1030-1 assume !(1 == ~T2_E~0); 39301#L1035-1 assume !(1 == ~T3_E~0); 39450#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 40703#L1045-1 assume !(1 == ~T5_E~0); 40702#L1050-1 assume !(1 == ~T6_E~0); 40700#L1055-1 assume !(1 == ~T7_E~0); 38508#L1060-1 assume !(1 == ~T8_E~0); 38509#L1065-1 assume !(1 == ~T9_E~0); 38575#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 40664#L1075-1 assume !(1 == ~E_2~0); 40661#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 40660#L1085-1 assume !(1 == ~E_4~0); 40659#L1090-1 assume !(1 == ~E_5~0); 40658#L1095-1 assume !(1 == ~E_6~0); 40633#L1100-1 assume !(1 == ~E_7~0); 40614#L1105-1 assume !(1 == ~E_8~0); 40601#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 40592#L1115-1 assume { :end_inline_reset_delta_events } true; 40585#L1396-2 [2023-11-29 04:11:48,795 INFO L750 eck$LassoCheckResult]: Loop: 40585#L1396-2 assume !false; 40579#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 40575#L897-1 assume !false; 40574#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 40573#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40563#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40562#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 40560#L766 assume !(0 != eval_~tmp~0#1); 40559#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 40558#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 40557#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 40556#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 40553#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 40554#L932-3 assume !(0 == ~T3_E~0); 42854#L937-3 assume !(0 == ~T4_E~0); 42852#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 42850#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 42848#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 42846#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 42845#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 42844#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 42843#L972-3 assume !(0 == ~E_2~0); 42842#L977-3 assume !(0 == ~E_3~0); 42841#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 42840#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 42839#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 42838#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 42837#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 42836#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 42835#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 42834#L443-30 assume 1 == ~m_pc~0; 42832#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 42831#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 42830#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 42829#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 42828#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 42827#L462-30 assume !(1 == ~t1_pc~0); 39499#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 39405#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 39095#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 39096#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 39448#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 38936#L481-30 assume !(1 == ~t2_pc~0); 38937#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 42821#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 42820#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 38607#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 38608#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 39268#L500-30 assume 1 == ~t3_pc~0; 38643#L501-10 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 38644#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 39000#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 39063#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 38872#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 38873#L519-30 assume !(1 == ~t4_pc~0); 39091#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 39064#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 39065#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 39077#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 39078#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 39223#L538-30 assume 1 == ~t5_pc~0; 38519#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 38520#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 38856#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 39206#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 38601#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 38602#L557-30 assume 1 == ~t6_pc~0; 38318#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 38320#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 38439#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 38440#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 38626#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 38627#L576-30 assume !(1 == ~t7_pc~0); 38393#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 38394#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 39037#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 39280#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 38782#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 38744#L595-30 assume !(1 == ~t8_pc~0); 38745#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 38683#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 38684#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 39526#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 39527#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 39578#L614-30 assume !(1 == ~t9_pc~0); 38688#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 38687#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 38357#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 38358#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 38512#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 39192#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 38922#L1025-5 assume !(1 == ~T1_E~0); 38923#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 39152#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 39547#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 39612#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 39535#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 39394#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 38403#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 38404#L1065-3 assume !(1 == ~T9_E~0); 39417#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 39226#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 39227#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 39548#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 39579#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 40845#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 40843#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 40811#L1105-3 assume !(1 == ~E_8~0); 40809#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 40807#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 40747#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40736#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40711#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 40689#L1415 assume !(0 == start_simulation_~tmp~3#1); 40663#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 40640#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 40619#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 40617#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 40616#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 40615#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 40602#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 40593#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 40585#L1396-2 [2023-11-29 04:11:48,796 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:48,796 INFO L85 PathProgramCache]: Analyzing trace with hash 212114046, now seen corresponding path program 1 times [2023-11-29 04:11:48,796 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:48,796 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1466777672] [2023-11-29 04:11:48,796 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:48,797 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:48,812 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:48,863 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:48,863 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:48,863 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1466777672] [2023-11-29 04:11:48,863 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1466777672] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:48,864 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:48,864 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:11:48,864 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [825832264] [2023-11-29 04:11:48,864 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:48,865 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:48,865 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:48,865 INFO L85 PathProgramCache]: Analyzing trace with hash 352264749, now seen corresponding path program 1 times [2023-11-29 04:11:48,865 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:48,865 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2076921111] [2023-11-29 04:11:48,866 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:48,866 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:48,917 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:48,962 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:48,962 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:48,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2076921111] [2023-11-29 04:11:48,963 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2076921111] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:48,963 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:48,963 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:48,963 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1751706949] [2023-11-29 04:11:48,963 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:48,964 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:48,964 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:48,964 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:48,964 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:48,964 INFO L87 Difference]: Start difference. First operand 7369 states and 10800 transitions. cyclomatic complexity: 3439 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:49,132 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:49,132 INFO L93 Difference]: Finished difference Result 13914 states and 20281 transitions. [2023-11-29 04:11:49,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 13914 states and 20281 transitions. [2023-11-29 04:11:49,203 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13728 [2023-11-29 04:11:49,264 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 13914 states to 13914 states and 20281 transitions. [2023-11-29 04:11:49,264 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 13914 [2023-11-29 04:11:49,278 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 13914 [2023-11-29 04:11:49,278 INFO L73 IsDeterministic]: Start isDeterministic. Operand 13914 states and 20281 transitions. [2023-11-29 04:11:49,296 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:49,296 INFO L218 hiAutomatonCegarLoop]: Abstraction has 13914 states and 20281 transitions. [2023-11-29 04:11:49,314 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 13914 states and 20281 transitions. [2023-11-29 04:11:49,479 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 13914 to 13898. [2023-11-29 04:11:49,500 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 13898 states, 13898 states have (on average 1.458123471003022) internal successors, (20265), 13897 states have internal predecessors, (20265), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:49,638 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 13898 states to 13898 states and 20265 transitions. [2023-11-29 04:11:49,638 INFO L240 hiAutomatonCegarLoop]: Abstraction has 13898 states and 20265 transitions. [2023-11-29 04:11:49,639 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:49,639 INFO L428 stractBuchiCegarLoop]: Abstraction has 13898 states and 20265 transitions. [2023-11-29 04:11:49,639 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 04:11:49,639 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 13898 states and 20265 transitions. [2023-11-29 04:11:49,681 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 13712 [2023-11-29 04:11:49,681 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:49,681 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:49,683 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:49,683 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:49,683 INFO L748 eck$LassoCheckResult]: Stem: 59892#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 59893#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 60775#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 60776#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 60708#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 60709#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 60686#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 60448#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 60449#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 60229#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 60230#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 60820#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 60675#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 60298#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 60050#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 60051#L922 assume !(0 == ~M_E~0); 60895#L922-2 assume !(0 == ~T1_E~0); 60896#L927-1 assume !(0 == ~T2_E~0); 60528#L932-1 assume !(0 == ~T3_E~0); 60375#L937-1 assume !(0 == ~T4_E~0); 60376#L942-1 assume !(0 == ~T5_E~0); 60447#L947-1 assume !(0 == ~T6_E~0); 60532#L952-1 assume !(0 == ~T7_E~0); 60533#L957-1 assume !(0 == ~T8_E~0); 60610#L962-1 assume !(0 == ~T9_E~0); 60352#L967-1 assume !(0 == ~E_1~0); 60353#L972-1 assume !(0 == ~E_2~0); 60692#L977-1 assume !(0 == ~E_3~0); 60693#L982-1 assume !(0 == ~E_4~0); 59824#L987-1 assume !(0 == ~E_5~0); 59825#L992-1 assume !(0 == ~E_6~0); 59831#L997-1 assume !(0 == ~E_7~0); 60271#L1002-1 assume !(0 == ~E_8~0); 60260#L1007-1 assume !(0 == ~E_9~0); 59618#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 59619#L443 assume !(1 == ~m_pc~0); 60551#L443-2 is_master_triggered_~__retres1~0#1 := 0; 60541#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60542#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 59988#L1140 assume !(0 != activate_threads_~tmp~1#1); 59723#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 59724#L462 assume !(1 == ~t1_pc~0); 60366#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 60367#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 59660#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 59661#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 60205#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60206#L481 assume !(1 == ~t2_pc~0); 59982#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 59981#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60114#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 60076#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 60077#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60174#L500 assume !(1 == ~t3_pc~0); 60763#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 60726#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 59625#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 59626#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 59620#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 59621#L519 assume 1 == ~t4_pc~0; 59924#L520 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 59925#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 59725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 59726#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 60023#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 59787#L538 assume !(1 == ~t5_pc~0); 59788#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 59685#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 59686#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 59968#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59969#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 60591#L557 assume 1 == ~t6_pc~0; 60340#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 60004#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 60094#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 60024#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 60025#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 60860#L576 assume !(1 == ~t7_pc~0); 59992#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 59993#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60339#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60889#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 60663#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60115#L595 assume 1 == ~t8_pc~0; 60116#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 60683#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 60597#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60480#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 60481#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 59917#L614 assume !(1 == ~t9_pc~0); 59918#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 59812#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59813#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 60150#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 60079#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60080#L1025 assume !(1 == ~M_E~0); 60361#L1025-2 assume !(1 == ~T1_E~0); 60425#L1030-1 assume !(1 == ~T2_E~0); 60585#L1035-1 assume !(1 == ~T3_E~0); 60733#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 69430#L1045-1 assume !(1 == ~T5_E~0); 69424#L1050-1 assume !(1 == ~T6_E~0); 69418#L1055-1 assume !(1 == ~T7_E~0); 69414#L1060-1 assume !(1 == ~T8_E~0); 69411#L1065-1 assume !(1 == ~T9_E~0); 69408#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 69404#L1075-1 assume !(1 == ~E_2~0); 69400#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 69401#L1085-1 assume !(1 == ~E_4~0); 70260#L1090-1 assume !(1 == ~E_5~0); 70258#L1095-1 assume !(1 == ~E_6~0); 70257#L1100-1 assume !(1 == ~E_7~0); 70246#L1105-1 assume !(1 == ~E_8~0); 70244#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 70236#L1115-1 assume { :end_inline_reset_delta_events } true; 70225#L1396-2 [2023-11-29 04:11:49,684 INFO L750 eck$LassoCheckResult]: Loop: 70225#L1396-2 assume !false; 70214#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 70204#L897-1 assume !false; 70199#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 70026#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 70010#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 70004#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 69997#L766 assume !(0 != eval_~tmp~0#1); 69998#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 71917#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 71915#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 71913#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 71910#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 60141#L932-3 assume !(0 == ~T3_E~0); 60142#L937-3 assume !(0 == ~T4_E~0); 59761#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 59762#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 60143#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 60144#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 60785#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 60633#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 60634#L972-3 assume !(0 == ~E_2~0); 60526#L977-3 assume !(0 == ~E_3~0); 60527#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 71956#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 71955#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 71954#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 60087#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 60088#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 71767#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 60134#L443-30 assume 1 == ~m_pc~0; 59834#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 59835#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 60121#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 60126#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 60695#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 60239#L462-30 assume !(1 == ~t1_pc~0); 60240#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 60691#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 60371#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 60372#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 60730#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 60222#L481-30 assume 1 == ~t2_pc~0; 59927#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 59928#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 60019#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 59896#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 59897#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 60179#L500-30 assume !(1 == ~t3_pc~0); 60548#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 60281#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 60282#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 60344#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 60163#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 60164#L519-30 assume !(1 == ~t4_pc~0); 60370#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 60345#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 60346#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 60357#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 60358#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 60504#L538-30 assume 1 == ~t5_pc~0; 59809#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 59810#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 60147#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 60487#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 59890#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 59891#L557-30 assume 1 == ~t6_pc~0; 59608#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 59610#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 59729#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 59730#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 59915#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 59916#L576-30 assume !(1 == ~t7_pc~0); 59683#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 59684#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 60314#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 60559#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 60072#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 60032#L595-30 assume !(1 == ~t8_pc~0); 60033#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 59970#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 59971#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 60806#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 60807#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 60863#L614-30 assume 1 == ~t9_pc~0; 59975#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 59976#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 59647#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 59648#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 59802#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 60470#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 60209#L1025-5 assume !(1 == ~T1_E~0); 60210#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 60427#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 60823#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 60890#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 70935#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 70930#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 70924#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 70919#L1065-3 assume !(1 == ~T9_E~0); 70911#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 70904#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 70897#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 69463#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 70885#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 70879#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 70871#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 70866#L1105-3 assume !(1 == ~E_8~0); 70861#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 70856#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 70462#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 70451#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 70449#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 70445#L1415 assume !(0 == start_simulation_~tmp~3#1); 70360#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 70253#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 70245#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 70243#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 70242#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 70241#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 70239#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 70237#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 70225#L1396-2 [2023-11-29 04:11:49,684 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:49,684 INFO L85 PathProgramCache]: Analyzing trace with hash 2031839965, now seen corresponding path program 1 times [2023-11-29 04:11:49,684 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:49,684 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [844628719] [2023-11-29 04:11:49,685 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:49,685 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:49,698 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:49,741 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:49,742 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:49,742 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [844628719] [2023-11-29 04:11:49,742 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [844628719] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:49,742 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:49,742 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:11:49,742 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [778176745] [2023-11-29 04:11:49,743 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:49,743 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:49,743 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:49,743 INFO L85 PathProgramCache]: Analyzing trace with hash 479135758, now seen corresponding path program 1 times [2023-11-29 04:11:49,744 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:49,744 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [81128326] [2023-11-29 04:11:49,744 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:49,744 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:49,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:49,796 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:49,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:49,797 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [81128326] [2023-11-29 04:11:49,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [81128326] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:49,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:49,797 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:49,797 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2052120748] [2023-11-29 04:11:49,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:49,798 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:49,798 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:49,798 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:49,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:49,799 INFO L87 Difference]: Start difference. First operand 13898 states and 20265 transitions. cyclomatic complexity: 6383 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:50,058 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:50,058 INFO L93 Difference]: Finished difference Result 26345 states and 38242 transitions. [2023-11-29 04:11:50,059 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 26345 states and 38242 transitions. [2023-11-29 04:11:50,168 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26104 [2023-11-29 04:11:50,290 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 26345 states to 26345 states and 38242 transitions. [2023-11-29 04:11:50,290 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 26345 [2023-11-29 04:11:50,307 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 26345 [2023-11-29 04:11:50,308 INFO L73 IsDeterministic]: Start isDeterministic. Operand 26345 states and 38242 transitions. [2023-11-29 04:11:50,325 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:50,325 INFO L218 hiAutomatonCegarLoop]: Abstraction has 26345 states and 38242 transitions. [2023-11-29 04:11:50,345 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 26345 states and 38242 transitions. [2023-11-29 04:11:50,731 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 26345 to 26313. [2023-11-29 04:11:50,772 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 26313 states, 26313 states have (on average 1.4521339261961768) internal successors, (38210), 26312 states have internal predecessors, (38210), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:50,863 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 26313 states to 26313 states and 38210 transitions. [2023-11-29 04:11:50,863 INFO L240 hiAutomatonCegarLoop]: Abstraction has 26313 states and 38210 transitions. [2023-11-29 04:11:50,863 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:50,864 INFO L428 stractBuchiCegarLoop]: Abstraction has 26313 states and 38210 transitions. [2023-11-29 04:11:50,864 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 04:11:50,864 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 26313 states and 38210 transitions. [2023-11-29 04:11:50,993 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26072 [2023-11-29 04:11:50,994 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:50,994 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:50,995 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:50,996 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:50,996 INFO L748 eck$LassoCheckResult]: Stem: 100144#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 100145#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 101018#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 101019#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 100956#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 100957#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 100928#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 100700#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 100701#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 100483#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 100484#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 101058#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 100917#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 100552#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 100301#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 100302#L922 assume !(0 == ~M_E~0); 101151#L922-2 assume !(0 == ~T1_E~0); 101152#L927-1 assume !(0 == ~T2_E~0); 100772#L932-1 assume !(0 == ~T3_E~0); 100634#L937-1 assume !(0 == ~T4_E~0); 100635#L942-1 assume !(0 == ~T5_E~0); 100699#L947-1 assume !(0 == ~T6_E~0); 100776#L952-1 assume !(0 == ~T7_E~0); 100777#L957-1 assume !(0 == ~T8_E~0); 100855#L962-1 assume !(0 == ~T9_E~0); 100609#L967-1 assume !(0 == ~E_1~0); 100610#L972-1 assume !(0 == ~E_2~0); 100936#L977-1 assume !(0 == ~E_3~0); 100937#L982-1 assume !(0 == ~E_4~0); 100075#L987-1 assume !(0 == ~E_5~0); 100076#L992-1 assume !(0 == ~E_6~0); 100082#L997-1 assume !(0 == ~E_7~0); 100525#L1002-1 assume !(0 == ~E_8~0); 100512#L1007-1 assume !(0 == ~E_9~0); 99868#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 99869#L443 assume !(1 == ~m_pc~0); 100796#L443-2 is_master_triggered_~__retres1~0#1 := 0; 100785#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 100786#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 100238#L1140 assume !(0 != activate_threads_~tmp~1#1); 99973#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 99974#L462 assume !(1 == ~t1_pc~0); 100625#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 100626#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 99910#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 99911#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 100460#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 100461#L481 assume !(1 == ~t2_pc~0); 100232#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 100231#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 100365#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 100326#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 100327#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 100430#L500 assume !(1 == ~t3_pc~0); 101007#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 100975#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 99875#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 99876#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 99870#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 99871#L519 assume !(1 == ~t4_pc~0); 100688#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 100429#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 99975#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 99976#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 100274#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 100038#L538 assume !(1 == ~t5_pc~0); 100039#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 99935#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 99936#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 100218#L1180 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 100219#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 100839#L557 assume 1 == ~t6_pc~0; 100594#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 100254#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 100345#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 100275#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 100276#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 101100#L576 assume !(1 == ~t7_pc~0); 100242#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 100243#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 100593#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 101139#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 100906#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 100366#L595 assume 1 == ~t8_pc~0; 100367#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 100923#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 100844#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 100724#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 100725#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 100169#L614 assume !(1 == ~t9_pc~0); 100170#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 100063#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 100064#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 100401#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 100329#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 100330#L1025 assume !(1 == ~M_E~0); 100618#L1025-2 assume !(1 == ~T1_E~0); 100679#L1030-1 assume !(1 == ~T2_E~0); 100828#L1035-1 assume !(1 == ~T3_E~0); 100320#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 100321#L1045-1 assume !(1 == ~T5_E~0); 106392#L1050-1 assume !(1 == ~T6_E~0); 100419#L1055-1 assume !(1 == ~T7_E~0); 100420#L1060-1 assume !(1 == ~T8_E~0); 100115#L1065-1 assume !(1 == ~T9_E~0); 100116#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 100778#L1075-1 assume !(1 == ~E_2~0); 100779#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 106334#L1085-1 assume !(1 == ~E_4~0); 106328#L1090-1 assume !(1 == ~E_5~0); 105933#L1095-1 assume !(1 == ~E_6~0); 105931#L1100-1 assume !(1 == ~E_7~0); 105841#L1105-1 assume !(1 == ~E_8~0); 105822#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 105811#L1115-1 assume { :end_inline_reset_delta_events } true; 105801#L1396-2 [2023-11-29 04:11:50,996 INFO L750 eck$LassoCheckResult]: Loop: 105801#L1396-2 assume !false; 105793#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 105787#L897-1 assume !false; 105784#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 105780#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 105766#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 105763#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 105759#L766 assume !(0 != eval_~tmp~0#1); 105760#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 106789#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 106787#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 106785#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 106783#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 106781#L932-3 assume !(0 == ~T3_E~0); 106779#L937-3 assume !(0 == ~T4_E~0); 106777#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 106776#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 106773#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 106771#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 106769#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 106767#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 106765#L972-3 assume !(0 == ~E_2~0); 106763#L977-3 assume !(0 == ~E_3~0); 106761#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 106759#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 106757#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 106755#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 106753#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 106751#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 106748#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 106746#L443-30 assume 1 == ~m_pc~0; 106743#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 106741#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 106739#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 106737#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 106735#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 106733#L462-30 assume !(1 == ~t1_pc~0); 106731#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 106729#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 106727#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 106725#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 106723#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 106721#L481-30 assume 1 == ~t2_pc~0; 106715#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 106713#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 106711#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 106709#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 106707#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 106704#L500-30 assume !(1 == ~t3_pc~0); 106702#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 106685#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 106679#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 106672#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 106664#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 106658#L519-30 assume !(1 == ~t4_pc~0); 106652#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 106645#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 106637#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 106629#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 106622#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 106611#L538-30 assume 1 == ~t5_pc~0; 106603#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 106580#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 106577#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 106575#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 106573#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 106571#L557-30 assume !(1 == ~t6_pc~0); 106567#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 106565#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 106563#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 106561#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 106559#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 106557#L576-30 assume !(1 == ~t7_pc~0); 106555#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 106552#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 106550#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 106548#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 106546#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 106543#L595-30 assume 1 == ~t8_pc~0; 106541#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 106538#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 106536#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 106534#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 106533#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 106521#L614-30 assume !(1 == ~t9_pc~0); 106401#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 106398#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 106396#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 106386#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 106375#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 106367#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 106357#L1025-5 assume !(1 == ~T1_E~0); 106348#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 106092#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 106085#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 106081#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 106079#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 106077#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 106074#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 106070#L1065-3 assume !(1 == ~T9_E~0); 106068#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 106066#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 106064#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 106060#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 106058#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 106056#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 106054#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 106050#L1105-3 assume !(1 == ~E_8~0); 106048#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 106046#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 106043#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 106026#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 106020#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 106013#L1415 assume !(0 == start_simulation_~tmp~3#1); 106010#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 105858#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 105849#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 105847#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 105845#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 105843#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 105823#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 105812#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 105801#L1396-2 [2023-11-29 04:11:50,997 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:50,997 INFO L85 PathProgramCache]: Analyzing trace with hash 2039590524, now seen corresponding path program 1 times [2023-11-29 04:11:50,997 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:50,997 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [763182805] [2023-11-29 04:11:50,997 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:50,997 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:51,012 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:51,072 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:51,073 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:51,073 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [763182805] [2023-11-29 04:11:51,073 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [763182805] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:51,073 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:51,073 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:11:51,074 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1148226294] [2023-11-29 04:11:51,074 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:51,074 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:51,074 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:51,075 INFO L85 PathProgramCache]: Analyzing trace with hash -2009657619, now seen corresponding path program 1 times [2023-11-29 04:11:51,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:51,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1351872171] [2023-11-29 04:11:51,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:51,075 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:51,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:51,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:51,126 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:51,126 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1351872171] [2023-11-29 04:11:51,126 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1351872171] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:51,126 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:51,127 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:51,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [295669970] [2023-11-29 04:11:51,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:51,127 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:51,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:51,128 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:11:51,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:11:51,128 INFO L87 Difference]: Start difference. First operand 26313 states and 38210 transitions. cyclomatic complexity: 11929 Second operand has 5 states, 5 states have (on average 23.0) internal successors, (115), 5 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:51,598 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:51,599 INFO L93 Difference]: Finished difference Result 60073 states and 86441 transitions. [2023-11-29 04:11:51,599 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60073 states and 86441 transitions. [2023-11-29 04:11:51,830 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 59632 [2023-11-29 04:11:51,957 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60073 states to 60073 states and 86441 transitions. [2023-11-29 04:11:51,957 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60073 [2023-11-29 04:11:51,981 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60073 [2023-11-29 04:11:51,982 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60073 states and 86441 transitions. [2023-11-29 04:11:52,004 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:52,004 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60073 states and 86441 transitions. [2023-11-29 04:11:52,160 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60073 states and 86441 transitions. [2023-11-29 04:11:52,468 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60073 to 27180. [2023-11-29 04:11:52,492 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 27180 states, 27180 states have (on average 1.4377115526122148) internal successors, (39077), 27179 states have internal predecessors, (39077), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:52,552 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 27180 states to 27180 states and 39077 transitions. [2023-11-29 04:11:52,552 INFO L240 hiAutomatonCegarLoop]: Abstraction has 27180 states and 39077 transitions. [2023-11-29 04:11:52,553 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:11:52,553 INFO L428 stractBuchiCegarLoop]: Abstraction has 27180 states and 39077 transitions. [2023-11-29 04:11:52,553 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 04:11:52,553 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 27180 states and 39077 transitions. [2023-11-29 04:11:52,627 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 26936 [2023-11-29 04:11:52,627 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:52,627 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:52,629 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:52,629 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:52,629 INFO L748 eck$LassoCheckResult]: Stem: 186544#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 186545#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 187377#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 187378#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 187323#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 187324#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 187296#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 187093#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 187094#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 186878#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 186879#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 187416#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 187283#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 186946#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 186701#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 186702#L922 assume !(0 == ~M_E~0); 187483#L922-2 assume !(0 == ~T1_E~0); 187484#L927-1 assume !(0 == ~T2_E~0); 187164#L932-1 assume !(0 == ~T3_E~0); 187027#L937-1 assume !(0 == ~T4_E~0); 187028#L942-1 assume !(0 == ~T5_E~0); 187092#L947-1 assume !(0 == ~T6_E~0); 187168#L952-1 assume !(0 == ~T7_E~0); 187169#L957-1 assume !(0 == ~T8_E~0); 187236#L962-1 assume !(0 == ~T9_E~0); 187004#L967-1 assume !(0 == ~E_1~0); 187005#L972-1 assume !(0 == ~E_2~0); 187306#L977-1 assume !(0 == ~E_3~0); 187307#L982-1 assume !(0 == ~E_4~0); 186477#L987-1 assume !(0 == ~E_5~0); 186478#L992-1 assume !(0 == ~E_6~0); 186482#L997-1 assume !(0 == ~E_7~0); 186922#L1002-1 assume !(0 == ~E_8~0); 186909#L1007-1 assume !(0 == ~E_9~0); 186267#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186268#L443 assume !(1 == ~m_pc~0); 187186#L443-2 is_master_triggered_~__retres1~0#1 := 0; 187176#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 187177#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 186638#L1140 assume !(0 != activate_threads_~tmp~1#1); 186374#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 186375#L462 assume !(1 == ~t1_pc~0); 187020#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 187021#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 186311#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 186312#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 186856#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 186857#L481 assume !(1 == ~t2_pc~0); 186631#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 186630#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 186761#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 186724#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 186725#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 186826#L500 assume !(1 == ~t3_pc~0); 187366#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 187339#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 186274#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 186275#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 186272#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 186273#L519 assume !(1 == ~t4_pc~0); 187081#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 186823#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 186376#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 186377#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 186676#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 186438#L538 assume !(1 == ~t5_pc~0); 186439#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 186336#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 186337#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 186616#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 186617#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 187220#L557 assume 1 == ~t6_pc~0; 186989#L558 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 186654#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 186743#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 186677#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 186678#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 187463#L576 assume !(1 == ~t7_pc~0); 186642#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 186643#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 186988#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 187480#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 187274#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 186764#L595 assume 1 == ~t8_pc~0; 186765#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 187292#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 187224#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 187119#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 187120#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 186567#L614 assume !(1 == ~t9_pc~0); 186568#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 186464#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 186465#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 186799#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 186727#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 186728#L1025 assume !(1 == ~M_E~0); 187010#L1025-2 assume !(1 == ~T1_E~0); 187073#L1030-1 assume !(1 == ~T2_E~0); 187209#L1035-1 assume !(1 == ~T3_E~0); 187342#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 200989#L1045-1 assume !(1 == ~T5_E~0); 207647#L1050-1 assume !(1 == ~T6_E~0); 207643#L1055-1 assume !(1 == ~T7_E~0); 207639#L1060-1 assume !(1 == ~T8_E~0); 207635#L1065-1 assume !(1 == ~T9_E~0); 207630#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 207563#L1075-1 assume !(1 == ~E_2~0); 207554#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 187159#L1085-1 assume !(1 == ~E_4~0); 187160#L1090-1 assume !(1 == ~E_5~0); 187405#L1095-1 assume !(1 == ~E_6~0); 187195#L1100-1 assume !(1 == ~E_7~0); 187196#L1105-1 assume !(1 == ~E_8~0); 186420#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 186421#L1115-1 assume { :end_inline_reset_delta_events } true; 186772#L1396-2 [2023-11-29 04:11:52,630 INFO L750 eck$LassoCheckResult]: Loop: 186772#L1396-2 assume !false; 207432#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 207428#L897-1 assume !false; 207427#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 207425#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 207414#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 207412#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 207410#L766 assume !(0 != eval_~tmp~0#1); 187227#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 186951#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 186899#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 186900#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 186608#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 186609#L932-3 assume !(0 == ~T3_E~0); 186790#L937-3 assume !(0 == ~T4_E~0); 186412#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 186413#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 186791#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 186792#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 187387#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 187250#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 187251#L972-3 assume !(0 == ~E_2~0); 187162#L977-3 assume !(0 == ~E_3~0); 187163#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 187493#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 186741#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 186742#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 186736#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 186737#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 186451#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 186452#L443-30 assume !(1 == ~m_pc~0); 186487#L443-32 is_master_triggered_~__retres1~0#1 := 0; 186486#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 186769#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 186775#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 187468#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 212864#L462-30 assume !(1 == ~t1_pc~0); 212863#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 212862#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 212861#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 212860#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 212859#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 212858#L481-30 assume !(1 == ~t2_pc~0); 212857#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 212855#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 212854#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 212852#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 212849#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 212847#L500-30 assume !(1 == ~t3_pc~0); 212845#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 212843#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 212841#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 212839#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 212837#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 212835#L519-30 assume !(1 == ~t4_pc~0); 212833#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 212831#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 212829#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 212828#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 212827#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 212826#L538-30 assume !(1 == ~t5_pc~0); 212825#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 212823#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 212821#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 212819#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 212816#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 212813#L557-30 assume 1 == ~t6_pc~0; 212811#L558-10 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 212808#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 212806#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 212804#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 212802#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 212801#L576-30 assume !(1 == ~t7_pc~0); 212798#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 212795#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 212793#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 212791#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 212789#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 212787#L595-30 assume 1 == ~t8_pc~0; 212784#L596-10 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 212763#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 209998#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 208580#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 208575#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 208551#L614-30 assume !(1 == ~t9_pc~0); 208434#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 208261#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 208260#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 208259#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 208208#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 208207#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 208206#L1025-5 assume !(1 == ~T1_E~0); 187075#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 187076#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 187419#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 187481#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 187411#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 187291#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 186342#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 186343#L1065-3 assume !(1 == ~T9_E~0); 187314#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 187144#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 187145#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 187420#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 187300#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 187301#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 187327#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 187328#L1105-3 assume !(1 == ~E_8~0); 186500#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 186501#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 187347#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 186353#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 186509#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 186703#L1415 assume !(0 == start_simulation_~tmp~3#1); 187310#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 207458#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 207448#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 207446#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 207444#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 207443#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 207440#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 207436#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 186772#L1396-2 [2023-11-29 04:11:52,630 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:52,630 INFO L85 PathProgramCache]: Analyzing trace with hash -327104070, now seen corresponding path program 1 times [2023-11-29 04:11:52,630 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:52,631 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [986436865] [2023-11-29 04:11:52,631 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:52,631 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:52,647 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:52,822 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:52,822 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:52,823 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [986436865] [2023-11-29 04:11:52,823 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [986436865] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:52,823 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:52,823 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:11:52,823 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [721320188] [2023-11-29 04:11:52,823 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:52,824 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:52,824 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:52,824 INFO L85 PathProgramCache]: Analyzing trace with hash -373555031, now seen corresponding path program 1 times [2023-11-29 04:11:52,824 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:52,824 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1779180140] [2023-11-29 04:11:52,824 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:52,825 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:52,837 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:52,866 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:52,866 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:52,866 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1779180140] [2023-11-29 04:11:52,866 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1779180140] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:52,866 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:52,866 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:52,866 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1967162435] [2023-11-29 04:11:52,867 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:52,867 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:52,867 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:52,867 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:52,867 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:52,868 INFO L87 Difference]: Start difference. First operand 27180 states and 39077 transitions. cyclomatic complexity: 11929 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:53,056 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:53,056 INFO L93 Difference]: Finished difference Result 51555 states and 73842 transitions. [2023-11-29 04:11:53,056 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51555 states and 73842 transitions. [2023-11-29 04:11:53,349 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 51168 [2023-11-29 04:11:53,508 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51555 states to 51555 states and 73842 transitions. [2023-11-29 04:11:53,508 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51555 [2023-11-29 04:11:53,629 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51555 [2023-11-29 04:11:53,630 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51555 states and 73842 transitions. [2023-11-29 04:11:53,653 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:53,653 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51555 states and 73842 transitions. [2023-11-29 04:11:53,680 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51555 states and 73842 transitions. [2023-11-29 04:11:54,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51555 to 51491. [2023-11-29 04:11:54,169 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 51491 states, 51491 states have (on average 1.4328329222582588) internal successors, (73778), 51490 states have internal predecessors, (73778), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:54,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 51491 states to 51491 states and 73778 transitions. [2023-11-29 04:11:54,277 INFO L240 hiAutomatonCegarLoop]: Abstraction has 51491 states and 73778 transitions. [2023-11-29 04:11:54,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:54,278 INFO L428 stractBuchiCegarLoop]: Abstraction has 51491 states and 73778 transitions. [2023-11-29 04:11:54,278 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 04:11:54,279 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 51491 states and 73778 transitions. [2023-11-29 04:11:54,425 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 51104 [2023-11-29 04:11:54,425 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:54,425 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:54,428 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:54,428 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:54,429 INFO L748 eck$LassoCheckResult]: Stem: 265282#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 265283#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 266200#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 266201#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 266123#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 266124#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 266090#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 265847#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 265848#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 265630#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 265631#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 266238#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 266078#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 265699#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 265448#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 265449#L922 assume !(0 == ~M_E~0); 266312#L922-2 assume !(0 == ~T1_E~0); 266313#L927-1 assume !(0 == ~T2_E~0); 265923#L932-1 assume !(0 == ~T3_E~0); 265774#L937-1 assume !(0 == ~T4_E~0); 265775#L942-1 assume !(0 == ~T5_E~0); 265846#L947-1 assume !(0 == ~T6_E~0); 265928#L952-1 assume !(0 == ~T7_E~0); 265929#L957-1 assume !(0 == ~T8_E~0); 266013#L962-1 assume !(0 == ~T9_E~0); 265750#L967-1 assume !(0 == ~E_1~0); 265751#L972-1 assume !(0 == ~E_2~0); 266102#L977-1 assume !(0 == ~E_3~0); 266103#L982-1 assume !(0 == ~E_4~0); 265216#L987-1 assume !(0 == ~E_5~0); 265217#L992-1 assume !(0 == ~E_6~0); 265223#L997-1 assume !(0 == ~E_7~0); 265670#L1002-1 assume !(0 == ~E_8~0); 265657#L1007-1 assume !(0 == ~E_9~0); 265009#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 265010#L443 assume !(1 == ~m_pc~0); 265945#L443-2 is_master_triggered_~__retres1~0#1 := 0; 265936#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 265937#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 265381#L1140 assume !(0 != activate_threads_~tmp~1#1); 265115#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 265116#L462 assume !(1 == ~t1_pc~0); 265764#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 265765#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 265051#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 265052#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 265607#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 265608#L481 assume !(1 == ~t2_pc~0); 265374#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 265373#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 265511#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 265473#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 265474#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 265575#L500 assume !(1 == ~t3_pc~0); 266189#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 266144#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 265016#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 265017#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 265011#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 265012#L519 assume !(1 == ~t4_pc~0); 265834#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 265574#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 265117#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 265118#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 265419#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 265179#L538 assume !(1 == ~t5_pc~0); 265180#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 265076#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 265077#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 265359#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 265360#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 265992#L557 assume !(1 == ~t6_pc~0); 265396#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 265397#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 265492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 265420#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 265421#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 266277#L576 assume !(1 == ~t7_pc~0); 265385#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 265386#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 265738#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 266309#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 266069#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 265513#L595 assume 1 == ~t8_pc~0; 265514#L596 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 266086#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 265999#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 265877#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 265878#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 265310#L614 assume !(1 == ~t9_pc~0); 265311#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 265205#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 265206#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 265549#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 265476#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 265477#L1025 assume !(1 == ~M_E~0); 265758#L1025-2 assume !(1 == ~T1_E~0); 265825#L1030-1 assume !(1 == ~T2_E~0); 265978#L1035-1 assume !(1 == ~T3_E~0); 271875#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 271873#L1045-1 assume !(1 == ~T5_E~0); 271872#L1050-1 assume !(1 == ~T6_E~0); 271871#L1055-1 assume !(1 == ~T7_E~0); 271869#L1060-1 assume !(1 == ~T8_E~0); 271867#L1065-1 assume !(1 == ~T9_E~0); 271865#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 271863#L1075-1 assume !(1 == ~E_2~0); 271860#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 271859#L1085-1 assume !(1 == ~E_4~0); 271855#L1090-1 assume !(1 == ~E_5~0); 271854#L1095-1 assume !(1 == ~E_6~0); 271853#L1100-1 assume !(1 == ~E_7~0); 271852#L1105-1 assume !(1 == ~E_8~0); 271851#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 271826#L1115-1 assume { :end_inline_reset_delta_events } true; 271823#L1396-2 [2023-11-29 04:11:54,429 INFO L750 eck$LassoCheckResult]: Loop: 271823#L1396-2 assume !false; 271821#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 271816#L897-1 assume !false; 271814#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 271811#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 271799#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 271797#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 271794#L766 assume !(0 != eval_~tmp~0#1); 271795#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 282639#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 282637#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 282634#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 282632#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 282630#L932-3 assume !(0 == ~T3_E~0); 282628#L937-3 assume !(0 == ~T4_E~0); 282626#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 282624#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 282622#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 282620#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 282590#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 282583#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 282576#L972-3 assume !(0 == ~E_2~0); 282568#L977-3 assume !(0 == ~E_3~0); 282560#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 282553#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 282544#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 282537#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 282529#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 282523#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 282517#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 282510#L443-30 assume 1 == ~m_pc~0; 282502#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 282499#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 282496#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 282495#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 282494#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 282493#L462-30 assume !(1 == ~t1_pc~0); 282491#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 282489#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 282487#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 282485#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 282483#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 282481#L481-30 assume !(1 == ~t2_pc~0); 282468#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 282463#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 282460#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 282419#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 282416#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 282414#L500-30 assume !(1 == ~t3_pc~0); 282412#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 282410#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 282408#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 282406#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 282404#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 282402#L519-30 assume !(1 == ~t4_pc~0); 282400#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 282398#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 282383#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 282377#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 282369#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 282362#L538-30 assume !(1 == ~t5_pc~0); 282356#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 282347#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 282339#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 282332#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 282325#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 282319#L557-30 assume !(1 == ~t6_pc~0); 282313#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 282307#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 282301#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 282295#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 282288#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 282282#L576-30 assume !(1 == ~t7_pc~0); 282276#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 282267#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 282261#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 282256#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 282250#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 282244#L595-30 assume !(1 == ~t8_pc~0); 282237#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 282231#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 282225#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 282220#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 282215#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 282210#L614-30 assume 1 == ~t9_pc~0; 281330#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 281324#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 281319#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 281314#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 281310#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 281305#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 281299#L1025-5 assume !(1 == ~T1_E~0); 281292#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 277288#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 281279#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 281271#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 281267#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 281261#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 281254#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 281248#L1065-3 assume !(1 == ~T9_E~0); 281243#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 281238#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 281233#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 281226#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 281219#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 281215#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 281210#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 281207#L1105-3 assume !(1 == ~E_8~0); 281201#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 281195#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 280765#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 280754#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 280752#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 280673#L1415 assume !(0 == start_simulation_~tmp~3#1); 280671#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 271846#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 271837#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 271835#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 271833#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 271831#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 271829#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 271827#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 271823#L1396-2 [2023-11-29 04:11:54,430 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:54,430 INFO L85 PathProgramCache]: Analyzing trace with hash -1602206759, now seen corresponding path program 1 times [2023-11-29 04:11:54,430 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:54,430 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [294215259] [2023-11-29 04:11:54,430 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:54,431 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:54,450 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:54,616 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:54,617 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:54,617 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [294215259] [2023-11-29 04:11:54,617 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [294215259] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:54,617 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:54,617 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:11:54,622 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [546283879] [2023-11-29 04:11:54,622 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:54,622 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:54,623 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:54,623 INFO L85 PathProgramCache]: Analyzing trace with hash -537698071, now seen corresponding path program 1 times [2023-11-29 04:11:54,623 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:54,623 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1769567418] [2023-11-29 04:11:54,623 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:54,624 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:54,638 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:54,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:54,674 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:54,674 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1769567418] [2023-11-29 04:11:54,674 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1769567418] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:54,675 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:54,675 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:54,675 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [539408102] [2023-11-29 04:11:54,675 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:54,675 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:54,675 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:54,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:11:54,676 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:11:54,676 INFO L87 Difference]: Start difference. First operand 51491 states and 73778 transitions. cyclomatic complexity: 22351 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:55,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:55,141 INFO L93 Difference]: Finished difference Result 97602 states and 139391 transitions. [2023-11-29 04:11:55,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 97602 states and 139391 transitions. [2023-11-29 04:11:55,404 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 96864 [2023-11-29 04:11:55,699 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 97602 states to 97602 states and 139391 transitions. [2023-11-29 04:11:55,700 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 97602 [2023-11-29 04:11:55,737 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 97602 [2023-11-29 04:11:55,737 INFO L73 IsDeterministic]: Start isDeterministic. Operand 97602 states and 139391 transitions. [2023-11-29 04:11:55,802 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:55,803 INFO L218 hiAutomatonCegarLoop]: Abstraction has 97602 states and 139391 transitions. [2023-11-29 04:11:55,843 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 97602 states and 139391 transitions. [2023-11-29 04:11:56,628 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 97602 to 97474. [2023-11-29 04:11:56,686 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 97474 states, 97474 states have (on average 1.4287194533926997) internal successors, (139263), 97473 states have internal predecessors, (139263), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:57,115 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 97474 states to 97474 states and 139263 transitions. [2023-11-29 04:11:57,115 INFO L240 hiAutomatonCegarLoop]: Abstraction has 97474 states and 139263 transitions. [2023-11-29 04:11:57,116 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:57,116 INFO L428 stractBuchiCegarLoop]: Abstraction has 97474 states and 139263 transitions. [2023-11-29 04:11:57,116 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 04:11:57,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 97474 states and 139263 transitions. [2023-11-29 04:11:57,270 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 96736 [2023-11-29 04:11:57,270 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:57,270 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:57,272 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:57,272 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:57,272 INFO L748 eck$LassoCheckResult]: Stem: 414384#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 414385#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 415284#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 415285#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 415214#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 415215#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 415184#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 414949#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 414950#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 414727#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 414728#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 415319#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 415166#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 414795#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 414544#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 414545#L922 assume !(0 == ~M_E~0); 415408#L922-2 assume !(0 == ~T1_E~0); 415409#L927-1 assume !(0 == ~T2_E~0); 415023#L932-1 assume !(0 == ~T3_E~0); 414875#L937-1 assume !(0 == ~T4_E~0); 414876#L942-1 assume !(0 == ~T5_E~0); 414948#L947-1 assume !(0 == ~T6_E~0); 415029#L952-1 assume !(0 == ~T7_E~0); 415030#L957-1 assume !(0 == ~T8_E~0); 415105#L962-1 assume !(0 == ~T9_E~0); 414851#L967-1 assume !(0 == ~E_1~0); 414852#L972-1 assume !(0 == ~E_2~0); 415196#L977-1 assume !(0 == ~E_3~0); 415197#L982-1 assume !(0 == ~E_4~0); 414316#L987-1 assume !(0 == ~E_5~0); 414317#L992-1 assume !(0 == ~E_6~0); 414323#L997-1 assume !(0 == ~E_7~0); 414770#L1002-1 assume !(0 == ~E_8~0); 414757#L1007-1 assume !(0 == ~E_9~0); 414109#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 414110#L443 assume !(1 == ~m_pc~0); 415048#L443-2 is_master_triggered_~__retres1~0#1 := 0; 415039#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 415040#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 414481#L1140 assume !(0 != activate_threads_~tmp~1#1); 414215#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 414216#L462 assume !(1 == ~t1_pc~0); 414865#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 414866#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 414151#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 414152#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 414705#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 414706#L481 assume !(1 == ~t2_pc~0); 414474#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 414473#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 414609#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 414568#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 414569#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 414672#L500 assume !(1 == ~t3_pc~0); 415273#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 415236#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 414116#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 414117#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 414111#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 414112#L519 assume !(1 == ~t4_pc~0); 414935#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 414671#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 414217#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 414218#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 414519#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 414279#L538 assume !(1 == ~t5_pc~0); 414280#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 414176#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 414177#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 414459#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 414460#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 415084#L557 assume !(1 == ~t6_pc~0); 414495#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 414496#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 414588#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 414520#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 414521#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 415360#L576 assume !(1 == ~t7_pc~0); 414485#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 414486#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 414838#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 415400#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 415155#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 414610#L595 assume !(1 == ~t8_pc~0); 414611#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 415178#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 415091#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 414975#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 414976#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 414410#L614 assume !(1 == ~t9_pc~0); 414411#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 414305#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 414306#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 414645#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 414572#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 414573#L1025 assume !(1 == ~M_E~0); 414859#L1025-2 assume !(1 == ~T1_E~0); 414923#L1030-1 assume !(1 == ~T2_E~0); 415074#L1035-1 assume !(1 == ~T3_E~0); 423198#L1040-1 assume 1 == ~T4_E~0;~T4_E~0 := 2; 415220#L1045-1 assume !(1 == ~T5_E~0); 414470#L1050-1 assume !(1 == ~T6_E~0); 414471#L1055-1 assume !(1 == ~T7_E~0); 414290#L1060-1 assume !(1 == ~T8_E~0); 414291#L1065-1 assume !(1 == ~T9_E~0); 414355#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 415031#L1075-1 assume !(1 == ~E_2~0); 415032#L1080-1 assume 1 == ~E_3~0;~E_3~0 := 2; 415439#L1085-1 assume !(1 == ~E_4~0); 423270#L1090-1 assume !(1 == ~E_5~0); 423269#L1095-1 assume !(1 == ~E_6~0); 423268#L1100-1 assume !(1 == ~E_7~0); 423267#L1105-1 assume !(1 == ~E_8~0); 423256#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 423246#L1115-1 assume { :end_inline_reset_delta_events } true; 423244#L1396-2 [2023-11-29 04:11:57,272 INFO L750 eck$LassoCheckResult]: Loop: 423244#L1396-2 assume !false; 423242#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 423237#L897-1 assume !false; 423235#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 423232#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 423221#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 423219#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 423216#L766 assume !(0 != eval_~tmp~0#1); 423217#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 439744#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 439743#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 439742#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 439741#L927-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 439740#L932-3 assume !(0 == ~T3_E~0); 439738#L937-3 assume !(0 == ~T4_E~0); 439736#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 439735#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 439734#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 439732#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 439731#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 439730#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 439729#L972-3 assume !(0 == ~E_2~0); 439728#L977-3 assume !(0 == ~E_3~0); 439727#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 439726#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 439724#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 439722#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 439720#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 439717#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 439715#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 439713#L443-30 assume !(1 == ~m_pc~0); 439710#L443-32 is_master_triggered_~__retres1~0#1 := 0; 439707#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 439705#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 439703#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 439701#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 439699#L462-30 assume !(1 == ~t1_pc~0); 439697#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 439695#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 439692#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 439690#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 439688#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 439686#L481-30 assume !(1 == ~t2_pc~0); 439684#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 439681#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 439679#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 439677#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 439675#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 439673#L500-30 assume !(1 == ~t3_pc~0); 439671#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 439669#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 439667#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 439665#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 439663#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 439661#L519-30 assume !(1 == ~t4_pc~0); 439659#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 439655#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 439653#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 439651#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 439649#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 439646#L538-30 assume !(1 == ~t5_pc~0); 439644#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 442938#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 442936#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 439636#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 439633#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 439631#L557-30 assume !(1 == ~t6_pc~0); 439629#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 439627#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 439625#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 439623#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 439621#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 439619#L576-30 assume 1 == ~t7_pc~0; 439616#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 426996#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 426993#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 426991#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 426985#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 426968#L595-30 assume !(1 == ~t8_pc~0); 426966#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 426964#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 426962#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 426959#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 426956#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 426953#L614-30 assume 1 == ~t9_pc~0; 426948#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 426945#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 426942#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 426938#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 426934#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 426928#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 426921#L1025-5 assume !(1 == ~T1_E~0); 426914#L1030-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 422768#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 425074#L1040-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 425069#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 425067#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 425065#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 425063#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 425061#L1065-3 assume !(1 == ~T9_E~0); 423326#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 423324#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 423322#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 423318#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 423316#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 423314#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 423312#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 423310#L1105-3 assume !(1 == ~E_8~0); 423308#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 423306#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 423304#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 423293#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 423291#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 423274#L1415 assume !(0 == start_simulation_~tmp~3#1); 423272#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 423263#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 423255#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 423254#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 423253#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 423252#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 423250#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 423247#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 423244#L1396-2 [2023-11-29 04:11:57,273 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:57,273 INFO L85 PathProgramCache]: Analyzing trace with hash -683232136, now seen corresponding path program 1 times [2023-11-29 04:11:57,273 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:57,273 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [592941020] [2023-11-29 04:11:57,273 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:57,274 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:57,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:57,350 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:57,351 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:57,351 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [592941020] [2023-11-29 04:11:57,351 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [592941020] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:57,351 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:57,351 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:57,351 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1264132769] [2023-11-29 04:11:57,351 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:57,352 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:57,352 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:57,352 INFO L85 PathProgramCache]: Analyzing trace with hash -433890775, now seen corresponding path program 1 times [2023-11-29 04:11:57,352 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:57,352 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [274871257] [2023-11-29 04:11:57,353 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:57,353 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:57,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:57,400 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:57,400 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:57,400 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [274871257] [2023-11-29 04:11:57,400 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [274871257] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:57,400 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:57,400 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:57,400 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1798645533] [2023-11-29 04:11:57,401 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:57,401 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:57,401 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:57,401 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:11:57,401 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:11:57,402 INFO L87 Difference]: Start difference. First operand 97474 states and 139263 transitions. cyclomatic complexity: 41917 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:57,575 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:57,576 INFO L93 Difference]: Finished difference Result 48786 states and 69423 transitions. [2023-11-29 04:11:57,576 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48786 states and 69423 transitions. [2023-11-29 04:11:57,900 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 48368 [2023-11-29 04:11:58,016 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48786 states to 48786 states and 69423 transitions. [2023-11-29 04:11:58,016 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48786 [2023-11-29 04:11:58,042 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48786 [2023-11-29 04:11:58,042 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48786 states and 69423 transitions. [2023-11-29 04:11:58,066 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:58,066 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48786 states and 69423 transitions. [2023-11-29 04:11:58,095 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48786 states and 69423 transitions. [2023-11-29 04:11:58,291 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48786 to 25611. [2023-11-29 04:11:58,305 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.4194681972589902) internal successors, (36354), 25610 states have internal predecessors, (36354), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:58,344 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 36354 transitions. [2023-11-29 04:11:58,344 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 36354 transitions. [2023-11-29 04:11:58,345 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:11:58,345 INFO L428 stractBuchiCegarLoop]: Abstraction has 25611 states and 36354 transitions. [2023-11-29 04:11:58,345 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 04:11:58,345 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 36354 transitions. [2023-11-29 04:11:58,401 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2023-11-29 04:11:58,401 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:58,401 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:58,403 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:58,403 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:58,403 INFO L748 eck$LassoCheckResult]: Stem: 560652#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 560653#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 561474#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 561475#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 561420#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 561421#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 561398#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 561195#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 561196#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 560986#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 560987#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 561504#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 561388#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 561055#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 560809#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 560810#L922 assume !(0 == ~M_E~0); 561553#L922-2 assume !(0 == ~T1_E~0); 561554#L927-1 assume !(0 == ~T2_E~0); 561265#L932-1 assume !(0 == ~T3_E~0); 561129#L937-1 assume !(0 == ~T4_E~0); 561130#L942-1 assume !(0 == ~T5_E~0); 561194#L947-1 assume !(0 == ~T6_E~0); 561270#L952-1 assume !(0 == ~T7_E~0); 561271#L957-1 assume !(0 == ~T8_E~0); 561336#L962-1 assume !(0 == ~T9_E~0); 561106#L967-1 assume !(0 == ~E_1~0); 561107#L972-1 assume !(0 == ~E_2~0); 561402#L977-1 assume !(0 == ~E_3~0); 561403#L982-1 assume !(0 == ~E_4~0); 560585#L987-1 assume !(0 == ~E_5~0); 560586#L992-1 assume !(0 == ~E_6~0); 560592#L997-1 assume !(0 == ~E_7~0); 561030#L1002-1 assume !(0 == ~E_8~0); 561017#L1007-1 assume !(0 == ~E_9~0); 560379#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 560380#L443 assume !(1 == ~m_pc~0); 561287#L443-2 is_master_triggered_~__retres1~0#1 := 0; 561278#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 561279#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 560745#L1140 assume !(0 != activate_threads_~tmp~1#1); 560485#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 560486#L462 assume !(1 == ~t1_pc~0); 561122#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 561123#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 560423#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 560424#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 560964#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 560965#L481 assume !(1 == ~t2_pc~0); 560738#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 560737#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 560871#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 560833#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 560834#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 560934#L500 assume !(1 == ~t3_pc~0); 561465#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 561436#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 560386#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 560387#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 560384#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 560385#L519 assume !(1 == ~t4_pc~0); 561182#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 560931#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 560487#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 560488#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 560783#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 560549#L538 assume !(1 == ~t5_pc~0); 560550#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 560448#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 560449#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 560723#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 560724#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 561321#L557 assume !(1 == ~t6_pc~0); 560760#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 560761#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 560852#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 560784#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 560785#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 561535#L576 assume !(1 == ~t7_pc~0); 560749#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 560750#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 561091#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 561549#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 561380#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 560874#L595 assume !(1 == ~t8_pc~0); 560875#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 561394#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 561325#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 561219#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 561220#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 560675#L614 assume !(1 == ~t9_pc~0); 560676#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 560575#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 560576#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 560908#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 560836#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 560837#L1025 assume !(1 == ~M_E~0); 561112#L1025-2 assume !(1 == ~T1_E~0); 561175#L1030-1 assume !(1 == ~T2_E~0); 561312#L1035-1 assume !(1 == ~T3_E~0); 560829#L1040-1 assume !(1 == ~T4_E~0); 560830#L1045-1 assume !(1 == ~T5_E~0); 560734#L1050-1 assume !(1 == ~T6_E~0); 560735#L1055-1 assume !(1 == ~T7_E~0); 560560#L1060-1 assume !(1 == ~T8_E~0); 560561#L1065-1 assume !(1 == ~T9_E~0); 560623#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 561273#L1075-1 assume !(1 == ~E_2~0); 561274#L1080-1 assume !(1 == ~E_3~0); 561260#L1085-1 assume !(1 == ~E_4~0); 561261#L1090-1 assume !(1 == ~E_5~0); 561496#L1095-1 assume !(1 == ~E_6~0); 561296#L1100-1 assume !(1 == ~E_7~0); 561297#L1105-1 assume !(1 == ~E_8~0); 560531#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 560532#L1115-1 assume { :end_inline_reset_delta_events } true; 560882#L1396-2 [2023-11-29 04:11:58,404 INFO L750 eck$LassoCheckResult]: Loop: 560882#L1396-2 assume !false; 569646#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 569642#L897-1 assume !false; 569640#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 569636#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 569625#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 569623#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 569620#L766 assume !(0 != eval_~tmp~0#1); 569621#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 569990#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 569988#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 569986#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 569984#L927-3 assume !(0 == ~T2_E~0); 569982#L932-3 assume !(0 == ~T3_E~0); 569980#L937-3 assume !(0 == ~T4_E~0); 569978#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 569973#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 569971#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 569969#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 569968#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 569957#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 569955#L972-3 assume !(0 == ~E_2~0); 569953#L977-3 assume !(0 == ~E_3~0); 569950#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 569946#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 569942#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 569938#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 569934#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 569931#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 569928#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 569927#L443-30 assume 1 == ~m_pc~0; 569925#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 569924#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 569923#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 569922#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 569921#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 569920#L462-30 assume !(1 == ~t1_pc~0); 569919#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 569918#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 569917#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 569916#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 569915#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 569914#L481-30 assume !(1 == ~t2_pc~0); 569912#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 569909#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 569907#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 569906#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 569903#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 569902#L500-30 assume !(1 == ~t3_pc~0); 569901#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 569900#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 569899#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 569898#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 569897#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 569896#L519-30 assume !(1 == ~t4_pc~0); 569895#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 569894#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 569893#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 569892#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 569891#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 569889#L538-30 assume !(1 == ~t5_pc~0); 569886#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 569885#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 569883#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 569881#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 569878#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 569877#L557-30 assume !(1 == ~t6_pc~0); 569874#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 569873#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 569872#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 569871#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 569870#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 569869#L576-30 assume 1 == ~t7_pc~0; 569867#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 569866#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 569865#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 569864#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 569863#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 569862#L595-30 assume !(1 == ~t8_pc~0); 569861#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 569860#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 569859#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 569858#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 569857#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 569856#L614-30 assume 1 == ~t9_pc~0; 569854#L615-10 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 569853#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 569852#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 569851#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 569849#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 569846#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 569844#L1025-5 assume !(1 == ~T1_E~0); 569842#L1030-3 assume !(1 == ~T2_E~0); 569840#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 569838#L1040-3 assume !(1 == ~T4_E~0); 569836#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 569834#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 569832#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 569830#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 569828#L1065-3 assume !(1 == ~T9_E~0); 569826#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 569824#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 569821#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 569819#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 569817#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 569815#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 569813#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 569811#L1105-3 assume !(1 == ~E_8~0); 569809#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 569807#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 569804#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 569793#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 569791#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 569682#L1415 assume !(0 == start_simulation_~tmp~3#1); 569679#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 569667#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 569659#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 569657#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 569655#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 569653#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 569651#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 569649#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 560882#L1396-2 [2023-11-29 04:11:58,404 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:58,405 INFO L85 PathProgramCache]: Analyzing trace with hash 1781320180, now seen corresponding path program 1 times [2023-11-29 04:11:58,405 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:58,405 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [686349668] [2023-11-29 04:11:58,405 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:58,405 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:58,420 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:58,478 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:58,479 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:58,479 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [686349668] [2023-11-29 04:11:58,479 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [686349668] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:58,479 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:58,479 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:58,479 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [555154821] [2023-11-29 04:11:58,479 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:58,480 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:58,480 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:58,480 INFO L85 PathProgramCache]: Analyzing trace with hash -1425552572, now seen corresponding path program 1 times [2023-11-29 04:11:58,480 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:58,480 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1736749462] [2023-11-29 04:11:58,481 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:58,481 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:58,494 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:58,526 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:58,526 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:58,526 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1736749462] [2023-11-29 04:11:58,526 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1736749462] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:58,526 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:58,526 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:58,527 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1809287441] [2023-11-29 04:11:58,527 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:58,527 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:58,527 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:58,528 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:11:58,528 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:11:58,528 INFO L87 Difference]: Start difference. First operand 25611 states and 36354 transitions. cyclomatic complexity: 10775 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:58,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:11:58,890 INFO L93 Difference]: Finished difference Result 52812 states and 74750 transitions. [2023-11-29 04:11:58,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 52812 states and 74750 transitions. [2023-11-29 04:11:59,053 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 52240 [2023-11-29 04:11:59,147 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 52812 states to 52812 states and 74750 transitions. [2023-11-29 04:11:59,147 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 52812 [2023-11-29 04:11:59,169 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 52812 [2023-11-29 04:11:59,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 52812 states and 74750 transitions. [2023-11-29 04:11:59,187 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:11:59,188 INFO L218 hiAutomatonCegarLoop]: Abstraction has 52812 states and 74750 transitions. [2023-11-29 04:11:59,210 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 52812 states and 74750 transitions. [2023-11-29 04:11:59,563 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 52812 to 28595. [2023-11-29 04:11:59,574 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28595 states, 28595 states have (on average 1.4160867284490295) internal successors, (40493), 28594 states have internal predecessors, (40493), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:11:59,627 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28595 states to 28595 states and 40493 transitions. [2023-11-29 04:11:59,627 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28595 states and 40493 transitions. [2023-11-29 04:11:59,628 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:11:59,628 INFO L428 stractBuchiCegarLoop]: Abstraction has 28595 states and 40493 transitions. [2023-11-29 04:11:59,628 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 04:11:59,628 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28595 states and 40493 transitions. [2023-11-29 04:11:59,696 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2023-11-29 04:11:59,696 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:11:59,696 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:11:59,697 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:59,698 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:11:59,698 INFO L748 eck$LassoCheckResult]: Stem: 639087#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 639088#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 639928#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 639929#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 639864#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 639865#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 639837#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 639628#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 639629#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 639419#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 639420#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 639959#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 639827#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 639489#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 639242#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 639243#L922 assume !(0 == ~M_E~0); 640024#L922-2 assume !(0 == ~T1_E~0); 640025#L927-1 assume !(0 == ~T2_E~0); 639700#L932-1 assume !(0 == ~T3_E~0); 639566#L937-1 assume !(0 == ~T4_E~0); 639567#L942-1 assume !(0 == ~T5_E~0); 639627#L947-1 assume !(0 == ~T6_E~0); 639705#L952-1 assume !(0 == ~T7_E~0); 639706#L957-1 assume !(0 == ~T8_E~0); 639778#L962-1 assume !(0 == ~T9_E~0); 639541#L967-1 assume 0 == ~E_1~0;~E_1~0 := 1; 639542#L972-1 assume !(0 == ~E_2~0); 639847#L977-1 assume !(0 == ~E_3~0); 639848#L982-1 assume !(0 == ~E_4~0); 639019#L987-1 assume !(0 == ~E_5~0); 639020#L992-1 assume !(0 == ~E_6~0); 639464#L997-1 assume !(0 == ~E_7~0); 639465#L1002-1 assume !(0 == ~E_8~0); 639448#L1007-1 assume !(0 == ~E_9~0); 639449#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 639970#L443 assume !(1 == ~m_pc~0); 639971#L443-2 is_master_triggered_~__retres1~0#1 := 0; 639714#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 639715#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 639181#L1140 assume !(0 != activate_threads_~tmp~1#1); 638918#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 638919#L462 assume !(1 == ~t1_pc~0); 639556#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 639557#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 638854#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 638855#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 639398#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 639399#L481 assume !(1 == ~t2_pc~0); 639175#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 639174#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 640097#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 640096#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 639365#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 639366#L500 assume !(1 == ~t3_pc~0); 640095#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 640094#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 638819#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 638820#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 638814#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 638815#L519 assume !(1 == ~t4_pc~0); 639619#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 639620#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 640089#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 640088#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 640087#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 640086#L538 assume !(1 == ~t5_pc~0); 639397#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 640085#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 640082#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 640079#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 639760#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 639761#L557 assume !(1 == ~t6_pc~0); 640077#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 640076#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 640075#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 640074#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 640073#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 640032#L576 assume !(1 == ~t7_pc~0); 639185#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 639186#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 639529#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 640020#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 640068#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 640067#L595 assume !(1 == ~t8_pc~0); 640066#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 640065#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 640064#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 640063#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 640062#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 640061#L614 assume !(1 == ~t9_pc~0); 640059#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 640058#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 639338#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 639339#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 639267#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 639268#L1025 assume !(1 == ~M_E~0); 639549#L1025-2 assume !(1 == ~T1_E~0); 639611#L1030-1 assume !(1 == ~T2_E~0); 639753#L1035-1 assume !(1 == ~T3_E~0); 639259#L1040-1 assume !(1 == ~T4_E~0); 639260#L1045-1 assume !(1 == ~T5_E~0); 639171#L1050-1 assume !(1 == ~T6_E~0); 639172#L1055-1 assume !(1 == ~T7_E~0); 640048#L1060-1 assume !(1 == ~T8_E~0); 640047#L1065-1 assume !(1 == ~T9_E~0); 640046#L1070-1 assume 1 == ~E_1~0;~E_1~0 := 2; 639707#L1075-1 assume !(1 == ~E_2~0); 639708#L1080-1 assume !(1 == ~E_3~0); 639695#L1085-1 assume !(1 == ~E_4~0); 639696#L1090-1 assume !(1 == ~E_5~0); 639950#L1095-1 assume !(1 == ~E_6~0); 639735#L1100-1 assume !(1 == ~E_7~0); 639736#L1105-1 assume !(1 == ~E_8~0); 638964#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 638965#L1115-1 assume { :end_inline_reset_delta_events } true; 639313#L1396-2 [2023-11-29 04:11:59,698 INFO L750 eck$LassoCheckResult]: Loop: 639313#L1396-2 assume !false; 649125#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 649120#L897-1 assume !false; 649118#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 649112#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 649021#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 648944#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 648934#L766 assume !(0 != eval_~tmp~0#1); 648935#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 649513#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 649511#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 649509#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 649413#L927-3 assume !(0 == ~T2_E~0); 649411#L932-3 assume !(0 == ~T3_E~0); 649409#L937-3 assume !(0 == ~T4_E~0); 649407#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 649405#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 649403#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 649401#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 649399#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 649397#L967-3 assume 0 == ~E_1~0;~E_1~0 := 1; 649396#L972-3 assume !(0 == ~E_2~0); 649395#L977-3 assume !(0 == ~E_3~0); 649394#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 649393#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 649392#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 649391#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 649390#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 649389#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 649388#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 649387#L443-30 assume 1 == ~m_pc~0; 649385#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 649384#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 649383#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 649382#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 649381#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 649380#L462-30 assume !(1 == ~t1_pc~0); 649379#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 649378#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 649377#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 649376#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 649375#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 649374#L481-30 assume !(1 == ~t2_pc~0); 649373#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 649371#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 649370#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 649369#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 649368#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 649367#L500-30 assume !(1 == ~t3_pc~0); 649366#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 649365#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 649364#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 649363#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 649362#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 649361#L519-30 assume !(1 == ~t4_pc~0); 649360#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 649359#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 649358#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 649357#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 649356#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 649355#L538-30 assume 1 == ~t5_pc~0; 649353#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 649351#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 649349#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 649347#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 649346#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 649345#L557-30 assume !(1 == ~t6_pc~0); 649344#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 649343#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 649342#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 649341#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 649340#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 649339#L576-30 assume 1 == ~t7_pc~0; 649337#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 649336#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 649335#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 649334#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 649333#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 649332#L595-30 assume !(1 == ~t8_pc~0); 649331#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 649330#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 649329#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 649328#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 649327#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 649326#L614-30 assume !(1 == ~t9_pc~0); 649325#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 649323#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 649322#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 649321#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 649320#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 649319#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 649318#L1025-5 assume !(1 == ~T1_E~0); 649317#L1030-3 assume !(1 == ~T2_E~0); 649316#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 649315#L1040-3 assume !(1 == ~T4_E~0); 649314#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 649313#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 649312#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 649311#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 649310#L1065-3 assume !(1 == ~T9_E~0); 649308#L1070-3 assume 1 == ~E_1~0;~E_1~0 := 2; 649306#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 649304#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 649301#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 649299#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 649297#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 649295#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 649293#L1105-3 assume !(1 == ~E_8~0); 649291#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 649289#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 649286#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 649275#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 649273#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 649162#L1415 assume !(0 == start_simulation_~tmp~3#1); 649160#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 649148#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 649140#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 649137#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 649135#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 649133#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 649131#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 649129#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 639313#L1396-2 [2023-11-29 04:11:59,699 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:59,699 INFO L85 PathProgramCache]: Analyzing trace with hash -95743050, now seen corresponding path program 1 times [2023-11-29 04:11:59,699 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:59,699 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [754018374] [2023-11-29 04:11:59,700 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:59,700 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:59,712 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:59,753 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:59,753 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:59,754 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [754018374] [2023-11-29 04:11:59,754 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [754018374] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:59,754 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:59,754 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:59,754 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48012376] [2023-11-29 04:11:59,754 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:59,755 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:11:59,755 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:11:59,755 INFO L85 PathProgramCache]: Analyzing trace with hash 1139280390, now seen corresponding path program 1 times [2023-11-29 04:11:59,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:11:59,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [600184610] [2023-11-29 04:11:59,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:11:59,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:11:59,769 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:11:59,795 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:11:59,795 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:11:59,795 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [600184610] [2023-11-29 04:11:59,796 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [600184610] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:11:59,796 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:11:59,796 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:11:59,796 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1915852245] [2023-11-29 04:11:59,796 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:11:59,797 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:11:59,797 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:11:59,798 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:11:59,798 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:11:59,798 INFO L87 Difference]: Start difference. First operand 28595 states and 40493 transitions. cyclomatic complexity: 11930 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:00,023 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:00,023 INFO L93 Difference]: Finished difference Result 48811 states and 68992 transitions. [2023-11-29 04:12:00,024 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 48811 states and 68992 transitions. [2023-11-29 04:12:00,194 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 48336 [2023-11-29 04:12:00,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 48811 states to 48811 states and 68992 transitions. [2023-11-29 04:12:00,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 48811 [2023-11-29 04:12:00,324 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 48811 [2023-11-29 04:12:00,325 INFO L73 IsDeterministic]: Start isDeterministic. Operand 48811 states and 68992 transitions. [2023-11-29 04:12:00,347 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:00,347 INFO L218 hiAutomatonCegarLoop]: Abstraction has 48811 states and 68992 transitions. [2023-11-29 04:12:00,372 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 48811 states and 68992 transitions. [2023-11-29 04:12:00,614 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 48811 to 25611. [2023-11-29 04:12:00,629 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.4106438639647028) internal successors, (36128), 25610 states have internal predecessors, (36128), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:00,679 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 36128 transitions. [2023-11-29 04:12:00,679 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 36128 transitions. [2023-11-29 04:12:00,680 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:12:00,680 INFO L428 stractBuchiCegarLoop]: Abstraction has 25611 states and 36128 transitions. [2023-11-29 04:12:00,680 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 04:12:00,681 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 36128 transitions. [2023-11-29 04:12:00,799 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2023-11-29 04:12:00,799 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:00,799 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:00,800 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:00,800 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:00,801 INFO L748 eck$LassoCheckResult]: Stem: 716501#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 716502#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 717366#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 717367#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 717301#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 717302#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 717270#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 717049#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 717050#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 716836#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 716837#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 717396#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 717256#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 716906#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 716656#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 716657#L922 assume !(0 == ~M_E~0); 717459#L922-2 assume !(0 == ~T1_E~0); 717460#L927-1 assume !(0 == ~T2_E~0); 717123#L932-1 assume !(0 == ~T3_E~0); 716982#L937-1 assume !(0 == ~T4_E~0); 716983#L942-1 assume !(0 == ~T5_E~0); 717048#L947-1 assume !(0 == ~T6_E~0); 717127#L952-1 assume !(0 == ~T7_E~0); 717128#L957-1 assume !(0 == ~T8_E~0); 717199#L962-1 assume !(0 == ~T9_E~0); 716958#L967-1 assume !(0 == ~E_1~0); 716959#L972-1 assume !(0 == ~E_2~0); 717282#L977-1 assume !(0 == ~E_3~0); 717283#L982-1 assume !(0 == ~E_4~0); 716435#L987-1 assume !(0 == ~E_5~0); 716436#L992-1 assume !(0 == ~E_6~0); 716442#L997-1 assume !(0 == ~E_7~0); 716882#L1002-1 assume !(0 == ~E_8~0); 716867#L1007-1 assume !(0 == ~E_9~0); 716228#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 716229#L443 assume !(1 == ~m_pc~0); 717146#L443-2 is_master_triggered_~__retres1~0#1 := 0; 717137#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 717138#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 716594#L1140 assume !(0 != activate_threads_~tmp~1#1); 716334#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 716335#L462 assume !(1 == ~t1_pc~0); 716973#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 716974#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 716270#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 716271#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 716813#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 716814#L481 assume !(1 == ~t2_pc~0); 716588#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 716587#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 716716#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 716679#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 716680#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 716781#L500 assume !(1 == ~t3_pc~0); 717356#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 717321#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 716235#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 716236#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 716230#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 716231#L519 assume !(1 == ~t4_pc~0); 717038#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 716780#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 716336#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 716337#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 716629#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 716398#L538 assume !(1 == ~t5_pc~0); 716399#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 716295#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 716296#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 716574#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 716575#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 717183#L557 assume !(1 == ~t6_pc~0); 716609#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 716610#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 716698#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 716630#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 716631#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 717433#L576 assume !(1 == ~t7_pc~0); 716598#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 716599#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 716945#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 717455#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 717247#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 716719#L595 assume !(1 == ~t8_pc~0); 716720#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 717266#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 717188#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 717074#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 717075#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 716525#L614 assume !(1 == ~t9_pc~0); 716526#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 716423#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 716424#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 716756#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 716682#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 716683#L1025 assume !(1 == ~M_E~0); 716967#L1025-2 assume !(1 == ~T1_E~0); 717031#L1030-1 assume !(1 == ~T2_E~0); 717173#L1035-1 assume !(1 == ~T3_E~0); 716673#L1040-1 assume !(1 == ~T4_E~0); 716674#L1045-1 assume !(1 == ~T5_E~0); 716584#L1050-1 assume !(1 == ~T6_E~0); 716585#L1055-1 assume !(1 == ~T7_E~0); 716409#L1060-1 assume !(1 == ~T8_E~0); 716410#L1065-1 assume !(1 == ~T9_E~0); 716474#L1070-1 assume !(1 == ~E_1~0); 717129#L1075-1 assume !(1 == ~E_2~0); 717130#L1080-1 assume !(1 == ~E_3~0); 717118#L1085-1 assume !(1 == ~E_4~0); 717119#L1090-1 assume !(1 == ~E_5~0); 717389#L1095-1 assume !(1 == ~E_6~0); 717157#L1100-1 assume !(1 == ~E_7~0); 717158#L1105-1 assume !(1 == ~E_8~0); 716380#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 716381#L1115-1 assume { :end_inline_reset_delta_events } true; 716728#L1396-2 [2023-11-29 04:12:00,801 INFO L750 eck$LassoCheckResult]: Loop: 716728#L1396-2 assume !false; 727670#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 727615#L897-1 assume !false; 727612#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 727487#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 727477#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 727476#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 727470#L766 assume !(0 != eval_~tmp~0#1); 727471#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 728425#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 728423#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 728421#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 728419#L927-3 assume !(0 == ~T2_E~0); 728417#L932-3 assume !(0 == ~T3_E~0); 728415#L937-3 assume !(0 == ~T4_E~0); 728413#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 728411#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 728409#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 728381#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 728376#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 728371#L967-3 assume !(0 == ~E_1~0); 728362#L972-3 assume !(0 == ~E_2~0); 728359#L977-3 assume !(0 == ~E_3~0); 728357#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 728355#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 728353#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 728351#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 728349#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 728347#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 728345#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 728343#L443-30 assume !(1 == ~m_pc~0); 728341#L443-32 is_master_triggered_~__retres1~0#1 := 0; 728338#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 728336#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 728323#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 728318#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 728312#L462-30 assume !(1 == ~t1_pc~0); 728307#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 728303#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 728299#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 728295#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 728290#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 728282#L481-30 assume !(1 == ~t2_pc~0); 728277#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 728271#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 728267#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 728263#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 728259#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 728253#L500-30 assume !(1 == ~t3_pc~0); 728249#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 728244#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 728239#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 728234#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 728228#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 728222#L519-30 assume !(1 == ~t4_pc~0); 728217#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 728212#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 728207#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 728202#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 728197#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 728191#L538-30 assume !(1 == ~t5_pc~0); 728186#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 728180#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 728174#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 728168#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 728162#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 728156#L557-30 assume !(1 == ~t6_pc~0); 728150#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 728144#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 728138#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 728133#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 728128#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 728121#L576-30 assume !(1 == ~t7_pc~0); 728115#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 728108#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 728102#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 728097#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 728093#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 728087#L595-30 assume !(1 == ~t8_pc~0); 728081#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 728075#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 728069#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 728063#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 728055#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 728052#L614-30 assume !(1 == ~t9_pc~0); 728050#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 728047#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 728045#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 728043#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 728041#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 728031#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 728024#L1025-5 assume !(1 == ~T1_E~0); 728018#L1030-3 assume !(1 == ~T2_E~0); 727795#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 727794#L1040-3 assume !(1 == ~T4_E~0); 727793#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 727792#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 727791#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 727789#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 727787#L1065-3 assume !(1 == ~T9_E~0); 727785#L1070-3 assume !(1 == ~E_1~0); 727782#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 727780#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 727778#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 727776#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 727774#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 727773#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 727772#L1105-3 assume !(1 == ~E_8~0); 727771#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 727770#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 727767#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 727755#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 727753#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 727744#L1415 assume !(0 == start_simulation_~tmp~3#1); 727741#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 727692#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 727683#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 727681#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 727679#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 727677#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 727675#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 727673#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 716728#L1396-2 [2023-11-29 04:12:00,801 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:00,801 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293170, now seen corresponding path program 1 times [2023-11-29 04:12:00,801 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:00,801 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [77427358] [2023-11-29 04:12:00,802 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:00,802 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:00,811 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:00,852 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:00,852 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:00,852 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [77427358] [2023-11-29 04:12:00,852 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [77427358] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:00,853 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:00,853 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:00,853 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [56809305] [2023-11-29 04:12:00,853 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:00,853 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:12:00,853 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:00,854 INFO L85 PathProgramCache]: Analyzing trace with hash -1611985379, now seen corresponding path program 1 times [2023-11-29 04:12:00,854 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:00,854 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1679506356] [2023-11-29 04:12:00,854 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:00,854 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:00,862 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:00,883 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:00,883 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:00,883 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1679506356] [2023-11-29 04:12:00,883 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1679506356] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:00,883 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:00,883 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:00,883 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1540255819] [2023-11-29 04:12:00,883 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:00,884 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:00,884 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:00,884 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:12:00,884 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:12:00,884 INFO L87 Difference]: Start difference. First operand 25611 states and 36128 transitions. cyclomatic complexity: 10549 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:01,111 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:01,111 INFO L93 Difference]: Finished difference Result 53052 states and 74347 transitions. [2023-11-29 04:12:01,111 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 53052 states and 74347 transitions. [2023-11-29 04:12:01,268 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 52512 [2023-11-29 04:12:01,369 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 53052 states to 53052 states and 74347 transitions. [2023-11-29 04:12:01,370 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 53052 [2023-11-29 04:12:01,394 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 53052 [2023-11-29 04:12:01,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 53052 states and 74347 transitions. [2023-11-29 04:12:01,413 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:01,414 INFO L218 hiAutomatonCegarLoop]: Abstraction has 53052 states and 74347 transitions. [2023-11-29 04:12:01,438 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 53052 states and 74347 transitions. [2023-11-29 04:12:01,630 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 53052 to 28595. [2023-11-29 04:12:01,646 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28595 states, 28595 states have (on average 1.4031124322433992) internal successors, (40122), 28594 states have internal predecessors, (40122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:01,689 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28595 states to 28595 states and 40122 transitions. [2023-11-29 04:12:01,689 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28595 states and 40122 transitions. [2023-11-29 04:12:01,689 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:12:01,690 INFO L428 stractBuchiCegarLoop]: Abstraction has 28595 states and 40122 transitions. [2023-11-29 04:12:01,690 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 04:12:01,690 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28595 states and 40122 transitions. [2023-11-29 04:12:01,792 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2023-11-29 04:12:01,792 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:01,792 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:01,793 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:01,793 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:01,793 INFO L748 eck$LassoCheckResult]: Stem: 795173#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 795174#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 796009#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 796010#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 795946#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 795947#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 795919#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 795708#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 795709#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 795504#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 795505#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 796038#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 795907#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 795573#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 795326#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 795327#L922 assume !(0 == ~M_E~0); 796097#L922-2 assume !(0 == ~T1_E~0); 796098#L927-1 assume !(0 == ~T2_E~0); 795779#L932-1 assume !(0 == ~T3_E~0); 795648#L937-1 assume !(0 == ~T4_E~0); 795649#L942-1 assume !(0 == ~T5_E~0); 795707#L947-1 assume !(0 == ~T6_E~0); 795784#L952-1 assume !(0 == ~T7_E~0); 795785#L957-1 assume !(0 == ~T8_E~0); 795854#L962-1 assume !(0 == ~T9_E~0); 795625#L967-1 assume !(0 == ~E_1~0); 795626#L972-1 assume !(0 == ~E_2~0); 795929#L977-1 assume !(0 == ~E_3~0); 795930#L982-1 assume !(0 == ~E_4~0); 795107#L987-1 assume !(0 == ~E_5~0); 795108#L992-1 assume !(0 == ~E_6~0); 795114#L997-1 assume !(0 == ~E_7~0); 795548#L1002-1 assume !(0 == ~E_8~0); 795532#L1007-1 assume 0 == ~E_9~0;~E_9~0 := 1; 794901#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 794902#L443 assume !(1 == ~m_pc~0); 796050#L443-2 is_master_triggered_~__retres1~0#1 := 0; 795791#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 795792#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 796196#L1140 assume !(0 != activate_threads_~tmp~1#1); 796195#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 796060#L462 assume !(1 == ~t1_pc~0); 795639#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 795640#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 794942#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 794943#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 795484#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 795485#L481 assume !(1 == ~t2_pc~0); 795258#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 795257#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 796188#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 796187#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 795450#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 795451#L500 assume !(1 == ~t3_pc~0); 796186#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 796185#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 794908#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 794909#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 794903#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 794904#L519 assume !(1 == ~t4_pc~0); 795699#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 795449#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 795008#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 795009#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 795300#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 795070#L538 assume !(1 == ~t5_pc~0); 795071#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 794967#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 794968#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 795245#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 795246#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 795838#L557 assume !(1 == ~t6_pc~0); 796164#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 796163#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 796162#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 796161#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 796160#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 796107#L576 assume !(1 == ~t7_pc~0); 795268#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 795269#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 795613#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 796093#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 796155#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 796154#L595 assume !(1 == ~t8_pc~0); 796153#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 796152#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 796151#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 796150#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 796149#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 796148#L614 assume !(1 == ~t9_pc~0); 796146#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 796145#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 796144#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 796143#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 796142#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 796141#L1025 assume !(1 == ~M_E~0); 796140#L1025-2 assume !(1 == ~T1_E~0); 796139#L1030-1 assume !(1 == ~T2_E~0); 796138#L1035-1 assume !(1 == ~T3_E~0); 796137#L1040-1 assume !(1 == ~T4_E~0); 796136#L1045-1 assume !(1 == ~T5_E~0); 796135#L1050-1 assume !(1 == ~T6_E~0); 796134#L1055-1 assume !(1 == ~T7_E~0); 796133#L1060-1 assume !(1 == ~T8_E~0); 796132#L1065-1 assume !(1 == ~T9_E~0); 796131#L1070-1 assume !(1 == ~E_1~0); 796130#L1075-1 assume !(1 == ~E_2~0); 796129#L1080-1 assume !(1 == ~E_3~0); 796128#L1085-1 assume !(1 == ~E_4~0); 796127#L1090-1 assume !(1 == ~E_5~0); 796126#L1095-1 assume !(1 == ~E_6~0); 796125#L1100-1 assume !(1 == ~E_7~0); 796124#L1105-1 assume !(1 == ~E_8~0); 796123#L1110-1 assume 1 == ~E_9~0;~E_9~0 := 2; 795053#L1115-1 assume { :end_inline_reset_delta_events } true; 795400#L1396-2 [2023-11-29 04:12:01,794 INFO L750 eck$LassoCheckResult]: Loop: 795400#L1396-2 assume !false; 799202#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 799193#L897-1 assume !false; 799189#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 799102#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 799084#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 799076#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 799068#L766 assume !(0 != eval_~tmp~0#1); 799069#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 799782#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 799776#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 799771#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 799766#L927-3 assume !(0 == ~T2_E~0); 799761#L932-3 assume !(0 == ~T3_E~0); 799755#L937-3 assume !(0 == ~T4_E~0); 799750#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 799744#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 799739#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 799734#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 799729#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 799724#L967-3 assume !(0 == ~E_1~0); 799719#L972-3 assume !(0 == ~E_2~0); 799713#L977-3 assume !(0 == ~E_3~0); 799708#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 799703#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 799698#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 799692#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 799685#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 799677#L1007-3 assume 0 == ~E_9~0;~E_9~0 := 1; 799676#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 799675#L443-30 assume 1 == ~m_pc~0; 799673#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 799672#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 799671#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 799670#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 799669#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 799668#L462-30 assume !(1 == ~t1_pc~0); 799667#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 799666#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 799665#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 799664#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 799663#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 799662#L481-30 assume 1 == ~t2_pc~0; 799660#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 799659#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 799658#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 799657#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 799656#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 799655#L500-30 assume !(1 == ~t3_pc~0); 799654#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 799653#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 799652#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 799651#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 799650#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 799649#L519-30 assume !(1 == ~t4_pc~0); 799648#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 799647#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 799646#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 799645#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 799644#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 799643#L538-30 assume 1 == ~t5_pc~0; 799641#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 799639#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 799637#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 799635#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 799634#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 799633#L557-30 assume !(1 == ~t6_pc~0); 799632#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 799631#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 799630#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 799629#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 799628#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 799627#L576-30 assume 1 == ~t7_pc~0; 799625#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 799624#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 799623#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 799622#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 799621#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 799620#L595-30 assume !(1 == ~t8_pc~0); 799619#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 799618#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 799617#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 799616#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 799615#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 799614#L614-30 assume !(1 == ~t9_pc~0); 799613#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 799610#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 799609#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 799608#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 799607#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 799606#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 799605#L1025-5 assume !(1 == ~T1_E~0); 799604#L1030-3 assume !(1 == ~T2_E~0); 799603#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 799602#L1040-3 assume !(1 == ~T4_E~0); 799601#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 799600#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 799599#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 799598#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 799597#L1065-3 assume !(1 == ~T9_E~0); 799596#L1070-3 assume !(1 == ~E_1~0); 799595#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 799594#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 799593#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 799592#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 799591#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 799590#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 799589#L1105-3 assume !(1 == ~E_8~0); 799587#L1110-3 assume 1 == ~E_9~0;~E_9~0 := 2; 799581#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 799504#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 799489#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 799483#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 799476#L1415 assume !(0 == start_simulation_~tmp~3#1); 799471#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 799461#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 799241#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 799237#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 799235#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 799233#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 799232#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 799229#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 795400#L1396-2 [2023-11-29 04:12:01,794 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:01,794 INFO L85 PathProgramCache]: Analyzing trace with hash -178464780, now seen corresponding path program 1 times [2023-11-29 04:12:01,794 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:01,794 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1085908987] [2023-11-29 04:12:01,795 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:01,795 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:01,803 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:01,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:01,836 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:01,836 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1085908987] [2023-11-29 04:12:01,836 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1085908987] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:01,836 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:01,836 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:01,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [98043654] [2023-11-29 04:12:01,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:01,837 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:12:01,837 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:01,837 INFO L85 PathProgramCache]: Analyzing trace with hash -1525501469, now seen corresponding path program 1 times [2023-11-29 04:12:01,838 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:01,838 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1958544358] [2023-11-29 04:12:01,838 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:01,838 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:01,848 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:01,867 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:01,867 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:01,867 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1958544358] [2023-11-29 04:12:01,868 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1958544358] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:01,868 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:01,868 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:01,868 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1317199150] [2023-11-29 04:12:01,868 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:01,868 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:01,869 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:01,869 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:12:01,869 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:12:01,869 INFO L87 Difference]: Start difference. First operand 28595 states and 40122 transitions. cyclomatic complexity: 11559 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:02,032 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:02,033 INFO L93 Difference]: Finished difference Result 37875 states and 53025 transitions. [2023-11-29 04:12:02,033 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37875 states and 53025 transitions. [2023-11-29 04:12:02,143 INFO L131 ngComponentsAnalysis]: Automaton has 48 accepting balls. 37536 [2023-11-29 04:12:02,211 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37875 states to 37875 states and 53025 transitions. [2023-11-29 04:12:02,211 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37875 [2023-11-29 04:12:02,228 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37875 [2023-11-29 04:12:02,228 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37875 states and 53025 transitions. [2023-11-29 04:12:02,242 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:02,243 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37875 states and 53025 transitions. [2023-11-29 04:12:02,261 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37875 states and 53025 transitions. [2023-11-29 04:12:02,412 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37875 to 25611. [2023-11-29 04:12:02,427 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.3967826324626138) internal successors, (35773), 25610 states have internal predecessors, (35773), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:02,465 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 35773 transitions. [2023-11-29 04:12:02,465 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 35773 transitions. [2023-11-29 04:12:02,466 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:12:02,466 INFO L428 stractBuchiCegarLoop]: Abstraction has 25611 states and 35773 transitions. [2023-11-29 04:12:02,466 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 04:12:02,466 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 35773 transitions. [2023-11-29 04:12:02,519 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2023-11-29 04:12:02,519 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:02,519 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:02,521 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:02,521 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:02,521 INFO L748 eck$LassoCheckResult]: Stem: 861656#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 861657#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 862489#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 862490#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 862433#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 862434#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 862408#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 862209#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 862210#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 861992#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 861993#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 862521#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 862399#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 862064#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 861812#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 861813#L922 assume !(0 == ~M_E~0); 862581#L922-2 assume !(0 == ~T1_E~0); 862582#L927-1 assume !(0 == ~T2_E~0); 862275#L932-1 assume !(0 == ~T3_E~0); 862142#L937-1 assume !(0 == ~T4_E~0); 862143#L942-1 assume !(0 == ~T5_E~0); 862208#L947-1 assume !(0 == ~T6_E~0); 862279#L952-1 assume !(0 == ~T7_E~0); 862280#L957-1 assume !(0 == ~T8_E~0); 862349#L962-1 assume !(0 == ~T9_E~0); 862115#L967-1 assume !(0 == ~E_1~0); 862116#L972-1 assume !(0 == ~E_2~0); 862415#L977-1 assume !(0 == ~E_3~0); 862416#L982-1 assume !(0 == ~E_4~0); 861586#L987-1 assume !(0 == ~E_5~0); 861587#L992-1 assume !(0 == ~E_6~0); 861593#L997-1 assume !(0 == ~E_7~0); 862035#L1002-1 assume !(0 == ~E_8~0); 862024#L1007-1 assume !(0 == ~E_9~0); 861381#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 861382#L443 assume !(1 == ~m_pc~0); 862296#L443-2 is_master_triggered_~__retres1~0#1 := 0; 862286#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 862287#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 861749#L1140 assume !(0 != activate_threads_~tmp~1#1); 861486#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 861487#L462 assume !(1 == ~t1_pc~0); 862136#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 862137#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 861424#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 861425#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 861971#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 861972#L481 assume !(1 == ~t2_pc~0); 861743#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 861742#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 861874#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 861834#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 861835#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 861937#L500 assume !(1 == ~t3_pc~0); 862478#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 862451#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 861388#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 861389#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 861386#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 861387#L519 assume !(1 == ~t4_pc~0); 862198#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 861936#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 861488#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 861489#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 861787#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 861550#L538 assume !(1 == ~t5_pc~0); 861551#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 861447#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 861448#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 861729#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 861730#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 862331#L557 assume !(1 == ~t6_pc~0); 861763#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 861764#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 861853#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 861788#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 861789#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 862560#L576 assume !(1 == ~t7_pc~0); 861753#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 861754#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 862102#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 862578#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 862391#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 861877#L595 assume !(1 == ~t8_pc~0); 861878#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 862405#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 862334#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 862232#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 862233#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 861681#L614 assume !(1 == ~t9_pc~0); 861682#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 861576#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 861577#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 861912#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 861837#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 861838#L1025 assume !(1 == ~M_E~0); 862124#L1025-2 assume !(1 == ~T1_E~0); 862190#L1030-1 assume !(1 == ~T2_E~0); 862321#L1035-1 assume !(1 == ~T3_E~0); 861830#L1040-1 assume !(1 == ~T4_E~0); 861831#L1045-1 assume !(1 == ~T5_E~0); 861739#L1050-1 assume !(1 == ~T6_E~0); 861740#L1055-1 assume !(1 == ~T7_E~0); 861561#L1060-1 assume !(1 == ~T8_E~0); 861562#L1065-1 assume !(1 == ~T9_E~0); 861625#L1070-1 assume !(1 == ~E_1~0); 862282#L1075-1 assume !(1 == ~E_2~0); 862283#L1080-1 assume !(1 == ~E_3~0); 862270#L1085-1 assume !(1 == ~E_4~0); 862271#L1090-1 assume !(1 == ~E_5~0); 862510#L1095-1 assume !(1 == ~E_6~0); 862306#L1100-1 assume !(1 == ~E_7~0); 862307#L1105-1 assume !(1 == ~E_8~0); 861532#L1110-1 assume !(1 == ~E_9~0); 861533#L1115-1 assume { :end_inline_reset_delta_events } true; 861884#L1396-2 [2023-11-29 04:12:02,521 INFO L750 eck$LassoCheckResult]: Loop: 861884#L1396-2 assume !false; 864080#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 864072#L897-1 assume !false; 864068#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 864042#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 864024#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 864018#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 864009#L766 assume !(0 != eval_~tmp~0#1); 864010#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 864583#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 864582#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 864581#L922-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 864580#L927-3 assume !(0 == ~T2_E~0); 864579#L932-3 assume !(0 == ~T3_E~0); 864578#L937-3 assume !(0 == ~T4_E~0); 864577#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 864576#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 864575#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 864574#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 864573#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 864572#L967-3 assume !(0 == ~E_1~0); 864571#L972-3 assume !(0 == ~E_2~0); 864570#L977-3 assume !(0 == ~E_3~0); 864569#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 864568#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 864567#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 864566#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 864565#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 864564#L1007-3 assume !(0 == ~E_9~0); 864563#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 864562#L443-30 assume !(1 == ~m_pc~0); 864561#L443-32 is_master_triggered_~__retres1~0#1 := 0; 864559#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 864558#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 864557#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 864556#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 864555#L462-30 assume !(1 == ~t1_pc~0); 864554#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 864553#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 864552#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 864550#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 864547#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 864545#L481-30 assume !(1 == ~t2_pc~0); 864543#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 864540#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 864538#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 864536#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 864534#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 864532#L500-30 assume !(1 == ~t3_pc~0); 864530#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 864528#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 864526#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 864524#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 864521#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 864519#L519-30 assume !(1 == ~t4_pc~0); 864517#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 864515#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 864513#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 864511#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 864509#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 864507#L538-30 assume !(1 == ~t5_pc~0); 864505#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 864502#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 864499#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 864496#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 864493#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 864491#L557-30 assume !(1 == ~t6_pc~0); 864489#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 864487#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 864485#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 864482#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 864477#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 864473#L576-30 assume !(1 == ~t7_pc~0); 864468#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 864461#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 864457#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 864453#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 864449#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 864445#L595-30 assume !(1 == ~t8_pc~0); 864441#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 864437#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 864433#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 864429#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 864423#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 864419#L614-30 assume !(1 == ~t9_pc~0); 864414#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 864409#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 864405#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 864401#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 864397#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 864393#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 864389#L1025-5 assume !(1 == ~T1_E~0); 864385#L1030-3 assume !(1 == ~T2_E~0); 864380#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 864374#L1040-3 assume !(1 == ~T4_E~0); 864368#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 864363#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 864358#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 864353#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 864349#L1065-3 assume !(1 == ~T9_E~0); 864345#L1070-3 assume !(1 == ~E_1~0); 864339#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 864334#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 864330#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 864324#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 864319#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 864314#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 864307#L1105-3 assume !(1 == ~E_8~0); 864302#L1110-3 assume !(1 == ~E_9~0); 864298#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 864171#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 864157#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 864150#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 864144#L1415 assume !(0 == start_simulation_~tmp~3#1); 864141#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 864131#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 864119#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 864114#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 864109#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 864104#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 864098#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 864092#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 861884#L1396-2 [2023-11-29 04:12:02,522 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:02,522 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 1 times [2023-11-29 04:12:02,522 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:02,522 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [443123954] [2023-11-29 04:12:02,522 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:02,522 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:02,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:02,537 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:02,545 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:02,611 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:02,612 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:02,612 INFO L85 PathProgramCache]: Analyzing trace with hash 52889753, now seen corresponding path program 1 times [2023-11-29 04:12:02,612 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:02,612 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2040261653] [2023-11-29 04:12:02,612 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:02,613 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:02,625 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:02,653 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:02,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:02,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2040261653] [2023-11-29 04:12:02,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2040261653] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:02,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:02,653 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:02,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071170967] [2023-11-29 04:12:02,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:02,654 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:02,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:02,654 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:12:02,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:12:02,655 INFO L87 Difference]: Start difference. First operand 25611 states and 35773 transitions. cyclomatic complexity: 10194 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:02,760 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:02,760 INFO L93 Difference]: Finished difference Result 28595 states and 39957 transitions. [2023-11-29 04:12:02,760 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28595 states and 39957 transitions. [2023-11-29 04:12:02,871 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2023-11-29 04:12:02,930 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28595 states to 28595 states and 39957 transitions. [2023-11-29 04:12:02,931 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28595 [2023-11-29 04:12:02,945 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28595 [2023-11-29 04:12:02,945 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28595 states and 39957 transitions. [2023-11-29 04:12:02,959 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:02,959 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28595 states and 39957 transitions. [2023-11-29 04:12:02,973 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28595 states and 39957 transitions. [2023-11-29 04:12:03,169 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28595 to 28595. [2023-11-29 04:12:03,186 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28595 states, 28595 states have (on average 1.3973421926910299) internal successors, (39957), 28594 states have internal predecessors, (39957), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:03,240 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28595 states to 28595 states and 39957 transitions. [2023-11-29 04:12:03,240 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28595 states and 39957 transitions. [2023-11-29 04:12:03,240 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:12:03,241 INFO L428 stractBuchiCegarLoop]: Abstraction has 28595 states and 39957 transitions. [2023-11-29 04:12:03,241 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 04:12:03,241 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28595 states and 39957 transitions. [2023-11-29 04:12:03,314 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2023-11-29 04:12:03,314 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:03,314 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:03,315 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:03,315 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:03,316 INFO L748 eck$LassoCheckResult]: Stem: 915866#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 915867#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 916732#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 916733#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 916665#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 916666#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 916635#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 916414#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 916415#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 916204#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 916205#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 916764#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 916620#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 916275#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 916027#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 916028#L922 assume !(0 == ~M_E~0); 916844#L922-2 assume 0 == ~T1_E~0;~T1_E~0 := 1; 916845#L927-1 assume !(0 == ~T2_E~0); 916486#L932-1 assume !(0 == ~T3_E~0); 916487#L937-1 assume !(0 == ~T4_E~0); 916412#L942-1 assume !(0 == ~T5_E~0); 916413#L947-1 assume !(0 == ~T6_E~0); 916491#L952-1 assume !(0 == ~T7_E~0); 916492#L957-1 assume !(0 == ~T8_E~0); 916822#L962-1 assume !(0 == ~T9_E~0); 916823#L967-1 assume !(0 == ~E_1~0); 916815#L972-1 assume !(0 == ~E_2~0); 916816#L977-1 assume !(0 == ~E_3~0); 916851#L982-1 assume !(0 == ~E_4~0); 916852#L987-1 assume !(0 == ~E_5~0); 915806#L992-1 assume !(0 == ~E_6~0); 915807#L997-1 assume !(0 == ~E_7~0); 916786#L1002-1 assume !(0 == ~E_8~0); 916787#L1007-1 assume !(0 == ~E_9~0); 915593#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 915594#L443 assume !(1 == ~m_pc~0); 916510#L443-2 is_master_triggered_~__retres1~0#1 := 0; 916511#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 916625#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 916626#L1140 assume !(0 != activate_threads_~tmp~1#1); 915698#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 915699#L462 assume !(1 == ~t1_pc~0); 916924#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 916923#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 915634#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 915635#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 916183#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 916184#L481 assume !(1 == ~t2_pc~0); 915954#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 915953#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 916919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 916918#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 916152#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 916153#L500 assume !(1 == ~t3_pc~0); 916917#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 916916#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 915600#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 915601#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 915595#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 915596#L519 assume !(1 == ~t4_pc~0); 916402#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 916403#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 916911#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 916910#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 916909#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 916907#L538 assume !(1 == ~t5_pc~0); 916904#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 916902#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 916900#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 916898#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 916897#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 916871#L557 assume !(1 == ~t6_pc~0); 915976#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 915977#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 916068#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 915999#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 916000#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 916814#L576 assume !(1 == ~t7_pc~0); 916890#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 916889#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 916888#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 916857#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 916613#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 916090#L595 assume !(1 == ~t8_pc~0); 916091#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 916630#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 916554#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 916439#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 916440#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 915891#L614 assume !(1 == ~t9_pc~0); 915892#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 915787#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 915788#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 916127#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 916052#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 916053#L1025 assume !(1 == ~M_E~0); 916334#L1025-2 assume 1 == ~T1_E~0;~T1_E~0 := 2; 916395#L1030-1 assume !(1 == ~T2_E~0); 916539#L1035-1 assume !(1 == ~T3_E~0); 916044#L1040-1 assume !(1 == ~T4_E~0); 916045#L1045-1 assume !(1 == ~T5_E~0); 915950#L1050-1 assume !(1 == ~T6_E~0); 915951#L1055-1 assume !(1 == ~T7_E~0); 915773#L1060-1 assume !(1 == ~T8_E~0); 915774#L1065-1 assume !(1 == ~T9_E~0); 915839#L1070-1 assume !(1 == ~E_1~0); 916493#L1075-1 assume !(1 == ~E_2~0); 916494#L1080-1 assume !(1 == ~E_3~0); 916481#L1085-1 assume !(1 == ~E_4~0); 916482#L1090-1 assume !(1 == ~E_5~0); 916757#L1095-1 assume !(1 == ~E_6~0); 916523#L1100-1 assume !(1 == ~E_7~0); 916524#L1105-1 assume !(1 == ~E_8~0); 915744#L1110-1 assume !(1 == ~E_9~0); 915745#L1115-1 assume { :end_inline_reset_delta_events } true; 916098#L1396-2 [2023-11-29 04:12:03,316 INFO L750 eck$LassoCheckResult]: Loop: 916098#L1396-2 assume !false; 920305#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 919705#L897-1 assume !false; 919704#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 919363#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 919346#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 919340#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 919330#L766 assume !(0 != eval_~tmp~0#1); 919331#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 922610#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 922608#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 922605#L922-5 assume !(0 == ~T1_E~0); 922606#L927-3 assume !(0 == ~T2_E~0); 922761#L932-3 assume !(0 == ~T3_E~0); 922760#L937-3 assume !(0 == ~T4_E~0); 922759#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 922758#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 922757#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 922756#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 922755#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 922753#L967-3 assume !(0 == ~E_1~0); 922751#L972-3 assume !(0 == ~E_2~0); 922749#L977-3 assume !(0 == ~E_3~0); 922746#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 922744#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 922742#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 922740#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 922738#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 922736#L1007-3 assume !(0 == ~E_9~0); 922734#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 922732#L443-30 assume !(1 == ~m_pc~0); 922730#L443-32 is_master_triggered_~__retres1~0#1 := 0; 922727#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 922725#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 922723#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 922720#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 922718#L462-30 assume !(1 == ~t1_pc~0); 922716#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 922714#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 922712#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 922710#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 922708#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 922706#L481-30 assume 1 == ~t2_pc~0; 922703#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 922701#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 922699#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 922697#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 922695#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 922693#L500-30 assume !(1 == ~t3_pc~0); 922691#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 922689#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 922687#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 922683#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 922681#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 922679#L519-30 assume !(1 == ~t4_pc~0); 922677#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 922674#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 922672#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 922670#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 922667#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 922665#L538-30 assume 1 == ~t5_pc~0; 922663#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 922664#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 922763#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 922654#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 922651#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 922649#L557-30 assume !(1 == ~t6_pc~0); 922647#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 922645#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 922643#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 922641#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 922639#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 922637#L576-30 assume 1 == ~t7_pc~0; 922634#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 922632#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 922630#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 922627#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 922625#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 922623#L595-30 assume !(1 == ~t8_pc~0); 922621#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 922619#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 922617#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 922616#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 922615#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 922614#L614-30 assume !(1 == ~t9_pc~0); 922612#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 922611#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 922609#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 922607#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 922604#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 922602#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 922446#L1025-5 assume !(1 == ~T1_E~0); 922443#L1030-3 assume !(1 == ~T2_E~0); 922441#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 922439#L1040-3 assume !(1 == ~T4_E~0); 922437#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 922435#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 922433#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 922431#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 922429#L1065-3 assume !(1 == ~T9_E~0); 922427#L1070-3 assume !(1 == ~E_1~0); 922425#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 922423#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 922420#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 922418#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 922416#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 922414#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 922413#L1105-3 assume !(1 == ~E_8~0); 922410#L1110-3 assume !(1 == ~E_9~0); 922408#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 922404#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 922387#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 922380#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 920861#L1415 assume !(0 == start_simulation_~tmp~3#1); 920858#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 920326#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 920318#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 920316#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 920314#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 920312#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 920310#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 920308#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 916098#L1396-2 [2023-11-29 04:12:03,317 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:03,317 INFO L85 PathProgramCache]: Analyzing trace with hash 2046196076, now seen corresponding path program 1 times [2023-11-29 04:12:03,317 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:03,317 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1362102349] [2023-11-29 04:12:03,317 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:03,317 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:03,328 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:03,356 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:03,356 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:03,356 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1362102349] [2023-11-29 04:12:03,356 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1362102349] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:03,356 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:03,356 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:12:03,356 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [19309112] [2023-11-29 04:12:03,357 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:03,357 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:12:03,357 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:03,357 INFO L85 PathProgramCache]: Analyzing trace with hash 1160448256, now seen corresponding path program 1 times [2023-11-29 04:12:03,358 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:03,358 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1964591190] [2023-11-29 04:12:03,358 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:03,358 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:03,369 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:03,396 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:03,397 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:03,397 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1964591190] [2023-11-29 04:12:03,397 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1964591190] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:03,397 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:03,397 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:03,397 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2115484584] [2023-11-29 04:12:03,397 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:03,398 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:03,398 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:03,398 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:12:03,398 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:12:03,399 INFO L87 Difference]: Start difference. First operand 28595 states and 39957 transitions. cyclomatic complexity: 11394 Second operand has 3 states, 3 states have (on average 38.333333333333336) internal successors, (115), 2 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:03,493 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:03,494 INFO L93 Difference]: Finished difference Result 25611 states and 35675 transitions. [2023-11-29 04:12:03,494 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 25611 states and 35675 transitions. [2023-11-29 04:12:03,593 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2023-11-29 04:12:03,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 25611 states to 25611 states and 35675 transitions. [2023-11-29 04:12:03,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 25611 [2023-11-29 04:12:03,666 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 25611 [2023-11-29 04:12:03,666 INFO L73 IsDeterministic]: Start isDeterministic. Operand 25611 states and 35675 transitions. [2023-11-29 04:12:03,678 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:03,678 INFO L218 hiAutomatonCegarLoop]: Abstraction has 25611 states and 35675 transitions. [2023-11-29 04:12:03,691 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 25611 states and 35675 transitions. [2023-11-29 04:12:03,866 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 25611 to 25611. [2023-11-29 04:12:03,880 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.3929561516535864) internal successors, (35675), 25610 states have internal predecessors, (35675), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:03,930 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 35675 transitions. [2023-11-29 04:12:03,931 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 35675 transitions. [2023-11-29 04:12:03,931 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:12:03,931 INFO L428 stractBuchiCegarLoop]: Abstraction has 25611 states and 35675 transitions. [2023-11-29 04:12:03,931 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 04:12:03,932 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 35675 transitions. [2023-11-29 04:12:03,998 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2023-11-29 04:12:03,998 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:03,998 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:04,000 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:04,000 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:04,000 INFO L748 eck$LassoCheckResult]: Stem: 970078#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 970079#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 970908#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 970909#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 970849#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 970850#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 970830#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 970629#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 970630#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 970412#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 970413#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 970942#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 970816#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 970485#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 970238#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 970239#L922 assume !(0 == ~M_E~0); 970999#L922-2 assume !(0 == ~T1_E~0); 971000#L927-1 assume !(0 == ~T2_E~0); 970696#L932-1 assume !(0 == ~T3_E~0); 970563#L937-1 assume !(0 == ~T4_E~0); 970564#L942-1 assume !(0 == ~T5_E~0); 970628#L947-1 assume !(0 == ~T6_E~0); 970700#L952-1 assume !(0 == ~T7_E~0); 970701#L957-1 assume !(0 == ~T8_E~0); 970764#L962-1 assume !(0 == ~T9_E~0); 970535#L967-1 assume !(0 == ~E_1~0); 970536#L972-1 assume !(0 == ~E_2~0); 970835#L977-1 assume !(0 == ~E_3~0); 970836#L982-1 assume !(0 == ~E_4~0); 970011#L987-1 assume !(0 == ~E_5~0); 970012#L992-1 assume !(0 == ~E_6~0); 970018#L997-1 assume !(0 == ~E_7~0); 970457#L1002-1 assume !(0 == ~E_8~0); 970443#L1007-1 assume !(0 == ~E_9~0); 969806#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 969807#L443 assume !(1 == ~m_pc~0); 970715#L443-2 is_master_triggered_~__retres1~0#1 := 0; 970707#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 970708#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 970172#L1140 assume !(0 != activate_threads_~tmp~1#1); 969911#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 969912#L462 assume !(1 == ~t1_pc~0); 970552#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 970553#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 969847#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 969848#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 970391#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 970392#L481 assume !(1 == ~t2_pc~0); 970166#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 970165#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 970298#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 970260#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 970261#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 970360#L500 assume !(1 == ~t3_pc~0); 970897#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 970866#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 969813#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 969814#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 969808#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 969809#L519 assume !(1 == ~t4_pc~0); 970615#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 970359#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 969913#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 969914#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 970209#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 969975#L538 assume !(1 == ~t5_pc~0); 969976#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 969872#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 969873#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 970152#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 970153#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 970748#L557 assume !(1 == ~t6_pc~0); 970187#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 970188#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 970279#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 970210#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 970211#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 970975#L576 assume !(1 == ~t7_pc~0); 970176#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 970177#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 970523#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 970995#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 970809#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 970299#L595 assume !(1 == ~t8_pc~0); 970300#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 970824#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 970753#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 970654#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 970655#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 970103#L614 assume !(1 == ~t9_pc~0); 970104#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 970000#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 970001#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 970334#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 970263#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 970264#L1025 assume !(1 == ~M_E~0); 970545#L1025-2 assume !(1 == ~T1_E~0); 970608#L1030-1 assume !(1 == ~T2_E~0); 970741#L1035-1 assume !(1 == ~T3_E~0); 970255#L1040-1 assume !(1 == ~T4_E~0); 970256#L1045-1 assume !(1 == ~T5_E~0); 970162#L1050-1 assume !(1 == ~T6_E~0); 970163#L1055-1 assume !(1 == ~T7_E~0); 969986#L1060-1 assume !(1 == ~T8_E~0); 969987#L1065-1 assume !(1 == ~T9_E~0); 970050#L1070-1 assume !(1 == ~E_1~0); 970702#L1075-1 assume !(1 == ~E_2~0); 970703#L1080-1 assume !(1 == ~E_3~0); 970691#L1085-1 assume !(1 == ~E_4~0); 970692#L1090-1 assume !(1 == ~E_5~0); 970935#L1095-1 assume !(1 == ~E_6~0); 970725#L1100-1 assume !(1 == ~E_7~0); 970726#L1105-1 assume !(1 == ~E_8~0); 969957#L1110-1 assume !(1 == ~E_9~0); 969958#L1115-1 assume { :end_inline_reset_delta_events } true; 970307#L1396-2 [2023-11-29 04:12:04,001 INFO L750 eck$LassoCheckResult]: Loop: 970307#L1396-2 assume !false; 974751#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 974745#L897-1 assume !false; 974743#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 974740#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 974729#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 974727#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 974724#L766 assume !(0 != eval_~tmp~0#1); 974725#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 975058#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 975056#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 975054#L922-5 assume !(0 == ~T1_E~0); 975052#L927-3 assume !(0 == ~T2_E~0); 975050#L932-3 assume !(0 == ~T3_E~0); 975048#L937-3 assume !(0 == ~T4_E~0); 975046#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 975044#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 975042#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 975040#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 975038#L962-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 975035#L967-3 assume !(0 == ~E_1~0); 975033#L972-3 assume !(0 == ~E_2~0); 975031#L977-3 assume !(0 == ~E_3~0); 975029#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 975027#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 975025#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 975024#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 975020#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 975018#L1007-3 assume !(0 == ~E_9~0); 975016#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 975015#L443-30 assume !(1 == ~m_pc~0); 975014#L443-32 is_master_triggered_~__retres1~0#1 := 0; 975010#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 975007#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 975003#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 975002#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 975001#L462-30 assume !(1 == ~t1_pc~0); 975000#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 974999#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 974998#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 974997#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 974996#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 974995#L481-30 assume !(1 == ~t2_pc~0); 974994#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 974992#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 974991#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 974990#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 974989#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 974988#L500-30 assume !(1 == ~t3_pc~0); 974987#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 974986#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 974985#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 974983#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 974982#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 974981#L519-30 assume !(1 == ~t4_pc~0); 974980#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 974979#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 974978#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 974976#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 974975#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 974974#L538-30 assume 1 == ~t5_pc~0; 974972#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 974973#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 974977#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 974964#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 974962#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 974960#L557-30 assume !(1 == ~t6_pc~0); 974958#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 974956#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 974954#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 974952#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 974950#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 974948#L576-30 assume !(1 == ~t7_pc~0); 974946#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 974943#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 974941#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 974938#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 974936#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 974934#L595-30 assume !(1 == ~t8_pc~0); 974932#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 974930#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 974928#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 974926#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 974924#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 974922#L614-30 assume !(1 == ~t9_pc~0); 974919#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 974917#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 974915#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 974913#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 974911#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 974909#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 974907#L1025-5 assume !(1 == ~T1_E~0); 974905#L1030-3 assume !(1 == ~T2_E~0); 974904#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 974900#L1040-3 assume !(1 == ~T4_E~0); 974898#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 974896#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 974894#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 974891#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 974889#L1065-3 assume !(1 == ~T9_E~0); 974887#L1070-3 assume !(1 == ~E_1~0); 974885#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 974883#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 974881#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 974879#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 974877#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 974875#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 974872#L1105-3 assume !(1 == ~E_8~0); 974870#L1110-3 assume !(1 == ~E_9~0); 974868#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 974865#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 974854#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 974852#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 974793#L1415 assume !(0 == start_simulation_~tmp~3#1); 974791#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 974773#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 974765#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 974763#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 974760#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 974758#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 974756#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 974754#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 970307#L1396-2 [2023-11-29 04:12:04,001 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:04,001 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 2 times [2023-11-29 04:12:04,001 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:04,001 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1584851764] [2023-11-29 04:12:04,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:04,002 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:04,017 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:04,017 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:04,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:04,074 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:04,075 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:04,075 INFO L85 PathProgramCache]: Analyzing trace with hash 447039102, now seen corresponding path program 1 times [2023-11-29 04:12:04,075 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:04,075 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [371288297] [2023-11-29 04:12:04,075 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:04,076 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:04,090 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:04,126 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:04,126 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:04,126 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [371288297] [2023-11-29 04:12:04,127 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [371288297] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:04,127 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:04,127 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:04,127 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [302424837] [2023-11-29 04:12:04,127 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:04,128 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:04,128 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:04,128 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:12:04,128 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:12:04,128 INFO L87 Difference]: Start difference. First operand 25611 states and 35675 transitions. cyclomatic complexity: 10096 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:04,264 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:04,264 INFO L93 Difference]: Finished difference Result 28595 states and 39826 transitions. [2023-11-29 04:12:04,264 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 28595 states and 39826 transitions. [2023-11-29 04:12:04,401 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2023-11-29 04:12:04,465 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 28595 states to 28595 states and 39826 transitions. [2023-11-29 04:12:04,465 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 28595 [2023-11-29 04:12:04,479 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 28595 [2023-11-29 04:12:04,479 INFO L73 IsDeterministic]: Start isDeterministic. Operand 28595 states and 39826 transitions. [2023-11-29 04:12:04,492 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:04,492 INFO L218 hiAutomatonCegarLoop]: Abstraction has 28595 states and 39826 transitions. [2023-11-29 04:12:04,506 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 28595 states and 39826 transitions. [2023-11-29 04:12:04,701 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 28595 to 28595. [2023-11-29 04:12:04,717 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 28595 states, 28595 states have (on average 1.3927609721979366) internal successors, (39826), 28594 states have internal predecessors, (39826), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:04,771 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 28595 states to 28595 states and 39826 transitions. [2023-11-29 04:12:04,771 INFO L240 hiAutomatonCegarLoop]: Abstraction has 28595 states and 39826 transitions. [2023-11-29 04:12:04,772 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:12:04,772 INFO L428 stractBuchiCegarLoop]: Abstraction has 28595 states and 39826 transitions. [2023-11-29 04:12:04,772 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-29 04:12:04,772 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 28595 states and 39826 transitions. [2023-11-29 04:12:04,846 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 28240 [2023-11-29 04:12:04,846 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:04,846 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:04,847 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:04,847 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:04,848 INFO L748 eck$LassoCheckResult]: Stem: 1024293#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1024294#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1025121#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1025122#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1025055#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1025056#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1025032#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1024833#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1024834#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1024629#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1024630#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1025154#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1025021#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1024695#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1024448#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1024449#L922 assume !(0 == ~M_E~0); 1025208#L922-2 assume !(0 == ~T1_E~0); 1025209#L927-1 assume !(0 == ~T2_E~0); 1024899#L932-1 assume !(0 == ~T3_E~0); 1024772#L937-1 assume !(0 == ~T4_E~0); 1024773#L942-1 assume !(0 == ~T5_E~0); 1024832#L947-1 assume !(0 == ~T6_E~0); 1024904#L952-1 assume !(0 == ~T7_E~0); 1024905#L957-1 assume !(0 == ~T8_E~0); 1024971#L962-1 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1024746#L967-1 assume !(0 == ~E_1~0); 1024747#L972-1 assume !(0 == ~E_2~0); 1025040#L977-1 assume !(0 == ~E_3~0); 1025041#L982-1 assume !(0 == ~E_4~0); 1024224#L987-1 assume !(0 == ~E_5~0); 1024225#L992-1 assume !(0 == ~E_6~0); 1024231#L997-1 assume !(0 == ~E_7~0); 1024669#L1002-1 assume !(0 == ~E_8~0); 1024658#L1007-1 assume !(0 == ~E_9~0); 1024018#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1024019#L443 assume !(1 == ~m_pc~0); 1024921#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1024912#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1024913#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1025290#L1140 assume !(0 != activate_threads_~tmp~1#1); 1025289#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1025288#L462 assume !(1 == ~t1_pc~0); 1025287#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1025286#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1025285#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1024929#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1024930#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1025284#L481 assume !(1 == ~t2_pc~0); 1025282#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1024889#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1024508#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1024470#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1024471#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1025221#L500 assume !(1 == ~t3_pc~0); 1025112#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1025075#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1025076#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1025277#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1025276#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1025275#L519 assume !(1 == ~t4_pc~0); 1025274#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1024573#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1024125#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1024126#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1024421#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1024187#L538 assume !(1 == ~t5_pc~0); 1024188#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1024084#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1024085#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1024367#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1024368#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1024955#L557 assume !(1 == ~t6_pc~0); 1025258#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1025257#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1025256#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1025255#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1025254#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1025216#L576 assume !(1 == ~t7_pc~0); 1024391#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1024392#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1024734#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1025204#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1025249#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1025248#L595 assume !(1 == ~t8_pc~0); 1025247#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1025246#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1025245#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1025244#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1025243#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1025241#L614 assume !(1 == ~t9_pc~0); 1025240#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1024212#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1024213#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1024549#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1024473#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1024474#L1025 assume !(1 == ~M_E~0); 1024754#L1025-2 assume !(1 == ~T1_E~0); 1024816#L1030-1 assume !(1 == ~T2_E~0); 1024947#L1035-1 assume !(1 == ~T3_E~0); 1024465#L1040-1 assume !(1 == ~T4_E~0); 1024466#L1045-1 assume !(1 == ~T5_E~0); 1024377#L1050-1 assume !(1 == ~T6_E~0); 1024378#L1055-1 assume !(1 == ~T7_E~0); 1024198#L1060-1 assume !(1 == ~T8_E~0); 1024199#L1065-1 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1024264#L1070-1 assume !(1 == ~E_1~0); 1024906#L1075-1 assume !(1 == ~E_2~0); 1024907#L1080-1 assume !(1 == ~E_3~0); 1024894#L1085-1 assume !(1 == ~E_4~0); 1024895#L1090-1 assume !(1 == ~E_5~0); 1025145#L1095-1 assume !(1 == ~E_6~0); 1024933#L1100-1 assume !(1 == ~E_7~0); 1024934#L1105-1 assume !(1 == ~E_8~0); 1024169#L1110-1 assume !(1 == ~E_9~0); 1024170#L1115-1 assume { :end_inline_reset_delta_events } true; 1024522#L1396-2 [2023-11-29 04:12:04,848 INFO L750 eck$LassoCheckResult]: Loop: 1024522#L1396-2 assume !false; 1030237#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1030226#L897-1 assume !false; 1030222#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1027788#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1027778#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1027775#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1027773#L766 assume !(0 != eval_~tmp~0#1); 1027774#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1031788#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1031782#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1031777#L922-5 assume !(0 == ~T1_E~0); 1031771#L927-3 assume !(0 == ~T2_E~0); 1031770#L932-3 assume !(0 == ~T3_E~0); 1031769#L937-3 assume !(0 == ~T4_E~0); 1031768#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1031767#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1031765#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1031762#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1031759#L962-3 assume !(0 == ~T9_E~0); 1031757#L967-3 assume !(0 == ~E_1~0); 1031755#L972-3 assume !(0 == ~E_2~0); 1031753#L977-3 assume !(0 == ~E_3~0); 1031751#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1031749#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1031747#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1031745#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1031734#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1031729#L1007-3 assume !(0 == ~E_9~0); 1031724#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1031716#L443-30 assume !(1 == ~m_pc~0); 1031710#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1031703#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1031696#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1031689#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1031682#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1031673#L462-30 assume !(1 == ~t1_pc~0); 1031667#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1031661#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1031655#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1031649#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1031643#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1031635#L481-30 assume !(1 == ~t2_pc~0); 1031629#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1031622#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1031615#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1031609#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1031604#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1031597#L500-30 assume !(1 == ~t3_pc~0); 1031591#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1031585#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1031579#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1031575#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1031570#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1031562#L519-30 assume !(1 == ~t4_pc~0); 1031556#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1031550#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1031544#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1031538#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1031532#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1031524#L538-30 assume !(1 == ~t5_pc~0); 1031517#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1031509#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1031501#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1031493#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1031487#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1031479#L557-30 assume !(1 == ~t6_pc~0); 1031471#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1031464#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1031457#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1031451#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1031447#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1031286#L576-30 assume !(1 == ~t7_pc~0); 1030695#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1030689#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1030684#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1030679#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1030673#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1030668#L595-30 assume !(1 == ~t8_pc~0); 1030663#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1030657#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1030652#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1030647#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1030642#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1030636#L614-30 assume !(1 == ~t9_pc~0); 1030630#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1030624#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1030619#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1030614#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1030608#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1030603#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1030597#L1025-5 assume !(1 == ~T1_E~0); 1030592#L1030-3 assume !(1 == ~T2_E~0); 1030587#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1030582#L1040-3 assume !(1 == ~T4_E~0); 1030577#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1030572#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1030566#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1030559#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1030553#L1065-3 assume !(1 == ~T9_E~0); 1030548#L1070-3 assume !(1 == ~E_1~0); 1030543#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1030538#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1030535#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1030532#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1030528#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1030524#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1030518#L1105-3 assume !(1 == ~E_8~0); 1030513#L1110-3 assume !(1 == ~E_9~0); 1030508#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1030471#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1030457#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1030452#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1030446#L1415 assume !(0 == start_simulation_~tmp~3#1); 1030443#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1030304#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1030291#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1030284#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1030276#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1030269#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1030262#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1030250#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1024522#L1396-2 [2023-11-29 04:12:04,848 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:04,849 INFO L85 PathProgramCache]: Analyzing trace with hash -1667156628, now seen corresponding path program 1 times [2023-11-29 04:12:04,849 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:04,849 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [872846253] [2023-11-29 04:12:04,849 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:04,849 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:04,858 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:04,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:04,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:04,898 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [872846253] [2023-11-29 04:12:04,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [872846253] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:04,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:04,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:04,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [517708850] [2023-11-29 04:12:04,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:04,899 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:12:04,899 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:04,899 INFO L85 PathProgramCache]: Analyzing trace with hash 667100061, now seen corresponding path program 1 times [2023-11-29 04:12:04,899 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:04,899 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [585829296] [2023-11-29 04:12:04,900 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:04,900 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:04,910 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:04,935 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:04,935 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:04,935 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [585829296] [2023-11-29 04:12:04,935 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [585829296] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:04,936 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:04,936 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:04,936 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2032197518] [2023-11-29 04:12:04,936 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:04,936 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:04,937 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:04,937 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:12:04,937 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:12:04,937 INFO L87 Difference]: Start difference. First operand 28595 states and 39826 transitions. cyclomatic complexity: 11263 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:05,138 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:05,138 INFO L93 Difference]: Finished difference Result 51109 states and 71131 transitions. [2023-11-29 04:12:05,138 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 51109 states and 71131 transitions. [2023-11-29 04:12:05,323 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 50688 [2023-11-29 04:12:05,436 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 51109 states to 51109 states and 71131 transitions. [2023-11-29 04:12:05,436 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 51109 [2023-11-29 04:12:05,460 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 51109 [2023-11-29 04:12:05,460 INFO L73 IsDeterministic]: Start isDeterministic. Operand 51109 states and 71131 transitions. [2023-11-29 04:12:05,482 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:05,482 INFO L218 hiAutomatonCegarLoop]: Abstraction has 51109 states and 71131 transitions. [2023-11-29 04:12:05,508 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 51109 states and 71131 transitions. [2023-11-29 04:12:05,745 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 51109 to 25611. [2023-11-29 04:12:05,759 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 25611 states, 25611 states have (on average 1.39166764280973) internal successors, (35642), 25610 states have internal predecessors, (35642), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:05,809 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 25611 states to 25611 states and 35642 transitions. [2023-11-29 04:12:05,809 INFO L240 hiAutomatonCegarLoop]: Abstraction has 25611 states and 35642 transitions. [2023-11-29 04:12:05,810 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:12:05,810 INFO L428 stractBuchiCegarLoop]: Abstraction has 25611 states and 35642 transitions. [2023-11-29 04:12:05,810 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-29 04:12:05,810 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 25611 states and 35642 transitions. [2023-11-29 04:12:05,876 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 25344 [2023-11-29 04:12:05,876 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:05,876 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:05,877 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:05,877 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:05,878 INFO L748 eck$LassoCheckResult]: Stem: 1104004#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1104005#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1104815#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1104816#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1104756#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1104757#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1104739#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1104549#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1104550#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1104337#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1104338#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1104845#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1104729#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1104405#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1104163#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1104164#L922 assume !(0 == ~M_E~0); 1104899#L922-2 assume !(0 == ~T1_E~0); 1104900#L927-1 assume !(0 == ~T2_E~0); 1104616#L932-1 assume !(0 == ~T3_E~0); 1104481#L937-1 assume !(0 == ~T4_E~0); 1104482#L942-1 assume !(0 == ~T5_E~0); 1104548#L947-1 assume !(0 == ~T6_E~0); 1104620#L952-1 assume !(0 == ~T7_E~0); 1104621#L957-1 assume !(0 == ~T8_E~0); 1104684#L962-1 assume !(0 == ~T9_E~0); 1104456#L967-1 assume !(0 == ~E_1~0); 1104457#L972-1 assume !(0 == ~E_2~0); 1104744#L977-1 assume !(0 == ~E_3~0); 1104745#L982-1 assume !(0 == ~E_4~0); 1103937#L987-1 assume !(0 == ~E_5~0); 1103938#L992-1 assume !(0 == ~E_6~0); 1103944#L997-1 assume !(0 == ~E_7~0); 1104379#L1002-1 assume !(0 == ~E_8~0); 1104367#L1007-1 assume !(0 == ~E_9~0); 1103732#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1103733#L443 assume !(1 == ~m_pc~0); 1104637#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1104628#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1104629#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1104098#L1140 assume !(0 != activate_threads_~tmp~1#1); 1103837#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1103838#L462 assume !(1 == ~t1_pc~0); 1104471#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1104472#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1103773#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1103774#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1104315#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1104316#L481 assume !(1 == ~t2_pc~0); 1104092#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1104091#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1104225#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1104185#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1104186#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1104285#L500 assume !(1 == ~t3_pc~0); 1104803#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1104774#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1103739#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1103740#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1103734#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1103735#L519 assume !(1 == ~t4_pc~0); 1104535#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1104284#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1103839#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1103840#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1104137#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1103901#L538 assume !(1 == ~t5_pc~0); 1103902#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1103798#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1103799#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1104079#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1104080#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1104668#L557 assume !(1 == ~t6_pc~0); 1104113#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1104114#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1104204#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1104135#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1104136#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1104882#L576 assume !(1 == ~t7_pc~0); 1104102#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1104103#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1104444#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1104896#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1104721#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1104226#L595 assume !(1 == ~t8_pc~0); 1104227#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1104735#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1104673#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1104573#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1104574#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1104031#L614 assume !(1 == ~t9_pc~0); 1104032#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1103926#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1103927#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1104261#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1104188#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1104189#L1025 assume !(1 == ~M_E~0); 1104463#L1025-2 assume !(1 == ~T1_E~0); 1104528#L1030-1 assume !(1 == ~T2_E~0); 1104660#L1035-1 assume !(1 == ~T3_E~0); 1104180#L1040-1 assume !(1 == ~T4_E~0); 1104181#L1045-1 assume !(1 == ~T5_E~0); 1104088#L1050-1 assume !(1 == ~T6_E~0); 1104089#L1055-1 assume !(1 == ~T7_E~0); 1103912#L1060-1 assume !(1 == ~T8_E~0); 1103913#L1065-1 assume !(1 == ~T9_E~0); 1103976#L1070-1 assume !(1 == ~E_1~0); 1104622#L1075-1 assume !(1 == ~E_2~0); 1104623#L1080-1 assume !(1 == ~E_3~0); 1104611#L1085-1 assume !(1 == ~E_4~0); 1104612#L1090-1 assume !(1 == ~E_5~0); 1104836#L1095-1 assume !(1 == ~E_6~0); 1104646#L1100-1 assume !(1 == ~E_7~0); 1104647#L1105-1 assume !(1 == ~E_8~0); 1103883#L1110-1 assume !(1 == ~E_9~0); 1103884#L1115-1 assume { :end_inline_reset_delta_events } true; 1104234#L1396-2 [2023-11-29 04:12:05,878 INFO L750 eck$LassoCheckResult]: Loop: 1104234#L1396-2 assume !false; 1110417#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1110412#L897-1 assume !false; 1110408#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1110405#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1110393#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1110391#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1110388#L766 assume !(0 != eval_~tmp~0#1); 1110389#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1110790#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1110788#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1110786#L922-5 assume !(0 == ~T1_E~0); 1110784#L927-3 assume !(0 == ~T2_E~0); 1110782#L932-3 assume !(0 == ~T3_E~0); 1110780#L937-3 assume !(0 == ~T4_E~0); 1110778#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1110776#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1110774#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1110772#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1110770#L962-3 assume !(0 == ~T9_E~0); 1110768#L967-3 assume !(0 == ~E_1~0); 1110765#L972-3 assume !(0 == ~E_2~0); 1110763#L977-3 assume !(0 == ~E_3~0); 1110761#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1110759#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1110757#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1110755#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1110753#L1002-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1110751#L1007-3 assume !(0 == ~E_9~0); 1110749#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1110747#L443-30 assume 1 == ~m_pc~0; 1110744#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1110742#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1110740#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1110738#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1110736#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1110734#L462-30 assume !(1 == ~t1_pc~0); 1110732#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1110728#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1110726#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1110724#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1110722#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1110719#L481-30 assume 1 == ~t2_pc~0; 1110716#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1110714#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1110712#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1110710#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1110708#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1110706#L500-30 assume !(1 == ~t3_pc~0); 1110704#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1110702#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1110699#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1110697#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1110695#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1110693#L519-30 assume !(1 == ~t4_pc~0); 1110691#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1110689#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1110687#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1110685#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1110683#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1110681#L538-30 assume !(1 == ~t5_pc~0); 1110677#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1110674#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1110672#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1110670#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1110667#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1110665#L557-30 assume !(1 == ~t6_pc~0); 1110663#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1110662#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1110658#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1110656#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1110654#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1110653#L576-30 assume 1 == ~t7_pc~0; 1110651#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1110648#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1110644#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1110640#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1110639#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1110638#L595-30 assume !(1 == ~t8_pc~0); 1110637#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1110636#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1110635#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1110634#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1110633#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1110632#L614-30 assume !(1 == ~t9_pc~0); 1110630#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1110629#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1110628#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1110627#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1110626#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1110625#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1110624#L1025-5 assume !(1 == ~T1_E~0); 1110623#L1030-3 assume !(1 == ~T2_E~0); 1110622#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1110621#L1040-3 assume !(1 == ~T4_E~0); 1110619#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1110616#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1110614#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1110612#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1110610#L1065-3 assume !(1 == ~T9_E~0); 1110608#L1070-3 assume !(1 == ~E_1~0); 1110606#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1110604#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1110602#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1110600#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1110598#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1110596#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1110594#L1105-3 assume !(1 == ~E_8~0); 1110591#L1110-3 assume !(1 == ~E_9~0); 1110589#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1110586#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1110575#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1110573#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1110451#L1415 assume !(0 == start_simulation_~tmp~3#1); 1110449#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1110439#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1110431#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1110429#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1110427#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1110424#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1110422#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1110420#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1104234#L1396-2 [2023-11-29 04:12:05,878 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:05,879 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 3 times [2023-11-29 04:12:05,879 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:05,879 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1329872080] [2023-11-29 04:12:05,879 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:05,879 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:05,894 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:05,895 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:05,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:05,931 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:05,932 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:05,932 INFO L85 PathProgramCache]: Analyzing trace with hash -1287928320, now seen corresponding path program 1 times [2023-11-29 04:12:05,932 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:05,933 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [447065869] [2023-11-29 04:12:05,933 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:05,933 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:05,946 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:05,980 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:05,980 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:05,980 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [447065869] [2023-11-29 04:12:05,980 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [447065869] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:05,980 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:05,981 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:05,981 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [350194477] [2023-11-29 04:12:05,981 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:05,981 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:05,981 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:05,982 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:12:05,982 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:12:05,982 INFO L87 Difference]: Start difference. First operand 25611 states and 35642 transitions. cyclomatic complexity: 10063 Second operand has 3 states, 3 states have (on average 40.666666666666664) internal successors, (122), 3 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:06,190 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:06,190 INFO L93 Difference]: Finished difference Result 37851 states and 52550 transitions. [2023-11-29 04:12:06,191 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 37851 states and 52550 transitions. [2023-11-29 04:12:06,336 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37440 [2023-11-29 04:12:06,418 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 37851 states to 37851 states and 52550 transitions. [2023-11-29 04:12:06,418 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 37851 [2023-11-29 04:12:06,436 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 37851 [2023-11-29 04:12:06,436 INFO L73 IsDeterministic]: Start isDeterministic. Operand 37851 states and 52550 transitions. [2023-11-29 04:12:06,454 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:06,454 INFO L218 hiAutomatonCegarLoop]: Abstraction has 37851 states and 52550 transitions. [2023-11-29 04:12:06,472 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 37851 states and 52550 transitions. [2023-11-29 04:12:06,725 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 37851 to 37835. [2023-11-29 04:12:06,746 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37835 states, 37835 states have (on average 1.3885027091317563) internal successors, (52534), 37834 states have internal predecessors, (52534), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:06,816 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37835 states to 37835 states and 52534 transitions. [2023-11-29 04:12:06,816 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37835 states and 52534 transitions. [2023-11-29 04:12:06,816 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:12:06,817 INFO L428 stractBuchiCegarLoop]: Abstraction has 37835 states and 52534 transitions. [2023-11-29 04:12:06,817 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-29 04:12:06,817 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37835 states and 52534 transitions. [2023-11-29 04:12:06,912 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37424 [2023-11-29 04:12:06,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:06,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:06,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:06,914 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:06,914 INFO L748 eck$LassoCheckResult]: Stem: 1167471#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1167472#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1168350#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1168351#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1168279#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1168280#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1168254#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1168030#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1168031#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1167806#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1167807#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1168382#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1168240#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1167879#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1167629#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1167630#L922 assume !(0 == ~M_E~0); 1168451#L922-2 assume !(0 == ~T1_E~0); 1168452#L927-1 assume !(0 == ~T2_E~0); 1168104#L932-1 assume !(0 == ~T3_E~0); 1167962#L937-1 assume !(0 == ~T4_E~0); 1167963#L942-1 assume !(0 == ~T5_E~0); 1168029#L947-1 assume !(0 == ~T6_E~0); 1168108#L952-1 assume !(0 == ~T7_E~0); 1168109#L957-1 assume !(0 == ~T8_E~0); 1168185#L962-1 assume !(0 == ~T9_E~0); 1167934#L967-1 assume !(0 == ~E_1~0); 1167935#L972-1 assume !(0 == ~E_2~0); 1168263#L977-1 assume !(0 == ~E_3~0); 1168264#L982-1 assume !(0 == ~E_4~0); 1167404#L987-1 assume !(0 == ~E_5~0); 1167405#L992-1 assume !(0 == ~E_6~0); 1167411#L997-1 assume !(0 == ~E_7~0); 1167851#L1002-1 assume 0 == ~E_8~0;~E_8~0 := 1; 1168401#L1007-1 assume !(0 == ~E_9~0); 1167200#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1167201#L443 assume !(1 == ~m_pc~0); 1168126#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1168127#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1168543#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1168542#L1140 assume !(0 != activate_threads_~tmp~1#1); 1167305#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1167306#L462 assume !(1 == ~t1_pc~0); 1168541#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1168540#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1168539#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1168136#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1168137#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1168538#L481 assume !(1 == ~t2_pc~0); 1168536#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1168093#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1167688#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1167651#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1167652#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1168471#L500 assume !(1 == ~t3_pc~0); 1168339#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1168299#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1168300#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1168531#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1168530#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1168529#L519 assume !(1 == ~t4_pc~0); 1168528#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1167753#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1167307#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1167308#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1167602#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1167368#L538 assume !(1 == ~t5_pc~0); 1167369#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1167266#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1167267#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1167544#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1167545#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1168476#L557 assume !(1 == ~t6_pc~0); 1167580#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1167581#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1167669#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1167603#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1167604#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1168426#L576 assume !(1 == ~t7_pc~0); 1168507#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1168506#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1168505#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1168458#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1168231#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1167691#L595 assume !(1 == ~t8_pc~0); 1167692#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1168250#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1168172#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1168056#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1168057#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1167496#L614 assume !(1 == ~t9_pc~0); 1167497#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1167393#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1167394#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1168493#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1168492#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1168491#L1025 assume !(1 == ~M_E~0); 1168490#L1025-2 assume !(1 == ~T1_E~0); 1168489#L1030-1 assume !(1 == ~T2_E~0); 1168488#L1035-1 assume !(1 == ~T3_E~0); 1168487#L1040-1 assume !(1 == ~T4_E~0); 1168486#L1045-1 assume !(1 == ~T5_E~0); 1168485#L1050-1 assume !(1 == ~T6_E~0); 1167744#L1055-1 assume !(1 == ~T7_E~0); 1167379#L1060-1 assume !(1 == ~T8_E~0); 1167380#L1065-1 assume !(1 == ~T9_E~0); 1167443#L1070-1 assume !(1 == ~E_1~0); 1168110#L1075-1 assume !(1 == ~E_2~0); 1168111#L1080-1 assume !(1 == ~E_3~0); 1168099#L1085-1 assume !(1 == ~E_4~0); 1168100#L1090-1 assume !(1 == ~E_5~0); 1168372#L1095-1 assume !(1 == ~E_6~0); 1168141#L1100-1 assume !(1 == ~E_7~0); 1168142#L1105-1 assume 1 == ~E_8~0;~E_8~0 := 2; 1167351#L1110-1 assume !(1 == ~E_9~0); 1167352#L1115-1 assume { :end_inline_reset_delta_events } true; 1167699#L1396-2 [2023-11-29 04:12:06,914 INFO L750 eck$LassoCheckResult]: Loop: 1167699#L1396-2 assume !false; 1178501#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1178493#L897-1 assume !false; 1178486#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1178339#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1178320#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1178319#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1178285#L766 assume !(0 != eval_~tmp~0#1); 1178286#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1179890#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1179888#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1179886#L922-5 assume !(0 == ~T1_E~0); 1179884#L927-3 assume !(0 == ~T2_E~0); 1179882#L932-3 assume !(0 == ~T3_E~0); 1179879#L937-3 assume !(0 == ~T4_E~0); 1179877#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1179875#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1179873#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1179871#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1179869#L962-3 assume !(0 == ~T9_E~0); 1179867#L967-3 assume !(0 == ~E_1~0); 1179866#L972-3 assume !(0 == ~E_2~0); 1179865#L977-3 assume !(0 == ~E_3~0); 1179863#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1179860#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1179858#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1179856#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1179853#L1002-3 assume !(0 == ~E_8~0); 1179851#L1007-3 assume !(0 == ~E_9~0); 1179849#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1179846#L443-30 assume 1 == ~m_pc~0; 1179843#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1179841#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1179839#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1179837#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1179835#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1179833#L462-30 assume !(1 == ~t1_pc~0); 1179831#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1179829#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1179827#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1179825#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1179823#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1179820#L481-30 assume 1 == ~t2_pc~0; 1179816#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1179814#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1179812#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1179810#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1179808#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1179806#L500-30 assume !(1 == ~t3_pc~0); 1179804#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1179802#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1179800#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1179798#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1179796#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1179792#L519-30 assume !(1 == ~t4_pc~0); 1179790#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1179771#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1179766#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1179761#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1179753#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1179743#L538-30 assume 1 == ~t5_pc~0; 1179736#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1179729#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1179721#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1179713#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1179706#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1179699#L557-30 assume !(1 == ~t6_pc~0); 1179692#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1179684#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1179677#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1179670#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1179664#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1179657#L576-30 assume !(1 == ~t7_pc~0); 1179650#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1179642#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1179633#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1179627#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1179620#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1179613#L595-30 assume !(1 == ~t8_pc~0); 1179607#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1179600#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1179592#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1179587#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1179584#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1179010#L614-30 assume !(1 == ~t9_pc~0); 1179007#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1179005#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1179002#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1179000#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1178998#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1178996#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1178994#L1025-5 assume !(1 == ~T1_E~0); 1178992#L1030-3 assume !(1 == ~T2_E~0); 1178990#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1178988#L1040-3 assume !(1 == ~T4_E~0); 1178986#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1178984#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1178982#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1178979#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1178977#L1065-3 assume !(1 == ~T9_E~0); 1178975#L1070-3 assume !(1 == ~E_1~0); 1178973#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1178971#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1178969#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1178889#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1178877#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1178868#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1178859#L1105-3 assume !(1 == ~E_8~0); 1178852#L1110-3 assume !(1 == ~E_9~0); 1178848#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1178775#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1178760#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1178754#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1178747#L1415 assume !(0 == start_simulation_~tmp~3#1); 1178745#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1178571#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1178556#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1178546#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1178536#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1178530#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1178522#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1178513#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1167699#L1396-2 [2023-11-29 04:12:06,915 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:06,915 INFO L85 PathProgramCache]: Analyzing trace with hash 63435116, now seen corresponding path program 1 times [2023-11-29 04:12:06,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:06,915 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [957672280] [2023-11-29 04:12:06,915 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:06,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:06,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:06,969 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:06,969 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:06,969 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [957672280] [2023-11-29 04:12:06,970 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [957672280] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:06,970 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:06,970 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:06,970 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1972520242] [2023-11-29 04:12:06,970 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:06,970 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 04:12:06,971 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:06,971 INFO L85 PathProgramCache]: Analyzing trace with hash 374632132, now seen corresponding path program 1 times [2023-11-29 04:12:06,971 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:06,971 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [226983545] [2023-11-29 04:12:06,972 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:06,972 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:06,983 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:07,023 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:07,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:07,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [226983545] [2023-11-29 04:12:07,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [226983545] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:07,024 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:07,024 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:07,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1567547120] [2023-11-29 04:12:07,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:07,024 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:07,025 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:07,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 04:12:07,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 04:12:07,025 INFO L87 Difference]: Start difference. First operand 37835 states and 52534 transitions. cyclomatic complexity: 14731 Second operand has 4 states, 4 states have (on average 28.75) internal successors, (115), 3 states have internal predecessors, (115), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:07,352 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:07,352 INFO L93 Difference]: Finished difference Result 70205 states and 97555 transitions. [2023-11-29 04:12:07,352 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 70205 states and 97555 transitions. [2023-11-29 04:12:07,652 INFO L131 ngComponentsAnalysis]: Automaton has 80 accepting balls. 67408 [2023-11-29 04:12:07,827 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 70205 states to 70205 states and 97555 transitions. [2023-11-29 04:12:07,827 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 70205 [2023-11-29 04:12:07,863 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 70205 [2023-11-29 04:12:07,863 INFO L73 IsDeterministic]: Start isDeterministic. Operand 70205 states and 97555 transitions. [2023-11-29 04:12:07,895 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:07,895 INFO L218 hiAutomatonCegarLoop]: Abstraction has 70205 states and 97555 transitions. [2023-11-29 04:12:07,931 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 70205 states and 97555 transitions. [2023-11-29 04:12:08,264 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 70205 to 36307. [2023-11-29 04:12:08,285 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36307 states, 36307 states have (on average 1.3874184041644861) internal successors, (50373), 36306 states have internal predecessors, (50373), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:08,352 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36307 states to 36307 states and 50373 transitions. [2023-11-29 04:12:08,352 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36307 states and 50373 transitions. [2023-11-29 04:12:08,352 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 04:12:08,353 INFO L428 stractBuchiCegarLoop]: Abstraction has 36307 states and 50373 transitions. [2023-11-29 04:12:08,353 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-29 04:12:08,353 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36307 states and 50373 transitions. [2023-11-29 04:12:08,444 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 35984 [2023-11-29 04:12:08,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:08,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:08,445 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:08,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:08,446 INFO L748 eck$LassoCheckResult]: Stem: 1275522#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1275523#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1276371#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1276372#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1276304#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1276305#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1276280#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1276072#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1276073#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1275853#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1275854#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1276402#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1276268#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1275924#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1275681#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1275682#L922 assume !(0 == ~M_E~0); 1276473#L922-2 assume !(0 == ~T1_E~0); 1276474#L927-1 assume !(0 == ~T2_E~0); 1276142#L932-1 assume !(0 == ~T3_E~0); 1276002#L937-1 assume !(0 == ~T4_E~0); 1276003#L942-1 assume !(0 == ~T5_E~0); 1276071#L947-1 assume !(0 == ~T6_E~0); 1276147#L952-1 assume !(0 == ~T7_E~0); 1276148#L957-1 assume !(0 == ~T8_E~0); 1276215#L962-1 assume !(0 == ~T9_E~0); 1275976#L967-1 assume !(0 == ~E_1~0); 1275977#L972-1 assume !(0 == ~E_2~0); 1276288#L977-1 assume !(0 == ~E_3~0); 1276289#L982-1 assume !(0 == ~E_4~0); 1275456#L987-1 assume !(0 == ~E_5~0); 1275457#L992-1 assume !(0 == ~E_6~0); 1275463#L997-1 assume !(0 == ~E_7~0); 1275896#L1002-1 assume !(0 == ~E_8~0); 1275883#L1007-1 assume !(0 == ~E_9~0); 1275252#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1275253#L443 assume !(1 == ~m_pc~0); 1276164#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1276155#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1276156#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1275618#L1140 assume !(0 != activate_threads_~tmp~1#1); 1275357#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1275358#L462 assume !(1 == ~t1_pc~0); 1275992#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1275993#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1275293#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1275294#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1275831#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1275832#L481 assume !(1 == ~t2_pc~0); 1275612#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1275611#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1275741#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1275704#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1275705#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1275801#L500 assume !(1 == ~t3_pc~0); 1276361#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1276325#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1275259#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1275260#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1275254#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1275255#L519 assume !(1 == ~t4_pc~0); 1276057#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1275800#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1275359#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1275360#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1275655#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1275420#L538 assume !(1 == ~t5_pc~0); 1275421#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1275318#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1275319#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1275598#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1275599#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1276199#L557 assume !(1 == ~t6_pc~0); 1275632#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1275633#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1275723#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1275653#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1275654#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1276444#L576 assume !(1 == ~t7_pc~0); 1275622#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1275623#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1275963#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1276469#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1276260#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1275742#L595 assume !(1 == ~t8_pc~0); 1275743#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1276275#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1276204#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1276099#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1276100#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1275549#L614 assume !(1 == ~t9_pc~0); 1275550#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1275445#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1275446#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1275777#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1275708#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1275709#L1025 assume !(1 == ~M_E~0); 1275983#L1025-2 assume !(1 == ~T1_E~0); 1276050#L1030-1 assume !(1 == ~T2_E~0); 1276191#L1035-1 assume !(1 == ~T3_E~0); 1275699#L1040-1 assume !(1 == ~T4_E~0); 1275700#L1045-1 assume !(1 == ~T5_E~0); 1275608#L1050-1 assume !(1 == ~T6_E~0); 1275609#L1055-1 assume !(1 == ~T7_E~0); 1275431#L1060-1 assume !(1 == ~T8_E~0); 1275432#L1065-1 assume !(1 == ~T9_E~0); 1275494#L1070-1 assume !(1 == ~E_1~0); 1276149#L1075-1 assume !(1 == ~E_2~0); 1276150#L1080-1 assume !(1 == ~E_3~0); 1276137#L1085-1 assume !(1 == ~E_4~0); 1276138#L1090-1 assume !(1 == ~E_5~0); 1276394#L1095-1 assume !(1 == ~E_6~0); 1276174#L1100-1 assume !(1 == ~E_7~0); 1276175#L1105-1 assume !(1 == ~E_8~0); 1275403#L1110-1 assume !(1 == ~E_9~0); 1275404#L1115-1 assume { :end_inline_reset_delta_events } true; 1275751#L1396-2 [2023-11-29 04:12:08,446 INFO L750 eck$LassoCheckResult]: Loop: 1275751#L1396-2 assume !false; 1282778#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1282773#L897-1 assume !false; 1282771#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1282768#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1282756#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1282754#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1282751#L766 assume !(0 != eval_~tmp~0#1); 1282752#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1284175#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1284173#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1284171#L922-5 assume !(0 == ~T1_E~0); 1284168#L927-3 assume !(0 == ~T2_E~0); 1284166#L932-3 assume !(0 == ~T3_E~0); 1284164#L937-3 assume !(0 == ~T4_E~0); 1284039#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1284029#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1284017#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1284006#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1283997#L962-3 assume !(0 == ~T9_E~0); 1283991#L967-3 assume !(0 == ~E_1~0); 1283988#L972-3 assume !(0 == ~E_2~0); 1283500#L977-3 assume !(0 == ~E_3~0); 1283495#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1283490#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1283045#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1283043#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1283041#L1002-3 assume !(0 == ~E_8~0); 1283040#L1007-3 assume !(0 == ~E_9~0); 1283037#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1283034#L443-30 assume !(1 == ~m_pc~0); 1283030#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1283028#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1283027#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1283026#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1283024#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1283023#L462-30 assume !(1 == ~t1_pc~0); 1283022#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1283021#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1283020#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1283019#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1283018#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1283017#L481-30 assume 1 == ~t2_pc~0; 1283015#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1283014#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1283013#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1283012#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1283011#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1283010#L500-30 assume !(1 == ~t3_pc~0); 1283009#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1283008#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1283007#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1283005#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1283004#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1283003#L519-30 assume !(1 == ~t4_pc~0); 1283002#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1283001#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1283000#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1282998#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1282997#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1282996#L538-30 assume 1 == ~t5_pc~0; 1282994#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1282995#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1282999#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1282986#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1282984#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1282982#L557-30 assume !(1 == ~t6_pc~0); 1282980#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1282978#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1282976#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1282974#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1282972#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1282970#L576-30 assume 1 == ~t7_pc~0; 1282967#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1282965#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1282963#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1282960#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1282958#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1282956#L595-30 assume !(1 == ~t8_pc~0); 1282954#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1282952#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1282950#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1282948#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1282946#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1282944#L614-30 assume !(1 == ~t9_pc~0); 1282941#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1282939#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1282937#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1282935#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1282933#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1282931#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1282929#L1025-5 assume !(1 == ~T1_E~0); 1282927#L1030-3 assume !(1 == ~T2_E~0); 1282926#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1282922#L1040-3 assume !(1 == ~T4_E~0); 1282920#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1282918#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1282916#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1282913#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1282911#L1065-3 assume !(1 == ~T9_E~0); 1282909#L1070-3 assume !(1 == ~E_1~0); 1282907#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1282905#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1282903#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1282901#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1282899#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1282897#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1282894#L1105-3 assume !(1 == ~E_8~0); 1282892#L1110-3 assume !(1 == ~E_9~0); 1282890#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1282887#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1282876#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1282874#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1282815#L1415 assume !(0 == start_simulation_~tmp~3#1); 1282813#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1282801#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1282793#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1282791#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1282789#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1282786#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1282784#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1282782#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1275751#L1396-2 [2023-11-29 04:12:08,447 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:08,447 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 4 times [2023-11-29 04:12:08,447 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:08,447 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1687997448] [2023-11-29 04:12:08,447 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:08,447 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:08,461 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:08,461 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:08,469 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:08,501 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:08,501 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:08,501 INFO L85 PathProgramCache]: Analyzing trace with hash 478439428, now seen corresponding path program 1 times [2023-11-29 04:12:08,502 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:08,502 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2095477233] [2023-11-29 04:12:08,502 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:08,502 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:08,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:08,566 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:08,567 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:08,567 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2095477233] [2023-11-29 04:12:08,567 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2095477233] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:08,567 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:08,567 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:08,567 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1811019842] [2023-11-29 04:12:08,568 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:08,568 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:08,568 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:08,569 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:12:08,569 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:12:08,569 INFO L87 Difference]: Start difference. First operand 36307 states and 50373 transitions. cyclomatic complexity: 14098 Second operand has 5 states, 5 states have (on average 24.4) internal successors, (122), 5 states have internal predecessors, (122), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:08,888 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:08,889 INFO L93 Difference]: Finished difference Result 66731 states and 91817 transitions. [2023-11-29 04:12:08,889 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66731 states and 91817 transitions. [2023-11-29 04:12:09,131 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 66208 [2023-11-29 04:12:09,268 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66731 states to 66731 states and 91817 transitions. [2023-11-29 04:12:09,268 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66731 [2023-11-29 04:12:09,297 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66731 [2023-11-29 04:12:09,297 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66731 states and 91817 transitions. [2023-11-29 04:12:09,322 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:09,322 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66731 states and 91817 transitions. [2023-11-29 04:12:09,354 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66731 states and 91817 transitions. [2023-11-29 04:12:09,599 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66731 to 36451. [2023-11-29 04:12:09,619 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 36451 states, 36451 states have (on average 1.3858879043098955) internal successors, (50517), 36450 states have internal predecessors, (50517), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:09,670 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 36451 states to 36451 states and 50517 transitions. [2023-11-29 04:12:09,670 INFO L240 hiAutomatonCegarLoop]: Abstraction has 36451 states and 50517 transitions. [2023-11-29 04:12:09,671 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-29 04:12:09,671 INFO L428 stractBuchiCegarLoop]: Abstraction has 36451 states and 50517 transitions. [2023-11-29 04:12:09,671 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-29 04:12:09,671 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 36451 states and 50517 transitions. [2023-11-29 04:12:09,744 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 36128 [2023-11-29 04:12:09,744 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:09,744 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:09,745 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:09,745 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:09,745 INFO L748 eck$LassoCheckResult]: Stem: 1378578#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1378579#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1379432#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1379433#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1379370#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1379371#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1379343#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1379128#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1379129#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1378911#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1378912#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1379464#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1379332#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1378980#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1378736#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1378737#L922 assume !(0 == ~M_E~0); 1379532#L922-2 assume !(0 == ~T1_E~0); 1379533#L927-1 assume !(0 == ~T2_E~0); 1379206#L932-1 assume !(0 == ~T3_E~0); 1379062#L937-1 assume !(0 == ~T4_E~0); 1379063#L942-1 assume !(0 == ~T5_E~0); 1379127#L947-1 assume !(0 == ~T6_E~0); 1379211#L952-1 assume !(0 == ~T7_E~0); 1379212#L957-1 assume !(0 == ~T8_E~0); 1379279#L962-1 assume !(0 == ~T9_E~0); 1379038#L967-1 assume !(0 == ~E_1~0); 1379039#L972-1 assume !(0 == ~E_2~0); 1379353#L977-1 assume !(0 == ~E_3~0); 1379354#L982-1 assume !(0 == ~E_4~0); 1378512#L987-1 assume !(0 == ~E_5~0); 1378513#L992-1 assume !(0 == ~E_6~0); 1378519#L997-1 assume !(0 == ~E_7~0); 1378954#L1002-1 assume !(0 == ~E_8~0); 1378939#L1007-1 assume !(0 == ~E_9~0); 1378307#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1378308#L443 assume !(1 == ~m_pc~0); 1379228#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1379219#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1379220#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1378672#L1140 assume !(0 != activate_threads_~tmp~1#1); 1378412#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1378413#L462 assume !(1 == ~t1_pc~0); 1379051#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1379052#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1378348#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1378349#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1378889#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1378890#L481 assume !(1 == ~t2_pc~0); 1378666#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1378665#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1378795#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1378758#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1378759#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1378859#L500 assume !(1 == ~t3_pc~0); 1379420#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1379388#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1378314#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1378315#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1378309#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1378310#L519 assume !(1 == ~t4_pc~0); 1379117#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1378858#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1378414#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1378415#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1378710#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1378475#L538 assume !(1 == ~t5_pc~0); 1378476#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1378373#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1378374#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1378652#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1378653#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1379262#L557 assume !(1 == ~t6_pc~0); 1378686#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1378687#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1378776#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1378708#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1378709#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1379506#L576 assume !(1 == ~t7_pc~0); 1378676#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1378677#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1379025#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1379526#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1379324#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1378798#L595 assume !(1 == ~t8_pc~0); 1378799#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1379339#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1379267#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1379156#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1379157#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1378604#L614 assume !(1 == ~t9_pc~0); 1378605#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1378500#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1378501#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1378835#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1378761#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1378762#L1025 assume !(1 == ~M_E~0); 1379045#L1025-2 assume !(1 == ~T1_E~0); 1379109#L1030-1 assume !(1 == ~T2_E~0); 1379254#L1035-1 assume !(1 == ~T3_E~0); 1378753#L1040-1 assume !(1 == ~T4_E~0); 1378754#L1045-1 assume !(1 == ~T5_E~0); 1378662#L1050-1 assume !(1 == ~T6_E~0); 1378663#L1055-1 assume !(1 == ~T7_E~0); 1378486#L1060-1 assume !(1 == ~T8_E~0); 1378487#L1065-1 assume !(1 == ~T9_E~0); 1378551#L1070-1 assume !(1 == ~E_1~0); 1379213#L1075-1 assume !(1 == ~E_2~0); 1379214#L1080-1 assume !(1 == ~E_3~0); 1379200#L1085-1 assume !(1 == ~E_4~0); 1379201#L1090-1 assume !(1 == ~E_5~0); 1379456#L1095-1 assume !(1 == ~E_6~0); 1379238#L1100-1 assume !(1 == ~E_7~0); 1379239#L1105-1 assume !(1 == ~E_8~0); 1378458#L1110-1 assume !(1 == ~E_9~0); 1378459#L1115-1 assume { :end_inline_reset_delta_events } true; 1378808#L1396-2 [2023-11-29 04:12:09,745 INFO L750 eck$LassoCheckResult]: Loop: 1378808#L1396-2 assume !false; 1391747#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1391743#L897-1 assume !false; 1391742#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1391741#L699 assume !(0 == ~m_st~0); 1391733#L703 assume !(0 == ~t1_st~0); 1391734#L707 assume !(0 == ~t2_st~0); 1391738#L711 assume !(0 == ~t3_st~0); 1391731#L715 assume !(0 == ~t4_st~0); 1391732#L719 assume !(0 == ~t5_st~0); 1391737#L723 assume !(0 == ~t6_st~0); 1391740#L727 assume !(0 == ~t7_st~0); 1391735#L731 assume !(0 == ~t8_st~0); 1391736#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1391739#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1386822#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1386823#L766 assume !(0 != eval_~tmp~0#1); 1391916#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1391915#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1391914#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1391913#L922-5 assume !(0 == ~T1_E~0); 1391912#L927-3 assume !(0 == ~T2_E~0); 1391911#L932-3 assume !(0 == ~T3_E~0); 1391910#L937-3 assume !(0 == ~T4_E~0); 1391909#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1391908#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1391907#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1391906#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1391905#L962-3 assume !(0 == ~T9_E~0); 1391904#L967-3 assume !(0 == ~E_1~0); 1391903#L972-3 assume !(0 == ~E_2~0); 1391902#L977-3 assume !(0 == ~E_3~0); 1391901#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1391900#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1391899#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1391898#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1391897#L1002-3 assume !(0 == ~E_8~0); 1391896#L1007-3 assume !(0 == ~E_9~0); 1391895#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1391894#L443-30 assume !(1 == ~m_pc~0); 1391893#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1391891#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1391890#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1391889#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1391888#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1391887#L462-30 assume !(1 == ~t1_pc~0); 1391886#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1391885#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1391884#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1391883#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1391882#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1391881#L481-30 assume 1 == ~t2_pc~0; 1391879#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1391878#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1391877#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1391876#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1391875#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1391874#L500-30 assume !(1 == ~t3_pc~0); 1391873#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1391872#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1391871#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1391870#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1391869#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1391868#L519-30 assume !(1 == ~t4_pc~0); 1391867#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1391866#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1391865#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1391864#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1391863#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1391862#L538-30 assume !(1 == ~t5_pc~0); 1391861#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1391859#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1391857#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1391855#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1391853#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1391852#L557-30 assume !(1 == ~t6_pc~0); 1391851#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1391850#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1391849#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1391848#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1391847#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1391846#L576-30 assume !(1 == ~t7_pc~0); 1391845#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1391843#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1391842#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1391841#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1391840#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1391839#L595-30 assume !(1 == ~t8_pc~0); 1391838#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1391837#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1391836#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1391835#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1391834#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1391833#L614-30 assume !(1 == ~t9_pc~0); 1391831#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1391830#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1391829#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1391828#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1391827#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1391826#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1391825#L1025-5 assume !(1 == ~T1_E~0); 1391824#L1030-3 assume !(1 == ~T2_E~0); 1391823#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1391822#L1040-3 assume !(1 == ~T4_E~0); 1391821#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1391820#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1391819#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1391818#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1391817#L1065-3 assume !(1 == ~T9_E~0); 1391816#L1070-3 assume !(1 == ~E_1~0); 1391815#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1391814#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1391813#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1391812#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1391811#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1391810#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1391809#L1105-3 assume !(1 == ~E_8~0); 1391808#L1110-3 assume !(1 == ~E_9~0); 1391807#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1391806#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1391793#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1391790#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1391786#L1415 assume !(0 == start_simulation_~tmp~3#1); 1391784#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1391780#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1391772#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1391770#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1391766#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1391764#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1391761#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1391757#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1378808#L1396-2 [2023-11-29 04:12:09,746 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:09,746 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 5 times [2023-11-29 04:12:09,746 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:09,746 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [819143362] [2023-11-29 04:12:09,746 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:09,746 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:09,757 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:09,757 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:09,763 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:09,787 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:09,788 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:09,788 INFO L85 PathProgramCache]: Analyzing trace with hash 1372687177, now seen corresponding path program 1 times [2023-11-29 04:12:09,788 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:09,788 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [201869459] [2023-11-29 04:12:09,789 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:09,789 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:09,799 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:09,842 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:09,842 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:09,842 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [201869459] [2023-11-29 04:12:09,842 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [201869459] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:09,842 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:09,842 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:09,843 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [701904771] [2023-11-29 04:12:09,843 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:09,843 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:09,843 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:09,843 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:12:09,844 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:12:09,844 INFO L87 Difference]: Start difference. First operand 36451 states and 50517 transitions. cyclomatic complexity: 14098 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:10,246 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:10,247 INFO L93 Difference]: Finished difference Result 71699 states and 98659 transitions. [2023-11-29 04:12:10,247 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 71699 states and 98659 transitions. [2023-11-29 04:12:10,509 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 71104 [2023-11-29 04:12:10,673 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 71699 states to 71699 states and 98659 transitions. [2023-11-29 04:12:10,673 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 71699 [2023-11-29 04:12:10,709 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 71699 [2023-11-29 04:12:10,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 71699 states and 98659 transitions. [2023-11-29 04:12:10,742 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:10,742 INFO L218 hiAutomatonCegarLoop]: Abstraction has 71699 states and 98659 transitions. [2023-11-29 04:12:10,778 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 71699 states and 98659 transitions. [2023-11-29 04:12:11,113 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 71699 to 37606. [2023-11-29 04:12:11,134 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37606 states, 37606 states have (on average 1.374036058075839) internal successors, (51672), 37605 states have internal predecessors, (51672), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:11,203 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37606 states to 37606 states and 51672 transitions. [2023-11-29 04:12:11,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37606 states and 51672 transitions. [2023-11-29 04:12:11,204 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-29 04:12:11,204 INFO L428 stractBuchiCegarLoop]: Abstraction has 37606 states and 51672 transitions. [2023-11-29 04:12:11,204 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-29 04:12:11,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37606 states and 51672 transitions. [2023-11-29 04:12:11,300 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37280 [2023-11-29 04:12:11,300 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:11,301 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:11,302 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:11,302 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:11,302 INFO L748 eck$LassoCheckResult]: Stem: 1486743#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1486744#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1487604#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1487605#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1487541#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1487542#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1487519#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1487302#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1487303#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1487080#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1487081#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1487637#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1487506#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1487152#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1486900#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1486901#L922 assume !(0 == ~M_E~0); 1487699#L922-2 assume !(0 == ~T1_E~0); 1487700#L927-1 assume !(0 == ~T2_E~0); 1487372#L932-1 assume !(0 == ~T3_E~0); 1487232#L937-1 assume !(0 == ~T4_E~0); 1487233#L942-1 assume !(0 == ~T5_E~0); 1487301#L947-1 assume !(0 == ~T6_E~0); 1487376#L952-1 assume !(0 == ~T7_E~0); 1487377#L957-1 assume !(0 == ~T8_E~0); 1487452#L962-1 assume !(0 == ~T9_E~0); 1487208#L967-1 assume !(0 == ~E_1~0); 1487209#L972-1 assume !(0 == ~E_2~0); 1487524#L977-1 assume !(0 == ~E_3~0); 1487525#L982-1 assume !(0 == ~E_4~0); 1486675#L987-1 assume !(0 == ~E_5~0); 1486676#L992-1 assume !(0 == ~E_6~0); 1486680#L997-1 assume !(0 == ~E_7~0); 1487127#L1002-1 assume !(0 == ~E_8~0); 1487111#L1007-1 assume !(0 == ~E_9~0); 1486469#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1486470#L443 assume !(1 == ~m_pc~0); 1487393#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1487384#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1487385#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1486838#L1140 assume !(0 != activate_threads_~tmp~1#1); 1486574#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1486575#L462 assume !(1 == ~t1_pc~0); 1487226#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1487227#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1486512#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1486513#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1487058#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1487059#L481 assume !(1 == ~t2_pc~0); 1486832#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1487581#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1487718#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1487717#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1486925#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1487029#L500 assume !(1 == ~t3_pc~0); 1487594#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1487559#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1486476#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1486477#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1486474#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1486475#L519 assume !(1 == ~t4_pc~0); 1487289#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1487026#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1486576#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1486577#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1486875#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1486637#L538 assume !(1 == ~t5_pc~0); 1486638#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1486537#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1486538#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1486818#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1486819#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1487433#L557 assume !(1 == ~t6_pc~0); 1486852#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1486853#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1486942#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1486876#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1486877#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1487673#L576 assume !(1 == ~t7_pc~0); 1486842#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1486843#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1487192#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1487694#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1487496#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1486965#L595 assume !(1 == ~t8_pc~0); 1486966#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1487515#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1487437#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1487325#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1487326#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1486768#L614 assume !(1 == ~t9_pc~0); 1486769#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1486663#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1486664#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1487001#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1486927#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1486928#L1025 assume !(1 == ~M_E~0); 1487214#L1025-2 assume !(1 == ~T1_E~0); 1487282#L1030-1 assume !(1 == ~T2_E~0); 1487425#L1035-1 assume !(1 == ~T3_E~0); 1486920#L1040-1 assume !(1 == ~T4_E~0); 1486921#L1045-1 assume !(1 == ~T5_E~0); 1486828#L1050-1 assume !(1 == ~T6_E~0); 1486829#L1055-1 assume !(1 == ~T7_E~0); 1486648#L1060-1 assume !(1 == ~T8_E~0); 1486649#L1065-1 assume !(1 == ~T9_E~0); 1486713#L1070-1 assume !(1 == ~E_1~0); 1487380#L1075-1 assume !(1 == ~E_2~0); 1487381#L1080-1 assume !(1 == ~E_3~0); 1487366#L1085-1 assume !(1 == ~E_4~0); 1487367#L1090-1 assume !(1 == ~E_5~0); 1487628#L1095-1 assume !(1 == ~E_6~0); 1487403#L1100-1 assume !(1 == ~E_7~0); 1487404#L1105-1 assume !(1 == ~E_8~0); 1486620#L1110-1 assume !(1 == ~E_9~0); 1486621#L1115-1 assume { :end_inline_reset_delta_events } true; 1486973#L1396-2 [2023-11-29 04:12:11,303 INFO L750 eck$LassoCheckResult]: Loop: 1486973#L1396-2 assume !false; 1491199#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1491193#L897-1 assume !false; 1491191#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1491187#L699 assume !(0 == ~m_st~0); 1491179#L703 assume !(0 == ~t1_st~0); 1491180#L707 assume !(0 == ~t2_st~0); 1491184#L711 assume !(0 == ~t3_st~0); 1491177#L715 assume !(0 == ~t4_st~0); 1491178#L719 assume !(0 == ~t5_st~0); 1491183#L723 assume !(0 == ~t6_st~0); 1491186#L727 assume !(0 == ~t7_st~0); 1491181#L731 assume !(0 == ~t8_st~0); 1491182#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1491185#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1493002#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1493000#L766 assume !(0 != eval_~tmp~0#1); 1492998#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1492996#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1492994#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1492992#L922-5 assume !(0 == ~T1_E~0); 1492990#L927-3 assume !(0 == ~T2_E~0); 1492988#L932-3 assume !(0 == ~T3_E~0); 1492986#L937-3 assume !(0 == ~T4_E~0); 1492984#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1492982#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1492980#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1492978#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1492976#L962-3 assume !(0 == ~T9_E~0); 1492972#L967-3 assume !(0 == ~E_1~0); 1492970#L972-3 assume !(0 == ~E_2~0); 1492968#L977-3 assume !(0 == ~E_3~0); 1492966#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1492963#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1492961#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1492959#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1492956#L1002-3 assume !(0 == ~E_8~0); 1492954#L1007-3 assume !(0 == ~E_9~0); 1492952#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1492950#L443-30 assume 1 == ~m_pc~0; 1492928#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1492926#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1492924#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1492922#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1492919#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1492882#L462-30 assume !(1 == ~t1_pc~0); 1492874#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1492867#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1492852#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1492846#L1148-30 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1492845#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1492844#L481-30 assume !(1 == ~t2_pc~0); 1492842#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1492840#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1492838#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1492836#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1492834#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1492803#L500-30 assume !(1 == ~t3_pc~0); 1492802#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1492801#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1492800#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1492799#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1492797#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1492794#L519-30 assume !(1 == ~t4_pc~0); 1492792#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1492790#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1492788#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1492786#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1492784#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1492782#L538-30 assume 1 == ~t5_pc~0; 1492780#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1492781#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1492824#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1492770#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1492694#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1492683#L557-30 assume !(1 == ~t6_pc~0); 1492676#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1492670#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1492666#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1492665#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1492664#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1492663#L576-30 assume !(1 == ~t7_pc~0); 1492634#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1492631#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1492629#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1492627#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1492625#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1492623#L595-30 assume !(1 == ~t8_pc~0); 1492621#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1492618#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1492616#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1492614#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1492546#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1492539#L614-30 assume !(1 == ~t9_pc~0); 1492531#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1492525#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1492516#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1492508#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1492501#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1492494#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1492489#L1025-5 assume !(1 == ~T1_E~0); 1492485#L1030-3 assume !(1 == ~T2_E~0); 1492477#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1492473#L1040-3 assume !(1 == ~T4_E~0); 1492469#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1492465#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1492460#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1492455#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1492451#L1065-3 assume !(1 == ~T9_E~0); 1492447#L1070-3 assume !(1 == ~E_1~0); 1492443#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1492438#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1492432#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1492419#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1492411#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1492405#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1492392#L1105-3 assume !(1 == ~E_8~0); 1492384#L1110-3 assume !(1 == ~E_9~0); 1492378#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1492322#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1492304#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1492296#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1492286#L1415 assume !(0 == start_simulation_~tmp~3#1); 1492279#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1491376#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1491361#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1491360#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1491358#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1491357#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1491356#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1491343#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1486973#L1396-2 [2023-11-29 04:12:11,303 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:11,303 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 6 times [2023-11-29 04:12:11,303 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:11,303 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1780070282] [2023-11-29 04:12:11,304 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:11,304 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:11,313 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:11,313 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:11,318 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:11,335 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:11,336 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:11,336 INFO L85 PathProgramCache]: Analyzing trace with hash 1762689836, now seen corresponding path program 1 times [2023-11-29 04:12:11,336 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:11,336 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [209024868] [2023-11-29 04:12:11,336 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:11,336 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:11,352 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:11,429 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:11,429 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:11,429 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [209024868] [2023-11-29 04:12:11,430 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [209024868] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:11,430 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:11,430 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:11,430 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1806584750] [2023-11-29 04:12:11,430 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:11,431 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:11,431 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:11,431 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:12:11,432 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:12:11,432 INFO L87 Difference]: Start difference. First operand 37606 states and 51672 transitions. cyclomatic complexity: 14098 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:11,727 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:11,727 INFO L93 Difference]: Finished difference Result 44878 states and 61467 transitions. [2023-11-29 04:12:11,728 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 44878 states and 61467 transitions. [2023-11-29 04:12:11,884 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 44476 [2023-11-29 04:12:11,980 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 44878 states to 44878 states and 61467 transitions. [2023-11-29 04:12:11,980 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 44878 [2023-11-29 04:12:12,002 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 44878 [2023-11-29 04:12:12,002 INFO L73 IsDeterministic]: Start isDeterministic. Operand 44878 states and 61467 transitions. [2023-11-29 04:12:12,021 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:12,021 INFO L218 hiAutomatonCegarLoop]: Abstraction has 44878 states and 61467 transitions. [2023-11-29 04:12:12,043 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 44878 states and 61467 transitions. [2023-11-29 04:12:12,317 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 44878 to 37678. [2023-11-29 04:12:12,337 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 37678 states, 37678 states have (on average 1.3637401135941398) internal successors, (51383), 37677 states have internal predecessors, (51383), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:12,406 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 37678 states to 37678 states and 51383 transitions. [2023-11-29 04:12:12,407 INFO L240 hiAutomatonCegarLoop]: Abstraction has 37678 states and 51383 transitions. [2023-11-29 04:12:12,407 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:12:12,407 INFO L428 stractBuchiCegarLoop]: Abstraction has 37678 states and 51383 transitions. [2023-11-29 04:12:12,407 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-29 04:12:12,408 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 37678 states and 51383 transitions. [2023-11-29 04:12:12,501 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37352 [2023-11-29 04:12:12,502 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:12,502 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:12,503 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:12,503 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:12,504 INFO L748 eck$LassoCheckResult]: Stem: 1569243#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1569244#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1570187#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1570188#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1570110#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1570111#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1570077#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1569828#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1569829#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1569591#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1569592#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1570233#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1570060#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1569665#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1569407#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1569408#L922 assume !(0 == ~M_E~0); 1570342#L922-2 assume !(0 == ~T1_E~0); 1570343#L927-1 assume !(0 == ~T2_E~0); 1569910#L932-1 assume !(0 == ~T3_E~0); 1569749#L937-1 assume !(0 == ~T4_E~0); 1569750#L942-1 assume !(0 == ~T5_E~0); 1569827#L947-1 assume !(0 == ~T6_E~0); 1569915#L952-1 assume !(0 == ~T7_E~0); 1569916#L957-1 assume !(0 == ~T8_E~0); 1569997#L962-1 assume !(0 == ~T9_E~0); 1569722#L967-1 assume !(0 == ~E_1~0); 1569723#L972-1 assume !(0 == ~E_2~0); 1570088#L977-1 assume !(0 == ~E_3~0); 1570089#L982-1 assume !(0 == ~E_4~0); 1569173#L987-1 assume !(0 == ~E_5~0); 1569174#L992-1 assume !(0 == ~E_6~0); 1569180#L997-1 assume !(0 == ~E_7~0); 1569635#L1002-1 assume !(0 == ~E_8~0); 1569624#L1007-1 assume !(0 == ~E_9~0); 1568965#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1568966#L443 assume !(1 == ~m_pc~0); 1569934#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1569925#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1569926#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1569341#L1140 assume !(0 != activate_threads_~tmp~1#1); 1569071#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1569072#L462 assume !(1 == ~t1_pc~0); 1569739#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1569740#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1569006#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1569007#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1569566#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1569567#L481 assume !(1 == ~t2_pc~0); 1569333#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1570160#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1570388#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1570387#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1569433#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1569534#L500 assume !(1 == ~t3_pc~0); 1570175#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1570129#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1568972#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1568973#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1568967#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1568968#L519 assume !(1 == ~t4_pc~0); 1569813#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1569533#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1569073#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1569074#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1569380#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1569136#L538 assume !(1 == ~t5_pc~0); 1569137#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1569031#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1569032#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1569319#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1569320#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1569977#L557 assume !(1 == ~t6_pc~0); 1569356#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1569357#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1569451#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1569381#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1569382#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1570287#L576 assume !(1 == ~t7_pc~0); 1569345#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1569346#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1569707#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1570335#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1570047#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1569474#L595 assume !(1 == ~t8_pc~0); 1569475#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1570071#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1569984#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1569858#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1569859#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1569269#L614 assume !(1 == ~t9_pc~0); 1569270#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1569162#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1569163#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1569508#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1569436#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1569437#L1025 assume !(1 == ~M_E~0); 1569733#L1025-2 assume !(1 == ~T1_E~0); 1569801#L1030-1 assume !(1 == ~T2_E~0); 1569969#L1035-1 assume !(1 == ~T3_E~0); 1569426#L1040-1 assume !(1 == ~T4_E~0); 1569427#L1045-1 assume !(1 == ~T5_E~0); 1569329#L1050-1 assume !(1 == ~T6_E~0); 1569330#L1055-1 assume !(1 == ~T7_E~0); 1569147#L1060-1 assume !(1 == ~T8_E~0); 1569148#L1065-1 assume !(1 == ~T9_E~0); 1569214#L1070-1 assume !(1 == ~E_1~0); 1569917#L1075-1 assume !(1 == ~E_2~0); 1569918#L1080-1 assume !(1 == ~E_3~0); 1569904#L1085-1 assume !(1 == ~E_4~0); 1569905#L1090-1 assume !(1 == ~E_5~0); 1570218#L1095-1 assume !(1 == ~E_6~0); 1569947#L1100-1 assume !(1 == ~E_7~0); 1569948#L1105-1 assume !(1 == ~E_8~0); 1569118#L1110-1 assume !(1 == ~E_9~0); 1569119#L1115-1 assume { :end_inline_reset_delta_events } true; 1569482#L1396-2 [2023-11-29 04:12:12,504 INFO L750 eck$LassoCheckResult]: Loop: 1569482#L1396-2 assume !false; 1574242#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1574233#L897-1 assume !false; 1574227#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1573633#L699 assume !(0 == ~m_st~0); 1573625#L703 assume !(0 == ~t1_st~0); 1573626#L707 assume !(0 == ~t2_st~0); 1573630#L711 assume !(0 == ~t3_st~0); 1573623#L715 assume !(0 == ~t4_st~0); 1573624#L719 assume !(0 == ~t5_st~0); 1573629#L723 assume !(0 == ~t6_st~0); 1573632#L727 assume !(0 == ~t7_st~0); 1573627#L731 assume !(0 == ~t8_st~0); 1573628#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1573631#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1575131#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1575129#L766 assume !(0 != eval_~tmp~0#1); 1575127#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1575125#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1575122#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1575120#L922-5 assume !(0 == ~T1_E~0); 1575118#L927-3 assume !(0 == ~T2_E~0); 1575116#L932-3 assume !(0 == ~T3_E~0); 1575114#L937-3 assume !(0 == ~T4_E~0); 1575112#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1575110#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1575108#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1575106#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1575104#L962-3 assume !(0 == ~T9_E~0); 1575102#L967-3 assume !(0 == ~E_1~0); 1575100#L972-3 assume !(0 == ~E_2~0); 1575098#L977-3 assume !(0 == ~E_3~0); 1575096#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1575095#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1575089#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1575086#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1575083#L1002-3 assume !(0 == ~E_8~0); 1575081#L1007-3 assume !(0 == ~E_9~0); 1575079#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1575077#L443-30 assume 1 == ~m_pc~0; 1575074#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1575072#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1575070#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1575068#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1575066#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1575064#L462-30 assume !(1 == ~t1_pc~0); 1575062#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1575060#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1575057#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1575055#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 1575053#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1575052#L481-30 assume 1 == ~t2_pc~0; 1575050#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 1575048#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1575046#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1575043#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1575040#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1575037#L500-30 assume !(1 == ~t3_pc~0); 1575033#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1575030#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1575028#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1575026#L1164-30 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1575024#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1575022#L519-30 assume !(1 == ~t4_pc~0); 1575020#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1575017#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1575014#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1575012#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1575008#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1575005#L538-30 assume 1 == ~t5_pc~0; 1575001#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1574994#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1574988#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1574983#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1574978#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1574974#L557-30 assume !(1 == ~t6_pc~0); 1574970#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1574966#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1574962#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1574958#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1574954#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1574950#L576-30 assume 1 == ~t7_pc~0; 1574945#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1574937#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1574932#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1574927#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1574922#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1574917#L595-30 assume !(1 == ~t8_pc~0); 1574913#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1574909#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1574904#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1574900#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1574896#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1574892#L614-30 assume !(1 == ~t9_pc~0); 1574886#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1574882#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1574878#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1574874#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1574870#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1574866#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1574860#L1025-5 assume !(1 == ~T1_E~0); 1574855#L1030-3 assume !(1 == ~T2_E~0); 1574849#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1574843#L1040-3 assume !(1 == ~T4_E~0); 1574837#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1574831#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1574826#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1574822#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1574817#L1065-3 assume !(1 == ~T9_E~0); 1574813#L1070-3 assume !(1 == ~E_1~0); 1574808#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1574804#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1574800#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1574795#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1574790#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1574786#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1574782#L1105-3 assume !(1 == ~E_8~0); 1574778#L1110-3 assume !(1 == ~E_9~0); 1574774#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1574755#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1574743#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1574742#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1574584#L1415 assume !(0 == start_simulation_~tmp~3#1); 1574581#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1574301#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1574294#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1574290#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1574288#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1574286#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1574285#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1574282#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1569482#L1396-2 [2023-11-29 04:12:12,504 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:12,504 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 7 times [2023-11-29 04:12:12,505 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:12,505 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1157891429] [2023-11-29 04:12:12,505 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:12,505 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:12,521 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:12,521 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:12,530 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:12,557 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:12,557 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:12,558 INFO L85 PathProgramCache]: Analyzing trace with hash 1825226542, now seen corresponding path program 1 times [2023-11-29 04:12:12,558 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:12,558 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [871876304] [2023-11-29 04:12:12,558 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:12,559 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:12,578 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:12,641 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:12,642 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:12,642 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [871876304] [2023-11-29 04:12:12,642 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [871876304] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:12,642 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:12,642 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:12,642 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1865300197] [2023-11-29 04:12:12,642 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:12,643 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:12,643 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:12,643 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:12:12,643 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:12:12,643 INFO L87 Difference]: Start difference. First operand 37678 states and 51383 transitions. cyclomatic complexity: 13737 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:13,022 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:13,022 INFO L93 Difference]: Finished difference Result 66106 states and 89254 transitions. [2023-11-29 04:12:13,022 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 66106 states and 89254 transitions. [2023-11-29 04:12:13,257 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 65692 [2023-11-29 04:12:13,402 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 66106 states to 66106 states and 89254 transitions. [2023-11-29 04:12:13,402 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 66106 [2023-11-29 04:12:13,434 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 66106 [2023-11-29 04:12:13,434 INFO L73 IsDeterministic]: Start isDeterministic. Operand 66106 states and 89254 transitions. [2023-11-29 04:12:13,463 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:13,464 INFO L218 hiAutomatonCegarLoop]: Abstraction has 66106 states and 89254 transitions. [2023-11-29 04:12:13,496 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 66106 states and 89254 transitions. [2023-11-29 04:12:13,811 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 66106 to 38290. [2023-11-29 04:12:13,832 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 38290 states, 38290 states have (on average 1.353199268738574) internal successors, (51814), 38289 states have internal predecessors, (51814), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:13,902 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 38290 states to 38290 states and 51814 transitions. [2023-11-29 04:12:13,902 INFO L240 hiAutomatonCegarLoop]: Abstraction has 38290 states and 51814 transitions. [2023-11-29 04:12:13,902 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:12:13,903 INFO L428 stractBuchiCegarLoop]: Abstraction has 38290 states and 51814 transitions. [2023-11-29 04:12:13,903 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-29 04:12:13,903 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 38290 states and 51814 transitions. [2023-11-29 04:12:14,008 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 37964 [2023-11-29 04:12:14,008 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:14,008 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:14,009 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:14,010 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:14,010 INFO L748 eck$LassoCheckResult]: Stem: 1673034#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1673035#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1673939#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1673940#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1673862#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1673863#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1673834#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1673590#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1673591#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1673370#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1673371#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1673977#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1673820#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1673440#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1673193#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1673194#L922 assume !(0 == ~M_E~0); 1674066#L922-2 assume !(0 == ~T1_E~0); 1674067#L927-1 assume !(0 == ~T2_E~0); 1673669#L932-1 assume !(0 == ~T3_E~0); 1673521#L937-1 assume !(0 == ~T4_E~0); 1673522#L942-1 assume !(0 == ~T5_E~0); 1673589#L947-1 assume !(0 == ~T6_E~0); 1673674#L952-1 assume !(0 == ~T7_E~0); 1673675#L957-1 assume !(0 == ~T8_E~0); 1673758#L962-1 assume !(0 == ~T9_E~0); 1673495#L967-1 assume !(0 == ~E_1~0); 1673496#L972-1 assume !(0 == ~E_2~0); 1673842#L977-1 assume !(0 == ~E_3~0); 1673843#L982-1 assume !(0 == ~E_4~0); 1672967#L987-1 assume !(0 == ~E_5~0); 1672968#L992-1 assume !(0 == ~E_6~0); 1672974#L997-1 assume !(0 == ~E_7~0); 1673413#L1002-1 assume !(0 == ~E_8~0); 1673401#L1007-1 assume !(0 == ~E_9~0); 1672761#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1672762#L443 assume !(1 == ~m_pc~0); 1673694#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1673682#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1673683#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1673129#L1140 assume !(0 != activate_threads_~tmp~1#1); 1672866#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1672867#L462 assume !(1 == ~t1_pc~0); 1673509#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1673510#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1672802#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1672803#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1673346#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1673347#L481 assume !(1 == ~t2_pc~0); 1673123#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1673913#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1674096#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1674095#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1673217#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1673316#L500 assume !(1 == ~t3_pc~0); 1673928#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1673885#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1672768#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1672769#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1672763#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1672764#L519 assume !(1 == ~t4_pc~0); 1673578#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1673315#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1672868#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1672869#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1673165#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1672930#L538 assume !(1 == ~t5_pc~0); 1672931#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1672827#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1672828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1673109#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1673110#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1673738#L557 assume !(1 == ~t6_pc~0); 1673144#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1673145#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1673234#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1673166#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1673167#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1674023#L576 assume !(1 == ~t7_pc~0); 1673133#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1673134#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1673481#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1674061#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1673810#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1673254#L595 assume !(1 == ~t8_pc~0); 1673255#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1673830#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1673745#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1673618#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1673619#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1673059#L614 assume !(1 == ~t9_pc~0); 1673060#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1672955#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1672956#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1673292#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1673219#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1673220#L1025 assume !(1 == ~M_E~0); 1673503#L1025-2 assume !(1 == ~T1_E~0); 1673569#L1030-1 assume !(1 == ~T2_E~0); 1673727#L1035-1 assume !(1 == ~T3_E~0); 1673211#L1040-1 assume !(1 == ~T4_E~0); 1673212#L1045-1 assume !(1 == ~T5_E~0); 1673119#L1050-1 assume !(1 == ~T6_E~0); 1673120#L1055-1 assume !(1 == ~T7_E~0); 1672941#L1060-1 assume !(1 == ~T8_E~0); 1672942#L1065-1 assume !(1 == ~T9_E~0); 1673007#L1070-1 assume !(1 == ~E_1~0); 1673676#L1075-1 assume !(1 == ~E_2~0); 1673677#L1080-1 assume !(1 == ~E_3~0); 1673663#L1085-1 assume !(1 == ~E_4~0); 1673664#L1090-1 assume !(1 == ~E_5~0); 1673968#L1095-1 assume !(1 == ~E_6~0); 1673704#L1100-1 assume !(1 == ~E_7~0); 1673705#L1105-1 assume !(1 == ~E_8~0); 1672913#L1110-1 assume !(1 == ~E_9~0); 1672914#L1115-1 assume { :end_inline_reset_delta_events } true; 1673263#L1396-2 [2023-11-29 04:12:14,010 INFO L750 eck$LassoCheckResult]: Loop: 1673263#L1396-2 assume !false; 1682599#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1682595#L897-1 assume !false; 1682593#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1682118#L699 assume !(0 == ~m_st~0); 1682110#L703 assume !(0 == ~t1_st~0); 1682111#L707 assume !(0 == ~t2_st~0); 1682115#L711 assume !(0 == ~t3_st~0); 1682108#L715 assume !(0 == ~t4_st~0); 1682109#L719 assume !(0 == ~t5_st~0); 1682114#L723 assume !(0 == ~t6_st~0); 1682117#L727 assume !(0 == ~t7_st~0); 1682112#L731 assume !(0 == ~t8_st~0); 1682113#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1682116#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1681956#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1681957#L766 assume !(0 != eval_~tmp~0#1); 1684178#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1684174#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1684170#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1684165#L922-5 assume !(0 == ~T1_E~0); 1684161#L927-3 assume !(0 == ~T2_E~0); 1684157#L932-3 assume !(0 == ~T3_E~0); 1684154#L937-3 assume !(0 == ~T4_E~0); 1684151#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1684147#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1684143#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1684139#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1684135#L962-3 assume !(0 == ~T9_E~0); 1684131#L967-3 assume !(0 == ~E_1~0); 1684127#L972-3 assume !(0 == ~E_2~0); 1684122#L977-3 assume !(0 == ~E_3~0); 1684117#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1684112#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1684100#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1684088#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1684085#L1002-3 assume !(0 == ~E_8~0); 1684083#L1007-3 assume !(0 == ~E_9~0); 1684081#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1684079#L443-30 assume !(1 == ~m_pc~0); 1684075#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1684069#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1684064#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1684057#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1684050#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1684042#L462-30 assume !(1 == ~t1_pc~0); 1684036#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1684029#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1684025#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1684020#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 1684015#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1684010#L481-30 assume !(1 == ~t2_pc~0); 1684003#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1683996#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1683989#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1683983#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1683978#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1683972#L500-30 assume !(1 == ~t3_pc~0); 1683966#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1683960#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1683954#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1683948#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 1683942#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1683935#L519-30 assume !(1 == ~t4_pc~0); 1683930#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1683925#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1683919#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1683912#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1683906#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1683681#L538-30 assume !(1 == ~t5_pc~0); 1683676#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 1683674#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1683672#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1683670#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 1683665#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1683663#L557-30 assume !(1 == ~t6_pc~0); 1683661#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1683659#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1683656#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1683654#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1683652#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1683650#L576-30 assume 1 == ~t7_pc~0; 1683647#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1683645#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1683643#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1683641#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1683639#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1683636#L595-30 assume !(1 == ~t8_pc~0); 1683634#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1683632#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1683630#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1683628#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1683626#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1683624#L614-30 assume !(1 == ~t9_pc~0); 1683621#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1683619#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1683617#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1683615#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1683612#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1683610#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1683608#L1025-5 assume !(1 == ~T1_E~0); 1683606#L1030-3 assume !(1 == ~T2_E~0); 1683604#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1683602#L1040-3 assume !(1 == ~T4_E~0); 1683600#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1683598#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1683596#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1683594#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1683592#L1065-3 assume !(1 == ~T9_E~0); 1683590#L1070-3 assume !(1 == ~E_1~0); 1683588#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1683586#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1683584#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1683582#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1683580#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1683578#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1683576#L1105-3 assume !(1 == ~E_8~0); 1683574#L1110-3 assume !(1 == ~E_9~0); 1683572#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1683569#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1683558#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1683556#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1683544#L1415 assume !(0 == start_simulation_~tmp~3#1); 1683534#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1683068#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1683060#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1683058#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1683056#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1683054#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1682874#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1682871#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1673263#L1396-2 [2023-11-29 04:12:14,011 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:14,011 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 8 times [2023-11-29 04:12:14,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:14,011 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1054517918] [2023-11-29 04:12:14,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:14,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:14,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:14,026 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:14,035 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:14,061 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:14,061 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:14,061 INFO L85 PathProgramCache]: Analyzing trace with hash -994766715, now seen corresponding path program 1 times [2023-11-29 04:12:14,062 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:14,062 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2135167064] [2023-11-29 04:12:14,062 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:14,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:14,077 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:14,154 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:14,154 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:14,154 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2135167064] [2023-11-29 04:12:14,155 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2135167064] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:14,155 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:14,155 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:14,155 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1045605996] [2023-11-29 04:12:14,155 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:14,156 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:14,156 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:14,156 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:12:14,156 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:12:14,157 INFO L87 Difference]: Start difference. First operand 38290 states and 51814 transitions. cyclomatic complexity: 13556 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:14,684 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:14,685 INFO L93 Difference]: Finished difference Result 102347 states and 135761 transitions. [2023-11-29 04:12:14,685 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 102347 states and 135761 transitions. [2023-11-29 04:12:15,073 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 101668 [2023-11-29 04:12:15,349 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 102347 states to 102347 states and 135761 transitions. [2023-11-29 04:12:15,350 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 102347 [2023-11-29 04:12:15,402 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 102347 [2023-11-29 04:12:15,402 INFO L73 IsDeterministic]: Start isDeterministic. Operand 102347 states and 135761 transitions. [2023-11-29 04:12:15,447 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:15,447 INFO L218 hiAutomatonCegarLoop]: Abstraction has 102347 states and 135761 transitions. [2023-11-29 04:12:15,498 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 102347 states and 135761 transitions. [2023-11-29 04:12:15,889 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 102347 to 39445. [2023-11-29 04:12:15,911 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 39445 states, 39445 states have (on average 1.3428571428571427) internal successors, (52969), 39444 states have internal predecessors, (52969), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:15,983 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 39445 states to 39445 states and 52969 transitions. [2023-11-29 04:12:15,983 INFO L240 hiAutomatonCegarLoop]: Abstraction has 39445 states and 52969 transitions. [2023-11-29 04:12:15,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:12:15,984 INFO L428 stractBuchiCegarLoop]: Abstraction has 39445 states and 52969 transitions. [2023-11-29 04:12:15,984 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2023-11-29 04:12:15,984 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 39445 states and 52969 transitions. [2023-11-29 04:12:16,083 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 39116 [2023-11-29 04:12:16,083 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:16,083 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:16,085 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:16,085 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:16,085 INFO L748 eck$LassoCheckResult]: Stem: 1813684#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1813685#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1814578#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1814579#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1814511#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1814512#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1814489#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1814243#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1814244#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1814026#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1814027#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1814614#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1814472#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1814096#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1813843#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1813844#L922 assume !(0 == ~M_E~0); 1814693#L922-2 assume !(0 == ~T1_E~0); 1814694#L927-1 assume !(0 == ~T2_E~0); 1814325#L932-1 assume !(0 == ~T3_E~0); 1814174#L937-1 assume !(0 == ~T4_E~0); 1814175#L942-1 assume !(0 == ~T5_E~0); 1814242#L947-1 assume !(0 == ~T6_E~0); 1814330#L952-1 assume !(0 == ~T7_E~0); 1814331#L957-1 assume !(0 == ~T8_E~0); 1814411#L962-1 assume !(0 == ~T9_E~0); 1814146#L967-1 assume !(0 == ~E_1~0); 1814147#L972-1 assume !(0 == ~E_2~0); 1814494#L977-1 assume !(0 == ~E_3~0); 1814495#L982-1 assume !(0 == ~E_4~0); 1813617#L987-1 assume !(0 == ~E_5~0); 1813618#L992-1 assume !(0 == ~E_6~0); 1813624#L997-1 assume !(0 == ~E_7~0); 1814069#L1002-1 assume !(0 == ~E_8~0); 1814054#L1007-1 assume !(0 == ~E_9~0); 1813410#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1813411#L443 assume !(1 == ~m_pc~0); 1814348#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1814338#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1814339#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1813780#L1140 assume !(0 != activate_threads_~tmp~1#1); 1813516#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1813517#L462 assume !(1 == ~t1_pc~0); 1814164#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1814165#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1813451#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1813452#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1814003#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1814004#L481 assume !(1 == ~t2_pc~0); 1813773#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1814555#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1814714#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1814712#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1813867#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1813972#L500 assume !(1 == ~t3_pc~0); 1814568#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1814529#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1813417#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1813418#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1813412#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1813413#L519 assume !(1 == ~t4_pc~0); 1814230#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1813971#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1813518#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1813519#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1813815#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1813581#L538 assume !(1 == ~t5_pc~0); 1813582#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1813476#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1813477#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1813759#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1813760#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1814390#L557 assume !(1 == ~t6_pc~0); 1813794#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1813795#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1813885#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1813816#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1813817#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1814662#L576 assume !(1 == ~t7_pc~0); 1813784#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1813785#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1814133#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1814689#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1814465#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1813906#L595 assume !(1 == ~t8_pc~0); 1813907#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1814484#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1814397#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1814272#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1814273#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1813708#L614 assume !(1 == ~t9_pc~0); 1813709#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1813606#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1813607#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1813947#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1813869#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1813870#L1025 assume !(1 == ~M_E~0); 1814155#L1025-2 assume !(1 == ~T1_E~0); 1814221#L1030-1 assume !(1 == ~T2_E~0); 1814381#L1035-1 assume !(1 == ~T3_E~0); 1813861#L1040-1 assume !(1 == ~T4_E~0); 1813862#L1045-1 assume !(1 == ~T5_E~0); 1813769#L1050-1 assume !(1 == ~T6_E~0); 1813770#L1055-1 assume !(1 == ~T7_E~0); 1813592#L1060-1 assume !(1 == ~T8_E~0); 1813593#L1065-1 assume !(1 == ~T9_E~0); 1813657#L1070-1 assume !(1 == ~E_1~0); 1814332#L1075-1 assume !(1 == ~E_2~0); 1814333#L1080-1 assume !(1 == ~E_3~0); 1814319#L1085-1 assume !(1 == ~E_4~0); 1814320#L1090-1 assume !(1 == ~E_5~0); 1814604#L1095-1 assume !(1 == ~E_6~0); 1814361#L1100-1 assume !(1 == ~E_7~0); 1814362#L1105-1 assume !(1 == ~E_8~0); 1813563#L1110-1 assume !(1 == ~E_9~0); 1813564#L1115-1 assume { :end_inline_reset_delta_events } true; 1813916#L1396-2 [2023-11-29 04:12:16,086 INFO L750 eck$LassoCheckResult]: Loop: 1813916#L1396-2 assume !false; 1842201#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1842197#L897-1 assume !false; 1842196#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1842195#L699 assume !(0 == ~m_st~0); 1842187#L703 assume !(0 == ~t1_st~0); 1842188#L707 assume !(0 == ~t2_st~0); 1842192#L711 assume !(0 == ~t3_st~0); 1842185#L715 assume !(0 == ~t4_st~0); 1842186#L719 assume !(0 == ~t5_st~0); 1842191#L723 assume !(0 == ~t6_st~0); 1842194#L727 assume !(0 == ~t7_st~0); 1842189#L731 assume !(0 == ~t8_st~0); 1842190#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1842193#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1841171#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1841172#L766 assume !(0 != eval_~tmp~0#1); 1842630#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1842629#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1842628#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1842627#L922-5 assume !(0 == ~T1_E~0); 1842626#L927-3 assume !(0 == ~T2_E~0); 1842625#L932-3 assume !(0 == ~T3_E~0); 1842624#L937-3 assume !(0 == ~T4_E~0); 1842623#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1842622#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1842621#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1842620#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1842619#L962-3 assume !(0 == ~T9_E~0); 1842618#L967-3 assume !(0 == ~E_1~0); 1842617#L972-3 assume !(0 == ~E_2~0); 1842616#L977-3 assume !(0 == ~E_3~0); 1842615#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1842614#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1842613#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1842612#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1842611#L1002-3 assume !(0 == ~E_8~0); 1842610#L1007-3 assume !(0 == ~E_9~0); 1842609#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1842608#L443-30 assume 1 == ~m_pc~0; 1842606#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1842604#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1842602#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1842600#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 1842597#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1842594#L462-30 assume !(1 == ~t1_pc~0); 1842591#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1842587#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1842583#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1842579#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 1842575#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1842572#L481-30 assume !(1 == ~t2_pc~0); 1842568#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1842564#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1842560#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1842556#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1842553#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1842550#L500-30 assume !(1 == ~t3_pc~0); 1842546#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1842511#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1842505#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1842499#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 1842495#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1842490#L519-30 assume !(1 == ~t4_pc~0); 1842486#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1842481#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1842477#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1842474#L1172-30 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1842470#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1842459#L538-30 assume 1 == ~t5_pc~0; 1842457#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1842458#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1842473#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1842448#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1842446#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1842444#L557-30 assume !(1 == ~t6_pc~0); 1842443#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1842430#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1842423#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1842420#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1842418#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1842416#L576-30 assume 1 == ~t7_pc~0; 1842409#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 1842403#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1842398#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1842391#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1842383#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1842375#L595-30 assume !(1 == ~t8_pc~0); 1842368#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1842361#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1842353#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1842347#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1842341#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1842335#L614-30 assume !(1 == ~t9_pc~0); 1842327#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1842321#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1842315#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1842309#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1842293#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1842292#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1842291#L1025-5 assume !(1 == ~T1_E~0); 1842290#L1030-3 assume !(1 == ~T2_E~0); 1842289#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1842287#L1040-3 assume !(1 == ~T4_E~0); 1842285#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1842283#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1842281#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1842279#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1842277#L1065-3 assume !(1 == ~T9_E~0); 1842275#L1070-3 assume !(1 == ~E_1~0); 1842273#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1842271#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1842269#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1842267#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1842265#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1842263#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1842261#L1105-3 assume !(1 == ~E_8~0); 1842259#L1110-3 assume !(1 == ~E_9~0); 1842257#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1842254#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1842243#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1842241#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1842238#L1415 assume !(0 == start_simulation_~tmp~3#1); 1842237#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1842233#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1842226#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1842224#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1842220#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1842218#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1842215#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1842211#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1813916#L1396-2 [2023-11-29 04:12:16,086 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:16,086 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 9 times [2023-11-29 04:12:16,087 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:16,087 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1303742539] [2023-11-29 04:12:16,087 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:16,087 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:16,101 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:16,101 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:16,109 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:16,131 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:16,132 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:16,132 INFO L85 PathProgramCache]: Analyzing trace with hash -1621691959, now seen corresponding path program 1 times [2023-11-29 04:12:16,132 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:16,132 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [787238977] [2023-11-29 04:12:16,132 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:16,132 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:16,148 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:16,209 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:16,209 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:16,209 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [787238977] [2023-11-29 04:12:16,209 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [787238977] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:16,210 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:16,210 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:16,210 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1946820720] [2023-11-29 04:12:16,210 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:16,210 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:16,211 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:16,211 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:12:16,211 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:12:16,212 INFO L87 Difference]: Start difference. First operand 39445 states and 52969 transitions. cyclomatic complexity: 13556 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:16,591 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:16,591 INFO L93 Difference]: Finished difference Result 67465 states and 89904 transitions. [2023-11-29 04:12:16,591 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 67465 states and 89904 transitions. [2023-11-29 04:12:16,847 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 67060 [2023-11-29 04:12:17,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 67465 states to 67465 states and 89904 transitions. [2023-11-29 04:12:17,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 67465 [2023-11-29 04:12:17,046 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 67465 [2023-11-29 04:12:17,046 INFO L73 IsDeterministic]: Start isDeterministic. Operand 67465 states and 89904 transitions. [2023-11-29 04:12:17,076 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:17,076 INFO L218 hiAutomatonCegarLoop]: Abstraction has 67465 states and 89904 transitions. [2023-11-29 04:12:17,111 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 67465 states and 89904 transitions. [2023-11-29 04:12:17,845 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 67465 to 40057. [2023-11-29 04:12:17,866 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 40057 states, 40057 states have (on average 1.3331003320268617) internal successors, (53400), 40056 states have internal predecessors, (53400), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:17,920 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 40057 states to 40057 states and 53400 transitions. [2023-11-29 04:12:17,920 INFO L240 hiAutomatonCegarLoop]: Abstraction has 40057 states and 53400 transitions. [2023-11-29 04:12:17,921 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:12:17,921 INFO L428 stractBuchiCegarLoop]: Abstraction has 40057 states and 53400 transitions. [2023-11-29 04:12:17,921 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2023-11-29 04:12:17,921 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 40057 states and 53400 transitions. [2023-11-29 04:12:18,006 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 39728 [2023-11-29 04:12:18,006 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:18,006 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:18,007 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:18,007 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:18,007 INFO L748 eck$LassoCheckResult]: Stem: 1920607#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 1920608#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 1921509#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1921510#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1921441#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 1921442#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1921413#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1921174#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1921175#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1920951#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1920952#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1921552#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1921397#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1921026#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1920763#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1920764#L922 assume !(0 == ~M_E~0); 1921645#L922-2 assume !(0 == ~T1_E~0); 1921646#L927-1 assume !(0 == ~T2_E~0); 1921251#L932-1 assume !(0 == ~T3_E~0); 1921105#L937-1 assume !(0 == ~T4_E~0); 1921106#L942-1 assume !(0 == ~T5_E~0); 1921173#L947-1 assume !(0 == ~T6_E~0); 1921256#L952-1 assume !(0 == ~T7_E~0); 1921257#L957-1 assume !(0 == ~T8_E~0); 1921338#L962-1 assume !(0 == ~T9_E~0); 1921081#L967-1 assume !(0 == ~E_1~0); 1921082#L972-1 assume !(0 == ~E_2~0); 1921424#L977-1 assume !(0 == ~E_3~0); 1921425#L982-1 assume !(0 == ~E_4~0); 1920538#L987-1 assume !(0 == ~E_5~0); 1920539#L992-1 assume !(0 == ~E_6~0); 1920545#L997-1 assume !(0 == ~E_7~0); 1920997#L1002-1 assume !(0 == ~E_8~0); 1920982#L1007-1 assume !(0 == ~E_9~0); 1920332#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1920333#L443 assume !(1 == ~m_pc~0); 1921279#L443-2 is_master_triggered_~__retres1~0#1 := 0; 1921265#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1921266#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1920698#L1140 assume !(0 != activate_threads_~tmp~1#1); 1920439#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1920440#L462 assume !(1 == ~t1_pc~0); 1921095#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1921096#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1920373#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1920374#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 1920925#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1920926#L481 assume !(1 == ~t2_pc~0); 1920692#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1921484#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1921684#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1921683#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 1920787#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1920894#L500 assume !(1 == ~t3_pc~0); 1921497#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1921459#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1920339#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1920340#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 1920334#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1920335#L519 assume !(1 == ~t4_pc~0); 1921160#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1920893#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1920437#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1920438#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 1920738#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1920501#L538 assume !(1 == ~t5_pc~0); 1920502#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1920398#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1920399#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1920679#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 1920680#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1921319#L557 assume !(1 == ~t6_pc~0); 1920713#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1920714#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1920805#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1920736#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 1920737#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1921604#L576 assume !(1 == ~t7_pc~0); 1920702#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1920703#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1921067#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1921639#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 1921387#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1920828#L595 assume !(1 == ~t8_pc~0); 1920829#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1921408#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1921325#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1921203#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 1921204#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1920631#L614 assume !(1 == ~t9_pc~0); 1920632#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1920526#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1920527#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1920871#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 1920789#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1920790#L1025 assume !(1 == ~M_E~0); 1921089#L1025-2 assume !(1 == ~T1_E~0); 1921153#L1030-1 assume !(1 == ~T2_E~0); 1921310#L1035-1 assume !(1 == ~T3_E~0); 1920781#L1040-1 assume !(1 == ~T4_E~0); 1920782#L1045-1 assume !(1 == ~T5_E~0); 1920688#L1050-1 assume !(1 == ~T6_E~0); 1920689#L1055-1 assume !(1 == ~T7_E~0); 1920512#L1060-1 assume !(1 == ~T8_E~0); 1920513#L1065-1 assume !(1 == ~T9_E~0); 1920578#L1070-1 assume !(1 == ~E_1~0); 1921258#L1075-1 assume !(1 == ~E_2~0); 1921259#L1080-1 assume !(1 == ~E_3~0); 1921245#L1085-1 assume !(1 == ~E_4~0); 1921246#L1090-1 assume !(1 == ~E_5~0); 1921544#L1095-1 assume !(1 == ~E_6~0); 1921292#L1100-1 assume !(1 == ~E_7~0); 1921293#L1105-1 assume !(1 == ~E_8~0); 1920483#L1110-1 assume !(1 == ~E_9~0); 1920484#L1115-1 assume { :end_inline_reset_delta_events } true; 1920839#L1396-2 [2023-11-29 04:12:18,007 INFO L750 eck$LassoCheckResult]: Loop: 1920839#L1396-2 assume !false; 1933273#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1933267#L897-1 assume !false; 1933266#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1933203#L699 assume !(0 == ~m_st~0); 1933196#L703 assume !(0 == ~t1_st~0); 1933197#L707 assume !(0 == ~t2_st~0); 1933201#L711 assume !(0 == ~t3_st~0); 1933193#L715 assume !(0 == ~t4_st~0); 1933195#L719 assume !(0 == ~t5_st~0); 1933200#L723 assume !(0 == ~t6_st~0); 1933202#L727 assume !(0 == ~t7_st~0); 1933198#L731 assume !(0 == ~t8_st~0); 1933199#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 1933141#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1933142#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1934627#L766 assume !(0 != eval_~tmp~0#1); 1934625#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1934623#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1934621#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 1934618#L922-5 assume !(0 == ~T1_E~0); 1934616#L927-3 assume !(0 == ~T2_E~0); 1934614#L932-3 assume !(0 == ~T3_E~0); 1934459#L937-3 assume !(0 == ~T4_E~0); 1934456#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1934303#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1934299#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1934297#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 1934295#L962-3 assume !(0 == ~T9_E~0); 1934293#L967-3 assume !(0 == ~E_1~0); 1934290#L972-3 assume !(0 == ~E_2~0); 1934288#L977-3 assume !(0 == ~E_3~0); 1934286#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1934284#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1934282#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 1934280#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1934278#L1002-3 assume !(0 == ~E_8~0); 1934276#L1007-3 assume !(0 == ~E_9~0); 1934274#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1934272#L443-30 assume !(1 == ~m_pc~0); 1934268#L443-32 is_master_triggered_~__retres1~0#1 := 0; 1934266#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1934264#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 1934262#L1140-30 assume !(0 != activate_threads_~tmp~1#1); 1934259#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1934256#L462-30 assume !(1 == ~t1_pc~0); 1934254#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 1934252#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1934249#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1934247#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 1934245#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1934243#L481-30 assume !(1 == ~t2_pc~0); 1934241#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 1934581#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1934578#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1934233#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 1934231#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1934230#L500-30 assume !(1 == ~t3_pc~0); 1934229#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 1934227#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1934226#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1934225#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 1934224#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1934223#L519-30 assume !(1 == ~t4_pc~0); 1934213#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 1934205#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1934197#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1934188#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 1933923#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1933919#L538-30 assume 1 == ~t5_pc~0; 1933917#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1933918#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1934106#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1933903#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1933902#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1933807#L557-30 assume !(1 == ~t6_pc~0); 1933801#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 1933794#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1933786#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1933778#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1933770#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1933763#L576-30 assume !(1 == ~t7_pc~0); 1933755#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 1933747#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1933741#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1933734#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1933728#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1933722#L595-30 assume !(1 == ~t8_pc~0); 1933715#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 1933710#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1933705#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1933700#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1933668#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1933661#L614-30 assume !(1 == ~t9_pc~0); 1933655#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 1933649#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1933643#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1933637#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 1933631#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1933626#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1933621#L1025-5 assume !(1 == ~T1_E~0); 1933615#L1030-3 assume !(1 == ~T2_E~0); 1933608#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 1933602#L1040-3 assume !(1 == ~T4_E~0); 1933596#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1933589#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1933583#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1933576#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1933570#L1065-3 assume !(1 == ~T9_E~0); 1933565#L1070-3 assume !(1 == ~E_1~0); 1933560#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1933553#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1933547#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1933513#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1933485#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1933479#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1933474#L1105-3 assume !(1 == ~E_8~0); 1933469#L1110-3 assume !(1 == ~E_9~0); 1933462#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1933426#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1933411#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1933404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 1933398#L1415 assume !(0 == start_simulation_~tmp~3#1); 1933395#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 1933379#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 1933365#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 1933332#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 1933328#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1933310#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1933309#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 1933292#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 1920839#L1396-2 [2023-11-29 04:12:18,008 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:18,008 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 10 times [2023-11-29 04:12:18,008 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:18,008 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [283418369] [2023-11-29 04:12:18,008 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:18,008 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:18,019 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:18,020 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:18,026 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:18,048 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:18,048 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:18,048 INFO L85 PathProgramCache]: Analyzing trace with hash -1732678077, now seen corresponding path program 1 times [2023-11-29 04:12:18,048 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:18,049 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [654484041] [2023-11-29 04:12:18,049 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:18,049 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:18,059 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:18,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:18,085 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:18,085 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [654484041] [2023-11-29 04:12:18,085 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [654484041] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:18,085 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:18,086 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:18,086 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3270612] [2023-11-29 04:12:18,086 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:18,086 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:18,086 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:18,086 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:12:18,087 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:12:18,087 INFO L87 Difference]: Start difference. First operand 40057 states and 53400 transitions. cyclomatic complexity: 13375 Second operand has 3 states, 3 states have (on average 43.666666666666664) internal successors, (131), 3 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:18,268 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:18,268 INFO L93 Difference]: Finished difference Result 76625 states and 101092 transitions. [2023-11-29 04:12:18,268 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 76625 states and 101092 transitions. [2023-11-29 04:12:18,496 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 76096 [2023-11-29 04:12:19,113 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 76625 states to 76625 states and 101092 transitions. [2023-11-29 04:12:19,114 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 76625 [2023-11-29 04:12:19,141 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 76625 [2023-11-29 04:12:19,141 INFO L73 IsDeterministic]: Start isDeterministic. Operand 76625 states and 101092 transitions. [2023-11-29 04:12:19,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:19,170 INFO L218 hiAutomatonCegarLoop]: Abstraction has 76625 states and 101092 transitions. [2023-11-29 04:12:19,197 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 76625 states and 101092 transitions. [2023-11-29 04:12:19,536 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 76625 to 73017. [2023-11-29 04:12:19,572 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 73017 states, 73017 states have (on average 1.3222674171768218) internal successors, (96548), 73016 states have internal predecessors, (96548), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:19,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 73017 states to 73017 states and 96548 transitions. [2023-11-29 04:12:19,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 73017 states and 96548 transitions. [2023-11-29 04:12:19,675 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:12:19,676 INFO L428 stractBuchiCegarLoop]: Abstraction has 73017 states and 96548 transitions. [2023-11-29 04:12:19,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2023-11-29 04:12:19,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 73017 states and 96548 transitions. [2023-11-29 04:12:20,087 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 72488 [2023-11-29 04:12:20,087 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:20,087 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:20,089 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:20,089 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:20,089 INFO L748 eck$LassoCheckResult]: Stem: 2037295#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2037296#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2038181#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2038182#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2038112#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2038113#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2038083#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2037845#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2037846#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2037632#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2037633#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2038219#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2038071#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2037702#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2037451#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2037452#L922 assume !(0 == ~M_E~0); 2038313#L922-2 assume !(0 == ~T1_E~0); 2038314#L927-1 assume !(0 == ~T2_E~0); 2037920#L932-1 assume !(0 == ~T3_E~0); 2037779#L937-1 assume !(0 == ~T4_E~0); 2037780#L942-1 assume !(0 == ~T5_E~0); 2037844#L947-1 assume !(0 == ~T6_E~0); 2037925#L952-1 assume !(0 == ~T7_E~0); 2037926#L957-1 assume !(0 == ~T8_E~0); 2038013#L962-1 assume !(0 == ~T9_E~0); 2037756#L967-1 assume !(0 == ~E_1~0); 2037757#L972-1 assume !(0 == ~E_2~0); 2038095#L977-1 assume !(0 == ~E_3~0); 2038096#L982-1 assume !(0 == ~E_4~0); 2037227#L987-1 assume !(0 == ~E_5~0); 2037228#L992-1 assume !(0 == ~E_6~0); 2037232#L997-1 assume !(0 == ~E_7~0); 2037676#L1002-1 assume !(0 == ~E_8~0); 2037660#L1007-1 assume !(0 == ~E_9~0); 2037020#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2037021#L443 assume !(1 == ~m_pc~0); 2037946#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2037936#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2037937#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2037386#L1140 assume !(0 != activate_threads_~tmp~1#1); 2037125#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2037126#L462 assume !(1 == ~t1_pc~0); 2037773#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2037774#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2037063#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2037064#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2037610#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2037611#L481 assume !(1 == ~t2_pc~0); 2037380#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2038158#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2038342#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2038340#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2037474#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2037580#L500 assume !(1 == ~t3_pc~0); 2038171#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2038130#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2037027#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2037028#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2037025#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2037026#L519 assume !(1 == ~t4_pc~0); 2037834#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2037577#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2037127#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2037128#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2037426#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2037188#L538 assume !(1 == ~t5_pc~0); 2037189#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2037088#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2037089#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2037366#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2037367#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2037992#L557 assume !(1 == ~t6_pc~0); 2037400#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2037401#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2037492#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2037424#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2037425#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2038269#L576 assume !(1 == ~t7_pc~0); 2037390#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2037391#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2037740#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2038306#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2038060#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2037516#L595 assume !(1 == ~t8_pc~0); 2037517#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2038079#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2037997#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2037873#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2037874#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2037317#L614 assume !(1 == ~t9_pc~0); 2037318#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2037214#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2037215#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2037552#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2037476#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2037477#L1025 assume !(1 == ~M_E~0); 2037764#L1025-2 assume !(1 == ~T1_E~0); 2037825#L1030-1 assume !(1 == ~T2_E~0); 2037982#L1035-1 assume !(1 == ~T3_E~0); 2037469#L1040-1 assume !(1 == ~T4_E~0); 2037470#L1045-1 assume !(1 == ~T5_E~0); 2037376#L1050-1 assume !(1 == ~T6_E~0); 2037377#L1055-1 assume !(1 == ~T7_E~0); 2037199#L1060-1 assume !(1 == ~T8_E~0); 2037200#L1065-1 assume !(1 == ~T9_E~0); 2037265#L1070-1 assume !(1 == ~E_1~0); 2037929#L1075-1 assume !(1 == ~E_2~0); 2037930#L1080-1 assume !(1 == ~E_3~0); 2037914#L1085-1 assume !(1 == ~E_4~0); 2037915#L1090-1 assume !(1 == ~E_5~0); 2038211#L1095-1 assume !(1 == ~E_6~0); 2037960#L1100-1 assume !(1 == ~E_7~0); 2037961#L1105-1 assume !(1 == ~E_8~0); 2037171#L1110-1 assume !(1 == ~E_9~0); 2037172#L1115-1 assume { :end_inline_reset_delta_events } true; 2037524#L1396-2 [2023-11-29 04:12:20,090 INFO L750 eck$LassoCheckResult]: Loop: 2037524#L1396-2 assume !false; 2054459#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2054455#L897-1 assume !false; 2054451#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2054448#L699 assume !(0 == ~m_st~0); 2054449#L703 assume !(0 == ~t1_st~0); 2056741#L707 assume !(0 == ~t2_st~0); 2056739#L711 assume !(0 == ~t3_st~0); 2056737#L715 assume !(0 == ~t4_st~0); 2056735#L719 assume !(0 == ~t5_st~0); 2056733#L723 assume !(0 == ~t6_st~0); 2056731#L727 assume !(0 == ~t7_st~0); 2056729#L731 assume !(0 == ~t8_st~0); 2056726#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2056724#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2056722#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2056720#L766 assume !(0 != eval_~tmp~0#1); 2056718#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2056716#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2056714#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2056712#L922-5 assume !(0 == ~T1_E~0); 2056710#L927-3 assume !(0 == ~T2_E~0); 2056708#L932-3 assume !(0 == ~T3_E~0); 2056706#L937-3 assume !(0 == ~T4_E~0); 2056705#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2056704#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2056703#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2056702#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2056701#L962-3 assume !(0 == ~T9_E~0); 2056700#L967-3 assume !(0 == ~E_1~0); 2056699#L972-3 assume !(0 == ~E_2~0); 2056690#L977-3 assume !(0 == ~E_3~0); 2056688#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2056686#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2056683#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2056681#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2056679#L1002-3 assume !(0 == ~E_8~0); 2056676#L1007-3 assume !(0 == ~E_9~0); 2056674#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2056672#L443-30 assume 1 == ~m_pc~0; 2056670#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2056669#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2056667#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2056665#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2056664#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2056663#L462-30 assume !(1 == ~t1_pc~0); 2056659#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2056657#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2056655#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2056653#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 2056648#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2056646#L481-30 assume !(1 == ~t2_pc~0); 2056644#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2057120#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2057118#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2056636#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 2056634#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2056632#L500-30 assume !(1 == ~t3_pc~0); 2056628#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2056626#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2056624#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2056622#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 2056619#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2056617#L519-30 assume !(1 == ~t4_pc~0); 2056615#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2056613#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2056611#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2056609#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 2056607#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2056605#L538-30 assume 1 == ~t5_pc~0; 2056603#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2056604#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2057130#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2056594#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2056592#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2056590#L557-30 assume !(1 == ~t6_pc~0); 2056589#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2056585#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2056583#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2056581#L1188-30 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2056579#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2056576#L576-30 assume !(1 == ~t7_pc~0); 2056574#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2056571#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2056569#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2056567#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2056565#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2056563#L595-30 assume !(1 == ~t8_pc~0); 2056561#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2056559#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2056556#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2056554#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2056552#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2056550#L614-30 assume !(1 == ~t9_pc~0); 2056547#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2056545#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2056543#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2056541#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2056539#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2056537#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2056535#L1025-5 assume !(1 == ~T1_E~0); 2056532#L1030-3 assume !(1 == ~T2_E~0); 2056530#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2056528#L1040-3 assume !(1 == ~T4_E~0); 2056526#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2056524#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2056522#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2056520#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2056518#L1065-3 assume !(1 == ~T9_E~0); 2056516#L1070-3 assume !(1 == ~E_1~0); 2056514#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2056512#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2056510#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2056508#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2056506#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2056504#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2056502#L1105-3 assume !(1 == ~E_8~0); 2056500#L1110-3 assume !(1 == ~E_9~0); 2056498#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2056495#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2056493#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2056491#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2056482#L1415 assume !(0 == start_simulation_~tmp~3#1); 2056480#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2056476#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2056474#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2056473#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2056472#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2054470#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2054467#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2054463#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2037524#L1396-2 [2023-11-29 04:12:20,090 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:20,090 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 11 times [2023-11-29 04:12:20,090 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:20,090 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [811170059] [2023-11-29 04:12:20,090 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:20,090 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:20,100 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:20,100 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:20,106 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:20,121 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:20,122 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:20,122 INFO L85 PathProgramCache]: Analyzing trace with hash 888545382, now seen corresponding path program 1 times [2023-11-29 04:12:20,122 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:20,122 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [87417832] [2023-11-29 04:12:20,122 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:20,122 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:20,135 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:20,188 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:20,188 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:20,188 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [87417832] [2023-11-29 04:12:20,188 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [87417832] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:20,188 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:20,188 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:20,188 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1386227081] [2023-11-29 04:12:20,188 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:20,189 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:20,189 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:20,189 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:12:20,189 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:12:20,189 INFO L87 Difference]: Start difference. First operand 73017 states and 96548 transitions. cyclomatic complexity: 23563 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:20,765 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:20,766 INFO L93 Difference]: Finished difference Result 119017 states and 156471 transitions. [2023-11-29 04:12:20,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 119017 states and 156471 transitions. [2023-11-29 04:12:21,242 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 118336 [2023-11-29 04:12:21,751 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 119017 states to 119017 states and 156471 transitions. [2023-11-29 04:12:21,751 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 119017 [2023-11-29 04:12:21,792 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 119017 [2023-11-29 04:12:21,792 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119017 states and 156471 transitions. [2023-11-29 04:12:21,823 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:21,823 INFO L218 hiAutomatonCegarLoop]: Abstraction has 119017 states and 156471 transitions. [2023-11-29 04:12:21,868 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119017 states and 156471 transitions. [2023-11-29 04:12:22,295 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119017 to 74169. [2023-11-29 04:12:22,334 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 74169 states, 74169 states have (on average 1.312718251560625) internal successors, (97363), 74168 states have internal predecessors, (97363), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:22,438 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 74169 states to 74169 states and 97363 transitions. [2023-11-29 04:12:22,438 INFO L240 hiAutomatonCegarLoop]: Abstraction has 74169 states and 97363 transitions. [2023-11-29 04:12:22,439 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:12:22,439 INFO L428 stractBuchiCegarLoop]: Abstraction has 74169 states and 97363 transitions. [2023-11-29 04:12:22,439 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2023-11-29 04:12:22,439 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 74169 states and 97363 transitions. [2023-11-29 04:12:22,875 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 73640 [2023-11-29 04:12:22,875 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:22,875 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:22,876 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:22,876 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:22,877 INFO L748 eck$LassoCheckResult]: Stem: 2229339#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2229340#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2230231#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2230232#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2230165#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2230166#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2230137#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2229906#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2229907#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2229682#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2229683#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2230273#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2230124#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2229755#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2229503#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2229504#L922 assume !(0 == ~M_E~0); 2230360#L922-2 assume !(0 == ~T1_E~0); 2230361#L927-1 assume !(0 == ~T2_E~0); 2229986#L932-1 assume !(0 == ~T3_E~0); 2229834#L937-1 assume !(0 == ~T4_E~0); 2229835#L942-1 assume !(0 == ~T5_E~0); 2229905#L947-1 assume !(0 == ~T6_E~0); 2229991#L952-1 assume !(0 == ~T7_E~0); 2229992#L957-1 assume !(0 == ~T8_E~0); 2230064#L962-1 assume !(0 == ~T9_E~0); 2229806#L967-1 assume !(0 == ~E_1~0); 2229807#L972-1 assume !(0 == ~E_2~0); 2230145#L977-1 assume !(0 == ~E_3~0); 2230146#L982-1 assume !(0 == ~E_4~0); 2229271#L987-1 assume !(0 == ~E_5~0); 2229272#L992-1 assume !(0 == ~E_6~0); 2229278#L997-1 assume !(0 == ~E_7~0); 2229725#L1002-1 assume !(0 == ~E_8~0); 2229712#L1007-1 assume !(0 == ~E_9~0); 2229066#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2229067#L443 assume !(1 == ~m_pc~0); 2230008#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2229998#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2229999#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2229437#L1140 assume !(0 != activate_threads_~tmp~1#1); 2229171#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2229172#L462 assume !(1 == ~t1_pc~0); 2229823#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2229824#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2229107#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2229108#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2229658#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2229659#L481 assume !(1 == ~t2_pc~0); 2229431#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2230210#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2230386#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2230385#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2229527#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2229627#L500 assume !(1 == ~t3_pc~0); 2230221#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2230185#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2229073#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2229074#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2229068#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2229069#L519 assume !(1 == ~t4_pc~0); 2229893#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2229626#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2229173#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2229174#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2229475#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2229235#L538 assume !(1 == ~t5_pc~0); 2229236#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2229132#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2229133#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2229417#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2229418#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2230046#L557 assume !(1 == ~t6_pc~0); 2229452#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2229453#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2229546#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2229473#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2229474#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2230325#L576 assume !(1 == ~t7_pc~0); 2229441#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2229442#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2229794#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2230355#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2230116#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2229565#L595 assume !(1 == ~t8_pc~0); 2229566#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2230132#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2230052#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2229936#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2229937#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2229367#L614 assume !(1 == ~t9_pc~0); 2229368#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2229260#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2229261#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2229602#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2229529#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2229530#L1025 assume !(1 == ~M_E~0); 2229815#L1025-2 assume !(1 == ~T1_E~0); 2229884#L1030-1 assume !(1 == ~T2_E~0); 2230039#L1035-1 assume !(1 == ~T3_E~0); 2229521#L1040-1 assume !(1 == ~T4_E~0); 2229522#L1045-1 assume !(1 == ~T5_E~0); 2229427#L1050-1 assume !(1 == ~T6_E~0); 2229428#L1055-1 assume !(1 == ~T7_E~0); 2229246#L1060-1 assume !(1 == ~T8_E~0); 2229247#L1065-1 assume !(1 == ~T9_E~0); 2229311#L1070-1 assume !(1 == ~E_1~0); 2229993#L1075-1 assume !(1 == ~E_2~0); 2229994#L1080-1 assume !(1 == ~E_3~0); 2229980#L1085-1 assume !(1 == ~E_4~0); 2229981#L1090-1 assume !(1 == ~E_5~0); 2230259#L1095-1 assume !(1 == ~E_6~0); 2230020#L1100-1 assume !(1 == ~E_7~0); 2230021#L1105-1 assume !(1 == ~E_8~0); 2229217#L1110-1 assume !(1 == ~E_9~0); 2229218#L1115-1 assume { :end_inline_reset_delta_events } true; 2229575#L1396-2 [2023-11-29 04:12:22,877 INFO L750 eck$LassoCheckResult]: Loop: 2229575#L1396-2 assume !false; 2243990#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2243986#L897-1 assume !false; 2243984#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2243981#L699 assume !(0 == ~m_st~0); 2243982#L703 assume !(0 == ~t1_st~0); 2257489#L707 assume !(0 == ~t2_st~0); 2257487#L711 assume !(0 == ~t3_st~0); 2257485#L715 assume !(0 == ~t4_st~0); 2257483#L719 assume !(0 == ~t5_st~0); 2257481#L723 assume !(0 == ~t6_st~0); 2257479#L727 assume !(0 == ~t7_st~0); 2257476#L731 assume !(0 == ~t8_st~0); 2257473#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2257471#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2257469#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2257467#L766 assume !(0 != eval_~tmp~0#1); 2257464#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2257462#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2257460#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2257458#L922-5 assume !(0 == ~T1_E~0); 2257456#L927-3 assume !(0 == ~T2_E~0); 2257454#L932-3 assume !(0 == ~T3_E~0); 2257452#L937-3 assume !(0 == ~T4_E~0); 2257450#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2257448#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2257446#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2257444#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2257442#L962-3 assume !(0 == ~T9_E~0); 2257440#L967-3 assume !(0 == ~E_1~0); 2257438#L972-3 assume !(0 == ~E_2~0); 2257436#L977-3 assume !(0 == ~E_3~0); 2257434#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2257432#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2257430#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2257428#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2257426#L1002-3 assume !(0 == ~E_8~0); 2257424#L1007-3 assume !(0 == ~E_9~0); 2257422#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2257420#L443-30 assume 1 == ~m_pc~0; 2257418#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2257417#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2257415#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2257413#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2257411#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2257410#L462-30 assume !(1 == ~t1_pc~0); 2257407#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2257404#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2257402#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2257400#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 2257399#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2257395#L481-30 assume !(1 == ~t2_pc~0); 2257394#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 2259018#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2259017#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2257379#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 2257377#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2257375#L500-30 assume !(1 == ~t3_pc~0); 2257373#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2257371#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2257369#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2257367#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 2257363#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2257361#L519-30 assume !(1 == ~t4_pc~0); 2257359#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2257358#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2257355#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2257351#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 2257348#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2257345#L538-30 assume !(1 == ~t5_pc~0); 2257339#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2257338#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2257336#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2257334#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 2257332#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2257331#L557-30 assume !(1 == ~t6_pc~0); 2257330#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2257328#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2257326#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2257324#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2257323#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2257320#L576-30 assume !(1 == ~t7_pc~0); 2257318#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2257316#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2247829#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2247825#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2247823#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2247821#L595-30 assume !(1 == ~t8_pc~0); 2247819#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2247814#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2247812#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2247810#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2247808#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2247806#L614-30 assume !(1 == ~t9_pc~0); 2247803#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2247801#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2247799#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2247797#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2247794#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2247792#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2247790#L1025-5 assume !(1 == ~T1_E~0); 2247787#L1030-3 assume !(1 == ~T2_E~0); 2247785#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2247783#L1040-3 assume !(1 == ~T4_E~0); 2247781#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2247779#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2247777#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2247775#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2247773#L1065-3 assume !(1 == ~T9_E~0); 2247771#L1070-3 assume !(1 == ~E_1~0); 2247769#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2247767#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2247765#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2247763#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2247761#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2247759#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2247756#L1105-3 assume !(1 == ~E_8~0); 2247754#L1110-3 assume !(1 == ~E_9~0); 2247752#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2247751#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2247750#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2247748#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2244011#L1415 assume !(0 == start_simulation_~tmp~3#1); 2244009#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2244006#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2244004#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2244002#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2244000#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2243998#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2243996#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2243994#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2229575#L1396-2 [2023-11-29 04:12:22,877 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:22,877 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 12 times [2023-11-29 04:12:22,877 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:22,878 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2080648503] [2023-11-29 04:12:22,878 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:22,878 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:22,887 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:22,888 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:22,893 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:22,914 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:22,915 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:22,915 INFO L85 PathProgramCache]: Analyzing trace with hash 385373121, now seen corresponding path program 1 times [2023-11-29 04:12:22,915 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:22,916 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [155732723] [2023-11-29 04:12:22,916 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:22,916 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:22,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:22,977 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:22,978 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:22,978 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [155732723] [2023-11-29 04:12:22,978 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [155732723] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:22,978 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:22,978 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:22,979 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [165301894] [2023-11-29 04:12:22,979 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:22,979 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:22,979 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:22,980 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:12:22,980 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:12:22,980 INFO L87 Difference]: Start difference. First operand 74169 states and 97363 transitions. cyclomatic complexity: 23226 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:23,456 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:23,456 INFO L93 Difference]: Finished difference Result 157012 states and 204258 transitions. [2023-11-29 04:12:23,456 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 157012 states and 204258 transitions. [2023-11-29 04:12:24,184 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 156032 [2023-11-29 04:12:24,407 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 157012 states to 157012 states and 204258 transitions. [2023-11-29 04:12:24,407 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 157012 [2023-11-29 04:12:24,457 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 157012 [2023-11-29 04:12:24,457 INFO L73 IsDeterministic]: Start isDeterministic. Operand 157012 states and 204258 transitions. [2023-11-29 04:12:24,497 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:24,497 INFO L218 hiAutomatonCegarLoop]: Abstraction has 157012 states and 204258 transitions. [2023-11-29 04:12:24,552 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 157012 states and 204258 transitions. [2023-11-29 04:12:25,326 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 157012 to 76332. [2023-11-29 04:12:25,360 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 76332 states, 76332 states have (on average 1.303856835927265) internal successors, (99526), 76331 states have internal predecessors, (99526), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:25,501 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 76332 states to 76332 states and 99526 transitions. [2023-11-29 04:12:25,501 INFO L240 hiAutomatonCegarLoop]: Abstraction has 76332 states and 99526 transitions. [2023-11-29 04:12:25,502 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:12:25,502 INFO L428 stractBuchiCegarLoop]: Abstraction has 76332 states and 99526 transitions. [2023-11-29 04:12:25,502 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2023-11-29 04:12:25,502 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 76332 states and 99526 transitions. [2023-11-29 04:12:25,704 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 75800 [2023-11-29 04:12:25,705 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:25,705 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:25,706 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:25,706 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:25,706 INFO L748 eck$LassoCheckResult]: Stem: 2460534#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2460535#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2461469#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2461470#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2461393#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2461394#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2461364#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2461110#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2461111#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2460881#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2460882#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2461512#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2461349#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2460953#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2460694#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2460695#L922 assume !(0 == ~M_E~0); 2461611#L922-2 assume !(0 == ~T1_E~0); 2461612#L927-1 assume !(0 == ~T2_E~0); 2461196#L932-1 assume !(0 == ~T3_E~0); 2461035#L937-1 assume !(0 == ~T4_E~0); 2461036#L942-1 assume !(0 == ~T5_E~0); 2461109#L947-1 assume !(0 == ~T6_E~0); 2461201#L952-1 assume !(0 == ~T7_E~0); 2461202#L957-1 assume !(0 == ~T8_E~0); 2461287#L962-1 assume !(0 == ~T9_E~0); 2461010#L967-1 assume !(0 == ~E_1~0); 2461011#L972-1 assume !(0 == ~E_2~0); 2461373#L977-1 assume !(0 == ~E_3~0); 2461374#L982-1 assume !(0 == ~E_4~0); 2460466#L987-1 assume !(0 == ~E_5~0); 2460467#L992-1 assume !(0 == ~E_6~0); 2460471#L997-1 assume !(0 == ~E_7~0); 2460925#L1002-1 assume !(0 == ~E_8~0); 2460910#L1007-1 assume !(0 == ~E_9~0); 2460259#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2460260#L443 assume !(1 == ~m_pc~0); 2461222#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2461211#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2461212#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2460629#L1140 assume !(0 != activate_threads_~tmp~1#1); 2460364#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2460365#L462 assume !(1 == ~t1_pc~0); 2461028#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2461029#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2460302#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2460303#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2460859#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2460860#L481 assume !(1 == ~t2_pc~0); 2460623#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2461443#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2461658#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2461656#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2460718#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2460827#L500 assume !(1 == ~t3_pc~0); 2461458#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2461415#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2460266#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2460267#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2460264#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2460265#L519 assume !(1 == ~t4_pc~0); 2461095#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2460824#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2460366#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2460367#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2460667#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2460428#L538 assume !(1 == ~t5_pc~0); 2460429#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2460327#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2460328#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2460609#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2460610#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2461269#L557 assume !(1 == ~t6_pc~0); 2460643#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2460644#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2460736#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2460668#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2460669#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2461568#L576 assume !(1 == ~t7_pc~0); 2460633#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2460836#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2460993#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2461624#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2461338#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2460760#L595 assume !(1 == ~t8_pc~0); 2460761#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2461360#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2461273#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2461139#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2461140#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2460560#L614 assume !(1 == ~t9_pc~0); 2460561#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2460454#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2460455#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2460799#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2460720#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2460721#L1025 assume !(1 == ~M_E~0); 2461015#L1025-2 assume !(1 == ~T1_E~0); 2461086#L1030-1 assume !(1 == ~T2_E~0); 2461259#L1035-1 assume !(1 == ~T3_E~0); 2460713#L1040-1 assume !(1 == ~T4_E~0); 2460714#L1045-1 assume !(1 == ~T5_E~0); 2460619#L1050-1 assume !(1 == ~T6_E~0); 2460620#L1055-1 assume !(1 == ~T7_E~0); 2460439#L1060-1 assume !(1 == ~T8_E~0); 2460440#L1065-1 assume !(1 == ~T9_E~0); 2460505#L1070-1 assume !(1 == ~E_1~0); 2461204#L1075-1 assume !(1 == ~E_2~0); 2461205#L1080-1 assume !(1 == ~E_3~0); 2461190#L1085-1 assume !(1 == ~E_4~0); 2461191#L1090-1 assume !(1 == ~E_5~0); 2461501#L1095-1 assume !(1 == ~E_6~0); 2461237#L1100-1 assume !(1 == ~E_7~0); 2461238#L1105-1 assume !(1 == ~E_8~0); 2460411#L1110-1 assume !(1 == ~E_9~0); 2460412#L1115-1 assume { :end_inline_reset_delta_events } true; 2460770#L1396-2 [2023-11-29 04:12:25,707 INFO L750 eck$LassoCheckResult]: Loop: 2460770#L1396-2 assume !false; 2465364#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2465358#L897-1 assume !false; 2465356#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2465353#L699 assume !(0 == ~m_st~0); 2465354#L703 assume !(0 == ~t1_st~0); 2470640#L707 assume !(0 == ~t2_st~0); 2470638#L711 assume !(0 == ~t3_st~0); 2470635#L715 assume !(0 == ~t4_st~0); 2470633#L719 assume !(0 == ~t5_st~0); 2470631#L723 assume !(0 == ~t6_st~0); 2470629#L727 assume !(0 == ~t7_st~0); 2470627#L731 assume !(0 == ~t8_st~0); 2470624#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2470606#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2470595#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2470587#L766 assume !(0 != eval_~tmp~0#1); 2470579#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2470572#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2470568#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2470558#L922-5 assume !(0 == ~T1_E~0); 2470553#L927-3 assume !(0 == ~T2_E~0); 2470545#L932-3 assume !(0 == ~T3_E~0); 2470537#L937-3 assume !(0 == ~T4_E~0); 2470527#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2470518#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2470510#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2470502#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2470494#L962-3 assume !(0 == ~T9_E~0); 2470484#L967-3 assume !(0 == ~E_1~0); 2470474#L972-3 assume !(0 == ~E_2~0); 2470466#L977-3 assume !(0 == ~E_3~0); 2470455#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2470448#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2470384#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2470380#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2470377#L1002-3 assume !(0 == ~E_8~0); 2470370#L1007-3 assume !(0 == ~E_9~0); 2470365#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2470361#L443-30 assume 1 == ~m_pc~0; 2470355#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2470349#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2470342#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2470337#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2470333#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2470329#L462-30 assume !(1 == ~t1_pc~0); 2470323#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2470317#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2470311#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2470304#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 2470298#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2470292#L481-30 assume 1 == ~t2_pc~0; 2470285#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2470276#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2470268#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2470260#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2470253#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2470247#L500-30 assume !(1 == ~t3_pc~0); 2470240#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2470232#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2470214#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2470209#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 2470175#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2470172#L519-30 assume !(1 == ~t4_pc~0); 2470170#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2470168#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2470165#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2470162#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 2470159#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2470156#L538-30 assume 1 == ~t5_pc~0; 2470153#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2470150#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2470146#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2470142#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2470138#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2470133#L557-30 assume !(1 == ~t6_pc~0); 2470129#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2470126#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2470122#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2470117#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2470110#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2470109#L576-30 assume !(1 == ~t7_pc~0); 2470108#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2470106#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2470104#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2470102#L1196-30 assume !(0 != activate_threads_~tmp___6~0#1); 2465541#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2465539#L595-30 assume !(1 == ~t8_pc~0); 2465537#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2465535#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2465533#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2465531#L1204-30 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2465529#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2465527#L614-30 assume !(1 == ~t9_pc~0); 2465523#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2465521#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2465519#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2465517#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2465515#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2465513#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2465511#L1025-5 assume !(1 == ~T1_E~0); 2465509#L1030-3 assume !(1 == ~T2_E~0); 2465507#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2465505#L1040-3 assume !(1 == ~T4_E~0); 2465503#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2465501#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2465499#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2465496#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2465491#L1065-3 assume !(1 == ~T9_E~0); 2465489#L1070-3 assume !(1 == ~E_1~0); 2465486#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2465467#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2465459#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2465451#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2465445#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2465422#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2465418#L1105-3 assume !(1 == ~E_8~0); 2465414#L1110-3 assume !(1 == ~E_9~0); 2465412#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2465409#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2465407#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2465404#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2465393#L1415 assume !(0 == start_simulation_~tmp~3#1); 2465391#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2465388#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2465387#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2465383#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2465381#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2465379#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2465378#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2465375#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2460770#L1396-2 [2023-11-29 04:12:25,707 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:25,708 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 13 times [2023-11-29 04:12:25,708 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:25,708 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [48803776] [2023-11-29 04:12:25,708 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:25,708 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:25,721 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:25,721 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:25,727 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:25,751 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:25,751 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:25,751 INFO L85 PathProgramCache]: Analyzing trace with hash 1120599813, now seen corresponding path program 1 times [2023-11-29 04:12:25,751 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:25,752 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888900323] [2023-11-29 04:12:25,752 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:25,752 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:25,768 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:25,833 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:25,833 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:25,833 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888900323] [2023-11-29 04:12:25,833 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888900323] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:25,833 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:25,834 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:25,834 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1027881771] [2023-11-29 04:12:25,834 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:25,834 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:25,834 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:25,835 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:12:25,835 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:12:25,835 INFO L87 Difference]: Start difference. First operand 76332 states and 99526 transitions. cyclomatic complexity: 23226 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:26,326 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:26,326 INFO L93 Difference]: Finished difference Result 123036 states and 158805 transitions. [2023-11-29 04:12:26,327 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 123036 states and 158805 transitions. [2023-11-29 04:12:27,008 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 122280 [2023-11-29 04:12:27,192 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 123036 states to 123036 states and 158805 transitions. [2023-11-29 04:12:27,192 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 123036 [2023-11-29 04:12:27,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 123036 [2023-11-29 04:12:27,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 123036 states and 158805 transitions. [2023-11-29 04:12:27,262 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:27,262 INFO L218 hiAutomatonCegarLoop]: Abstraction has 123036 states and 158805 transitions. [2023-11-29 04:12:27,308 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 123036 states and 158805 transitions. [2023-11-29 04:12:28,039 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 123036 to 77052. [2023-11-29 04:12:28,069 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77052 states, 77052 states have (on average 1.2947749571717801) internal successors, (99765), 77051 states have internal predecessors, (99765), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:28,205 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77052 states to 77052 states and 99765 transitions. [2023-11-29 04:12:28,205 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77052 states and 99765 transitions. [2023-11-29 04:12:28,206 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:12:28,206 INFO L428 stractBuchiCegarLoop]: Abstraction has 77052 states and 99765 transitions. [2023-11-29 04:12:28,206 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2023-11-29 04:12:28,206 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77052 states and 99765 transitions. [2023-11-29 04:12:28,353 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 76520 [2023-11-29 04:12:28,354 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:28,354 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:28,355 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:28,355 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:28,355 INFO L748 eck$LassoCheckResult]: Stem: 2659916#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2659917#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2660844#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2660845#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2660762#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2660763#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2660737#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2660494#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2660495#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2660263#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2660264#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2660882#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2660723#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2660337#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2660074#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2660075#L922 assume !(0 == ~M_E~0); 2660968#L922-2 assume !(0 == ~T1_E~0); 2660969#L927-1 assume !(0 == ~T2_E~0); 2660569#L932-1 assume !(0 == ~T3_E~0); 2660415#L937-1 assume !(0 == ~T4_E~0); 2660416#L942-1 assume !(0 == ~T5_E~0); 2660493#L947-1 assume !(0 == ~T6_E~0); 2660574#L952-1 assume !(0 == ~T7_E~0); 2660575#L957-1 assume !(0 == ~T8_E~0); 2660655#L962-1 assume !(0 == ~T9_E~0); 2660392#L967-1 assume !(0 == ~E_1~0); 2660393#L972-1 assume !(0 == ~E_2~0); 2660745#L977-1 assume !(0 == ~E_3~0); 2660746#L982-1 assume !(0 == ~E_4~0); 2659847#L987-1 assume !(0 == ~E_5~0); 2659848#L992-1 assume !(0 == ~E_6~0); 2659852#L997-1 assume !(0 == ~E_7~0); 2660309#L1002-1 assume !(0 == ~E_8~0); 2660294#L1007-1 assume !(0 == ~E_9~0); 2659639#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2659640#L443 assume !(1 == ~m_pc~0); 2660593#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2660583#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2660584#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2660007#L1140 assume !(0 != activate_threads_~tmp~1#1); 2659745#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2659746#L462 assume !(1 == ~t1_pc~0); 2660409#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2660410#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2659682#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2659683#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2660242#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2660243#L481 assume !(1 == ~t2_pc~0); 2660001#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2660820#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2661004#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2661002#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2660100#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2660210#L500 assume !(1 == ~t3_pc~0); 2660832#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2660788#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2659646#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2659647#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2659644#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2659645#L519 assume !(1 == ~t4_pc~0); 2660479#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2660207#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2659747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2659748#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2660048#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2659809#L538 assume !(1 == ~t5_pc~0); 2659810#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2659707#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2659708#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2659988#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2659989#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2660638#L557 assume !(1 == ~t6_pc~0); 2660021#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2660022#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2660118#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2660046#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2660047#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2660927#L576 assume !(1 == ~t7_pc~0); 2660011#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2660218#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2661006#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2660977#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2660709#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2660140#L595 assume !(1 == ~t8_pc~0); 2660141#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2660733#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2660642#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2660522#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2660523#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2659939#L614 assume !(1 == ~t9_pc~0); 2659940#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2659835#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2659836#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2660180#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2660102#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2660103#L1025 assume !(1 == ~M_E~0); 2660398#L1025-2 assume !(1 == ~T1_E~0); 2660470#L1030-1 assume !(1 == ~T2_E~0); 2660628#L1035-1 assume !(1 == ~T3_E~0); 2660094#L1040-1 assume !(1 == ~T4_E~0); 2660095#L1045-1 assume !(1 == ~T5_E~0); 2659997#L1050-1 assume !(1 == ~T6_E~0); 2659998#L1055-1 assume !(1 == ~T7_E~0); 2659820#L1060-1 assume !(1 == ~T8_E~0); 2659821#L1065-1 assume !(1 == ~T9_E~0); 2659885#L1070-1 assume !(1 == ~E_1~0); 2660578#L1075-1 assume !(1 == ~E_2~0); 2660579#L1080-1 assume !(1 == ~E_3~0); 2660563#L1085-1 assume !(1 == ~E_4~0); 2660564#L1090-1 assume !(1 == ~E_5~0); 2660869#L1095-1 assume !(1 == ~E_6~0); 2660606#L1100-1 assume !(1 == ~E_7~0); 2660607#L1105-1 assume !(1 == ~E_8~0); 2659791#L1110-1 assume !(1 == ~E_9~0); 2659792#L1115-1 assume { :end_inline_reset_delta_events } true; 2660151#L1396-2 [2023-11-29 04:12:28,355 INFO L750 eck$LassoCheckResult]: Loop: 2660151#L1396-2 assume !false; 2673144#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2673137#L897-1 assume !false; 2673135#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2673132#L699 assume !(0 == ~m_st~0); 2673133#L703 assume !(0 == ~t1_st~0); 2673562#L707 assume !(0 == ~t2_st~0); 2673561#L711 assume !(0 == ~t3_st~0); 2673559#L715 assume !(0 == ~t4_st~0); 2673557#L719 assume !(0 == ~t5_st~0); 2673555#L723 assume !(0 == ~t6_st~0); 2673552#L727 assume !(0 == ~t7_st~0); 2673550#L731 assume !(0 == ~t8_st~0); 2673547#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2673546#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2673545#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2673542#L766 assume !(0 != eval_~tmp~0#1); 2673541#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2673540#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2673539#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2673537#L922-5 assume !(0 == ~T1_E~0); 2673535#L927-3 assume !(0 == ~T2_E~0); 2673531#L932-3 assume !(0 == ~T3_E~0); 2673529#L937-3 assume !(0 == ~T4_E~0); 2673527#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2673525#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2673520#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2673518#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2673515#L962-3 assume !(0 == ~T9_E~0); 2673513#L967-3 assume !(0 == ~E_1~0); 2673511#L972-3 assume !(0 == ~E_2~0); 2673509#L977-3 assume !(0 == ~E_3~0); 2673507#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2673505#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2673501#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2673499#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2673497#L1002-3 assume !(0 == ~E_8~0); 2673495#L1007-3 assume !(0 == ~E_9~0); 2673492#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2673490#L443-30 assume 1 == ~m_pc~0; 2673487#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2673485#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2673483#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2673480#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2673478#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2673476#L462-30 assume !(1 == ~t1_pc~0); 2673474#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2673472#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2673470#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2673468#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 2673466#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2673464#L481-30 assume 1 == ~t2_pc~0; 2673459#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2673457#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2673455#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2673453#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2673449#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2673447#L500-30 assume !(1 == ~t3_pc~0); 2673445#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2673443#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2673441#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2673439#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 2673437#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2673435#L519-30 assume !(1 == ~t4_pc~0); 2673431#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2673429#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2673427#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2673425#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 2673422#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2673420#L538-30 assume 1 == ~t5_pc~0; 2673418#L539-10 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2673419#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2674978#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2673407#L1180-30 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2673405#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2673403#L557-30 assume !(1 == ~t6_pc~0); 2673400#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2673398#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2673396#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2673394#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2673392#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2673390#L576-30 assume 1 == ~t7_pc~0; 2673388#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 2673384#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2673382#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2673379#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 2673378#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2673369#L595-30 assume !(1 == ~t8_pc~0); 2673367#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2673365#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2673362#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2673360#L1204-30 assume !(0 != activate_threads_~tmp___7~0#1); 2673358#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2673355#L614-30 assume !(1 == ~t9_pc~0); 2673352#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2673350#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2673349#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2673348#L1212-30 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 2673346#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2673344#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2673343#L1025-5 assume !(1 == ~T1_E~0); 2673342#L1030-3 assume !(1 == ~T2_E~0); 2673340#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2673337#L1040-3 assume !(1 == ~T4_E~0); 2673335#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2673333#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2673328#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2673326#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2673324#L1065-3 assume !(1 == ~T9_E~0); 2673322#L1070-3 assume !(1 == ~E_1~0); 2673320#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2673318#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2673316#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2673314#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2673310#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2673308#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2673306#L1105-3 assume !(1 == ~E_8~0); 2673304#L1110-3 assume !(1 == ~E_9~0); 2673301#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2673298#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2673296#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2673294#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2673168#L1415 assume !(0 == start_simulation_~tmp~3#1); 2673166#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2673163#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2673160#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2673158#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2673154#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2673152#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2673150#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2673148#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2660151#L1396-2 [2023-11-29 04:12:28,355 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:28,356 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 14 times [2023-11-29 04:12:28,356 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:28,356 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [509419337] [2023-11-29 04:12:28,356 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:28,356 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:28,362 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:28,363 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:28,367 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:28,380 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:28,381 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:28,381 INFO L85 PathProgramCache]: Analyzing trace with hash -449143130, now seen corresponding path program 1 times [2023-11-29 04:12:28,381 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:28,381 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [535424839] [2023-11-29 04:12:28,381 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:28,381 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:28,390 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:28,428 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:28,428 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:28,428 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [535424839] [2023-11-29 04:12:28,428 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [535424839] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:28,428 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:28,428 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 04:12:28,428 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1840280014] [2023-11-29 04:12:28,429 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:28,429 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 04:12:28,429 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:28,429 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 04:12:28,429 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 04:12:28,429 INFO L87 Difference]: Start difference. First operand 77052 states and 99765 transitions. cyclomatic complexity: 22745 Second operand has 5 states, 5 states have (on average 26.2) internal successors, (131), 5 states have internal predecessors, (131), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:28,838 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:28,838 INFO L93 Difference]: Finished difference Result 119244 states and 152788 transitions. [2023-11-29 04:12:28,839 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 119244 states and 152788 transitions. [2023-11-29 04:12:29,464 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 118488 [2023-11-29 04:12:29,653 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 119244 states to 119244 states and 152788 transitions. [2023-11-29 04:12:29,653 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 119244 [2023-11-29 04:12:29,693 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 119244 [2023-11-29 04:12:29,693 INFO L73 IsDeterministic]: Start isDeterministic. Operand 119244 states and 152788 transitions. [2023-11-29 04:12:29,724 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 04:12:29,724 INFO L218 hiAutomatonCegarLoop]: Abstraction has 119244 states and 152788 transitions. [2023-11-29 04:12:29,768 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 119244 states and 152788 transitions. [2023-11-29 04:12:30,503 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 119244 to 77244. [2023-11-29 04:12:30,536 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 77244 states, 77244 states have (on average 1.2851224690590854) internal successors, (99268), 77243 states have internal predecessors, (99268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:30,728 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 77244 states to 77244 states and 99268 transitions. [2023-11-29 04:12:30,729 INFO L240 hiAutomatonCegarLoop]: Abstraction has 77244 states and 99268 transitions. [2023-11-29 04:12:30,729 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 04:12:30,729 INFO L428 stractBuchiCegarLoop]: Abstraction has 77244 states and 99268 transitions. [2023-11-29 04:12:30,730 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2023-11-29 04:12:30,730 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 77244 states and 99268 transitions. [2023-11-29 04:12:30,919 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 76712 [2023-11-29 04:12:30,919 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:30,919 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:30,921 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:30,921 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:30,921 INFO L748 eck$LassoCheckResult]: Stem: 2856220#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 2856221#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 2857133#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2857134#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2857066#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 2857067#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2857038#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2856793#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2856794#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2856563#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2856564#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2857167#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2857025#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2856639#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2856379#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2856380#L922 assume !(0 == ~M_E~0); 2857258#L922-2 assume !(0 == ~T1_E~0); 2857259#L927-1 assume !(0 == ~T2_E~0); 2856878#L932-1 assume !(0 == ~T3_E~0); 2856719#L937-1 assume !(0 == ~T4_E~0); 2856720#L942-1 assume !(0 == ~T5_E~0); 2856792#L947-1 assume !(0 == ~T6_E~0); 2856883#L952-1 assume !(0 == ~T7_E~0); 2856884#L957-1 assume !(0 == ~T8_E~0); 2856966#L962-1 assume !(0 == ~T9_E~0); 2856694#L967-1 assume !(0 == ~E_1~0); 2856695#L972-1 assume !(0 == ~E_2~0); 2857048#L977-1 assume !(0 == ~E_3~0); 2857049#L982-1 assume !(0 == ~E_4~0); 2856152#L987-1 assume !(0 == ~E_5~0); 2856153#L992-1 assume !(0 == ~E_6~0); 2856159#L997-1 assume !(0 == ~E_7~0); 2856610#L1002-1 assume !(0 == ~E_8~0); 2856595#L1007-1 assume !(0 == ~E_9~0); 2855947#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2855948#L443 assume !(1 == ~m_pc~0); 2856900#L443-2 is_master_triggered_~__retres1~0#1 := 0; 2856891#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2856892#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2856315#L1140 assume !(0 != activate_threads_~tmp~1#1); 2856054#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2856055#L462 assume !(1 == ~t1_pc~0); 2856710#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2856711#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2855988#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2855989#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 2856540#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2856541#L481 assume !(1 == ~t2_pc~0); 2856308#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2857113#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2857290#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2857289#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 2856403#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2856508#L500 assume !(1 == ~t3_pc~0); 2857123#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2857085#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2855954#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2855955#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 2855949#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2855950#L519 assume !(1 == ~t4_pc~0); 2856781#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2856507#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2856052#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2856053#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 2856350#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2856116#L538 assume !(1 == ~t5_pc~0); 2856117#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2856013#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2856014#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2856294#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 2856295#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2856946#L557 assume !(1 == ~t6_pc~0); 2856329#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2856330#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2856423#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2856351#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 2856352#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2857214#L576 assume !(1 == ~t7_pc~0); 2856319#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2856514#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2857293#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2857263#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 2857016#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2856444#L595 assume !(1 == ~t8_pc~0); 2856445#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2857033#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2856952#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2856823#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 2856824#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2856245#L614 assume !(1 == ~t9_pc~0); 2856246#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2856141#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2856142#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2856482#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 2856406#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2856407#L1025 assume !(1 == ~M_E~0); 2856703#L1025-2 assume !(1 == ~T1_E~0); 2856771#L1030-1 assume !(1 == ~T2_E~0); 2856937#L1035-1 assume !(1 == ~T3_E~0); 2856397#L1040-1 assume !(1 == ~T4_E~0); 2856398#L1045-1 assume !(1 == ~T5_E~0); 2856304#L1050-1 assume !(1 == ~T6_E~0); 2856305#L1055-1 assume !(1 == ~T7_E~0); 2856127#L1060-1 assume !(1 == ~T8_E~0); 2856128#L1065-1 assume !(1 == ~T9_E~0); 2856193#L1070-1 assume !(1 == ~E_1~0); 2856885#L1075-1 assume !(1 == ~E_2~0); 2856886#L1080-1 assume !(1 == ~E_3~0); 2856872#L1085-1 assume !(1 == ~E_4~0); 2856873#L1090-1 assume !(1 == ~E_5~0); 2857157#L1095-1 assume !(1 == ~E_6~0); 2856917#L1100-1 assume !(1 == ~E_7~0); 2856918#L1105-1 assume !(1 == ~E_8~0); 2856098#L1110-1 assume !(1 == ~E_9~0); 2856099#L1115-1 assume { :end_inline_reset_delta_events } true; 2856454#L1396-2 [2023-11-29 04:12:30,921 INFO L750 eck$LassoCheckResult]: Loop: 2856454#L1396-2 assume !false; 2869581#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2869576#L897-1 assume !false; 2869574#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2869564#L699 assume !(0 == ~m_st~0); 2869565#L703 assume !(0 == ~t1_st~0); 2870386#L707 assume !(0 == ~t2_st~0); 2870384#L711 assume !(0 == ~t3_st~0); 2870382#L715 assume !(0 == ~t4_st~0); 2870380#L719 assume !(0 == ~t5_st~0); 2870378#L723 assume !(0 == ~t6_st~0); 2870376#L727 assume !(0 == ~t7_st~0); 2870374#L731 assume !(0 == ~t8_st~0); 2870371#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 2870369#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2870367#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2870365#L766 assume !(0 != eval_~tmp~0#1); 2870363#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2870361#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2870357#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 2870355#L922-5 assume !(0 == ~T1_E~0); 2870353#L927-3 assume !(0 == ~T2_E~0); 2870351#L932-3 assume !(0 == ~T3_E~0); 2870348#L937-3 assume !(0 == ~T4_E~0); 2870346#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2870344#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2870342#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2870340#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 2870338#L962-3 assume !(0 == ~T9_E~0); 2870336#L967-3 assume !(0 == ~E_1~0); 2870334#L972-3 assume !(0 == ~E_2~0); 2870332#L977-3 assume !(0 == ~E_3~0); 2870329#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2870327#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2870325#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 2870324#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2870306#L1002-3 assume !(0 == ~E_8~0); 2870301#L1007-3 assume !(0 == ~E_9~0); 2870294#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2870289#L443-30 assume 1 == ~m_pc~0; 2870284#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 2870280#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2870275#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 2870271#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 2870266#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2870262#L462-30 assume !(1 == ~t1_pc~0); 2870256#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 2870251#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2870244#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2870239#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 2870233#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2870228#L481-30 assume 1 == ~t2_pc~0; 2870223#L482-10 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2870218#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2870213#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2870208#L1156-30 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2870201#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2870196#L500-30 assume !(1 == ~t3_pc~0); 2870192#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 2870187#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2870179#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2870174#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 2870170#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2870164#L519-30 assume !(1 == ~t4_pc~0); 2870158#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 2870152#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2870146#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2870140#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 2870134#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2870129#L538-30 assume !(1 == ~t5_pc~0); 2870123#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 2870116#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2870109#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2870102#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 2870096#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2870090#L557-30 assume !(1 == ~t6_pc~0); 2870084#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 2870077#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2870070#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2870063#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 2870056#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2870050#L576-30 assume !(1 == ~t7_pc~0); 2870043#L576-32 is_transmit7_triggered_~__retres1~7#1 := 0; 2870036#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2870029#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2870022#L1196-30 assume !(0 != activate_threads_~tmp___6~0#1); 2870016#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2870010#L595-30 assume !(1 == ~t8_pc~0); 2870002#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 2869995#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2869988#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2869981#L1204-30 assume !(0 != activate_threads_~tmp___7~0#1); 2869975#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2869894#L614-30 assume !(1 == ~t9_pc~0); 2869891#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 2869889#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2869887#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2869885#L1212-30 assume !(0 != activate_threads_~tmp___8~0#1); 2869882#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2869880#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2869878#L1025-5 assume !(1 == ~T1_E~0); 2869876#L1030-3 assume !(1 == ~T2_E~0); 2869874#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 2869872#L1040-3 assume !(1 == ~T4_E~0); 2869870#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2869868#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2869866#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2869864#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2869862#L1065-3 assume !(1 == ~T9_E~0); 2869860#L1070-3 assume !(1 == ~E_1~0); 2869858#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2869856#L1080-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2869854#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2869852#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2869850#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2869848#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2869846#L1105-3 assume !(1 == ~E_8~0); 2869844#L1110-3 assume !(1 == ~E_9~0); 2869842#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2869839#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2869837#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2869835#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 2869831#L1415 assume !(0 == start_simulation_~tmp~3#1); 2869828#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 2869825#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 2869823#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 2869821#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 2869819#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2869817#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2869815#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 2869813#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 2856454#L1396-2 [2023-11-29 04:12:30,922 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:30,922 INFO L85 PathProgramCache]: Analyzing trace with hash 1388293232, now seen corresponding path program 15 times [2023-11-29 04:12:30,922 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:30,922 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2115703082] [2023-11-29 04:12:30,922 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:30,922 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:30,935 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:30,935 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:30,942 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:30,965 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:30,966 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:30,966 INFO L85 PathProgramCache]: Analyzing trace with hash -241735778, now seen corresponding path program 1 times [2023-11-29 04:12:30,966 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:30,966 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [242473126] [2023-11-29 04:12:30,966 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:30,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:30,981 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:30,981 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:30,990 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:31,010 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:31,011 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:31,011 INFO L85 PathProgramCache]: Analyzing trace with hash 1524015311, now seen corresponding path program 1 times [2023-11-29 04:12:31,011 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:31,011 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [888708191] [2023-11-29 04:12:31,012 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:31,012 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:31,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:31,085 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:31,085 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:31,085 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [888708191] [2023-11-29 04:12:31,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [888708191] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:31,086 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:31,086 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:12:31,086 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271423155] [2023-11-29 04:12:31,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:33,425 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 04:12:33,425 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 04:12:33,425 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 04:12:33,425 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 04:12:33,426 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-29 04:12:33,426 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:33,426 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 04:12:33,426 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 04:12:33,426 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.09.cil.c_Iteration39_Loop [2023-11-29 04:12:33,426 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 04:12:33,426 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 04:12:33,449 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,456 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,459 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,461 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,463 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,469 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,471 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,473 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,475 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,478 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,481 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,483 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,485 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,487 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,489 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,492 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,495 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,500 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,502 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,505 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,507 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,509 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,514 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,516 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,519 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,521 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,523 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,525 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,527 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,530 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,532 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,533 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,539 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,541 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,543 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,547 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,550 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,554 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,556 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,559 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,561 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,565 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,567 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,569 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,571 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,575 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,579 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,581 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,586 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,588 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,591 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,596 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,600 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,602 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,607 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,610 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,614 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,616 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,618 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,620 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,622 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,626 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,635 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,645 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,648 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,653 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,654 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,657 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,661 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,663 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,668 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,679 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,681 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,697 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,699 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,710 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,711 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,715 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,725 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,727 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,731 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,742 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,744 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,754 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,755 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:33,758 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,422 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 04:12:34,422 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-29 04:12:34,425 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,425 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,426 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,427 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-29 04:12:34,428 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,428 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,446 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,446 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,452 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:34,453 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,453 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,454 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,456 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-29 04:12:34,457 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,457 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,469 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,469 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit5_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,471 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2023-11-29 04:12:34,472 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,472 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,473 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,473 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-29 04:12:34,475 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,475 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,487 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,487 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Honda state: {ULTIMATE.start_is_transmit1_triggered_~__retres1~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,490 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2023-11-29 04:12:34,492 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,492 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,493 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,495 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-29 04:12:34,496 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,496 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,513 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,514 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,516 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2023-11-29 04:12:34,517 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,517 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,518 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,519 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-29 04:12:34,520 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,520 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,539 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,540 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_pc~0=4} Honda state: {~t4_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,542 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2023-11-29 04:12:34,542 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,543 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,543 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,545 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-29 04:12:34,546 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,546 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,560 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,560 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,563 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2023-11-29 04:12:34,564 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,564 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,565 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,568 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-29 04:12:34,569 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,569 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,583 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,583 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,586 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:34,586 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,586 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,587 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,588 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-29 04:12:34,590 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,590 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,601 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,602 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,604 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Ended with exit code 0 [2023-11-29 04:12:34,604 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,604 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,605 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,606 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-29 04:12:34,607 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,607 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,619 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,619 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit4_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,621 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2023-11-29 04:12:34,621 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,621 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,622 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,623 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-29 04:12:34,625 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,625 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,642 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,643 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,645 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:34,645 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,645 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,646 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,647 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-29 04:12:34,648 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,648 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,659 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,659 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,661 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Ended with exit code 0 [2023-11-29 04:12:34,662 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,662 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,663 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,663 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-29 04:12:34,665 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,665 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,676 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,676 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret20#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret20#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,678 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Ended with exit code 0 [2023-11-29 04:12:34,679 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,679 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,679 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,680 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-29 04:12:34,681 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,681 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,700 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,700 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t7_pc~0=4} Honda state: {~t7_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,702 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2023-11-29 04:12:34,702 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,703 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,703 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,704 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-29 04:12:34,705 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,706 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,717 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,717 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit7_triggered_~__retres1~7#1=0} Honda state: {ULTIMATE.start_is_transmit7_triggered_~__retres1~7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,719 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2023-11-29 04:12:34,719 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,720 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,720 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,721 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-29 04:12:34,723 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,723 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,734 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,734 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_9~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_9~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,736 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2023-11-29 04:12:34,737 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,737 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,737 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,738 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-29 04:12:34,739 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,740 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,757 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:34,757 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t9_st~0=4} Honda state: {~t9_st~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:34,759 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2023-11-29 04:12:34,759 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,759 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,760 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,762 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-29 04:12:34,762 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:34,762 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,776 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:34,776 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,776 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:34,777 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:34,778 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-29 04:12:34,779 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-29 04:12:34,779 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:34,792 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-29 04:12:34,794 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2023-11-29 04:12:34,794 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 04:12:34,795 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 04:12:34,795 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 04:12:34,795 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 04:12:34,795 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-29 04:12:34,795 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:34,795 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 04:12:34,795 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 04:12:34,795 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.09.cil.c_Iteration39_Loop [2023-11-29 04:12:34,795 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 04:12:34,795 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 04:12:34,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,803 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,806 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,808 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,812 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,814 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,815 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,817 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,818 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,820 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,822 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,824 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,825 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,827 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,831 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,833 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,837 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,845 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,851 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,853 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,854 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,856 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,858 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,859 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,861 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,862 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,866 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,868 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,873 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,876 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,878 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,882 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,886 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,889 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,891 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,892 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,896 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,900 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,902 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,904 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,908 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,910 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,913 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,917 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,919 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,921 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,924 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,926 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,927 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,929 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,930 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,934 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,937 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,939 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,942 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,945 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,949 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,950 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,952 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,954 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,958 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,960 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,964 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,966 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,974 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,976 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,978 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,983 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,985 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,987 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,990 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,991 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,993 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,996 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:34,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,001 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,003 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,005 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,006 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,008 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,010 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,014 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,016 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,017 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,019 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,020 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,024 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,025 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,026 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,030 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,031 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,035 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,037 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:35,635 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 04:12:35,640 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-29 04:12:35,641 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,641 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,642 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,648 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-29 04:12:35,649 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,660 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,660 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,661 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,661 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:35,661 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,662 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:35,662 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,665 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,667 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2023-11-29 04:12:35,667 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,668 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,668 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,669 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-29 04:12:35,670 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,680 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,680 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,680 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,680 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:12:35,680 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,681 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:12:35,681 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,683 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,685 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2023-11-29 04:12:35,685 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,686 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,686 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,687 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-29 04:12:35,689 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,698 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,698 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,698 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,698 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:12:35,698 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,699 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:12:35,699 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,701 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,703 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2023-11-29 04:12:35,703 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,703 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,704 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,705 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2023-11-29 04:12:35,706 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,715 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,715 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,716 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,716 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:35,716 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,716 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:35,716 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,718 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,720 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:35,720 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,720 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,721 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,722 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2023-11-29 04:12:35,724 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,733 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,734 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,734 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,734 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:35,734 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,734 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:35,735 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,736 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,738 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Ended with exit code 0 [2023-11-29 04:12:35,739 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,739 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,739 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,740 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2023-11-29 04:12:35,742 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,751 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,751 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,752 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,752 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:35,752 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,752 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:35,752 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,754 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,755 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Ended with exit code 0 [2023-11-29 04:12:35,756 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,756 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,757 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,757 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-29 04:12:35,759 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,768 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,769 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,769 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,769 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:35,769 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,769 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:35,769 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,770 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,772 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:35,773 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,773 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,774 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,775 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-29 04:12:35,776 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,786 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,786 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,786 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,786 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:35,786 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,786 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:35,786 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,787 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,789 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:35,790 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,790 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,790 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,791 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2023-11-29 04:12:35,793 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,802 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,802 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,802 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,802 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:35,802 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,803 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:35,803 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,804 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,806 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:35,806 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,807 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,807 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,808 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2023-11-29 04:12:35,809 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,819 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,819 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,819 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,819 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:12:35,819 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,820 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:12:35,820 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,822 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,824 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2023-11-29 04:12:35,824 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,824 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,825 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,826 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2023-11-29 04:12:35,826 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,836 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,836 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,836 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,836 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:35,836 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,837 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:35,837 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,838 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,840 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2023-11-29 04:12:35,840 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,840 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,841 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,842 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2023-11-29 04:12:35,843 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,853 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,853 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,853 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,853 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:12:35,853 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,854 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:12:35,854 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,855 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,857 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:35,857 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,858 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,858 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,859 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2023-11-29 04:12:35,861 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,870 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,870 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,870 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,870 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:35,871 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,871 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:35,871 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,872 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,874 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2023-11-29 04:12:35,874 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,874 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,875 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,876 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2023-11-29 04:12:35,877 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,887 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,887 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,887 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,887 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:12:35,887 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,888 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:12:35,888 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,890 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:35,892 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:35,893 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,893 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,893 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,894 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2023-11-29 04:12:35,895 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:35,905 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:35,905 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:35,905 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:35,905 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:35,906 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:35,906 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:35,906 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:35,909 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-29 04:12:35,911 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-29 04:12:35,912 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-29 04:12:35,913 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:35,913 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:35,936 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:35,937 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2023-11-29 04:12:35,938 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-29 04:12:35,938 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-29 04:12:35,938 INFO L513 LassoAnalysis]: Proved termination. [2023-11-29 04:12:35,939 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_3~0) = -2*~E_3~0 + 3 Supporting invariants [] [2023-11-29 04:12:35,941 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Ended with exit code 0 [2023-11-29 04:12:35,943 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-29 04:12:35,959 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:36,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:36,026 INFO L262 TraceCheckSpWp]: Trace formula consists of 323 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-29 04:12:36,029 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 04:12:36,232 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:36,234 INFO L262 TraceCheckSpWp]: Trace formula consists of 267 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-29 04:12:36,237 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 04:12:36,537 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:36,542 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 2 loop predicates [2023-11-29 04:12:36,543 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 77244 states and 99268 transitions. cyclomatic complexity: 22056 Second operand has 4 states, 4 states have (on average 61.5) internal successors, (246), 4 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:37,112 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2023-11-29 04:12:37,693 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 77244 states and 99268 transitions. cyclomatic complexity: 22056. Second operand has 4 states, 4 states have (on average 61.5) internal successors, (246), 4 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 215310 states and 278071 transitions. Complement of second has 5 states. [2023-11-29 04:12:37,695 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-29 04:12:37,696 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4 states, 4 states have (on average 61.5) internal successors, (246), 4 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:37,698 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1446 transitions. [2023-11-29 04:12:37,700 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1446 transitions. Stem has 115 letters. Loop has 131 letters. [2023-11-29 04:12:37,706 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 04:12:37,706 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1446 transitions. Stem has 246 letters. Loop has 131 letters. [2023-11-29 04:12:37,708 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 04:12:37,708 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1446 transitions. Stem has 115 letters. Loop has 262 letters. [2023-11-29 04:12:37,710 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 04:12:37,710 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 215310 states and 278071 transitions. [2023-11-29 04:12:38,372 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 145056 [2023-11-29 04:12:39,098 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 215310 states to 215214 states and 277975 transitions. [2023-11-29 04:12:39,098 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146085 [2023-11-29 04:12:39,162 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146278 [2023-11-29 04:12:39,162 INFO L73 IsDeterministic]: Start isDeterministic. Operand 215214 states and 277975 transitions. [2023-11-29 04:12:39,163 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:12:39,163 INFO L218 hiAutomatonCegarLoop]: Abstraction has 215214 states and 277975 transitions. [2023-11-29 04:12:39,243 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 215214 states and 277975 transitions. [2023-11-29 04:12:40,905 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 215214 to 214925. [2023-11-29 04:12:41,031 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 214925 states, 214925 states have (on average 1.2911201581947191) internal successors, (277494), 214924 states have internal predecessors, (277494), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:41,775 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214925 states to 214925 states and 277494 transitions. [2023-11-29 04:12:41,775 INFO L240 hiAutomatonCegarLoop]: Abstraction has 214925 states and 277494 transitions. [2023-11-29 04:12:41,776 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:41,776 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:12:41,776 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:12:41,776 INFO L87 Difference]: Start difference. First operand 214925 states and 277494 transitions. Second operand has 3 states, 3 states have (on average 82.0) internal successors, (246), 3 states have internal predecessors, (246), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:42,761 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:12:42,761 INFO L93 Difference]: Finished difference Result 226541 states and 291126 transitions. [2023-11-29 04:12:42,761 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 226541 states and 291126 transitions. [2023-11-29 04:12:43,792 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 152800 [2023-11-29 04:12:44,164 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 226541 states to 226541 states and 291126 transitions. [2023-11-29 04:12:44,164 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 153733 [2023-11-29 04:12:44,210 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 153733 [2023-11-29 04:12:44,210 INFO L73 IsDeterministic]: Start isDeterministic. Operand 226541 states and 291126 transitions. [2023-11-29 04:12:44,211 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:12:44,211 INFO L218 hiAutomatonCegarLoop]: Abstraction has 226541 states and 291126 transitions. [2023-11-29 04:12:44,298 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 226541 states and 291126 transitions. [2023-11-29 04:12:45,981 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 226541 to 214925. [2023-11-29 04:12:46,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 214925 states, 214925 states have (on average 1.2888868209840643) internal successors, (277014), 214924 states have internal predecessors, (277014), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:46,532 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 214925 states to 214925 states and 277014 transitions. [2023-11-29 04:12:46,532 INFO L240 hiAutomatonCegarLoop]: Abstraction has 214925 states and 277014 transitions. [2023-11-29 04:12:46,533 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:12:46,533 INFO L428 stractBuchiCegarLoop]: Abstraction has 214925 states and 277014 transitions. [2023-11-29 04:12:46,533 INFO L335 stractBuchiCegarLoop]: ======== Iteration 40 ============ [2023-11-29 04:12:46,534 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 214925 states and 277014 transitions. [2023-11-29 04:12:47,058 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 145056 [2023-11-29 04:12:47,058 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:12:47,058 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:12:47,060 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:47,060 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:12:47,060 INFO L748 eck$LassoCheckResult]: Stem: 3591231#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 3591232#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 3593022#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3593023#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3592872#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 3592873#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3592810#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3592332#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3592333#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3591875#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3591876#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3593114#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3592778#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3592025#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3591532#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3591533#L922 assume !(0 == ~M_E~0); 3593305#L922-2 assume !(0 == ~T1_E~0); 3593306#L927-1 assume !(0 == ~T2_E~0); 3592478#L932-1 assume !(0 == ~T3_E~0); 3592187#L937-1 assume !(0 == ~T4_E~0); 3592188#L942-1 assume !(0 == ~T5_E~0); 3592331#L947-1 assume !(0 == ~T6_E~0); 3592488#L952-1 assume !(0 == ~T7_E~0); 3592489#L957-1 assume !(0 == ~T8_E~0); 3592649#L962-1 assume !(0 == ~T9_E~0); 3592136#L967-1 assume !(0 == ~E_1~0); 3592137#L972-1 assume !(0 == ~E_2~0); 3592831#L977-1 assume !(0 == ~E_3~0); 3592832#L982-1 assume !(0 == ~E_4~0); 3591106#L987-1 assume !(0 == ~E_5~0); 3591107#L992-1 assume !(0 == ~E_6~0); 3591118#L997-1 assume !(0 == ~E_7~0); 3591966#L1002-1 assume !(0 == ~E_8~0); 3591937#L1007-1 assume !(0 == ~E_9~0); 3590733#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3590734#L443 assume !(1 == ~m_pc~0); 3592523#L443-2 is_master_triggered_~__retres1~0#1 := 0; 3592524#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3592791#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3591411#L1140 assume !(0 != activate_threads_~tmp~1#1); 3590928#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3590929#L462 assume !(1 == ~t1_pc~0); 3592168#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3592169#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3590809#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3590810#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 3591830#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3591831#L481 assume !(1 == ~t2_pc~0); 3591398#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3592978#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3591646#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3591647#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 3591576#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3591773#L500 assume !(1 == ~t3_pc~0); 3593005#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3592917#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3590743#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3590744#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 3590735#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3590736#L519 assume !(1 == ~t4_pc~0); 3592306#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3591772#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3590930#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3590931#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 3591480#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3591043#L538 assume !(1 == ~t5_pc~0); 3591044#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3590855#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3590856#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3591377#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 3591378#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3592611#L557 assume !(1 == ~t6_pc~0); 3591437#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3591438#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3591610#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3591478#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 3591479#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3593222#L576 assume !(1 == ~t7_pc~0); 3591417#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3591785#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3592108#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3593320#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 3592754#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3591652#L595 assume !(1 == ~t8_pc~0); 3591653#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3592802#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3592623#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3592382#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 3592383#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3591282#L614 assume !(1 == ~t9_pc~0); 3591283#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3591086#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3591087#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3591726#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 3591580#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3591581#L1025 assume !(1 == ~M_E~0); 3592152#L1025-2 assume !(1 == ~T1_E~0); 3592283#L1030-1 assume !(1 == ~T2_E~0); 3592593#L1035-1 assume !(1 == ~T3_E~0); 3591565#L1040-1 assume !(1 == ~T4_E~0); 3591566#L1045-1 assume !(1 == ~T5_E~0); 3591394#L1050-1 assume !(1 == ~T6_E~0); 3591395#L1055-1 assume !(1 == ~T7_E~0); 3591062#L1060-1 assume !(1 == ~T8_E~0); 3591063#L1065-1 assume !(1 == ~T9_E~0); 3591181#L1070-1 assume !(1 == ~E_1~0); 3592490#L1075-1 assume !(1 == ~E_2~0); 3592491#L1080-1 assume !(1 == ~E_3~0); 3592468#L1085-1 assume !(1 == ~E_4~0); 3592469#L1090-1 assume !(1 == ~E_5~0); 3593090#L1095-1 assume !(1 == ~E_6~0); 3592553#L1100-1 assume !(1 == ~E_7~0); 3592554#L1105-1 assume !(1 == ~E_8~0); 3591012#L1110-1 assume !(1 == ~E_9~0); 3591013#L1115-1 assume { :end_inline_reset_delta_events } true; 3591669#L1396-2 assume !false; 3597056#L1397 [2023-11-29 04:12:47,061 INFO L750 eck$LassoCheckResult]: Loop: 3597056#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3682873#L897-1 assume !false; 3682872#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3682871#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3682869#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3682848#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3682822#L766 assume 0 != eval_~tmp~0#1; 3682817#L766-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 3682812#L774 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 3682813#L89 assume !(0 == ~m_pc~0); 3797856#L92 assume 1 == ~m_pc~0; 3797850#$Ultimate##355 assume !false; 3680922#L109 ~m_pc~0 := 1;~m_st~0 := 2; 3680920#master_returnLabel#1 assume { :end_inline_master } true; 3680710#L774-2 havoc eval_~tmp_ndt_1~0#1; 3680707#L771-1 assume !(0 == ~t1_st~0); 3680703#L785-1 assume !(0 == ~t2_st~0); 3680697#L799-1 assume !(0 == ~t3_st~0); 3680693#L813-1 assume !(0 == ~t4_st~0); 3680690#L827-1 assume !(0 == ~t5_st~0); 3680191#L841-1 assume !(0 == ~t6_st~0); 3679631#L855-1 assume !(0 == ~t7_st~0); 3679628#L869-1 assume !(0 == ~t8_st~0); 3679629#L883-1 assume !(0 == ~t9_st~0); 3593233#L897-1 assume !false; 3593324#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3592874#L699 assume !(0 == ~m_st~0); 3592875#L703 assume !(0 == ~t1_st~0); 3592358#L707 assume !(0 == ~t2_st~0); 3591307#L711 assume !(0 == ~t3_st~0); 3591309#L715 assume !(0 == ~t4_st~0); 3592339#L719 assume !(0 == ~t5_st~0); 3592340#L723 assume !(0 == ~t6_st~0); 3592183#L727 assume !(0 == ~t7_st~0); 3592184#L731 assume !(0 == ~t8_st~0); 3592470#L735 assume !(0 == ~t9_st~0);exists_runnable_thread_~__retres1~10#1 := 0; 3592471#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3805108#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3799434#L766 assume !(0 != eval_~tmp~0#1); 3799435#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3801465#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3801464#L922-3 assume 0 == ~M_E~0;~M_E~0 := 1; 3801463#L922-5 assume !(0 == ~T1_E~0); 3801462#L927-3 assume !(0 == ~T2_E~0); 3801458#L932-3 assume !(0 == ~T3_E~0); 3801456#L937-3 assume !(0 == ~T4_E~0); 3801454#L942-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3801452#L947-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3801449#L952-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3801447#L957-3 assume 0 == ~T8_E~0;~T8_E~0 := 1; 3801443#L962-3 assume !(0 == ~T9_E~0); 3592690#L967-3 assume !(0 == ~E_1~0); 3592691#L972-3 assume !(0 == ~E_2~0); 3592474#L977-3 assume !(0 == ~E_3~0); 3592475#L982-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3593331#L987-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3591606#L992-3 assume 0 == ~E_6~0;~E_6~0 := 1; 3591607#L997-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3591598#L1002-3 assume !(0 == ~E_8~0); 3591599#L1007-3 assume !(0 == ~E_9~0); 3591064#L1012-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3591065#L443-30 assume 1 == ~m_pc~0; 3591123#L444-10 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3591124#L454-10 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3803865#is_master_triggered_returnLabel#11 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 3803864#L1140-30 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 3592843#L1140-32 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3591893#L462-30 assume !(1 == ~t1_pc~0); 3591894#L462-32 is_transmit1_triggered_~__retres1~1#1 := 0; 3592821#L473-10 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3592822#is_transmit1_triggered_returnLabel#11 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3592924#L1148-30 assume !(0 != activate_threads_~tmp___0~0#1); 3592925#L1148-32 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3591864#L481-30 assume !(1 == ~t2_pc~0); 3591293#L481-32 is_transmit2_triggered_~__retres1~2#1 := 0; 3799943#L492-10 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3799941#is_transmit2_triggered_returnLabel#11 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3799939#L1156-30 assume !(0 != activate_threads_~tmp___1~0#1); 3591242#L1156-32 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3591782#L500-30 assume !(1 == ~t3_pc~0); 3592515#L500-32 is_transmit3_triggered_~__retres1~3#1 := 0; 3593347#L511-10 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3592118#is_transmit3_triggered_returnLabel#11 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3592119#L1164-30 assume !(0 != activate_threads_~tmp___2~0#1); 3591750#L1164-32 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3591751#L519-30 assume !(1 == ~t4_pc~0); 3592176#L519-32 is_transmit4_triggered_~__retres1~4#1 := 0; 3592122#L530-10 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3592123#is_transmit4_triggered_returnLabel#11 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3592143#L1172-30 assume !(0 != activate_threads_~tmp___3~0#1); 3592144#L1172-32 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3592426#L538-30 assume !(1 == ~t5_pc~0); 3591082#L538-32 is_transmit5_triggered_~__retres1~5#1 := 0; 3593136#L549-10 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3803892#is_transmit5_triggered_returnLabel#11 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3592759#L1180-30 assume !(0 != activate_threads_~tmp___4~0#1); 3591227#L1180-32 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3591228#L557-30 assume !(1 == ~t6_pc~0); 3591253#L557-32 is_transmit6_triggered_~__retres1~6#1 := 0; 3592004#L568-10 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3590936#is_transmit6_triggered_returnLabel#11 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3590937#L1188-30 assume !(0 != activate_threads_~tmp___5~0#1); 3593319#L1188-32 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3592403#L576-30 assume 1 == ~t7_pc~0; 3592404#L577-10 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3593309#L587-10 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3797844#is_transmit7_triggered_returnLabel#11 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3797773#L1196-30 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3591567#L1196-32 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3591493#L595-30 assume !(1 == ~t8_pc~0); 3591494#L595-32 is_transmit8_triggered_~__retres1~8#1 := 0; 3591383#L606-10 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3591384#is_transmit8_triggered_returnLabel#11 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3593084#L1204-30 assume !(0 != activate_threads_~tmp___7~0#1); 3593085#L1204-32 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3593224#L614-30 assume !(1 == ~t9_pc~0); 3591391#L614-32 is_transmit9_triggered_~__retres1~9#1 := 0; 3692874#L625-10 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3692871#is_transmit9_triggered_returnLabel#11 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3692869#L1212-30 assume !(0 != activate_threads_~tmp___8~0#1); 3692867#L1212-32 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3692865#L1025-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3692863#L1025-5 assume !(1 == ~T1_E~0); 3692861#L1030-3 assume !(1 == ~T2_E~0); 3692859#L1035-3 assume 1 == ~T3_E~0;~T3_E~0 := 2; 3692857#L1040-3 assume !(1 == ~T4_E~0); 3692855#L1045-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3692853#L1050-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3692851#L1055-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3692849#L1060-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3692847#L1065-3 assume !(1 == ~T9_E~0); 3692845#L1070-3 assume !(1 == ~E_1~0); 3692843#L1075-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3692841#L1080-3 assume !(1 == ~E_3~0); 3692839#L1085-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3692837#L1090-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3692835#L1095-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3692834#L1100-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3692833#L1105-3 assume !(1 == ~E_8~0); 3692831#L1110-3 assume !(1 == ~E_9~0); 3692829#L1115-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3692827#L699-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3692825#L751-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3692823#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret26#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret26#1;havoc start_simulation_#t~ret26#1; 3692819#L1415 assume !(0 == start_simulation_~tmp~3#1); 3692816#L1415-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 3692815#L699-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 3692814#L751-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 3692813#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret25#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret25#1;havoc stop_simulation_#t~ret25#1; 3692812#L1370 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3692811#L1377 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3692809#stop_simulation_returnLabel#1 start_simulation_#t~ret27#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret25#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret27#1;havoc start_simulation_#t~ret27#1; 3692807#L1428 assume !(0 != start_simulation_~tmp___0~1#1); 3692805#L1396-2 assume !false; 3597056#L1397 [2023-11-29 04:12:47,061 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:47,061 INFO L85 PathProgramCache]: Analyzing trace with hash 87417772, now seen corresponding path program 1 times [2023-11-29 04:12:47,061 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:47,061 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [31228509] [2023-11-29 04:12:47,061 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:47,062 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:47,073 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:47,073 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:47,079 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:47,094 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:47,094 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:47,094 INFO L85 PathProgramCache]: Analyzing trace with hash -453674312, now seen corresponding path program 1 times [2023-11-29 04:12:47,094 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:47,094 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [837955133] [2023-11-29 04:12:47,095 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:47,095 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:47,108 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:47,109 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:12:47,117 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:12:47,132 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:12:47,132 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:47,133 INFO L85 PathProgramCache]: Analyzing trace with hash -452845917, now seen corresponding path program 1 times [2023-11-29 04:12:47,133 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:12:47,133 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1371895879] [2023-11-29 04:12:47,133 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:12:47,133 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:12:47,151 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:47,200 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:12:47,200 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:12:47,200 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1371895879] [2023-11-29 04:12:47,201 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1371895879] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:12:47,201 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:12:47,201 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 04:12:47,201 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1542977059] [2023-11-29 04:12:47,201 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:12:49,691 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 04:12:49,691 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 04:12:49,691 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 04:12:49,691 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 04:12:49,691 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-29 04:12:49,691 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:49,691 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 04:12:49,691 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 04:12:49,691 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.09.cil.c_Iteration40_Loop [2023-11-29 04:12:49,692 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 04:12:49,692 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 04:12:49,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,705 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,711 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,712 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,714 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,715 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,718 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,719 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,722 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,723 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,725 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,726 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,728 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,730 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,732 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,733 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,734 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,735 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,737 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,739 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,741 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,748 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,753 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,755 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,757 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,759 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,760 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,762 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,763 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,765 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,766 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,767 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,769 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,770 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,772 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,773 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,775 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,778 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,781 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,784 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,785 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,786 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,788 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,790 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,792 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,795 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,796 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,797 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,800 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,802 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,804 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,807 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,810 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,813 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,814 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,817 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,818 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,821 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,823 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,824 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,827 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,829 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,830 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,832 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,835 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,836 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,837 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,839 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,840 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,842 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,843 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,844 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,846 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,847 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,850 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,852 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,853 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,854 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,855 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,856 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,857 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,859 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,860 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,861 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,863 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,866 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,868 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,869 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,872 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,873 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,875 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,877 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,879 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,880 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,883 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,885 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,886 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,887 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,888 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:49,890 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,431 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 04:12:50,431 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-29 04:12:50,431 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:50,431 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:50,432 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:50,435 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2023-11-29 04:12:50,436 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:50,436 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:50,457 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 04:12:50,457 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 04:12:50,460 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Ended with exit code 0 [2023-11-29 04:12:50,460 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:50,460 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:50,461 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:50,462 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2023-11-29 04:12:50,463 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 04:12:50,463 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:50,477 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2023-11-29 04:12:50,477 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:50,477 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:50,478 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:50,479 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2023-11-29 04:12:50,480 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-29 04:12:50,480 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 04:12:50,493 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-29 04:12:50,496 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2023-11-29 04:12:50,496 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 04:12:50,496 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 04:12:50,496 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 04:12:50,496 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 04:12:50,496 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-29 04:12:50,496 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:50,497 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 04:12:50,497 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 04:12:50,497 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.09.cil.c_Iteration40_Loop [2023-11-29 04:12:50,497 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 04:12:50,497 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 04:12:50,501 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,503 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,506 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,507 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,509 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,510 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,514 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,515 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,517 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,518 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,520 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,522 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,524 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,525 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,527 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,529 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,531 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,533 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,534 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,536 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,538 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,539 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,541 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,542 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,544 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,545 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,546 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,547 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,549 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,551 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,554 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,556 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,560 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,562 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,565 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,567 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,568 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,570 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,571 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,574 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,576 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,577 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,578 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,579 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,581 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,582 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,584 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,586 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,589 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,592 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,595 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,597 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,600 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,603 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,606 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,608 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,609 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,611 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,614 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,615 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,619 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,622 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,625 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,628 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,630 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,631 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,637 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,639 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,642 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,645 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,647 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,648 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,653 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,654 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,656 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,657 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,659 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,660 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,662 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,663 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,665 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,670 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,673 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,678 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,681 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,688 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,690 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,693 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,696 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,697 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,700 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,701 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,702 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:50,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 04:12:51,233 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 04:12:51,233 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-29 04:12:51,233 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:51,233 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:51,234 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:51,240 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2023-11-29 04:12:51,240 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:51,250 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:51,250 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:51,250 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:51,251 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 04:12:51,251 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:51,251 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 04:12:51,252 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:51,253 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 04:12:51,256 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:51,256 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:51,256 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:51,257 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:51,260 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2023-11-29 04:12:51,261 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 04:12:51,270 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 04:12:51,271 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 04:12:51,271 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 04:12:51,271 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 04:12:51,271 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 04:12:51,272 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 04:12:51,272 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 04:12:51,274 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-29 04:12:51,275 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-29 04:12:51,276 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-29 04:12:51,276 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 04:12:51,276 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 04:12:51,276 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 04:12:51,277 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2023-11-29 04:12:51,279 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-29 04:12:51,279 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-29 04:12:51,279 INFO L513 LassoAnalysis]: Proved termination. [2023-11-29 04:12:51,279 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T6_E~0) = -1*~T6_E~0 + 1 Supporting invariants [] [2023-11-29 04:12:51,282 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Forceful destruction successful, exit code 0 [2023-11-29 04:12:51,282 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-29 04:12:51,290 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:12:51,330 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:51,332 INFO L262 TraceCheckSpWp]: Trace formula consists of 324 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-29 04:12:51,334 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 04:12:51,486 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:12:51,488 INFO L262 TraceCheckSpWp]: Trace formula consists of 299 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-29 04:12:51,490 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 04:12:51,718 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2023-11-29 04:12:51,719 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-29 04:12:51,719 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 214925 states and 277014 transitions. cyclomatic complexity: 62185 Second operand has 5 states, 5 states have (on average 53.2) internal successors, (266), 5 states have internal predecessors, (266), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:51,888 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_88310c04-ba24-41e7-a61d-7353eb6fe10e/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Ended with exit code 0 [2023-11-29 04:12:52,983 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 214925 states and 277014 transitions. cyclomatic complexity: 62185. Second operand has 5 states, 5 states have (on average 53.2) internal successors, (266), 5 states have internal predecessors, (266), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 431112 states and 557363 transitions. Complement of second has 4 states. [2023-11-29 04:12:52,984 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-29 04:12:52,984 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 53.2) internal successors, (266), 5 states have internal predecessors, (266), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:52,985 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1547 transitions. [2023-11-29 04:12:52,985 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1547 transitions. Stem has 116 letters. Loop has 154 letters. [2023-11-29 04:12:52,986 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 04:12:52,986 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1547 transitions. Stem has 270 letters. Loop has 154 letters. [2023-11-29 04:12:52,987 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 04:12:52,987 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1547 transitions. Stem has 116 letters. Loop has 308 letters. [2023-11-29 04:12:52,989 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 04:12:52,989 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 431112 states and 557363 transitions. [2023-11-29 04:12:54,415 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 145056 [2023-11-29 04:12:55,469 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 431112 states to 431112 states and 557363 transitions. [2023-11-29 04:12:55,470 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 146182 [2023-11-29 04:12:55,517 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 146663 [2023-11-29 04:12:55,518 INFO L73 IsDeterministic]: Start isDeterministic. Operand 431112 states and 557363 transitions. [2023-11-29 04:12:55,519 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:12:55,519 INFO L218 hiAutomatonCegarLoop]: Abstraction has 431112 states and 557363 transitions. [2023-11-29 04:12:55,688 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 431112 states and 557363 transitions. [2023-11-29 04:12:58,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 431112 to 430631. [2023-11-29 04:12:58,919 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 430631 states, 430631 states have (on average 1.292062113503208) internal successors, (556402), 430630 states have internal predecessors, (556402), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:12:59,683 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 430631 states to 430631 states and 556402 transitions. [2023-11-29 04:12:59,683 INFO L240 hiAutomatonCegarLoop]: Abstraction has 430631 states and 556402 transitions. [2023-11-29 04:12:59,683 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:12:59,684 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:12:59,684 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:12:59,684 INFO L87 Difference]: Start difference. First operand 430631 states and 556402 transitions. Second operand has 3 states, 3 states have (on average 90.0) internal successors, (270), 2 states have internal predecessors, (270), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:13:01,678 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:13:01,678 INFO L93 Difference]: Finished difference Result 590843 states and 754179 transitions. [2023-11-29 04:13:01,678 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 590843 states and 754179 transitions. [2023-11-29 04:13:04,000 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 199296 [2023-11-29 04:13:04,895 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 590843 states to 590843 states and 754179 transitions. [2023-11-29 04:13:04,895 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 200914 [2023-11-29 04:13:05,231 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 200914 [2023-11-29 04:13:05,231 INFO L73 IsDeterministic]: Start isDeterministic. Operand 590843 states and 754179 transitions. [2023-11-29 04:13:05,231 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 04:13:05,231 INFO L218 hiAutomatonCegarLoop]: Abstraction has 590843 states and 754179 transitions. [2023-11-29 04:13:05,463 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 590843 states and 754179 transitions. [2023-11-29 04:13:09,192 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 590843 to 566459. [2023-11-29 04:13:09,435 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 566459 states, 566459 states have (on average 1.279533028868815) internal successors, (724803), 566458 states have internal predecessors, (724803), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:13:11,040 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 566459 states to 566459 states and 724803 transitions. [2023-11-29 04:13:11,040 INFO L240 hiAutomatonCegarLoop]: Abstraction has 566459 states and 724803 transitions. [2023-11-29 04:13:11,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 04:13:11,041 INFO L428 stractBuchiCegarLoop]: Abstraction has 566459 states and 724803 transitions. [2023-11-29 04:13:11,041 INFO L335 stractBuchiCegarLoop]: ======== Iteration 41 ============ [2023-11-29 04:13:11,041 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 566459 states and 724803 transitions. [2023-11-29 04:13:11,886 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 191168 [2023-11-29 04:13:11,886 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 04:13:11,886 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 04:13:11,887 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:13:11,887 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 04:13:11,887 INFO L748 eck$LassoCheckResult]: Stem: 5259598#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2; 5259599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~11#1;havoc main_~__retres1~11#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1; 5261367#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret26#1, start_simulation_#t~ret27#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5261368#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5261220#L641 assume 1 == ~m_i~0;~m_st~0 := 0; 5261221#L641-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5261162#L646-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5260706#L651-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5260707#L656-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5260250#L661-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5260251#L666-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5261439#L671-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5261128#L676-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5260395#L681-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5259900#L686-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5259901#L922 assume !(0 == ~M_E~0); 5261606#L922-2 assume !(0 == ~T1_E~0); 5261607#L927-1 assume !(0 == ~T2_E~0); 5260858#L932-1 assume !(0 == ~T3_E~0); 5260551#L937-1 assume !(0 == ~T4_E~0); 5260552#L942-1 assume !(0 == ~T5_E~0); 5260705#L947-1 assume !(0 == ~T6_E~0); 5260867#L952-1 assume !(0 == ~T7_E~0); 5260868#L957-1 assume !(0 == ~T8_E~0); 5261005#L962-1 assume !(0 == ~T9_E~0); 5260502#L967-1 assume !(0 == ~E_1~0); 5260503#L972-1 assume !(0 == ~E_2~0); 5261177#L977-1 assume !(0 == ~E_3~0); 5261178#L982-1 assume !(0 == ~E_4~0); 5259465#L987-1 assume !(0 == ~E_5~0); 5259466#L992-1 assume !(0 == ~E_6~0); 5259477#L997-1 assume !(0 == ~E_7~0); 5260335#L1002-1 assume !(0 == ~E_8~0); 5260307#L1007-1 assume !(0 == ~E_9~0); 5259078#L1012-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5259079#L443 assume !(1 == ~m_pc~0); 5260903#L443-2 is_master_triggered_~__retres1~0#1 := 0; 5260880#L454 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5260881#is_master_triggered_returnLabel#1 activate_threads_#t~ret15#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret15#1;havoc activate_threads_#t~ret15#1; 5259781#L1140 assume !(0 != activate_threads_~tmp~1#1); 5259278#L1140-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5259279#L462 assume !(1 == ~t1_pc~0); 5260531#L462-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5260532#L473 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5259154#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5259155#L1148 assume !(0 != activate_threads_~tmp___0~0#1); 5260209#L1148-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5260210#L481 assume !(1 == ~t2_pc~0); 5259770#L481-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5261321#L492 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5261666#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5261664#L1156 assume !(0 != activate_threads_~tmp___1~0#1); 5259941#L1156-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5260145#L500 assume !(1 == ~t3_pc~0); 5261346#L500-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5261258#L511 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5259088#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5259089#L1164 assume !(0 != activate_threads_~tmp___2~0#1); 5259080#L1164-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5259081#L519 assume !(1 == ~t4_pc~0); 5260677#L519-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5260144#L530 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5259280#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5259281#L1172 assume !(0 != activate_threads_~tmp___3~0#1); 5259844#L1172-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5259400#L538 assume !(1 == ~t5_pc~0); 5259401#L538-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5259202#L549 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5259203#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5259748#L1180 assume !(0 != activate_threads_~tmp___4~0#1); 5259749#L1180-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5260967#L557 assume !(1 == ~t6_pc~0); 5259803#L557-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5259804#L568 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5259976#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5259845#L1188 assume !(0 != activate_threads_~tmp___5~0#1); 5259846#L1188-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5261538#L576 assume !(1 == ~t7_pc~0); 5259787#L576-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5260156#L587 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5261594#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5261595#L1196 assume !(0 != activate_threads_~tmp___6~0#1); 5261111#L1196-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5260021#L595 assume !(1 == ~t8_pc~0); 5260022#L595-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5261152#L606 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5260980#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5260761#L1204 assume !(0 != activate_threads_~tmp___7~0#1); 5260762#L1204-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5259650#L614 assume !(1 == ~t9_pc~0); 5259651#L614-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5259447#L625 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5259448#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5260097#L1212 assume !(0 != activate_threads_~tmp___8~0#1); 5259944#L1212-2 havoc activate_threads_#t~ret15#1, activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5259945#L1025 assume !(1 == ~M_E~0); 5260517#L1025-2 assume !(1 == ~T1_E~0); 5260660#L1030-1 assume !(1 == ~T2_E~0); 5260955#L1035-1 assume !(1 == ~T3_E~0); 5259932#L1040-1 assume !(1 == ~T4_E~0); 5259933#L1045-1 assume !(1 == ~T5_E~0); 5259766#L1050-1 assume !(1 == ~T6_E~0); 5259767#L1055-1 assume !(1 == ~T7_E~0); 5259419#L1060-1 assume !(1 == ~T8_E~0); 5259420#L1065-1 assume !(1 == ~T9_E~0); 5259542#L1070-1 assume !(1 == ~E_1~0); 5260869#L1075-1 assume !(1 == ~E_2~0); 5260870#L1080-1 assume !(1 == ~E_3~0); 5260848#L1085-1 assume !(1 == ~E_4~0); 5260849#L1090-1 assume !(1 == ~E_5~0); 5261419#L1095-1 assume !(1 == ~E_6~0); 5260929#L1100-1 assume !(1 == ~E_7~0); 5260930#L1105-1 assume !(1 == ~E_8~0); 5259366#L1110-1 assume !(1 == ~E_9~0); 5259367#L1115-1 assume { :end_inline_reset_delta_events } true; 5260037#L1396-2 assume !false; 5300542#L1397 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5300543#L897-1 [2023-11-29 04:13:11,887 INFO L750 eck$LassoCheckResult]: Loop: 5300543#L897-1 assume !false; 5305156#L762 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;havoc exists_runnable_thread_~__retres1~10#1; 5305153#L699 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~10#1 := 1; 5305151#L751 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~10#1; 5305149#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~10#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5305147#L766 assume 0 != eval_~tmp~0#1; 5305145#L766-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 5305142#L774 assume !(0 != eval_~tmp_ndt_1~0#1); 5305140#L774-2 havoc eval_~tmp_ndt_1~0#1; 5305136#L771-1 assume !(0 == ~t1_st~0); 5305131#L785-1 assume !(0 == ~t2_st~0); 5305127#L799-1 assume !(0 == ~t3_st~0); 5305128#L813-1 assume !(0 == ~t4_st~0); 5307463#L827-1 assume !(0 == ~t5_st~0); 5307449#L841-1 assume !(0 == ~t6_st~0); 5307439#L855-1 assume !(0 == ~t7_st~0); 5305169#L869-1 assume !(0 == ~t8_st~0); 5305162#L883-1 assume !(0 == ~t9_st~0); 5300543#L897-1 [2023-11-29 04:13:11,887 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:13:11,887 INFO L85 PathProgramCache]: Analyzing trace with hash -1585015822, now seen corresponding path program 1 times [2023-11-29 04:13:11,887 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:13:11,888 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [380618712] [2023-11-29 04:13:11,888 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:13:11,888 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:13:11,896 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:13:11,897 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:13:11,903 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:13:11,924 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:13:11,924 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:13:11,924 INFO L85 PathProgramCache]: Analyzing trace with hash 1096957799, now seen corresponding path program 1 times [2023-11-29 04:13:11,924 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:13:11,924 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1517689529] [2023-11-29 04:13:11,924 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:13:11,925 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:13:11,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:13:11,927 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 04:13:11,928 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 04:13:11,930 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 04:13:11,930 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 04:13:11,930 INFO L85 PathProgramCache]: Analyzing trace with hash 1089476888, now seen corresponding path program 1 times [2023-11-29 04:13:11,930 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 04:13:11,930 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1648081905] [2023-11-29 04:13:11,930 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 04:13:11,930 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 04:13:11,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 04:13:11,961 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 04:13:11,961 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 04:13:11,962 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1648081905] [2023-11-29 04:13:11,962 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1648081905] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 04:13:11,962 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 04:13:11,962 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 04:13:11,962 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [981587494] [2023-11-29 04:13:11,962 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 04:13:12,059 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 04:13:12,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 04:13:12,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 04:13:12,060 INFO L87 Difference]: Start difference. First operand 566459 states and 724803 transitions. cyclomatic complexity: 158728 Second operand has 3 states, 3 states have (on average 45.0) internal successors, (135), 3 states have internal predecessors, (135), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 04:13:15,131 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 04:13:15,131 INFO L93 Difference]: Finished difference Result 1017328 states and 1293095 transitions. [2023-11-29 04:13:15,132 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1017328 states and 1293095 transitions. [2023-11-29 04:13:18,596 INFO L131 ngComponentsAnalysis]: Automaton has 192 accepting balls. 336272