./Ultimate.py --spec ../../sv-benchmarks/c/properties/termination.prp --file ../../sv-benchmarks/c/systemc/transmitter.10.cil.c --full-output --architecture 32bit -------------------------------------------------------------------------------- Checking for termination Using default analysis Version 0e0057cc Calling Ultimate with: /usr/lib/jvm/java-1.11.0-openjdk-amd64/bin/java -Dosgi.configuration.area=/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/data/config -Xmx15G -Xms4m -jar /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/plugins/org.eclipse.equinox.launcher_1.5.800.v20200727-1323.jar -data @noDefault -ultimatedata /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/data -tc /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/config/AutomizerTermination.xml -i ../../sv-benchmarks/c/systemc/transmitter.10.cil.c -s /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf --cacsl2boogietranslator.entry.function main --witnessprinter.witness.directory /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya --witnessprinter.witness.filename witness --witnessprinter.write.witness.besides.input.file false --witnessprinter.graph.data.specification CHECK( init(main()), LTL(F end) ) --witnessprinter.graph.data.producer Automizer --witnessprinter.graph.data.architecture 32bit --witnessprinter.graph.data.programhash c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 --- Real Ultimate output --- This is Ultimate 0.2.4-dev-0e0057c [2023-11-29 02:54:16,084 INFO L188 SettingsManager]: Resetting all preferences to default values... [2023-11-29 02:54:16,163 INFO L114 SettingsManager]: Loading settings from /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/config/svcomp-Termination-32bit-Automizer_Default.epf [2023-11-29 02:54:16,167 WARN L101 SettingsManager]: Preference file contains the following unknown settings: [2023-11-29 02:54:16,168 WARN L103 SettingsManager]: * de.uni_freiburg.informatik.ultimate.core.Log level for class [2023-11-29 02:54:16,198 INFO L130 SettingsManager]: Preferences different from defaults after loading the file: [2023-11-29 02:54:16,199 INFO L151 SettingsManager]: Preferences of UltimateCore differ from their defaults: [2023-11-29 02:54:16,200 INFO L153 SettingsManager]: * Log level for class=de.uni_freiburg.informatik.ultimate.lib.smtlibutils.quantifier.QuantifierPusher=ERROR; [2023-11-29 02:54:16,200 INFO L151 SettingsManager]: Preferences of Boogie Preprocessor differ from their defaults: [2023-11-29 02:54:16,201 INFO L153 SettingsManager]: * Use memory slicer=true [2023-11-29 02:54:16,202 INFO L151 SettingsManager]: Preferences of BlockEncodingV2 differ from their defaults: [2023-11-29 02:54:16,202 INFO L153 SettingsManager]: * Create parallel compositions if possible=false [2023-11-29 02:54:16,203 INFO L153 SettingsManager]: * Use SBE=true [2023-11-29 02:54:16,203 INFO L151 SettingsManager]: Preferences of BuchiAutomizer differ from their defaults: [2023-11-29 02:54:16,204 INFO L153 SettingsManager]: * NCSB implementation=INTSET_LAZY3 [2023-11-29 02:54:16,204 INFO L153 SettingsManager]: * Use old map elimination=false [2023-11-29 02:54:16,205 INFO L153 SettingsManager]: * Use external solver (rank synthesis)=false [2023-11-29 02:54:16,205 INFO L153 SettingsManager]: * Use only trivial implications for array writes=true [2023-11-29 02:54:16,206 INFO L153 SettingsManager]: * Rank analysis=LINEAR_WITH_GUESSES [2023-11-29 02:54:16,206 INFO L151 SettingsManager]: Preferences of CACSL2BoogieTranslator differ from their defaults: [2023-11-29 02:54:16,207 INFO L153 SettingsManager]: * Pointer base address is valid at dereference=ASSUME [2023-11-29 02:54:16,207 INFO L153 SettingsManager]: * sizeof long=4 [2023-11-29 02:54:16,207 INFO L153 SettingsManager]: * Overapproximate operations on floating types=true [2023-11-29 02:54:16,208 INFO L153 SettingsManager]: * sizeof POINTER=4 [2023-11-29 02:54:16,208 INFO L153 SettingsManager]: * Check division by zero=IGNORE [2023-11-29 02:54:16,209 INFO L153 SettingsManager]: * Pointer to allocated memory at dereference=ASSUME [2023-11-29 02:54:16,209 INFO L153 SettingsManager]: * If two pointers are subtracted or compared they have the same base address=ASSUME [2023-11-29 02:54:16,209 INFO L153 SettingsManager]: * Check array bounds for arrays that are off heap=ASSUME [2023-11-29 02:54:16,210 INFO L153 SettingsManager]: * Check unreachability of reach_error function=false [2023-11-29 02:54:16,210 INFO L153 SettingsManager]: * sizeof long double=12 [2023-11-29 02:54:16,210 INFO L153 SettingsManager]: * Check if freed pointer was valid=false [2023-11-29 02:54:16,211 INFO L153 SettingsManager]: * Assume nondeterminstic values are in range=false [2023-11-29 02:54:16,211 INFO L153 SettingsManager]: * Use constant arrays=true [2023-11-29 02:54:16,211 INFO L151 SettingsManager]: Preferences of RCFGBuilder differ from their defaults: [2023-11-29 02:54:16,211 INFO L153 SettingsManager]: * Size of a code block=SequenceOfStatements [2023-11-29 02:54:16,211 INFO L151 SettingsManager]: Preferences of TraceAbstraction differ from their defaults: [2023-11-29 02:54:16,212 INFO L153 SettingsManager]: * Trace refinement strategy=CAMEL [2023-11-29 02:54:16,212 INFO L151 SettingsManager]: Preferences of IcfgTransformer differ from their defaults: [2023-11-29 02:54:16,212 INFO L153 SettingsManager]: * TransformationType=MODULO_NEIGHBOR WARNING: An illegal reflective access operation has occurred WARNING: Illegal reflective access by com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 (file:/tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/plugins/com.sun.xml.bind_2.2.0.v201505121915.jar) to method java.lang.ClassLoader.defineClass(java.lang.String,byte[],int,int) WARNING: Please consider reporting this to the maintainers of com.sun.xml.bind.v2.runtime.reflect.opt.Injector$1 WARNING: Use --illegal-access=warn to enable warnings of further illegal reflective access operations WARNING: All illegal access operations will be denied in a future release Applying setting for plugin de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator: Entry function -> main Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness directory -> /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Witness filename -> witness Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Write witness besides input file -> false Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data specification -> CHECK( init(main()), LTL(F end) ) Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data producer -> Automizer Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data architecture -> 32bit Applying setting for plugin de.uni_freiburg.informatik.ultimate.witnessprinter: Graph data programhash -> c68befe0cb772d649d152823cc17c89d77797d55cc04257d4beaaad2b518a7a0 [2023-11-29 02:54:16,438 INFO L75 nceAwareModelManager]: Repository-Root is: /tmp [2023-11-29 02:54:16,458 INFO L261 ainManager$Toolchain]: [Toolchain 1]: Applicable parser(s) successfully (re)initialized [2023-11-29 02:54:16,461 INFO L217 ainManager$Toolchain]: [Toolchain 1]: Toolchain selected. [2023-11-29 02:54:16,462 INFO L270 PluginConnector]: Initializing CDTParser... [2023-11-29 02:54:16,463 INFO L274 PluginConnector]: CDTParser initialized [2023-11-29 02:54:16,464 INFO L431 ainManager$Toolchain]: [Toolchain 1]: Parsing single file: /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/../../sv-benchmarks/c/systemc/transmitter.10.cil.c [2023-11-29 02:54:19,269 INFO L533 CDTParser]: Created temporary CDT project at NULL [2023-11-29 02:54:19,517 INFO L384 CDTParser]: Found 1 translation units. [2023-11-29 02:54:19,518 INFO L180 CDTParser]: Scanning /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/sv-benchmarks/c/systemc/transmitter.10.cil.c [2023-11-29 02:54:19,534 INFO L427 CDTParser]: About to delete temporary CDT project at /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/data/65498bbd3/5af50fe7a5ba465ea4a5d0ee3a84f584/FLAG6647e1118 [2023-11-29 02:54:19,549 INFO L435 CDTParser]: Successfully deleted /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/data/65498bbd3/5af50fe7a5ba465ea4a5d0ee3a84f584 [2023-11-29 02:54:19,551 INFO L299 ainManager$Toolchain]: ####################### [Toolchain 1] ####################### [2023-11-29 02:54:19,553 INFO L133 ToolchainWalker]: Walking toolchain with 6 elements. [2023-11-29 02:54:19,554 INFO L112 PluginConnector]: ------------------------CACSL2BoogieTranslator---------------------------- [2023-11-29 02:54:19,554 INFO L270 PluginConnector]: Initializing CACSL2BoogieTranslator... [2023-11-29 02:54:19,559 INFO L274 PluginConnector]: CACSL2BoogieTranslator initialized [2023-11-29 02:54:19,560 INFO L184 PluginConnector]: Executing the observer ACSLObjectContainerObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:19,561 INFO L204 PluginConnector]: Invalid model from CACSL2BoogieTranslator for observer de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator.ACSLObjectContainerObserver@46d0d495 and model type de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19, skipping insertion in model container [2023-11-29 02:54:19,561 INFO L184 PluginConnector]: Executing the observer CACSL2BoogieTranslatorObserver from plugin CACSL2BoogieTranslator for "CDTParser AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:19,610 INFO L177 MainTranslator]: Built tables and reachable declarations [2023-11-29 02:54:19,855 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 02:54:19,872 INFO L202 MainTranslator]: Completed pre-run [2023-11-29 02:54:19,943 INFO L209 PostProcessor]: Analyzing one entry point: main [2023-11-29 02:54:19,967 INFO L206 MainTranslator]: Completed translation [2023-11-29 02:54:19,968 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19 WrapperNode [2023-11-29 02:54:19,968 INFO L131 PluginConnector]: ------------------------ END CACSL2BoogieTranslator---------------------------- [2023-11-29 02:54:19,969 INFO L112 PluginConnector]: ------------------------Boogie Procedure Inliner---------------------------- [2023-11-29 02:54:19,970 INFO L270 PluginConnector]: Initializing Boogie Procedure Inliner... [2023-11-29 02:54:19,970 INFO L274 PluginConnector]: Boogie Procedure Inliner initialized [2023-11-29 02:54:19,978 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:19,992 INFO L184 PluginConnector]: Executing the observer Inliner from plugin Boogie Procedure Inliner for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,080 INFO L138 Inliner]: procedures = 48, calls = 61, calls flagged for inlining = 56, calls inlined = 197, statements flattened = 3016 [2023-11-29 02:54:20,081 INFO L131 PluginConnector]: ------------------------ END Boogie Procedure Inliner---------------------------- [2023-11-29 02:54:20,082 INFO L112 PluginConnector]: ------------------------Boogie Preprocessor---------------------------- [2023-11-29 02:54:20,082 INFO L270 PluginConnector]: Initializing Boogie Preprocessor... [2023-11-29 02:54:20,082 INFO L274 PluginConnector]: Boogie Preprocessor initialized [2023-11-29 02:54:20,092 INFO L184 PluginConnector]: Executing the observer EnsureBoogieModelObserver from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,092 INFO L184 PluginConnector]: Executing the observer TypeChecker from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,105 INFO L184 PluginConnector]: Executing the observer MemorySlicer from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,140 INFO L175 MemorySlicer]: Split 2 memory accesses to 1 slices as follows [2]. 100 percent of accesses are in the largest equivalence class. The 2 initializations are split as follows [2]. The 0 writes are split as follows [0]. [2023-11-29 02:54:20,141 INFO L184 PluginConnector]: Executing the observer ConstExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,141 INFO L184 PluginConnector]: Executing the observer StructExpander from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,179 INFO L184 PluginConnector]: Executing the observer UnstructureCode from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,211 INFO L184 PluginConnector]: Executing the observer FunctionInliner from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,217 INFO L184 PluginConnector]: Executing the observer LTLStepAnnotator from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,226 INFO L184 PluginConnector]: Executing the observer BoogieSymbolTableConstructor from plugin Boogie Preprocessor for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,235 INFO L131 PluginConnector]: ------------------------ END Boogie Preprocessor---------------------------- [2023-11-29 02:54:20,236 INFO L112 PluginConnector]: ------------------------RCFGBuilder---------------------------- [2023-11-29 02:54:20,236 INFO L270 PluginConnector]: Initializing RCFGBuilder... [2023-11-29 02:54:20,237 INFO L274 PluginConnector]: RCFGBuilder initialized [2023-11-29 02:54:20,237 INFO L184 PluginConnector]: Executing the observer RCFGBuilderObserver from plugin RCFGBuilder for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (1/1) ... [2023-11-29 02:54:20,242 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:54:20,252 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:54:20,264 INFO L229 MonitoredProcess]: Starting monitored process 1 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:54:20,280 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (1)] Waiting until timeout for monitored process [2023-11-29 02:54:20,306 INFO L130 BoogieDeclarations]: Found specification of procedure #Ultimate.allocInit [2023-11-29 02:54:20,306 INFO L130 BoogieDeclarations]: Found specification of procedure write~init~int#0 [2023-11-29 02:54:20,306 INFO L130 BoogieDeclarations]: Found specification of procedure ULTIMATE.start [2023-11-29 02:54:20,307 INFO L138 BoogieDeclarations]: Found implementation of procedure ULTIMATE.start [2023-11-29 02:54:20,410 INFO L241 CfgBuilder]: Building ICFG [2023-11-29 02:54:20,412 INFO L267 CfgBuilder]: Building CFG for each procedure with an implementation [2023-11-29 02:54:21,979 INFO L282 CfgBuilder]: Performing block encoding [2023-11-29 02:54:22,013 INFO L304 CfgBuilder]: Using the 1 location(s) as analysis (start of procedure ULTIMATE.start) [2023-11-29 02:54:22,013 INFO L309 CfgBuilder]: Removed 14 assume(true) statements. [2023-11-29 02:54:22,015 INFO L201 PluginConnector]: Adding new model de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 02:54:22 BoogieIcfgContainer [2023-11-29 02:54:22,016 INFO L131 PluginConnector]: ------------------------ END RCFGBuilder---------------------------- [2023-11-29 02:54:22,017 INFO L112 PluginConnector]: ------------------------BuchiAutomizer---------------------------- [2023-11-29 02:54:22,017 INFO L270 PluginConnector]: Initializing BuchiAutomizer... [2023-11-29 02:54:22,021 INFO L274 PluginConnector]: BuchiAutomizer initialized [2023-11-29 02:54:22,022 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 02:54:22,022 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "CDTParser AST 29.11 02:54:19" (1/3) ... [2023-11-29 02:54:22,023 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@287c9daf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 02:54:22, skipping insertion in model container [2023-11-29 02:54:22,023 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 02:54:22,023 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.cacsl2boogietranslator AST 29.11 02:54:19" (2/3) ... [2023-11-29 02:54:22,024 INFO L204 PluginConnector]: Invalid model from BuchiAutomizer for observer de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer.BuchiAutomizerObserver@287c9daf and model type de.uni_freiburg.informatik.ultimate.plugins.generator.buchiautomizer AST 29.11 02:54:22, skipping insertion in model container [2023-11-29 02:54:22,024 INFO L99 BuchiAutomizer]: Safety of program was proven or not checked, starting termination analysis [2023-11-29 02:54:22,024 INFO L184 PluginConnector]: Executing the observer BuchiAutomizerObserver from plugin BuchiAutomizer for "de.uni_freiburg.informatik.ultimate.plugins.generator.rcfgbuilder CFG 29.11 02:54:22" (3/3) ... [2023-11-29 02:54:22,025 INFO L332 chiAutomizerObserver]: Analyzing ICFG transmitter.10.cil.c [2023-11-29 02:54:22,104 INFO L303 stractBuchiCegarLoop]: Interprodecural is true [2023-11-29 02:54:22,105 INFO L304 stractBuchiCegarLoop]: Hoare is false [2023-11-29 02:54:22,105 INFO L305 stractBuchiCegarLoop]: Compute interpolants for ForwardPredicates [2023-11-29 02:54:22,105 INFO L306 stractBuchiCegarLoop]: Backedges is STRAIGHT_LINE [2023-11-29 02:54:22,105 INFO L307 stractBuchiCegarLoop]: Determinization is PREDICATE_ABSTRACTION [2023-11-29 02:54:22,105 INFO L308 stractBuchiCegarLoop]: Difference is false [2023-11-29 02:54:22,105 INFO L309 stractBuchiCegarLoop]: Minimize is MINIMIZE_SEVPA [2023-11-29 02:54:22,106 INFO L313 stractBuchiCegarLoop]: ======== Iteration 0 == of CEGAR loop == BuchiAutomatonCegarLoop ======== [2023-11-29 02:54:22,116 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1297 states, 1296 states have (on average 1.5046296296296295) internal successors, (1950), 1296 states have internal predecessors, (1950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:22,178 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1156 [2023-11-29 02:54:22,179 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:22,179 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:22,195 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:22,195 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:22,195 INFO L335 stractBuchiCegarLoop]: ======== Iteration 1 ============ [2023-11-29 02:54:22,199 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand has 1297 states, 1296 states have (on average 1.5046296296296295) internal successors, (1950), 1296 states have internal predecessors, (1950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:22,217 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1156 [2023-11-29 02:54:22,218 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:22,218 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:22,223 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:22,223 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:22,234 INFO L748 eck$LassoCheckResult]: Stem: 182#$Ultimate##0true assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1179#L-1true assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 951#init_model_returnLabel#1true assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1175#update_channels_returnLabel#1true assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1282#L701true assume !(1 == ~m_i~0);~m_st~0 := 2; 1156#L701-2true assume 1 == ~t1_i~0;~t1_st~0 := 0; 1178#L706-1true assume !(1 == ~t2_i~0);~t2_st~0 := 2; 269#L711-1true assume !(1 == ~t3_i~0);~t3_st~0 := 2; 136#L716-1true assume !(1 == ~t4_i~0);~t4_st~0 := 2; 1200#L721-1true assume !(1 == ~t5_i~0);~t5_st~0 := 2; 891#L726-1true assume !(1 == ~t6_i~0);~t6_st~0 := 2; 1085#L731-1true assume !(1 == ~t7_i~0);~t7_st~0 := 2; 861#L736-1true assume !(1 == ~t8_i~0);~t8_st~0 := 2; 936#L741-1true assume 1 == ~t9_i~0;~t9_st~0 := 0; 1236#L746-1true assume !(1 == ~t10_i~0);~t10_st~0 := 2; 161#L751-1true assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 798#L1006true assume !(0 == ~M_E~0); 84#L1006-2true assume !(0 == ~T1_E~0); 994#L1011-1true assume !(0 == ~T2_E~0); 1036#L1016-1true assume 0 == ~T3_E~0;~T3_E~0 := 1; 1182#L1021-1true assume !(0 == ~T4_E~0); 24#L1026-1true assume !(0 == ~T5_E~0); 1250#L1031-1true assume !(0 == ~T6_E~0); 566#L1036-1true assume !(0 == ~T7_E~0); 564#L1041-1true assume !(0 == ~T8_E~0); 908#L1046-1true assume !(0 == ~T9_E~0); 177#L1051-1true assume !(0 == ~T10_E~0); 706#L1056-1true assume 0 == ~E_1~0;~E_1~0 := 1; 754#L1061-1true assume !(0 == ~E_2~0); 138#L1066-1true assume !(0 == ~E_3~0); 1077#L1071-1true assume !(0 == ~E_4~0); 682#L1076-1true assume !(0 == ~E_5~0); 88#L1081-1true assume !(0 == ~E_6~0); 257#L1086-1true assume !(0 == ~E_7~0); 1091#L1091-1true assume !(0 == ~E_8~0); 967#L1096-1true assume 0 == ~E_9~0;~E_9~0 := 1; 1183#L1101-1true assume !(0 == ~E_10~0); 298#L1106-1true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1108#L484true assume !(1 == ~m_pc~0); 365#L484-2true is_master_triggered_~__retres1~0#1 := 0; 495#L495true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 807#is_master_triggered_returnLabel#1true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 801#L1245true assume !(0 != activate_threads_~tmp~1#1); 1221#L1245-2true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 558#L503true assume 1 == ~t1_pc~0; 571#L504true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 738#L514true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 44#is_transmit1_triggered_returnLabel#1true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 381#L1253true assume !(0 != activate_threads_~tmp___0~0#1); 42#L1253-2true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 912#L522true assume !(1 == ~t2_pc~0); 526#L522-2true is_transmit2_triggered_~__retres1~2#1 := 0; 144#L533true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 294#is_transmit2_triggered_returnLabel#1true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 892#L1261true assume !(0 != activate_threads_~tmp___1~0#1); 1213#L1261-2true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1059#L541true assume 1 == ~t3_pc~0; 483#L542true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 836#L552true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 16#is_transmit3_triggered_returnLabel#1true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 593#L1269true assume !(0 != activate_threads_~tmp___2~0#1); 531#L1269-2true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 982#L560true assume !(1 == ~t4_pc~0); 1083#L560-2true is_transmit4_triggered_~__retres1~4#1 := 0; 459#L571true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 95#is_transmit4_triggered_returnLabel#1true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23#L1277true assume !(0 != activate_threads_~tmp___3~0#1); 898#L1277-2true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 166#L579true assume 1 == ~t5_pc~0; 2#L580true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 55#L590true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 811#is_transmit5_triggered_returnLabel#1true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1034#L1285true assume !(0 != activate_threads_~tmp___4~0#1); 1111#L1285-2true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1276#L598true assume 1 == ~t6_pc~0; 212#L599true assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 402#L609true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 281#is_transmit6_triggered_returnLabel#1true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 844#L1293true assume !(0 != activate_threads_~tmp___5~0#1); 600#L1293-2true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 552#L617true assume !(1 == ~t7_pc~0); 455#L617-2true is_transmit7_triggered_~__retres1~7#1 := 0; 1193#L628true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1203#is_transmit7_triggered_returnLabel#1true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 914#L1301true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 314#L1301-2true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 597#L636true assume 1 == ~t8_pc~0; 440#L637true assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 789#L647true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 739#is_transmit8_triggered_returnLabel#1true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 609#L1309true assume !(0 != activate_threads_~tmp___7~0#1); 408#L1309-2true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 687#L655true assume !(1 == ~t9_pc~0); 770#L655-2true is_transmit9_triggered_~__retres1~9#1 := 0; 1138#L666true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 340#is_transmit9_triggered_returnLabel#1true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1041#L1317true assume !(0 != activate_threads_~tmp___8~0#1); 621#L1317-2true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 979#L674true assume 1 == ~t10_pc~0; 78#L675true assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1065#L685true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 432#is_transmit10_triggered_returnLabel#1true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1296#L1325true assume !(0 != activate_threads_~tmp___9~0#1); 400#L1325-2true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 901#L1119true assume !(1 == ~M_E~0); 127#L1119-2true assume !(1 == ~T1_E~0); 349#L1124-1true assume !(1 == ~T2_E~0); 37#L1129-1true assume !(1 == ~T3_E~0); 538#L1134-1true assume !(1 == ~T4_E~0); 192#L1139-1true assume !(1 == ~T5_E~0); 312#L1144-1true assume 1 == ~T6_E~0;~T6_E~0 := 2; 1256#L1149-1true assume !(1 == ~T7_E~0); 124#L1154-1true assume !(1 == ~T8_E~0); 168#L1159-1true assume !(1 == ~T9_E~0); 1227#L1164-1true assume !(1 == ~T10_E~0); 419#L1169-1true assume !(1 == ~E_1~0); 343#L1174-1true assume !(1 == ~E_2~0); 219#L1179-1true assume !(1 == ~E_3~0); 163#L1184-1true assume 1 == ~E_4~0;~E_4~0 := 2; 190#L1189-1true assume !(1 == ~E_5~0); 247#L1194-1true assume !(1 == ~E_6~0); 1271#L1199-1true assume !(1 == ~E_7~0); 226#L1204-1true assume !(1 == ~E_8~0); 1134#L1209-1true assume !(1 == ~E_9~0); 619#L1214-1true assume !(1 == ~E_10~0); 1226#L1219-1true assume { :end_inline_reset_delta_events } true; 17#L1520-2true [2023-11-29 02:54:22,237 INFO L750 eck$LassoCheckResult]: Loop: 17#L1520-2true assume !false; 1279#L1521true start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 683#L981-1true assume !true; 749#eval_returnLabel#1true havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 450#update_channels_returnLabel#2true assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 309#L1006-3true assume !(0 == ~M_E~0); 976#L1006-5true assume 0 == ~T1_E~0;~T1_E~0 := 1; 735#L1011-3true assume 0 == ~T2_E~0;~T2_E~0 := 1; 986#L1016-3true assume 0 == ~T3_E~0;~T3_E~0 := 1; 784#L1021-3true assume 0 == ~T4_E~0;~T4_E~0 := 1; 460#L1026-3true assume 0 == ~T5_E~0;~T5_E~0 := 1; 1152#L1031-3true assume 0 == ~T6_E~0;~T6_E~0 := 1; 701#L1036-3true assume 0 == ~T7_E~0;~T7_E~0 := 1; 1222#L1041-3true assume !(0 == ~T8_E~0); 777#L1046-3true assume 0 == ~T9_E~0;~T9_E~0 := 1; 1107#L1051-3true assume 0 == ~T10_E~0;~T10_E~0 := 1; 702#L1056-3true assume 0 == ~E_1~0;~E_1~0 := 1; 175#L1061-3true assume 0 == ~E_2~0;~E_2~0 := 1; 176#L1066-3true assume 0 == ~E_3~0;~E_3~0 := 1; 1239#L1071-3true assume 0 == ~E_4~0;~E_4~0 := 1; 1008#L1076-3true assume 0 == ~E_5~0;~E_5~0 := 1; 69#L1081-3true assume !(0 == ~E_6~0); 1153#L1086-3true assume 0 == ~E_7~0;~E_7~0 := 1; 90#L1091-3true assume 0 == ~E_8~0;~E_8~0 := 1; 1068#L1096-3true assume 0 == ~E_9~0;~E_9~0 := 1; 940#L1101-3true assume 0 == ~E_10~0;~E_10~0 := 1; 1001#L1106-3true assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 480#L484-33true assume 1 == ~m_pc~0; 1190#L485-11true assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 412#L495-11true is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 766#is_master_triggered_returnLabel#12true activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20#L1245-33true assume !(0 != activate_threads_~tmp~1#1); 636#L1245-35true assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 251#L503-33true assume 1 == ~t1_pc~0; 1191#L504-11true assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 603#L514-11true is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1161#is_transmit1_triggered_returnLabel#12true activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 209#L1253-33true assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 647#L1253-35true assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 506#L522-33true assume !(1 == ~t2_pc~0); 1169#L522-35true is_transmit2_triggered_~__retres1~2#1 := 0; 86#L533-11true is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 716#is_transmit2_triggered_returnLabel#12true activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 813#L1261-33true assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 524#L1261-35true assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 887#L541-33true assume 1 == ~t3_pc~0; 96#L542-11true assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 19#L552-11true is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 101#is_transmit3_triggered_returnLabel#12true activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 500#L1269-33true assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 944#L1269-35true assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 698#L560-33true assume 1 == ~t4_pc~0; 414#L561-11true assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 58#L571-11true is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1013#is_transmit4_triggered_returnLabel#12true activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1090#L1277-33true assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 673#L1277-35true assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 14#L579-33true assume 1 == ~t5_pc~0; 456#L580-11true assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 1053#L590-11true is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1100#is_transmit5_triggered_returnLabel#12true activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 553#L1285-33true assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 575#L1285-35true assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1055#L598-33true assume !(1 == ~t6_pc~0); 386#L598-35true is_transmit6_triggered_~__retres1~6#1 := 0; 263#L609-11true is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 376#is_transmit6_triggered_returnLabel#12true activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 189#L1293-33true assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 913#L1293-35true assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1166#L617-33true assume 1 == ~t7_pc~0; 932#L618-11true assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 782#L628-11true is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 823#is_transmit7_triggered_returnLabel#12true activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1140#L1301-33true assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 1010#L1301-35true assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 52#L636-33true assume !(1 == ~t8_pc~0); 1029#L636-35true is_transmit8_triggered_~__retres1~8#1 := 0; 666#L647-11true is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 525#is_transmit8_triggered_returnLabel#12true activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1071#L1309-33true assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 654#L1309-35true assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1269#L655-33true assume !(1 == ~t9_pc~0); 1198#L655-35true is_transmit9_triggered_~__retres1~9#1 := 0; 238#L666-11true is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 720#is_transmit9_triggered_returnLabel#12true activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 756#L1317-33true assume !(0 != activate_threads_~tmp___8~0#1); 1019#L1317-35true assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 342#L674-33true assume !(1 == ~t10_pc~0); 1049#L674-35true is_transmit10_triggered_~__retres1~10#1 := 0; 1082#L685-11true is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 835#is_transmit10_triggered_returnLabel#12true activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 513#L1325-33true assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1076#L1325-35true havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1114#L1119-3true assume 1 == ~M_E~0;~M_E~0 := 2; 1120#L1119-5true assume 1 == ~T1_E~0;~T1_E~0 := 2; 1274#L1124-3true assume 1 == ~T2_E~0;~T2_E~0 := 2; 1162#L1129-3true assume !(1 == ~T3_E~0); 207#L1134-3true assume 1 == ~T4_E~0;~T4_E~0 := 2; 497#L1139-3true assume 1 == ~T5_E~0;~T5_E~0 := 2; 335#L1144-3true assume 1 == ~T6_E~0;~T6_E~0 := 2; 445#L1149-3true assume 1 == ~T7_E~0;~T7_E~0 := 2; 1260#L1154-3true assume 1 == ~T8_E~0;~T8_E~0 := 2; 710#L1159-3true assume 1 == ~T9_E~0;~T9_E~0 := 2; 1243#L1164-3true assume 1 == ~T10_E~0;~T10_E~0 := 2; 1024#L1169-3true assume !(1 == ~E_1~0); 262#L1174-3true assume 1 == ~E_2~0;~E_2~0 := 2; 1104#L1179-3true assume 1 == ~E_3~0;~E_3~0 := 2; 846#L1184-3true assume 1 == ~E_4~0;~E_4~0 := 2; 81#L1189-3true assume 1 == ~E_5~0;~E_5~0 := 2; 851#L1194-3true assume 1 == ~E_6~0;~E_6~0 := 2; 235#L1199-3true assume 1 == ~E_7~0;~E_7~0 := 2; 1278#L1204-3true assume 1 == ~E_8~0;~E_8~0 := 2; 433#L1209-3true assume !(1 == ~E_9~0); 27#L1214-3true assume 1 == ~E_10~0;~E_10~0 := 2; 948#L1219-3true assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 611#L764-1true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 959#L821-1true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 256#exists_runnable_thread_returnLabel#2true start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 296#L1539true assume !(0 == start_simulation_~tmp~3#1); 501#L1539-2true assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 420#L764-2true assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 876#L821-2true exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 41#exists_runnable_thread_returnLabel#3true stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 240#L1494true assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 745#L1501true stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 470#stop_simulation_returnLabel#1true start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 297#L1552true assume !(0 != start_simulation_~tmp___0~1#1); 17#L1520-2true [2023-11-29 02:54:22,245 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:22,246 INFO L85 PathProgramCache]: Analyzing trace with hash 1310232617, now seen corresponding path program 1 times [2023-11-29 02:54:22,256 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:22,256 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1772762201] [2023-11-29 02:54:22,257 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:22,257 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:22,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:22,552 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:22,552 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:22,553 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1772762201] [2023-11-29 02:54:22,554 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1772762201] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:22,554 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:22,554 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:22,555 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382663220] [2023-11-29 02:54:22,556 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:22,560 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:22,560 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:22,561 INFO L85 PathProgramCache]: Analyzing trace with hash 939086972, now seen corresponding path program 1 times [2023-11-29 02:54:22,561 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:22,561 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [438168233] [2023-11-29 02:54:22,561 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:22,561 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:22,580 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:22,625 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:22,625 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:22,626 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [438168233] [2023-11-29 02:54:22,626 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [438168233] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:22,626 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:22,627 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:54:22,627 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [766765769] [2023-11-29 02:54:22,627 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:22,629 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:22,630 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:22,676 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:22,677 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:22,682 INFO L87 Difference]: Start difference. First operand has 1297 states, 1296 states have (on average 1.5046296296296295) internal successors, (1950), 1296 states have internal predecessors, (1950), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:22,764 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:22,764 INFO L93 Difference]: Finished difference Result 1295 states and 1918 transitions. [2023-11-29 02:54:22,766 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1295 states and 1918 transitions. [2023-11-29 02:54:22,780 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:22,797 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1295 states to 1289 states and 1912 transitions. [2023-11-29 02:54:22,799 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-29 02:54:22,801 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-29 02:54:22,802 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1912 transitions. [2023-11-29 02:54:22,810 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:22,810 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1912 transitions. [2023-11-29 02:54:22,833 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1912 transitions. [2023-11-29 02:54:22,880 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-29 02:54:22,884 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4833204034134988) internal successors, (1912), 1288 states have internal predecessors, (1912), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:22,890 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1912 transitions. [2023-11-29 02:54:22,891 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1912 transitions. [2023-11-29 02:54:22,892 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:22,896 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1912 transitions. [2023-11-29 02:54:22,896 INFO L335 stractBuchiCegarLoop]: ======== Iteration 2 ============ [2023-11-29 02:54:22,897 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1912 transitions. [2023-11-29 02:54:22,906 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:22,906 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:22,906 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:22,909 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:22,910 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:22,911 INFO L748 eck$LassoCheckResult]: Stem: 2961#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 2962#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3814#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3815#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3882#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3876#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3877#L706-1 assume !(1 == ~t2_i~0);~t2_st~0 := 2; 3130#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 2873#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 2874#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 3783#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 3784#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 3765#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 3766#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3806#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 2924#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2925#L1006 assume !(0 == ~M_E~0); 2776#L1006-2 assume !(0 == ~T1_E~0); 2777#L1011-1 assume !(0 == ~T2_E~0); 3831#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3848#L1021-1 assume !(0 == ~T4_E~0); 2654#L1026-1 assume !(0 == ~T5_E~0); 2655#L1031-1 assume !(0 == ~T6_E~0); 3542#L1036-1 assume !(0 == ~T7_E~0); 3539#L1041-1 assume !(0 == ~T8_E~0); 3540#L1046-1 assume !(0 == ~T9_E~0); 2952#L1051-1 assume !(0 == ~T10_E~0); 2953#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 3669#L1061-1 assume !(0 == ~E_2~0); 2877#L1066-1 assume !(0 == ~E_3~0); 2878#L1071-1 assume !(0 == ~E_4~0); 3644#L1076-1 assume !(0 == ~E_5~0); 2784#L1081-1 assume !(0 == ~E_6~0); 2785#L1086-1 assume !(0 == ~E_7~0); 3104#L1091-1 assume !(0 == ~E_8~0); 3823#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 3824#L1101-1 assume !(0 == ~E_10~0); 3173#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3174#L484 assume !(1 == ~m_pc~0); 2834#L484-2 is_master_triggered_~__retres1~0#1 := 0; 2833#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3456#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3737#L1245 assume !(0 != activate_threads_~tmp~1#1); 3738#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3529#L503 assume 1 == ~t1_pc~0; 3530#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3549#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2695#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2696#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 2689#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2690#L522 assume !(1 == ~t2_pc~0); 3495#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2888#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2889#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3168#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3785#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3856#L541 assume 1 == ~t3_pc~0; 3438#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 3240#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2636#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2637#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3501#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3502#L560 assume !(1 == ~t4_pc~0); 2770#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2769#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2800#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2650#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 2651#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2933#L579 assume 1 == ~t5_pc~0; 2601#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2602#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2715#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3742#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3847#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3866#L598 assume 1 == ~t6_pc~0; 3017#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 3018#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3145#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3146#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3575#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3520#L617 assume !(1 == ~t7_pc~0); 2993#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2992#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3886#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3797#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3207#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3208#L636 assume 1 == ~t8_pc~0; 3391#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3392#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3698#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3584#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3340#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3341#L655 assume !(1 == ~t9_pc~0); 3368#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3369#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3254#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3255#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3595#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3596#L674 assume 1 == ~t10_pc~0; 2761#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 2762#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3382#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3383#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3329#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3330#L1119 assume !(1 == ~M_E~0); 2860#L1119-2 assume !(1 == ~T1_E~0); 2861#L1124-1 assume !(1 == ~T2_E~0); 2679#L1129-1 assume !(1 == ~T3_E~0); 2680#L1134-1 assume !(1 == ~T4_E~0); 2978#L1139-1 assume !(1 == ~T5_E~0); 2979#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3203#L1149-1 assume !(1 == ~T7_E~0); 2854#L1154-1 assume !(1 == ~T8_E~0); 2855#L1159-1 assume !(1 == ~T9_E~0); 2936#L1164-1 assume !(1 == ~T10_E~0); 3357#L1169-1 assume !(1 == ~E_1~0); 3256#L1174-1 assume !(1 == ~E_2~0); 3030#L1179-1 assume !(1 == ~E_3~0); 2926#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2927#L1189-1 assume !(1 == ~E_5~0); 2976#L1194-1 assume !(1 == ~E_6~0); 3082#L1199-1 assume !(1 == ~E_7~0); 3042#L1204-1 assume !(1 == ~E_8~0); 3043#L1209-1 assume !(1 == ~E_9~0); 3593#L1214-1 assume !(1 == ~E_10~0); 3594#L1219-1 assume { :end_inline_reset_delta_events } true; 2638#L1520-2 [2023-11-29 02:54:22,912 INFO L750 eck$LassoCheckResult]: Loop: 2638#L1520-2 assume !false; 2639#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3430#L981-1 assume !false; 3615#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3616#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2622#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3223#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3224#L836 assume !(0 != eval_~tmp~0#1); 3707#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3399#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3195#L1006-3 assume !(0 == ~M_E~0); 3196#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3693#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 3694#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 3731#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3410#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3411#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 3661#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3662#L1041-3 assume !(0 == ~T8_E~0); 3725#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3726#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3663#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 2949#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2950#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2951#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3834#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2743#L1081-3 assume !(0 == ~E_6~0); 2744#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2791#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2792#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 3807#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3808#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3432#L484-33 assume !(1 == ~m_pc~0); 3433#L484-35 is_master_triggered_~__retres1~0#1 := 0; 3343#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3344#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2644#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 2645#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3090#L503-33 assume 1 == ~t1_pc~0; 3091#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 3578#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3579#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3011#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3012#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3470#L522-33 assume 1 == ~t2_pc~0; 3472#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2781#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2782#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3679#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3493#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3494#L541-33 assume 1 == ~t3_pc~0; 2801#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 2642#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2643#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2813#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3462#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3659#L560-33 assume 1 == ~t4_pc~0; 3347#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2719#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2720#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3836#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3638#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2628#L579-33 assume 1 == ~t5_pc~0; 2629#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 2881#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3852#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3521#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3522#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3548#L598-33 assume !(1 == ~t6_pc~0); 3304#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3114#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3115#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2973#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2974#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3796#L617-33 assume !(1 == ~t7_pc~0); 2774#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2775#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3730#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3749#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3835#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2709#L636-33 assume 1 == ~t8_pc~0; 2710#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 3631#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3491#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3492#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3620#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3621#L655-33 assume 1 == ~t9_pc~0; 3883#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3059#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3060#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3682#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 3711#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3253#L674-33 assume 1 == ~t10_pc~0; 3109#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 3110#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3755#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3479#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3480#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3857#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3867#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3869#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 3879#L1129-3 assume !(1 == ~T3_E~0); 3004#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3005#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3242#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 3243#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3397#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3674#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3675#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3842#L1169-3 assume !(1 == ~E_1~0); 3112#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3113#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3760#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2766#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2767#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3057#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3058#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3381#L1209-3 assume !(1 == ~E_9~0); 2656#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2657#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3583#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2746#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3100#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3101#L1539 assume !(0 == start_simulation_~tmp~3#1); 3171#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3358#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3153#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2685#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2686#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3065#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3419#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3172#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 2638#L1520-2 [2023-11-29 02:54:22,913 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:22,913 INFO L85 PathProgramCache]: Analyzing trace with hash -934325781, now seen corresponding path program 1 times [2023-11-29 02:54:22,914 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:22,914 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [704281497] [2023-11-29 02:54:22,914 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:22,915 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:22,938 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:22,996 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:22,997 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:22,997 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [704281497] [2023-11-29 02:54:22,997 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [704281497] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:22,997 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:22,998 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:22,998 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1222544129] [2023-11-29 02:54:22,998 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:22,999 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:22,999 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:23,000 INFO L85 PathProgramCache]: Analyzing trace with hash 867756010, now seen corresponding path program 1 times [2023-11-29 02:54:23,000 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:23,000 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1592688732] [2023-11-29 02:54:23,001 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:23,001 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:23,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:23,100 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:23,100 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:23,101 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1592688732] [2023-11-29 02:54:23,101 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1592688732] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:23,101 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:23,102 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:23,102 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [886510288] [2023-11-29 02:54:23,102 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:23,103 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:23,103 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:23,103 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:23,104 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:23,104 INFO L87 Difference]: Start difference. First operand 1289 states and 1912 transitions. cyclomatic complexity: 624 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:23,144 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:23,144 INFO L93 Difference]: Finished difference Result 1289 states and 1911 transitions. [2023-11-29 02:54:23,144 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1911 transitions. [2023-11-29 02:54:23,155 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:23,166 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1911 transitions. [2023-11-29 02:54:23,166 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-29 02:54:23,168 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-29 02:54:23,168 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1911 transitions. [2023-11-29 02:54:23,170 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:23,171 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1911 transitions. [2023-11-29 02:54:23,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1911 transitions. [2023-11-29 02:54:23,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-29 02:54:23,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.482544608223429) internal successors, (1911), 1288 states have internal predecessors, (1911), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:23,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1911 transitions. [2023-11-29 02:54:23,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1911 transitions. [2023-11-29 02:54:23,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:23,204 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1911 transitions. [2023-11-29 02:54:23,204 INFO L335 stractBuchiCegarLoop]: ======== Iteration 3 ============ [2023-11-29 02:54:23,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1911 transitions. [2023-11-29 02:54:23,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:23,213 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:23,213 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:23,215 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:23,216 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:23,216 INFO L748 eck$LassoCheckResult]: Stem: 5546#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 5547#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6399#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6400#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6467#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 6461#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6462#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5715#L711-1 assume !(1 == ~t3_i~0);~t3_st~0 := 2; 5460#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 5461#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 6368#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 6369#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 6350#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 6351#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6391#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 5509#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5510#L1006 assume !(0 == ~M_E~0); 5364#L1006-2 assume !(0 == ~T1_E~0); 5365#L1011-1 assume !(0 == ~T2_E~0); 6416#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6433#L1021-1 assume !(0 == ~T4_E~0); 5239#L1026-1 assume !(0 == ~T5_E~0); 5240#L1031-1 assume !(0 == ~T6_E~0); 6129#L1036-1 assume !(0 == ~T7_E~0); 6124#L1041-1 assume !(0 == ~T8_E~0); 6125#L1046-1 assume !(0 == ~T9_E~0); 5537#L1051-1 assume !(0 == ~T10_E~0); 5538#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 6254#L1061-1 assume !(0 == ~E_2~0); 5462#L1066-1 assume !(0 == ~E_3~0); 5463#L1071-1 assume !(0 == ~E_4~0); 6229#L1076-1 assume !(0 == ~E_5~0); 5369#L1081-1 assume !(0 == ~E_6~0); 5370#L1086-1 assume !(0 == ~E_7~0); 5689#L1091-1 assume !(0 == ~E_8~0); 6408#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 6409#L1101-1 assume !(0 == ~E_10~0); 5758#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5759#L484 assume !(1 == ~m_pc~0); 5421#L484-2 is_master_triggered_~__retres1~0#1 := 0; 5420#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6041#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6322#L1245 assume !(0 != activate_threads_~tmp~1#1); 6323#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6114#L503 assume 1 == ~t1_pc~0; 6115#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6136#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5280#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5281#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 5276#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5277#L522 assume !(1 == ~t2_pc~0); 6080#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5474#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5475#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5754#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 6370#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6441#L541 assume 1 == ~t3_pc~0; 6025#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5825#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5221#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5222#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 6090#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6091#L560 assume !(1 == ~t4_pc~0); 5355#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5354#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5385#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5235#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 5236#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5520#L579 assume 1 == ~t5_pc~0; 5186#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5187#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5300#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6327#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 6432#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6451#L598 assume 1 == ~t6_pc~0; 5602#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 5603#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5731#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5732#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 6160#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6105#L617 assume !(1 == ~t7_pc~0); 5578#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5577#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6471#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6382#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 5795#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5796#L636 assume 1 == ~t8_pc~0; 5976#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 5977#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6287#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6170#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 5925#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5926#L655 assume !(1 == ~t9_pc~0); 5955#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5956#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5839#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5840#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 6180#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6181#L674 assume 1 == ~t10_pc~0; 5346#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 5347#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5967#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5968#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 5914#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5915#L1119 assume !(1 == ~M_E~0); 5445#L1119-2 assume !(1 == ~T1_E~0); 5446#L1124-1 assume !(1 == ~T2_E~0); 5264#L1129-1 assume !(1 == ~T3_E~0); 5265#L1134-1 assume !(1 == ~T4_E~0); 5563#L1139-1 assume !(1 == ~T5_E~0); 5564#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5791#L1149-1 assume !(1 == ~T7_E~0); 5439#L1154-1 assume !(1 == ~T8_E~0); 5440#L1159-1 assume !(1 == ~T9_E~0); 5521#L1164-1 assume !(1 == ~T10_E~0); 5942#L1169-1 assume !(1 == ~E_1~0); 5842#L1174-1 assume !(1 == ~E_2~0); 5617#L1179-1 assume !(1 == ~E_3~0); 5511#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 5512#L1189-1 assume !(1 == ~E_5~0); 5561#L1194-1 assume !(1 == ~E_6~0); 5667#L1199-1 assume !(1 == ~E_7~0); 5627#L1204-1 assume !(1 == ~E_8~0); 5628#L1209-1 assume !(1 == ~E_9~0); 6178#L1214-1 assume !(1 == ~E_10~0); 6179#L1219-1 assume { :end_inline_reset_delta_events } true; 5223#L1520-2 [2023-11-29 02:54:23,217 INFO L750 eck$LassoCheckResult]: Loop: 5223#L1520-2 assume !false; 5224#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6015#L981-1 assume !false; 6200#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6201#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5207#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5808#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5809#L836 assume !(0 != eval_~tmp~0#1); 6292#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5984#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5780#L1006-3 assume !(0 == ~M_E~0); 5781#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6278#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 6279#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 6316#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5993#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5994#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 6246#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6247#L1041-3 assume !(0 == ~T8_E~0); 6308#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6309#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6248#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 5534#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5535#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5536#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 6419#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5328#L1081-3 assume !(0 == ~E_6~0); 5329#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5374#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5375#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 6392#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6393#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6017#L484-33 assume !(1 == ~m_pc~0); 6018#L484-35 is_master_triggered_~__retres1~0#1 := 0; 5928#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5929#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5229#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 5230#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5674#L503-33 assume 1 == ~t1_pc~0; 5675#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 6163#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6164#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5594#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 5595#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6055#L522-33 assume !(1 == ~t2_pc~0); 6056#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5366#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5367#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6264#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 6076#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6077#L541-33 assume 1 == ~t3_pc~0; 5386#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 5227#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5228#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5395#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6047#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6244#L560-33 assume 1 == ~t4_pc~0; 5932#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 5304#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5305#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6421#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6223#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5216#L579-33 assume 1 == ~t5_pc~0; 5217#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 5467#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6437#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6106#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6107#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6135#L598-33 assume !(1 == ~t6_pc~0); 5892#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5699#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5700#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5558#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5559#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6381#L617-33 assume 1 == ~t7_pc~0; 6389#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 5360#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6315#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6334#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6420#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5294#L636-33 assume !(1 == ~t8_pc~0); 5296#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 6216#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6078#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6079#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6207#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6208#L655-33 assume 1 == ~t9_pc~0; 6468#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 5647#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5648#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6267#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 6296#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5838#L674-33 assume !(1 == ~t10_pc~0); 5696#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 5695#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6340#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6064#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6065#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6442#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6452#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6454#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 6464#L1129-3 assume !(1 == ~T3_E~0); 5592#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5593#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5827#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 5828#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5982#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6259#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6260#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6428#L1169-3 assume !(1 == ~E_1~0); 5697#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5698#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6345#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 5351#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5352#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5642#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5643#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5966#L1209-3 assume !(1 == ~E_9~0); 5243#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5244#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6169#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5331#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5685#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5686#L1539 assume !(0 == start_simulation_~tmp~3#1); 5756#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5943#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5738#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5272#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 5273#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5650#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6004#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5757#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 5223#L1520-2 [2023-11-29 02:54:23,219 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:23,219 INFO L85 PathProgramCache]: Analyzing trace with hash 158309421, now seen corresponding path program 1 times [2023-11-29 02:54:23,219 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:23,220 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [75759268] [2023-11-29 02:54:23,220 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:23,220 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:23,270 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:23,316 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:23,316 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:23,316 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [75759268] [2023-11-29 02:54:23,317 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [75759268] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:23,317 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:23,317 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:23,318 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1960791359] [2023-11-29 02:54:23,318 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:23,318 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:23,319 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:23,319 INFO L85 PathProgramCache]: Analyzing trace with hash -1384946584, now seen corresponding path program 1 times [2023-11-29 02:54:23,320 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:23,320 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1124099188] [2023-11-29 02:54:23,320 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:23,321 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:23,344 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:23,404 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:23,405 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:23,405 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1124099188] [2023-11-29 02:54:23,405 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1124099188] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:23,406 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:23,406 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:23,406 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [3571323] [2023-11-29 02:54:23,406 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:23,407 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:23,407 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:23,408 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:23,408 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:23,408 INFO L87 Difference]: Start difference. First operand 1289 states and 1911 transitions. cyclomatic complexity: 623 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:23,450 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:23,450 INFO L93 Difference]: Finished difference Result 1289 states and 1910 transitions. [2023-11-29 02:54:23,450 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1910 transitions. [2023-11-29 02:54:23,462 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:23,474 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1910 transitions. [2023-11-29 02:54:23,474 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-29 02:54:23,476 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-29 02:54:23,476 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1910 transitions. [2023-11-29 02:54:23,479 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:23,479 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1910 transitions. [2023-11-29 02:54:23,483 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1910 transitions. [2023-11-29 02:54:23,506 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-29 02:54:23,510 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4817688130333593) internal successors, (1910), 1288 states have internal predecessors, (1910), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:23,516 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1910 transitions. [2023-11-29 02:54:23,517 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1910 transitions. [2023-11-29 02:54:23,517 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:23,519 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1910 transitions. [2023-11-29 02:54:23,519 INFO L335 stractBuchiCegarLoop]: ======== Iteration 4 ============ [2023-11-29 02:54:23,519 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1910 transitions. [2023-11-29 02:54:23,528 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:23,529 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:23,529 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:23,531 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:23,532 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:23,533 INFO L748 eck$LassoCheckResult]: Stem: 8131#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 8132#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8983#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8984#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9052#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 9046#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9047#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8298#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8043#L716-1 assume !(1 == ~t4_i~0);~t4_st~0 := 2; 8044#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 8953#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 8954#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 8935#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 8936#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8976#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 8092#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8093#L1006 assume !(0 == ~M_E~0); 7946#L1006-2 assume !(0 == ~T1_E~0); 7947#L1011-1 assume !(0 == ~T2_E~0); 9001#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 9018#L1021-1 assume !(0 == ~T4_E~0); 7822#L1026-1 assume !(0 == ~T5_E~0); 7823#L1031-1 assume !(0 == ~T6_E~0); 8712#L1036-1 assume !(0 == ~T7_E~0); 8709#L1041-1 assume !(0 == ~T8_E~0); 8710#L1046-1 assume !(0 == ~T9_E~0); 8122#L1051-1 assume !(0 == ~T10_E~0); 8123#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 8839#L1061-1 assume !(0 == ~E_2~0); 8047#L1066-1 assume !(0 == ~E_3~0); 8048#L1071-1 assume !(0 == ~E_4~0); 8814#L1076-1 assume !(0 == ~E_5~0); 7954#L1081-1 assume !(0 == ~E_6~0); 7955#L1086-1 assume !(0 == ~E_7~0); 8272#L1091-1 assume !(0 == ~E_8~0); 8991#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 8992#L1101-1 assume !(0 == ~E_10~0); 8343#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8344#L484 assume !(1 == ~m_pc~0); 8004#L484-2 is_master_triggered_~__retres1~0#1 := 0; 8003#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8626#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8907#L1245 assume !(0 != activate_threads_~tmp~1#1); 8908#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8699#L503 assume 1 == ~t1_pc~0; 8700#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8718#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7863#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7864#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 7859#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7860#L522 assume !(1 == ~t2_pc~0); 8665#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8058#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8059#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8338#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 8955#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9026#L541 assume 1 == ~t3_pc~0; 8608#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 8410#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7806#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7807#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 8671#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8672#L560 assume !(1 == ~t4_pc~0); 7938#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7937#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7970#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7820#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 7821#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8103#L579 assume 1 == ~t5_pc~0; 7771#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 7772#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7885#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8912#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 9016#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9036#L598 assume 1 == ~t6_pc~0; 8187#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8188#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8313#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8314#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 8745#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8690#L617 assume !(1 == ~t7_pc~0); 8163#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8162#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9056#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8967#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 8377#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8378#L636 assume 1 == ~t8_pc~0; 8561#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8562#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8867#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8753#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 8508#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8509#L655 assume !(1 == ~t9_pc~0); 8536#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8537#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8420#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8421#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 8765#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8766#L674 assume 1 == ~t10_pc~0; 7931#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 7932#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8551#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8552#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 8499#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8500#L1119 assume !(1 == ~M_E~0); 8030#L1119-2 assume !(1 == ~T1_E~0); 8031#L1124-1 assume !(1 == ~T2_E~0); 7849#L1129-1 assume !(1 == ~T3_E~0); 7850#L1134-1 assume !(1 == ~T4_E~0); 8147#L1139-1 assume !(1 == ~T5_E~0); 8148#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8373#L1149-1 assume !(1 == ~T7_E~0); 8024#L1154-1 assume !(1 == ~T8_E~0); 8025#L1159-1 assume !(1 == ~T9_E~0); 8106#L1164-1 assume !(1 == ~T10_E~0); 8527#L1169-1 assume !(1 == ~E_1~0); 8426#L1174-1 assume !(1 == ~E_2~0); 8200#L1179-1 assume !(1 == ~E_3~0); 8096#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 8097#L1189-1 assume !(1 == ~E_5~0); 8145#L1194-1 assume !(1 == ~E_6~0); 8251#L1199-1 assume !(1 == ~E_7~0); 8212#L1204-1 assume !(1 == ~E_8~0); 8213#L1209-1 assume !(1 == ~E_9~0); 8763#L1214-1 assume !(1 == ~E_10~0); 8764#L1219-1 assume { :end_inline_reset_delta_events } true; 7808#L1520-2 [2023-11-29 02:54:23,533 INFO L750 eck$LassoCheckResult]: Loop: 7808#L1520-2 assume !false; 7809#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8600#L981-1 assume !false; 8785#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8786#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7792#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8390#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8391#L836 assume !(0 != eval_~tmp~0#1); 8877#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8569#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8365#L1006-3 assume !(0 == ~M_E~0); 8366#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8863#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 8864#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 8901#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8578#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8579#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 8831#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8832#L1041-3 assume !(0 == ~T8_E~0); 8893#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8894#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8833#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 8119#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8120#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8121#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 9004#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7913#L1081-3 assume !(0 == ~E_6~0); 7914#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7959#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7960#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 8977#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8978#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8602#L484-33 assume !(1 == ~m_pc~0); 8603#L484-35 is_master_triggered_~__retres1~0#1 := 0; 8513#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8514#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7814#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 7815#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8259#L503-33 assume 1 == ~t1_pc~0; 8260#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 8748#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8749#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8181#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 8182#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8640#L522-33 assume !(1 == ~t2_pc~0); 8641#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 7951#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7952#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8849#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8661#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8662#L541-33 assume 1 == ~t3_pc~0; 7971#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 7812#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7813#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7980#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 8632#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8829#L560-33 assume 1 == ~t4_pc~0; 8517#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 7889#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7890#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9006#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 8808#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7801#L579-33 assume 1 == ~t5_pc~0; 7802#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 8052#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9022#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8691#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8692#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8723#L598-33 assume 1 == ~t6_pc~0; 9024#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 8284#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8285#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8143#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8144#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8966#L617-33 assume !(1 == ~t7_pc~0); 7944#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 7945#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8900#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8919#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 9005#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7879#L636-33 assume 1 == ~t8_pc~0; 7880#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 8801#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8663#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8664#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8792#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8793#L655-33 assume 1 == ~t9_pc~0; 9053#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8232#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8233#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8852#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 8881#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8425#L674-33 assume 1 == ~t10_pc~0; 8279#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 8280#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8925#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8649#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8650#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9027#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9037#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9039#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 9049#L1129-3 assume !(1 == ~T3_E~0); 8177#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8178#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8412#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 8413#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8567#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8844#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8845#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9013#L1169-3 assume !(1 == ~E_1~0); 8282#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8283#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8930#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 7939#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7940#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8227#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8228#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8553#L1209-3 assume !(1 == ~E_9~0); 7828#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7829#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8755#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7916#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8270#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 8271#L1539 assume !(0 == start_simulation_~tmp~3#1); 8341#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8528#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8323#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 7857#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 7858#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8235#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8589#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8342#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 7808#L1520-2 [2023-11-29 02:54:23,534 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:23,534 INFO L85 PathProgramCache]: Analyzing trace with hash 1440481707, now seen corresponding path program 1 times [2023-11-29 02:54:23,534 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:23,535 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [265358632] [2023-11-29 02:54:23,535 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:23,535 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:23,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:23,585 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:23,585 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:23,585 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [265358632] [2023-11-29 02:54:23,586 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [265358632] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:23,586 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:23,586 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:23,586 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [503315404] [2023-11-29 02:54:23,586 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:23,587 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:23,587 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:23,587 INFO L85 PathProgramCache]: Analyzing trace with hash 1365031658, now seen corresponding path program 1 times [2023-11-29 02:54:23,588 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:23,588 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1123757909] [2023-11-29 02:54:23,588 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:23,588 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:23,605 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:23,652 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:23,653 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:23,653 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1123757909] [2023-11-29 02:54:23,653 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1123757909] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:23,653 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:23,653 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:23,654 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985675546] [2023-11-29 02:54:23,654 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:23,654 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:23,654 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:23,655 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:23,655 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:23,655 INFO L87 Difference]: Start difference. First operand 1289 states and 1910 transitions. cyclomatic complexity: 622 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:23,688 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:23,688 INFO L93 Difference]: Finished difference Result 1289 states and 1909 transitions. [2023-11-29 02:54:23,688 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1909 transitions. [2023-11-29 02:54:23,698 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:23,708 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1909 transitions. [2023-11-29 02:54:23,708 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-29 02:54:23,710 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-29 02:54:23,710 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1909 transitions. [2023-11-29 02:54:23,712 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:23,713 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1909 transitions. [2023-11-29 02:54:23,715 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1909 transitions. [2023-11-29 02:54:23,734 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-29 02:54:23,737 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4809930178432893) internal successors, (1909), 1288 states have internal predecessors, (1909), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:23,742 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1909 transitions. [2023-11-29 02:54:23,742 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1909 transitions. [2023-11-29 02:54:23,743 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:23,743 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1909 transitions. [2023-11-29 02:54:23,744 INFO L335 stractBuchiCegarLoop]: ======== Iteration 5 ============ [2023-11-29 02:54:23,744 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1909 transitions. [2023-11-29 02:54:23,751 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:23,751 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:23,751 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:23,753 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:23,753 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:23,754 INFO L748 eck$LassoCheckResult]: Stem: 10716#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 10717#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 11569#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 11570#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 11637#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 11631#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 11632#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10883#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10628#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10629#L721-1 assume !(1 == ~t5_i~0);~t5_st~0 := 2; 11538#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 11539#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 11520#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 11521#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 11561#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 10677#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10678#L1006 assume !(0 == ~M_E~0); 10531#L1006-2 assume !(0 == ~T1_E~0); 10532#L1011-1 assume !(0 == ~T2_E~0); 11586#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11603#L1021-1 assume !(0 == ~T4_E~0); 10407#L1026-1 assume !(0 == ~T5_E~0); 10408#L1031-1 assume !(0 == ~T6_E~0); 11297#L1036-1 assume !(0 == ~T7_E~0); 11294#L1041-1 assume !(0 == ~T8_E~0); 11295#L1046-1 assume !(0 == ~T9_E~0); 10707#L1051-1 assume !(0 == ~T10_E~0); 10708#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 11424#L1061-1 assume !(0 == ~E_2~0); 10632#L1066-1 assume !(0 == ~E_3~0); 10633#L1071-1 assume !(0 == ~E_4~0); 11399#L1076-1 assume !(0 == ~E_5~0); 10539#L1081-1 assume !(0 == ~E_6~0); 10540#L1086-1 assume !(0 == ~E_7~0); 10857#L1091-1 assume !(0 == ~E_8~0); 11576#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 11577#L1101-1 assume !(0 == ~E_10~0); 10928#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10929#L484 assume !(1 == ~m_pc~0); 10589#L484-2 is_master_triggered_~__retres1~0#1 := 0; 10588#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11211#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 11492#L1245 assume !(0 != activate_threads_~tmp~1#1); 11493#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 11284#L503 assume 1 == ~t1_pc~0; 11285#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11303#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10448#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10449#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 10444#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10445#L522 assume !(1 == ~t2_pc~0); 11250#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10643#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10644#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10923#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 11540#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11611#L541 assume 1 == ~t3_pc~0; 11193#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10995#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10391#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10392#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 11256#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11257#L560 assume !(1 == ~t4_pc~0); 10523#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10522#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10555#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10405#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 10406#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10688#L579 assume 1 == ~t5_pc~0; 10356#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10357#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10470#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11497#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 11601#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11621#L598 assume 1 == ~t6_pc~0; 10772#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 10773#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10898#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10899#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 11330#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11275#L617 assume !(1 == ~t7_pc~0); 10748#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10747#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11641#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11552#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10962#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10963#L636 assume 1 == ~t8_pc~0; 11146#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11147#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11452#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11338#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 11093#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11094#L655 assume !(1 == ~t9_pc~0); 11123#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 11124#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 11005#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11006#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 11350#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11351#L674 assume 1 == ~t10_pc~0; 10516#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10517#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11136#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11137#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 11084#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11085#L1119 assume !(1 == ~M_E~0); 10615#L1119-2 assume !(1 == ~T1_E~0); 10616#L1124-1 assume !(1 == ~T2_E~0); 10434#L1129-1 assume !(1 == ~T3_E~0); 10435#L1134-1 assume !(1 == ~T4_E~0); 10733#L1139-1 assume !(1 == ~T5_E~0); 10734#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10958#L1149-1 assume !(1 == ~T7_E~0); 10609#L1154-1 assume !(1 == ~T8_E~0); 10610#L1159-1 assume !(1 == ~T9_E~0); 10691#L1164-1 assume !(1 == ~T10_E~0); 11112#L1169-1 assume !(1 == ~E_1~0); 11011#L1174-1 assume !(1 == ~E_2~0); 10785#L1179-1 assume !(1 == ~E_3~0); 10681#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 10682#L1189-1 assume !(1 == ~E_5~0); 10730#L1194-1 assume !(1 == ~E_6~0); 10836#L1199-1 assume !(1 == ~E_7~0); 10797#L1204-1 assume !(1 == ~E_8~0); 10798#L1209-1 assume !(1 == ~E_9~0); 11348#L1214-1 assume !(1 == ~E_10~0); 11349#L1219-1 assume { :end_inline_reset_delta_events } true; 10393#L1520-2 [2023-11-29 02:54:23,755 INFO L750 eck$LassoCheckResult]: Loop: 10393#L1520-2 assume !false; 10394#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 11185#L981-1 assume !false; 11370#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11371#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10377#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10978#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10979#L836 assume !(0 != eval_~tmp~0#1); 11462#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 11154#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10950#L1006-3 assume !(0 == ~M_E~0); 10951#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 11448#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 11449#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 11486#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 11163#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 11164#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 11416#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 11417#L1041-3 assume !(0 == ~T8_E~0); 11478#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 11479#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 11418#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 10704#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10705#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10706#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 11589#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10498#L1081-3 assume !(0 == ~E_6~0); 10499#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10544#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10545#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 11562#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 11563#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 11187#L484-33 assume !(1 == ~m_pc~0); 11188#L484-35 is_master_triggered_~__retres1~0#1 := 0; 11098#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 11099#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10399#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 10400#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10844#L503-33 assume 1 == ~t1_pc~0; 10845#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 11333#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 11334#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10766#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 10767#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 11225#L522-33 assume !(1 == ~t2_pc~0); 11226#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 10536#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10537#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 11434#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 11246#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 11247#L541-33 assume 1 == ~t3_pc~0; 10556#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 10397#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10398#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10565#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 11217#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 11414#L560-33 assume 1 == ~t4_pc~0; 11102#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 10474#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10475#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 11591#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 11393#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10386#L579-33 assume 1 == ~t5_pc~0; 10387#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 10637#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 11607#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 11276#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 11277#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 11308#L598-33 assume !(1 == ~t6_pc~0); 11063#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 10869#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10870#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10728#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 10729#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 11551#L617-33 assume !(1 == ~t7_pc~0); 10529#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 10530#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 11485#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 11504#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 11590#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10464#L636-33 assume 1 == ~t8_pc~0; 10465#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 11386#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 11248#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 11249#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 11379#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 11380#L655-33 assume 1 == ~t9_pc~0; 11638#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10817#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10818#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 11437#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 11466#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 11010#L674-33 assume 1 == ~t10_pc~0; 10864#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 10865#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 11510#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 11234#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 11235#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 11612#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 11622#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 11624#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 11634#L1129-3 assume !(1 == ~T3_E~0); 10762#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10763#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10997#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 10998#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 11152#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 11429#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 11430#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 11598#L1169-3 assume !(1 == ~E_1~0); 10867#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10868#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 11515#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 10524#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10525#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10812#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10813#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 11138#L1209-3 assume !(1 == ~E_9~0); 10413#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10414#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11340#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10501#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10855#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10856#L1539 assume !(0 == start_simulation_~tmp~3#1); 10927#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 11113#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10908#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10440#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 10441#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10820#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 11174#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10925#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 10393#L1520-2 [2023-11-29 02:54:23,755 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:23,755 INFO L85 PathProgramCache]: Analyzing trace with hash -1012009875, now seen corresponding path program 1 times [2023-11-29 02:54:23,756 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:23,756 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1308623829] [2023-11-29 02:54:23,756 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:23,756 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:23,772 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:23,807 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:23,807 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:23,808 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1308623829] [2023-11-29 02:54:23,808 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1308623829] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:23,808 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:23,808 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:23,808 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1672831531] [2023-11-29 02:54:23,809 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:23,809 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:23,810 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:23,810 INFO L85 PathProgramCache]: Analyzing trace with hash 2069950345, now seen corresponding path program 1 times [2023-11-29 02:54:23,810 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:23,810 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610700249] [2023-11-29 02:54:23,811 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:23,811 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:23,827 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:23,897 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:23,897 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:23,897 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610700249] [2023-11-29 02:54:23,898 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [610700249] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:23,898 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:23,898 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:23,898 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1271075224] [2023-11-29 02:54:23,898 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:23,899 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:23,899 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:23,899 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:23,899 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:23,900 INFO L87 Difference]: Start difference. First operand 1289 states and 1909 transitions. cyclomatic complexity: 621 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:23,931 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:23,931 INFO L93 Difference]: Finished difference Result 1289 states and 1908 transitions. [2023-11-29 02:54:23,931 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1908 transitions. [2023-11-29 02:54:23,941 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:23,950 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1908 transitions. [2023-11-29 02:54:23,950 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-29 02:54:23,951 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-29 02:54:23,951 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1908 transitions. [2023-11-29 02:54:23,954 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:23,954 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1908 transitions. [2023-11-29 02:54:23,956 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1908 transitions. [2023-11-29 02:54:23,973 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-29 02:54:23,976 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4802172226532195) internal successors, (1908), 1288 states have internal predecessors, (1908), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:23,980 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1908 transitions. [2023-11-29 02:54:23,981 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1908 transitions. [2023-11-29 02:54:23,981 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:23,982 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1908 transitions. [2023-11-29 02:54:23,982 INFO L335 stractBuchiCegarLoop]: ======== Iteration 6 ============ [2023-11-29 02:54:23,982 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1908 transitions. [2023-11-29 02:54:23,989 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:23,989 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:23,990 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:23,992 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:23,992 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:23,992 INFO L748 eck$LassoCheckResult]: Stem: 13301#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 13302#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 14154#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 14155#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 14222#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 14216#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 14217#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 13470#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 13213#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 13214#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 14123#L726-1 assume !(1 == ~t6_i~0);~t6_st~0 := 2; 14124#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 14105#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 14106#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 14146#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 13264#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 13265#L1006 assume !(0 == ~M_E~0); 13116#L1006-2 assume !(0 == ~T1_E~0); 13117#L1011-1 assume !(0 == ~T2_E~0); 14171#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14188#L1021-1 assume !(0 == ~T4_E~0); 12994#L1026-1 assume !(0 == ~T5_E~0); 12995#L1031-1 assume !(0 == ~T6_E~0); 13883#L1036-1 assume !(0 == ~T7_E~0); 13879#L1041-1 assume !(0 == ~T8_E~0); 13880#L1046-1 assume !(0 == ~T9_E~0); 13292#L1051-1 assume !(0 == ~T10_E~0); 13293#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 14009#L1061-1 assume !(0 == ~E_2~0); 13217#L1066-1 assume !(0 == ~E_3~0); 13218#L1071-1 assume !(0 == ~E_4~0); 13984#L1076-1 assume !(0 == ~E_5~0); 13124#L1081-1 assume !(0 == ~E_6~0); 13125#L1086-1 assume !(0 == ~E_7~0); 13444#L1091-1 assume !(0 == ~E_8~0); 14163#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 14164#L1101-1 assume !(0 == ~E_10~0); 13513#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13514#L484 assume !(1 == ~m_pc~0); 13174#L484-2 is_master_triggered_~__retres1~0#1 := 0; 13173#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13796#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 14077#L1245 assume !(0 != activate_threads_~tmp~1#1); 14078#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13869#L503 assume 1 == ~t1_pc~0; 13870#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13889#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13035#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13036#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 13029#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13030#L522 assume !(1 == ~t2_pc~0); 13835#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 13228#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13229#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 13508#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 14125#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 14196#L541 assume 1 == ~t3_pc~0; 13778#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 13580#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12976#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12977#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 13841#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13842#L560 assume !(1 == ~t4_pc~0); 13110#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 13109#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13140#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12990#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 12991#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 13275#L579 assume 1 == ~t5_pc~0; 12941#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 12942#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 13055#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 14082#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 14187#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 14206#L598 assume 1 == ~t6_pc~0; 13357#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13358#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13486#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13487#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 13915#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 13860#L617 assume !(1 == ~t7_pc~0); 13333#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 13332#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14226#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14137#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 13548#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13549#L636 assume 1 == ~t8_pc~0; 13731#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13732#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 14038#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13924#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 13680#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13681#L655 assume !(1 == ~t9_pc~0); 13708#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 13709#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13594#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 13595#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 13935#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13936#L674 assume 1 == ~t10_pc~0; 13101#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13102#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 13722#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13723#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 13669#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 13670#L1119 assume !(1 == ~M_E~0); 13200#L1119-2 assume !(1 == ~T1_E~0); 13201#L1124-1 assume !(1 == ~T2_E~0); 13019#L1129-1 assume !(1 == ~T3_E~0); 13020#L1134-1 assume !(1 == ~T4_E~0); 13318#L1139-1 assume !(1 == ~T5_E~0); 13319#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13543#L1149-1 assume !(1 == ~T7_E~0); 13194#L1154-1 assume !(1 == ~T8_E~0); 13195#L1159-1 assume !(1 == ~T9_E~0); 13276#L1164-1 assume !(1 == ~T10_E~0); 13697#L1169-1 assume !(1 == ~E_1~0); 13596#L1174-1 assume !(1 == ~E_2~0); 13370#L1179-1 assume !(1 == ~E_3~0); 13266#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 13267#L1189-1 assume !(1 == ~E_5~0); 13316#L1194-1 assume !(1 == ~E_6~0); 13422#L1199-1 assume !(1 == ~E_7~0); 13382#L1204-1 assume !(1 == ~E_8~0); 13383#L1209-1 assume !(1 == ~E_9~0); 13933#L1214-1 assume !(1 == ~E_10~0); 13934#L1219-1 assume { :end_inline_reset_delta_events } true; 12978#L1520-2 [2023-11-29 02:54:23,993 INFO L750 eck$LassoCheckResult]: Loop: 12978#L1520-2 assume !false; 12979#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 13770#L981-1 assume !false; 13955#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13956#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12962#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13563#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 13564#L836 assume !(0 != eval_~tmp~0#1); 14047#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 13739#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 13535#L1006-3 assume !(0 == ~M_E~0); 13536#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 14033#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 14034#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 14071#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 13750#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 13751#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 14001#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 14002#L1041-3 assume !(0 == ~T8_E~0); 14065#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 14066#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 14003#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 13289#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 13290#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 13291#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 14174#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 13083#L1081-3 assume !(0 == ~E_6~0); 13084#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 13131#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 13132#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 14147#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 14148#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 13772#L484-33 assume !(1 == ~m_pc~0); 13773#L484-35 is_master_triggered_~__retres1~0#1 := 0; 13683#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 13684#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12984#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 12985#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 13430#L503-33 assume 1 == ~t1_pc~0; 13431#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 13918#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 13919#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 13351#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 13352#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 13810#L522-33 assume !(1 == ~t2_pc~0); 13811#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 13121#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 13122#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 14019#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 13831#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 13832#L541-33 assume 1 == ~t3_pc~0; 13141#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 12982#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12983#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 13150#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 13802#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 13999#L560-33 assume 1 == ~t4_pc~0; 13687#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 13059#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 13060#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 14176#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 13978#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12968#L579-33 assume 1 == ~t5_pc~0; 12969#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 13222#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 14192#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 13861#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 13862#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 13888#L598-33 assume 1 == ~t6_pc~0; 14194#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 13454#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 13455#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 13313#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 13314#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 14136#L617-33 assume 1 == ~t7_pc~0; 14144#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 13115#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 14070#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 14089#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 14175#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 13049#L636-33 assume 1 == ~t8_pc~0; 13050#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 13971#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 13833#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 13834#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 13962#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 13963#L655-33 assume !(1 == ~t9_pc~0); 14224#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 13400#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 13401#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 14022#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 14051#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 13593#L674-33 assume 1 == ~t10_pc~0; 13449#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 13450#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 14095#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 13819#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 13820#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 14197#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 14207#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 14209#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 14219#L1129-3 assume !(1 == ~T3_E~0); 13344#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 13345#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 13582#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 13583#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 13737#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 14014#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 14015#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 14182#L1169-3 assume !(1 == ~E_1~0); 13452#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 13453#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 14100#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 13106#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 13107#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 13397#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 13398#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 13721#L1209-3 assume !(1 == ~E_9~0); 12996#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 12997#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13923#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13086#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13440#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 13441#L1539 assume !(0 == start_simulation_~tmp~3#1); 13511#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 13698#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 13493#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 13025#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 13026#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 13405#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 13759#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 13512#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 12978#L1520-2 [2023-11-29 02:54:23,993 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:23,993 INFO L85 PathProgramCache]: Analyzing trace with hash 709992811, now seen corresponding path program 1 times [2023-11-29 02:54:23,993 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:23,994 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1608036485] [2023-11-29 02:54:23,994 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:23,994 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:24,008 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:24,044 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:24,045 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:24,045 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1608036485] [2023-11-29 02:54:24,045 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1608036485] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:24,045 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:24,046 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:24,046 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [57429066] [2023-11-29 02:54:24,046 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:24,046 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:24,047 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:24,047 INFO L85 PathProgramCache]: Analyzing trace with hash 1198674282, now seen corresponding path program 1 times [2023-11-29 02:54:24,047 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:24,048 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2037003239] [2023-11-29 02:54:24,048 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:24,048 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:24,065 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:24,115 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:24,115 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:24,115 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2037003239] [2023-11-29 02:54:24,115 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2037003239] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:24,116 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:24,116 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:24,116 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [454321526] [2023-11-29 02:54:24,116 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:24,117 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:24,117 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:24,117 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:24,118 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:24,118 INFO L87 Difference]: Start difference. First operand 1289 states and 1908 transitions. cyclomatic complexity: 620 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:24,150 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:24,150 INFO L93 Difference]: Finished difference Result 1289 states and 1907 transitions. [2023-11-29 02:54:24,150 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1907 transitions. [2023-11-29 02:54:24,160 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:24,170 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1907 transitions. [2023-11-29 02:54:24,170 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-29 02:54:24,171 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-29 02:54:24,172 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1907 transitions. [2023-11-29 02:54:24,174 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:24,174 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1907 transitions. [2023-11-29 02:54:24,177 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1907 transitions. [2023-11-29 02:54:24,194 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-29 02:54:24,197 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4794414274631498) internal successors, (1907), 1288 states have internal predecessors, (1907), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:24,202 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1907 transitions. [2023-11-29 02:54:24,203 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1907 transitions. [2023-11-29 02:54:24,203 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:24,204 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1907 transitions. [2023-11-29 02:54:24,204 INFO L335 stractBuchiCegarLoop]: ======== Iteration 7 ============ [2023-11-29 02:54:24,204 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1907 transitions. [2023-11-29 02:54:24,212 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:24,212 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:24,212 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:24,215 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:24,215 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:24,216 INFO L748 eck$LassoCheckResult]: Stem: 15886#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 15887#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 16739#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 16740#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 16807#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 16801#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 16802#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 16055#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 15800#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 15801#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 16708#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 16709#L731-1 assume !(1 == ~t7_i~0);~t7_st~0 := 2; 16690#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 16691#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 16731#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 15849#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 15850#L1006 assume !(0 == ~M_E~0); 15704#L1006-2 assume !(0 == ~T1_E~0); 15705#L1011-1 assume !(0 == ~T2_E~0); 16756#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16773#L1021-1 assume !(0 == ~T4_E~0); 15579#L1026-1 assume !(0 == ~T5_E~0); 15580#L1031-1 assume !(0 == ~T6_E~0); 16469#L1036-1 assume !(0 == ~T7_E~0); 16464#L1041-1 assume !(0 == ~T8_E~0); 16465#L1046-1 assume !(0 == ~T9_E~0); 15877#L1051-1 assume !(0 == ~T10_E~0); 15878#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 16594#L1061-1 assume !(0 == ~E_2~0); 15802#L1066-1 assume !(0 == ~E_3~0); 15803#L1071-1 assume !(0 == ~E_4~0); 16569#L1076-1 assume !(0 == ~E_5~0); 15709#L1081-1 assume !(0 == ~E_6~0); 15710#L1086-1 assume !(0 == ~E_7~0); 16029#L1091-1 assume !(0 == ~E_8~0); 16748#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 16749#L1101-1 assume !(0 == ~E_10~0); 16098#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16099#L484 assume !(1 == ~m_pc~0); 15761#L484-2 is_master_triggered_~__retres1~0#1 := 0; 15760#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16381#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 16662#L1245 assume !(0 != activate_threads_~tmp~1#1); 16663#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16454#L503 assume 1 == ~t1_pc~0; 16455#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 16478#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 15620#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15621#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 15616#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 15617#L522 assume !(1 == ~t2_pc~0); 16420#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 15817#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15818#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16094#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 16710#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16781#L541 assume 1 == ~t3_pc~0; 16365#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 16165#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15563#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15564#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 16430#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16431#L560 assume !(1 == ~t4_pc~0); 15695#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 15694#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15725#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 15575#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 15576#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15860#L579 assume 1 == ~t5_pc~0; 15526#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15527#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 15640#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16667#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 16772#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16791#L598 assume 1 == ~t6_pc~0; 15942#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 15943#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16071#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 16072#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 16500#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16445#L617 assume !(1 == ~t7_pc~0); 15918#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 15917#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16811#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16722#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16135#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 16136#L636 assume 1 == ~t8_pc~0; 16316#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16317#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16627#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16508#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 16263#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16264#L655 assume !(1 == ~t9_pc~0); 16291#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 16292#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 16175#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16176#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 16520#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16521#L674 assume 1 == ~t10_pc~0; 15686#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 15687#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16306#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16307#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 16254#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16255#L1119 assume !(1 == ~M_E~0); 15785#L1119-2 assume !(1 == ~T1_E~0); 15786#L1124-1 assume !(1 == ~T2_E~0); 15604#L1129-1 assume !(1 == ~T3_E~0); 15605#L1134-1 assume !(1 == ~T4_E~0); 15902#L1139-1 assume !(1 == ~T5_E~0); 15903#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16128#L1149-1 assume !(1 == ~T7_E~0); 15779#L1154-1 assume !(1 == ~T8_E~0); 15780#L1159-1 assume !(1 == ~T9_E~0); 15861#L1164-1 assume !(1 == ~T10_E~0); 16282#L1169-1 assume !(1 == ~E_1~0); 16181#L1174-1 assume !(1 == ~E_2~0); 15955#L1179-1 assume !(1 == ~E_3~0); 15851#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 15852#L1189-1 assume !(1 == ~E_5~0); 15900#L1194-1 assume !(1 == ~E_6~0); 16006#L1199-1 assume !(1 == ~E_7~0); 15967#L1204-1 assume !(1 == ~E_8~0); 15968#L1209-1 assume !(1 == ~E_9~0); 16518#L1214-1 assume !(1 == ~E_10~0); 16519#L1219-1 assume { :end_inline_reset_delta_events } true; 15561#L1520-2 [2023-11-29 02:54:24,216 INFO L750 eck$LassoCheckResult]: Loop: 15561#L1520-2 assume !false; 15562#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 16355#L981-1 assume !false; 16540#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16541#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15547#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16145#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 16146#L836 assume !(0 != eval_~tmp~0#1); 16632#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 16324#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 16120#L1006-3 assume !(0 == ~M_E~0); 16121#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 16618#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 16619#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 16656#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 16333#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 16334#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 16586#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 16587#L1041-3 assume !(0 == ~T8_E~0); 16648#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 16649#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 16588#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 15874#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 15875#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 15876#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 16759#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 15668#L1081-3 assume !(0 == ~E_6~0); 15669#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 15714#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 15715#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 16732#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 16733#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 16357#L484-33 assume !(1 == ~m_pc~0); 16358#L484-35 is_master_triggered_~__retres1~0#1 := 0; 16268#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 16269#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 15569#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 15570#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 16014#L503-33 assume !(1 == ~t1_pc~0); 16016#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 16503#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 16504#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 15936#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 15937#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 16395#L522-33 assume !(1 == ~t2_pc~0); 16396#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 15706#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 15707#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 16604#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 16416#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 16417#L541-33 assume 1 == ~t3_pc~0; 15726#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 15567#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 15568#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 15735#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 16387#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 16584#L560-33 assume 1 == ~t4_pc~0; 16272#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 15644#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 15645#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 16761#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 16563#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 15556#L579-33 assume 1 == ~t5_pc~0; 15557#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 15807#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 16777#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 16446#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 16447#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 16477#L598-33 assume !(1 == ~t6_pc~0); 16232#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 16039#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 16040#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 15898#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 15899#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 16721#L617-33 assume !(1 == ~t7_pc~0); 15699#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 15700#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 16655#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 16674#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 16760#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 15634#L636-33 assume 1 == ~t8_pc~0; 15635#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 16556#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 16418#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 16419#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 16547#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 16548#L655-33 assume 1 == ~t9_pc~0; 16808#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 15987#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 15988#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 16607#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 16636#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 16180#L674-33 assume 1 == ~t10_pc~0; 16034#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 16035#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 16680#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 16404#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 16405#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 16782#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 16792#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 16794#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 16804#L1129-3 assume !(1 == ~T3_E~0); 15932#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 15933#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 16167#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 16168#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 16322#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 16599#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 16600#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 16768#L1169-3 assume !(1 == ~E_1~0); 16037#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 16038#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 16685#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 15691#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 15692#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 15982#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 15983#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 16308#L1209-3 assume !(1 == ~E_9~0); 15583#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 15584#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16510#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 15671#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 16025#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 16026#L1539 assume !(0 == start_simulation_~tmp~3#1); 16096#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 16283#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 16078#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 15612#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 15613#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 15990#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 16344#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 16097#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 15561#L1520-2 [2023-11-29 02:54:24,217 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:24,217 INFO L85 PathProgramCache]: Analyzing trace with hash 1042635949, now seen corresponding path program 1 times [2023-11-29 02:54:24,218 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:24,218 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1678963339] [2023-11-29 02:54:24,218 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:24,218 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:24,234 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:24,268 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:24,268 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:24,268 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1678963339] [2023-11-29 02:54:24,268 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1678963339] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:24,269 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:24,269 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:24,269 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [796614720] [2023-11-29 02:54:24,269 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:24,270 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:24,270 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:24,270 INFO L85 PathProgramCache]: Analyzing trace with hash -1952021528, now seen corresponding path program 1 times [2023-11-29 02:54:24,270 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:24,271 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1052433578] [2023-11-29 02:54:24,271 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:24,271 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:24,289 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:24,335 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:24,335 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:24,336 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1052433578] [2023-11-29 02:54:24,336 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1052433578] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:24,336 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:24,336 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:24,336 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [640465650] [2023-11-29 02:54:24,336 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:24,337 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:24,337 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:24,337 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:24,337 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:24,337 INFO L87 Difference]: Start difference. First operand 1289 states and 1907 transitions. cyclomatic complexity: 619 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:24,371 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:24,371 INFO L93 Difference]: Finished difference Result 1289 states and 1906 transitions. [2023-11-29 02:54:24,371 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1906 transitions. [2023-11-29 02:54:24,381 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:24,392 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1906 transitions. [2023-11-29 02:54:24,392 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-29 02:54:24,393 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-29 02:54:24,394 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1906 transitions. [2023-11-29 02:54:24,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:24,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1906 transitions. [2023-11-29 02:54:24,399 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1906 transitions. [2023-11-29 02:54:24,435 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-29 02:54:24,438 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.47866563227308) internal successors, (1906), 1288 states have internal predecessors, (1906), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:24,443 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1906 transitions. [2023-11-29 02:54:24,443 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1906 transitions. [2023-11-29 02:54:24,444 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:24,445 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1906 transitions. [2023-11-29 02:54:24,445 INFO L335 stractBuchiCegarLoop]: ======== Iteration 8 ============ [2023-11-29 02:54:24,446 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1906 transitions. [2023-11-29 02:54:24,451 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:24,451 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:24,451 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:24,454 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:24,454 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:24,454 INFO L748 eck$LassoCheckResult]: Stem: 18471#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 18472#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 19323#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 19324#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 19392#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 19386#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 19387#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 18638#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 18383#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 18384#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 19293#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 19294#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 19275#L736-1 assume !(1 == ~t8_i~0);~t8_st~0 := 2; 19276#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 19316#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 18432#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 18433#L1006 assume !(0 == ~M_E~0); 18286#L1006-2 assume !(0 == ~T1_E~0); 18287#L1011-1 assume !(0 == ~T2_E~0); 19341#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19358#L1021-1 assume !(0 == ~T4_E~0); 18162#L1026-1 assume !(0 == ~T5_E~0); 18163#L1031-1 assume !(0 == ~T6_E~0); 19052#L1036-1 assume !(0 == ~T7_E~0); 19049#L1041-1 assume !(0 == ~T8_E~0); 19050#L1046-1 assume !(0 == ~T9_E~0); 18462#L1051-1 assume !(0 == ~T10_E~0); 18463#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 19179#L1061-1 assume !(0 == ~E_2~0); 18387#L1066-1 assume !(0 == ~E_3~0); 18388#L1071-1 assume !(0 == ~E_4~0); 19154#L1076-1 assume !(0 == ~E_5~0); 18294#L1081-1 assume !(0 == ~E_6~0); 18295#L1086-1 assume !(0 == ~E_7~0); 18612#L1091-1 assume !(0 == ~E_8~0); 19331#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 19332#L1101-1 assume !(0 == ~E_10~0); 18683#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18684#L484 assume !(1 == ~m_pc~0); 18344#L484-2 is_master_triggered_~__retres1~0#1 := 0; 18343#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18966#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 19247#L1245 assume !(0 != activate_threads_~tmp~1#1); 19248#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 19039#L503 assume 1 == ~t1_pc~0; 19040#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19058#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 18203#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18204#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 18199#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18200#L522 assume !(1 == ~t2_pc~0); 19005#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 18398#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18399#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 18678#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 19295#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19366#L541 assume 1 == ~t3_pc~0; 18948#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18750#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18146#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18147#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 19011#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19012#L560 assume !(1 == ~t4_pc~0); 18278#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 18277#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18310#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 18160#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 18161#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18443#L579 assume 1 == ~t5_pc~0; 18111#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18112#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 18225#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19252#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 19356#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19376#L598 assume 1 == ~t6_pc~0; 18527#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 18528#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18653#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18654#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 19085#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19030#L617 assume !(1 == ~t7_pc~0); 18503#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 18502#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19396#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19307#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 18717#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18718#L636 assume 1 == ~t8_pc~0; 18901#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 18902#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19207#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19093#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 18848#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 18849#L655 assume !(1 == ~t9_pc~0); 18876#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 18877#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18760#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 18761#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 19105#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 19106#L674 assume 1 == ~t10_pc~0; 18271#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18272#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 18891#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18892#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 18839#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 18840#L1119 assume !(1 == ~M_E~0); 18370#L1119-2 assume !(1 == ~T1_E~0); 18371#L1124-1 assume !(1 == ~T2_E~0); 18189#L1129-1 assume !(1 == ~T3_E~0); 18190#L1134-1 assume !(1 == ~T4_E~0); 18487#L1139-1 assume !(1 == ~T5_E~0); 18488#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18713#L1149-1 assume !(1 == ~T7_E~0); 18364#L1154-1 assume !(1 == ~T8_E~0); 18365#L1159-1 assume !(1 == ~T9_E~0); 18446#L1164-1 assume !(1 == ~T10_E~0); 18867#L1169-1 assume !(1 == ~E_1~0); 18766#L1174-1 assume !(1 == ~E_2~0); 18540#L1179-1 assume !(1 == ~E_3~0); 18436#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 18437#L1189-1 assume !(1 == ~E_5~0); 18485#L1194-1 assume !(1 == ~E_6~0); 18591#L1199-1 assume !(1 == ~E_7~0); 18552#L1204-1 assume !(1 == ~E_8~0); 18553#L1209-1 assume !(1 == ~E_9~0); 19103#L1214-1 assume !(1 == ~E_10~0); 19104#L1219-1 assume { :end_inline_reset_delta_events } true; 18148#L1520-2 [2023-11-29 02:54:24,454 INFO L750 eck$LassoCheckResult]: Loop: 18148#L1520-2 assume !false; 18149#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 18940#L981-1 assume !false; 19125#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19126#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18132#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18730#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 18731#L836 assume !(0 != eval_~tmp~0#1); 19217#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 18909#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 18705#L1006-3 assume !(0 == ~M_E~0); 18706#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 19203#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 19204#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 19241#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 18918#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 18919#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 19171#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 19172#L1041-3 assume !(0 == ~T8_E~0); 19233#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 19234#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 19173#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 18459#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 18460#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 18461#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 19344#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 18253#L1081-3 assume !(0 == ~E_6~0); 18254#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 18299#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 18300#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 19317#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 19318#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 18942#L484-33 assume 1 == ~m_pc~0; 18944#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 18853#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 18854#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 18154#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 18155#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 18599#L503-33 assume 1 == ~t1_pc~0; 18600#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 19088#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 19089#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 18521#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 18522#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 18980#L522-33 assume !(1 == ~t2_pc~0); 18981#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 18291#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 18292#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 19189#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 19001#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 19002#L541-33 assume 1 == ~t3_pc~0; 18311#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 18152#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 18153#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 18320#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 18972#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 19169#L560-33 assume 1 == ~t4_pc~0; 18857#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 18229#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 18230#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 19346#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 19148#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 18141#L579-33 assume 1 == ~t5_pc~0; 18142#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 18392#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 19362#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 19031#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 19032#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 19063#L598-33 assume !(1 == ~t6_pc~0); 18817#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 18624#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 18625#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 18483#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 18484#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 19306#L617-33 assume 1 == ~t7_pc~0; 19314#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 18285#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 19240#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 19259#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 19345#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 18219#L636-33 assume 1 == ~t8_pc~0; 18220#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 19141#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 19003#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 19004#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 19132#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 19133#L655-33 assume 1 == ~t9_pc~0; 19393#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 18572#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 18573#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 19192#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 19221#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 18765#L674-33 assume 1 == ~t10_pc~0; 18619#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 18620#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 19265#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 18989#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 18990#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 19367#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 19377#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 19379#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 19389#L1129-3 assume !(1 == ~T3_E~0); 18517#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 18518#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 18752#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 18753#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 18907#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 19184#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 19185#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 19353#L1169-3 assume !(1 == ~E_1~0); 18622#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 18623#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 19270#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 18279#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 18280#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 18567#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 18568#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 18893#L1209-3 assume !(1 == ~E_9~0); 18168#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 18169#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 19095#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18256#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18610#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 18611#L1539 assume !(0 == start_simulation_~tmp~3#1); 18681#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 18868#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 18663#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 18197#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 18198#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 18575#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 18929#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 18682#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 18148#L1520-2 [2023-11-29 02:54:24,455 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:24,455 INFO L85 PathProgramCache]: Analyzing trace with hash -886296277, now seen corresponding path program 1 times [2023-11-29 02:54:24,455 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:24,457 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [230449122] [2023-11-29 02:54:24,457 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:24,457 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:24,477 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:24,510 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:24,512 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:24,512 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [230449122] [2023-11-29 02:54:24,513 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [230449122] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:24,513 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:24,513 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:24,513 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [985576698] [2023-11-29 02:54:24,513 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:24,514 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:24,514 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:24,515 INFO L85 PathProgramCache]: Analyzing trace with hash -80312693, now seen corresponding path program 1 times [2023-11-29 02:54:24,515 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:24,515 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1598994169] [2023-11-29 02:54:24,515 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:24,515 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:24,533 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:24,579 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:24,579 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:24,579 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1598994169] [2023-11-29 02:54:24,580 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1598994169] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:24,580 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:24,580 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:24,580 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [984771475] [2023-11-29 02:54:24,580 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:24,581 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:24,581 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:24,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:24,582 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:24,582 INFO L87 Difference]: Start difference. First operand 1289 states and 1906 transitions. cyclomatic complexity: 618 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:24,614 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:24,614 INFO L93 Difference]: Finished difference Result 1289 states and 1905 transitions. [2023-11-29 02:54:24,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1905 transitions. [2023-11-29 02:54:24,622 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:24,632 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1905 transitions. [2023-11-29 02:54:24,633 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-29 02:54:24,634 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-29 02:54:24,634 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1905 transitions. [2023-11-29 02:54:24,637 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:24,637 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1905 transitions. [2023-11-29 02:54:24,640 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1905 transitions. [2023-11-29 02:54:24,657 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-29 02:54:24,660 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.47788983708301) internal successors, (1905), 1288 states have internal predecessors, (1905), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:24,665 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1905 transitions. [2023-11-29 02:54:24,665 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1905 transitions. [2023-11-29 02:54:24,666 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:24,666 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1905 transitions. [2023-11-29 02:54:24,667 INFO L335 stractBuchiCegarLoop]: ======== Iteration 9 ============ [2023-11-29 02:54:24,667 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1905 transitions. [2023-11-29 02:54:24,672 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:24,673 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:24,673 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:24,677 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:24,677 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:24,677 INFO L748 eck$LassoCheckResult]: Stem: 21056#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 21057#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 21909#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 21910#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 21977#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 21971#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 21972#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 21223#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 20968#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 20969#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 21878#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 21879#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 21860#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 21861#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 21901#L746-1 assume !(1 == ~t10_i~0);~t10_st~0 := 2; 21019#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 21020#L1006 assume !(0 == ~M_E~0); 20871#L1006-2 assume !(0 == ~T1_E~0); 20872#L1011-1 assume !(0 == ~T2_E~0); 21926#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21943#L1021-1 assume !(0 == ~T4_E~0); 20749#L1026-1 assume !(0 == ~T5_E~0); 20750#L1031-1 assume !(0 == ~T6_E~0); 21637#L1036-1 assume !(0 == ~T7_E~0); 21634#L1041-1 assume !(0 == ~T8_E~0); 21635#L1046-1 assume !(0 == ~T9_E~0); 21047#L1051-1 assume !(0 == ~T10_E~0); 21048#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 21764#L1061-1 assume !(0 == ~E_2~0); 20972#L1066-1 assume !(0 == ~E_3~0); 20973#L1071-1 assume !(0 == ~E_4~0); 21739#L1076-1 assume !(0 == ~E_5~0); 20879#L1081-1 assume !(0 == ~E_6~0); 20880#L1086-1 assume !(0 == ~E_7~0); 21197#L1091-1 assume !(0 == ~E_8~0); 21916#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 21917#L1101-1 assume !(0 == ~E_10~0); 21268#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21269#L484 assume !(1 == ~m_pc~0); 20929#L484-2 is_master_triggered_~__retres1~0#1 := 0; 20928#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21551#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 21832#L1245 assume !(0 != activate_threads_~tmp~1#1); 21833#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21624#L503 assume 1 == ~t1_pc~0; 21625#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21643#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 20788#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 20789#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 20784#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 20785#L522 assume !(1 == ~t2_pc~0); 21590#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 20983#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20984#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21263#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 21880#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21951#L541 assume 1 == ~t3_pc~0; 21533#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 21335#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20731#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20732#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 21596#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21597#L560 assume !(1 == ~t4_pc~0); 20865#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 20864#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20895#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 20745#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 20746#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 21028#L579 assume 1 == ~t5_pc~0; 20696#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20697#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 20810#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21837#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 21941#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21961#L598 assume 1 == ~t6_pc~0; 21112#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 21113#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21238#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21239#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 21670#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21615#L617 assume !(1 == ~t7_pc~0); 21088#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 21087#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21981#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21892#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21302#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 21303#L636 assume 1 == ~t8_pc~0; 21486#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21487#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21792#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21679#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 21433#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21434#L655 assume !(1 == ~t9_pc~0); 21463#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 21464#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21346#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21347#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 21690#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21691#L674 assume 1 == ~t10_pc~0; 20856#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 20857#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21477#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21478#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 21424#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21425#L1119 assume !(1 == ~M_E~0); 20955#L1119-2 assume !(1 == ~T1_E~0); 20956#L1124-1 assume !(1 == ~T2_E~0); 20774#L1129-1 assume !(1 == ~T3_E~0); 20775#L1134-1 assume !(1 == ~T4_E~0); 21073#L1139-1 assume !(1 == ~T5_E~0); 21074#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21298#L1149-1 assume !(1 == ~T7_E~0); 20949#L1154-1 assume !(1 == ~T8_E~0); 20950#L1159-1 assume !(1 == ~T9_E~0); 21031#L1164-1 assume !(1 == ~T10_E~0); 21452#L1169-1 assume !(1 == ~E_1~0); 21351#L1174-1 assume !(1 == ~E_2~0); 21125#L1179-1 assume !(1 == ~E_3~0); 21021#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 21022#L1189-1 assume !(1 == ~E_5~0); 21070#L1194-1 assume !(1 == ~E_6~0); 21176#L1199-1 assume !(1 == ~E_7~0); 21137#L1204-1 assume !(1 == ~E_8~0); 21138#L1209-1 assume !(1 == ~E_9~0); 21688#L1214-1 assume !(1 == ~E_10~0); 21689#L1219-1 assume { :end_inline_reset_delta_events } true; 20733#L1520-2 [2023-11-29 02:54:24,678 INFO L750 eck$LassoCheckResult]: Loop: 20733#L1520-2 assume !false; 20734#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 21525#L981-1 assume !false; 21710#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21711#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20717#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21318#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 21319#L836 assume !(0 != eval_~tmp~0#1); 21802#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 21494#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 21290#L1006-3 assume !(0 == ~M_E~0); 21291#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 21788#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 21789#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 21826#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 21503#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 21504#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 21756#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 21757#L1041-3 assume !(0 == ~T8_E~0); 21818#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 21819#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 21758#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 21044#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 21045#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 21046#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 21929#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 20838#L1081-3 assume !(0 == ~E_6~0); 20839#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 20884#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 20885#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 21902#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 21903#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 21527#L484-33 assume !(1 == ~m_pc~0); 21528#L484-35 is_master_triggered_~__retres1~0#1 := 0; 21438#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 21439#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 20739#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 20740#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 21184#L503-33 assume 1 == ~t1_pc~0; 21185#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 21673#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 21674#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 21106#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 21107#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 21565#L522-33 assume !(1 == ~t2_pc~0); 21566#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 20876#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 20877#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 21774#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 21588#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 21589#L541-33 assume 1 == ~t3_pc~0; 20896#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 20737#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 20738#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 20905#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 21557#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 21754#L560-33 assume 1 == ~t4_pc~0; 21442#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 20814#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 20815#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 21931#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 21733#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 20726#L579-33 assume 1 == ~t5_pc~0; 20727#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 20977#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 21947#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 21616#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 21617#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 21648#L598-33 assume !(1 == ~t6_pc~0); 21403#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 21209#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 21210#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 21068#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 21069#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 21891#L617-33 assume !(1 == ~t7_pc~0); 20869#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 20870#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 21825#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 21844#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 21930#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 20801#L636-33 assume 1 == ~t8_pc~0; 20802#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 21726#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 21586#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 21587#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 21715#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 21716#L655-33 assume 1 == ~t9_pc~0; 21978#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 21154#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 21155#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 21777#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 21805#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 21345#L674-33 assume 1 == ~t10_pc~0; 21204#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 21205#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 21849#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 21574#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 21575#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 21952#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 21962#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 21964#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 21974#L1129-3 assume !(1 == ~T3_E~0); 21099#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 21100#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 21337#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 21338#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 21492#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 21769#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 21770#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 21937#L1169-3 assume !(1 == ~E_1~0); 21207#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 21208#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 21855#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 20861#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 20862#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 21152#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 21153#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 21476#L1209-3 assume !(1 == ~E_9~0); 20751#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 20752#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21678#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 20841#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 21195#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 21196#L1539 assume !(0 == start_simulation_~tmp~3#1); 21266#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 21453#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 21248#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 20780#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 20781#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 21160#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 21514#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 21267#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 20733#L1520-2 [2023-11-29 02:54:24,678 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:24,678 INFO L85 PathProgramCache]: Analyzing trace with hash 1406784749, now seen corresponding path program 1 times [2023-11-29 02:54:24,679 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:24,679 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1600629319] [2023-11-29 02:54:24,679 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:24,679 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:24,697 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:24,736 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:24,736 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:24,736 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1600629319] [2023-11-29 02:54:24,737 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1600629319] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:24,737 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:24,737 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:24,737 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [690771561] [2023-11-29 02:54:24,737 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:24,737 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:24,738 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:24,738 INFO L85 PathProgramCache]: Analyzing trace with hash 2069950345, now seen corresponding path program 2 times [2023-11-29 02:54:24,738 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:24,738 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [793666378] [2023-11-29 02:54:24,739 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:24,739 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:24,759 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:24,812 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:24,812 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:24,812 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [793666378] [2023-11-29 02:54:24,813 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [793666378] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:24,813 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:24,813 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:24,813 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [996872257] [2023-11-29 02:54:24,813 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:24,814 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:24,814 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:24,814 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:24,814 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:24,814 INFO L87 Difference]: Start difference. First operand 1289 states and 1905 transitions. cyclomatic complexity: 617 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:24,847 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:24,847 INFO L93 Difference]: Finished difference Result 1289 states and 1904 transitions. [2023-11-29 02:54:24,847 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1289 states and 1904 transitions. [2023-11-29 02:54:24,854 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:24,863 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1289 states to 1289 states and 1904 transitions. [2023-11-29 02:54:24,863 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 1289 [2023-11-29 02:54:24,865 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 1289 [2023-11-29 02:54:24,865 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1289 states and 1904 transitions. [2023-11-29 02:54:24,867 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:24,867 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1904 transitions. [2023-11-29 02:54:24,870 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1289 states and 1904 transitions. [2023-11-29 02:54:24,886 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1289 to 1289. [2023-11-29 02:54:24,890 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1289 states, 1289 states have (on average 1.4771140418929403) internal successors, (1904), 1288 states have internal predecessors, (1904), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:24,894 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1289 states to 1289 states and 1904 transitions. [2023-11-29 02:54:24,895 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1289 states and 1904 transitions. [2023-11-29 02:54:24,895 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:24,896 INFO L428 stractBuchiCegarLoop]: Abstraction has 1289 states and 1904 transitions. [2023-11-29 02:54:24,896 INFO L335 stractBuchiCegarLoop]: ======== Iteration 10 ============ [2023-11-29 02:54:24,896 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 1289 states and 1904 transitions. [2023-11-29 02:54:24,901 INFO L131 ngComponentsAnalysis]: Automaton has 1 accepting balls. 1152 [2023-11-29 02:54:24,902 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:24,902 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:24,904 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:24,904 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:24,905 INFO L748 eck$LassoCheckResult]: Stem: 23641#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 23642#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 24494#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 24495#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 24562#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 24556#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 24557#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 23810#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 23553#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 23554#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 24463#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 24464#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 24445#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 24446#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 24486#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 23604#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 23605#L1006 assume !(0 == ~M_E~0); 23456#L1006-2 assume !(0 == ~T1_E~0); 23457#L1011-1 assume !(0 == ~T2_E~0); 24511#L1016-1 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24528#L1021-1 assume !(0 == ~T4_E~0); 23334#L1026-1 assume !(0 == ~T5_E~0); 23335#L1031-1 assume !(0 == ~T6_E~0); 24223#L1036-1 assume !(0 == ~T7_E~0); 24219#L1041-1 assume !(0 == ~T8_E~0); 24220#L1046-1 assume !(0 == ~T9_E~0); 23632#L1051-1 assume !(0 == ~T10_E~0); 23633#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 24349#L1061-1 assume !(0 == ~E_2~0); 23557#L1066-1 assume !(0 == ~E_3~0); 23558#L1071-1 assume !(0 == ~E_4~0); 24324#L1076-1 assume !(0 == ~E_5~0); 23464#L1081-1 assume !(0 == ~E_6~0); 23465#L1086-1 assume !(0 == ~E_7~0); 23784#L1091-1 assume !(0 == ~E_8~0); 24503#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 24504#L1101-1 assume !(0 == ~E_10~0); 23853#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 23854#L484 assume !(1 == ~m_pc~0); 23516#L484-2 is_master_triggered_~__retres1~0#1 := 0; 23515#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24136#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 24417#L1245 assume !(0 != activate_threads_~tmp~1#1); 24418#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 24209#L503 assume 1 == ~t1_pc~0; 24210#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24229#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 23375#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23376#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 23369#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 23370#L522 assume !(1 == ~t2_pc~0); 24175#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 23569#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23570#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 23849#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 24465#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24536#L541 assume 1 == ~t3_pc~0; 24118#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23920#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23316#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23317#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 24181#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24182#L560 assume !(1 == ~t4_pc~0); 23450#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 23449#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23480#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 23330#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 23331#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23615#L579 assume 1 == ~t5_pc~0; 23281#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23282#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 23395#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24422#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 24527#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24546#L598 assume 1 == ~t6_pc~0; 23697#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 23698#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23826#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23827#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 24255#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24200#L617 assume !(1 == ~t7_pc~0); 23673#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 23672#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24566#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24477#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 23888#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23889#L636 assume 1 == ~t8_pc~0; 24071#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24072#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24378#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24264#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 24020#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24021#L655 assume !(1 == ~t9_pc~0); 24049#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 24050#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23934#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 23935#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 24275#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 24276#L674 assume 1 == ~t10_pc~0; 23441#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23442#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24062#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24063#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 24009#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24010#L1119 assume !(1 == ~M_E~0); 23540#L1119-2 assume !(1 == ~T1_E~0); 23541#L1124-1 assume !(1 == ~T2_E~0); 23359#L1129-1 assume !(1 == ~T3_E~0); 23360#L1134-1 assume !(1 == ~T4_E~0); 23658#L1139-1 assume !(1 == ~T5_E~0); 23659#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23883#L1149-1 assume !(1 == ~T7_E~0); 23534#L1154-1 assume !(1 == ~T8_E~0); 23535#L1159-1 assume !(1 == ~T9_E~0); 23616#L1164-1 assume !(1 == ~T10_E~0); 24037#L1169-1 assume !(1 == ~E_1~0); 23936#L1174-1 assume !(1 == ~E_2~0); 23710#L1179-1 assume !(1 == ~E_3~0); 23606#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 23607#L1189-1 assume !(1 == ~E_5~0); 23656#L1194-1 assume !(1 == ~E_6~0); 23762#L1199-1 assume !(1 == ~E_7~0); 23722#L1204-1 assume !(1 == ~E_8~0); 23723#L1209-1 assume !(1 == ~E_9~0); 24273#L1214-1 assume !(1 == ~E_10~0); 24274#L1219-1 assume { :end_inline_reset_delta_events } true; 23318#L1520-2 [2023-11-29 02:54:24,905 INFO L750 eck$LassoCheckResult]: Loop: 23318#L1520-2 assume !false; 23319#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 24110#L981-1 assume !false; 24295#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24296#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23302#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23903#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 23904#L836 assume !(0 != eval_~tmp~0#1); 24387#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 24079#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 23875#L1006-3 assume !(0 == ~M_E~0); 23876#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 24373#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 24374#L1016-3 assume 0 == ~T3_E~0;~T3_E~0 := 1; 24411#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 24090#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 24091#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 24341#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 24342#L1041-3 assume !(0 == ~T8_E~0); 24405#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 24406#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 24343#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 23629#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 23630#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 23631#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 24514#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 23423#L1081-3 assume !(0 == ~E_6~0); 23424#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 23473#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 23474#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 24487#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 24488#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 24113#L484-33 assume !(1 == ~m_pc~0); 24114#L484-35 is_master_triggered_~__retres1~0#1 := 0; 24023#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 24024#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 23324#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 23325#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 23766#L503-33 assume 1 == ~t1_pc~0; 23767#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 24258#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 24259#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 23689#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 23690#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 24147#L522-33 assume !(1 == ~t2_pc~0); 24148#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 23461#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 23462#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 24359#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 24171#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 24172#L541-33 assume 1 == ~t3_pc~0; 23481#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 23322#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 23323#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 23490#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 24142#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 24339#L560-33 assume 1 == ~t4_pc~0; 24027#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 23399#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 23400#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 24516#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 24318#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 23311#L579-33 assume 1 == ~t5_pc~0; 23312#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 23562#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 24532#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 24201#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 24202#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 24228#L598-33 assume !(1 == ~t6_pc~0); 23986#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 23794#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 23795#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 23653#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 23654#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 24476#L617-33 assume 1 == ~t7_pc~0; 24484#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 23455#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 24410#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 24429#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 24515#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 23389#L636-33 assume 1 == ~t8_pc~0; 23390#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 24311#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 24173#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 24174#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 24302#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 24303#L655-33 assume 1 == ~t9_pc~0; 24563#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 23740#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 23741#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 24362#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 24391#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 23933#L674-33 assume 1 == ~t10_pc~0; 23789#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 23790#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 24435#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 24159#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 24160#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 24537#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 24547#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 24549#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 24559#L1129-3 assume !(1 == ~T3_E~0); 23684#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 23685#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 23922#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 23923#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 24077#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 24354#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 24355#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 24522#L1169-3 assume !(1 == ~E_1~0); 23792#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 23793#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 24440#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 23446#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 23447#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 23737#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 23738#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 24061#L1209-3 assume !(1 == ~E_9~0); 23336#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 23337#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24263#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23426#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23780#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 23781#L1539 assume !(0 == start_simulation_~tmp~3#1); 23851#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 24038#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 23833#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 23367#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 23368#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 23745#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 24099#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 23852#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 23318#L1520-2 [2023-11-29 02:54:24,906 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:24,906 INFO L85 PathProgramCache]: Analyzing trace with hash 935428399, now seen corresponding path program 1 times [2023-11-29 02:54:24,907 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:24,907 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [17661686] [2023-11-29 02:54:24,907 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:24,907 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:24,927 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:25,025 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:25,026 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:25,026 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [17661686] [2023-11-29 02:54:25,026 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [17661686] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:25,026 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:25,026 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:25,026 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1613467559] [2023-11-29 02:54:25,027 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:25,027 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:25,027 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:25,028 INFO L85 PathProgramCache]: Analyzing trace with hash -1083369558, now seen corresponding path program 1 times [2023-11-29 02:54:25,028 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:25,028 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [544737979] [2023-11-29 02:54:25,028 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:25,028 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:25,044 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:25,086 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:25,086 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:25,086 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [544737979] [2023-11-29 02:54:25,086 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [544737979] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:25,087 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:25,087 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:25,087 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1112365922] [2023-11-29 02:54:25,087 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:25,087 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:25,087 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:25,088 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 02:54:25,088 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 02:54:25,088 INFO L87 Difference]: Start difference. First operand 1289 states and 1904 transitions. cyclomatic complexity: 616 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:25,229 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:25,229 INFO L93 Difference]: Finished difference Result 2460 states and 3626 transitions. [2023-11-29 02:54:25,229 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 2460 states and 3626 transitions. [2023-11-29 02:54:25,242 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2304 [2023-11-29 02:54:25,260 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 2460 states to 2460 states and 3626 transitions. [2023-11-29 02:54:25,260 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 2460 [2023-11-29 02:54:25,262 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 2460 [2023-11-29 02:54:25,262 INFO L73 IsDeterministic]: Start isDeterministic. Operand 2460 states and 3626 transitions. [2023-11-29 02:54:25,267 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:25,267 INFO L218 hiAutomatonCegarLoop]: Abstraction has 2460 states and 3626 transitions. [2023-11-29 02:54:25,270 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 2460 states and 3626 transitions. [2023-11-29 02:54:25,308 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 2460 to 2460. [2023-11-29 02:54:25,313 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 2460 states, 2460 states have (on average 1.4739837398373983) internal successors, (3626), 2459 states have internal predecessors, (3626), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:25,321 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 2460 states to 2460 states and 3626 transitions. [2023-11-29 02:54:25,321 INFO L240 hiAutomatonCegarLoop]: Abstraction has 2460 states and 3626 transitions. [2023-11-29 02:54:25,322 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 02:54:25,322 INFO L428 stractBuchiCegarLoop]: Abstraction has 2460 states and 3626 transitions. [2023-11-29 02:54:25,322 INFO L335 stractBuchiCegarLoop]: ======== Iteration 11 ============ [2023-11-29 02:54:25,323 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 2460 states and 3626 transitions. [2023-11-29 02:54:25,331 INFO L131 ngComponentsAnalysis]: Automaton has 2 accepting balls. 2304 [2023-11-29 02:54:25,331 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:25,331 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:25,333 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:25,333 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:25,334 INFO L748 eck$LassoCheckResult]: Stem: 27404#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 27405#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 28273#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 28274#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 28369#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 28359#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 28360#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 27571#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 27315#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 27316#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 28241#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 28242#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 28223#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 28224#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 28265#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 27365#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 27366#L1006 assume !(0 == ~M_E~0); 27217#L1006-2 assume !(0 == ~T1_E~0); 27218#L1011-1 assume !(0 == ~T2_E~0); 28296#L1016-1 assume !(0 == ~T3_E~0); 28318#L1021-1 assume !(0 == ~T4_E~0); 27091#L1026-1 assume !(0 == ~T5_E~0); 27092#L1031-1 assume !(0 == ~T6_E~0); 27991#L1036-1 assume !(0 == ~T7_E~0); 27988#L1041-1 assume !(0 == ~T8_E~0); 27989#L1046-1 assume !(0 == ~T9_E~0); 27395#L1051-1 assume !(0 == ~T10_E~0); 27396#L1056-1 assume 0 == ~E_1~0;~E_1~0 := 1; 28125#L1061-1 assume !(0 == ~E_2~0); 27319#L1066-1 assume !(0 == ~E_3~0); 27320#L1071-1 assume !(0 == ~E_4~0); 28100#L1076-1 assume !(0 == ~E_5~0); 27225#L1081-1 assume !(0 == ~E_6~0); 27226#L1086-1 assume !(0 == ~E_7~0); 27545#L1091-1 assume !(0 == ~E_8~0); 28284#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 28285#L1101-1 assume !(0 == ~E_10~0); 27617#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 27618#L484 assume !(1 == ~m_pc~0); 27276#L484-2 is_master_triggered_~__retres1~0#1 := 0; 27275#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 27901#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 28195#L1245 assume !(0 != activate_threads_~tmp~1#1); 28196#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 27978#L503 assume 1 == ~t1_pc~0; 27979#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 27997#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 27133#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 27134#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 27129#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 27130#L522 assume !(1 == ~t2_pc~0); 27941#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 27330#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 27331#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 27612#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 28243#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 28330#L541 assume 1 == ~t3_pc~0; 27883#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 27684#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 27075#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 27076#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 27948#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 27949#L560 assume !(1 == ~t4_pc~0); 27209#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 27208#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 27241#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 27089#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 27090#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 27376#L579 assume 1 == ~t5_pc~0; 27040#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 27041#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 27155#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 28200#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 28316#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28347#L598 assume 1 == ~t6_pc~0; 27460#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 27461#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 27586#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 27587#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 28026#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 27969#L617 assume !(1 == ~t7_pc~0); 27436#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 27435#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28373#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28256#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 27651#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 27652#L636 assume 1 == ~t8_pc~0; 27836#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 27837#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28153#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28034#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 27783#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 27784#L655 assume !(1 == ~t9_pc~0); 27811#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 27812#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 27694#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 27695#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 28047#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28048#L674 assume 1 == ~t10_pc~0; 27202#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 27203#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 27826#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 27827#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 27774#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 27775#L1119 assume !(1 == ~M_E~0); 27302#L1119-2 assume !(1 == ~T1_E~0); 27303#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 27705#L1129-1 assume !(1 == ~T3_E~0); 27119#L1134-1 assume !(1 == ~T4_E~0); 28729#L1139-1 assume !(1 == ~T5_E~0); 28725#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28462#L1149-1 assume !(1 == ~T7_E~0); 28461#L1154-1 assume !(1 == ~T8_E~0); 28459#L1159-1 assume !(1 == ~T9_E~0); 28457#L1164-1 assume !(1 == ~T10_E~0); 28456#L1169-1 assume !(1 == ~E_1~0); 28452#L1174-1 assume !(1 == ~E_2~0); 28450#L1179-1 assume !(1 == ~E_3~0); 28448#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 28447#L1189-1 assume !(1 == ~E_5~0); 28435#L1194-1 assume !(1 == ~E_6~0); 28433#L1199-1 assume !(1 == ~E_7~0); 28431#L1204-1 assume !(1 == ~E_8~0); 28429#L1209-1 assume !(1 == ~E_9~0); 28427#L1214-1 assume !(1 == ~E_10~0); 28414#L1219-1 assume { :end_inline_reset_delta_events } true; 28410#L1520-2 [2023-11-29 02:54:25,334 INFO L750 eck$LassoCheckResult]: Loop: 28410#L1520-2 assume !false; 28406#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 28404#L981-1 assume !false; 28403#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28394#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28391#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28390#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 28389#L836 assume !(0 != eval_~tmp~0#1); 28388#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 28387#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 28386#L1006-3 assume !(0 == ~M_E~0); 28385#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 28384#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 28293#L1016-3 assume !(0 == ~T3_E~0); 28188#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 27853#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 27854#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 28117#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 28118#L1041-3 assume !(0 == ~T8_E~0); 28180#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 28181#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 28119#L1056-3 assume 0 == ~E_1~0;~E_1~0 := 1; 27392#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 27393#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 27394#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 28300#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 27184#L1081-3 assume !(0 == ~E_6~0); 27185#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 29088#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 29086#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 29084#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 29082#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 29081#L484-33 assume 1 == ~m_pc~0; 29079#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 29076#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 29074#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 29072#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 29070#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 29068#L503-33 assume 1 == ~t1_pc~0; 29065#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 29064#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 29063#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 29062#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 29059#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 29057#L522-33 assume 1 == ~t2_pc~0; 29054#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 29052#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 29050#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 29048#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 29045#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 29043#L541-33 assume !(1 == ~t3_pc~0); 29040#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 29037#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 29035#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 29032#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 29030#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 29028#L560-33 assume !(1 == ~t4_pc~0); 29025#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 29023#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 29021#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 29018#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 29016#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 29014#L579-33 assume 1 == ~t5_pc~0; 29011#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 28324#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 28325#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 27970#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 27971#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 28002#L598-33 assume !(1 == ~t6_pc~0); 28994#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 28992#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 28990#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 28988#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 28986#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 28983#L617-33 assume 1 == ~t7_pc~0; 28980#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 28978#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 28976#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 28974#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 28972#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 28969#L636-33 assume !(1 == ~t8_pc~0); 28966#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 28964#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 28962#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 28960#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 28958#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 28956#L655-33 assume 1 == ~t9_pc~0; 28953#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 28952#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 28951#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 28949#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 28947#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 28945#L674-33 assume 1 == ~t10_pc~0; 28942#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 28940#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 28938#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 28936#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 28934#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 28932#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 28930#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 28928#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 28382#L1129-3 assume !(1 == ~T3_E~0); 28364#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 28925#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 28924#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 28923#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 28922#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 28921#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 28920#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 28919#L1169-3 assume !(1 == ~E_1~0); 28917#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 28343#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 28218#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 27210#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 27211#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 27500#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 27501#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 27828#L1209-3 assume !(1 == ~E_9~0); 27097#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 27098#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28036#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 27187#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28277#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 28723#L1539 assume !(0 == start_simulation_~tmp~3#1); 28719#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 28446#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 28434#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 28432#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 28430#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 28428#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 28426#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 28413#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 28410#L1520-2 [2023-11-29 02:54:25,334 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:25,334 INFO L85 PathProgramCache]: Analyzing trace with hash -388783629, now seen corresponding path program 1 times [2023-11-29 02:54:25,335 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:25,335 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [168273318] [2023-11-29 02:54:25,335 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:25,335 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:25,350 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:25,413 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:25,413 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:25,413 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [168273318] [2023-11-29 02:54:25,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [168273318] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:25,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:25,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:25,414 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [39764000] [2023-11-29 02:54:25,414 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:25,414 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:25,415 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:25,415 INFO L85 PathProgramCache]: Analyzing trace with hash -876991093, now seen corresponding path program 1 times [2023-11-29 02:54:25,415 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:25,415 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1221360750] [2023-11-29 02:54:25,415 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:25,415 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:25,431 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:25,473 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:25,473 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:25,473 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1221360750] [2023-11-29 02:54:25,473 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1221360750] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:25,473 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:25,473 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:25,474 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1382791073] [2023-11-29 02:54:25,474 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:25,474 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:25,474 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:25,475 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 02:54:25,475 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 02:54:25,475 INFO L87 Difference]: Start difference. First operand 2460 states and 3626 transitions. cyclomatic complexity: 1168 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:25,681 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:25,681 INFO L93 Difference]: Finished difference Result 4636 states and 6829 transitions. [2023-11-29 02:54:25,681 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 4636 states and 6829 transitions. [2023-11-29 02:54:25,726 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4448 [2023-11-29 02:54:25,759 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 4636 states to 4636 states and 6829 transitions. [2023-11-29 02:54:25,760 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 4636 [2023-11-29 02:54:25,764 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 4636 [2023-11-29 02:54:25,764 INFO L73 IsDeterministic]: Start isDeterministic. Operand 4636 states and 6829 transitions. [2023-11-29 02:54:25,773 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:25,773 INFO L218 hiAutomatonCegarLoop]: Abstraction has 4636 states and 6829 transitions. [2023-11-29 02:54:25,780 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 4636 states and 6829 transitions. [2023-11-29 02:54:25,862 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 4636 to 4632. [2023-11-29 02:54:25,872 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 4632 states, 4632 states have (on average 1.4734455958549222) internal successors, (6825), 4631 states have internal predecessors, (6825), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:25,889 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 4632 states to 4632 states and 6825 transitions. [2023-11-29 02:54:25,889 INFO L240 hiAutomatonCegarLoop]: Abstraction has 4632 states and 6825 transitions. [2023-11-29 02:54:25,889 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 02:54:25,890 INFO L428 stractBuchiCegarLoop]: Abstraction has 4632 states and 6825 transitions. [2023-11-29 02:54:25,890 INFO L335 stractBuchiCegarLoop]: ======== Iteration 12 ============ [2023-11-29 02:54:25,890 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 4632 states and 6825 transitions. [2023-11-29 02:54:25,911 INFO L131 ngComponentsAnalysis]: Automaton has 4 accepting balls. 4448 [2023-11-29 02:54:25,912 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:25,912 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:25,914 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:25,915 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:25,915 INFO L748 eck$LassoCheckResult]: Stem: 34509#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 34510#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 35379#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 35380#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 35455#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 35448#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 35449#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 34676#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 34420#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 34421#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 35347#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 35348#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 35329#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 35330#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 35371#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 34472#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 34473#L1006 assume !(0 == ~M_E~0); 34322#L1006-2 assume !(0 == ~T1_E~0); 34323#L1011-1 assume !(0 == ~T2_E~0); 35396#L1016-1 assume !(0 == ~T3_E~0); 35415#L1021-1 assume !(0 == ~T4_E~0); 34199#L1026-1 assume !(0 == ~T5_E~0); 34200#L1031-1 assume !(0 == ~T6_E~0); 35097#L1036-1 assume !(0 == ~T7_E~0); 35094#L1041-1 assume !(0 == ~T8_E~0); 35095#L1046-1 assume !(0 == ~T9_E~0); 34500#L1051-1 assume !(0 == ~T10_E~0); 34501#L1056-1 assume !(0 == ~E_1~0); 35229#L1061-1 assume !(0 == ~E_2~0); 34424#L1066-1 assume !(0 == ~E_3~0); 34425#L1071-1 assume !(0 == ~E_4~0); 35203#L1076-1 assume !(0 == ~E_5~0); 34330#L1081-1 assume !(0 == ~E_6~0); 34331#L1086-1 assume !(0 == ~E_7~0); 34650#L1091-1 assume !(0 == ~E_8~0); 35388#L1096-1 assume 0 == ~E_9~0;~E_9~0 := 1; 35389#L1101-1 assume !(0 == ~E_10~0); 34721#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 34722#L484 assume !(1 == ~m_pc~0); 34381#L484-2 is_master_triggered_~__retres1~0#1 := 0; 34380#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 35008#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 35297#L1245 assume !(0 != activate_threads_~tmp~1#1); 35298#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 35084#L503 assume 1 == ~t1_pc~0; 35085#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 35103#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 34240#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 34241#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 34234#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 34235#L522 assume !(1 == ~t2_pc~0); 35047#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 34435#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 34436#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 34716#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 35349#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 35424#L541 assume 1 == ~t3_pc~0; 34990#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 34789#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 34181#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 34182#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 35053#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 35054#L560 assume !(1 == ~t4_pc~0); 34316#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 34315#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 34346#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 34195#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 34196#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 34481#L579 assume 1 == ~t5_pc~0; 34146#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 34147#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 34260#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 35302#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 35413#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 35438#L598 assume 1 == ~t6_pc~0; 34565#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 34566#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 34691#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 34692#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 35132#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 35075#L617 assume !(1 == ~t7_pc~0); 34541#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 34540#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 35459#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 35361#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 34756#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 34757#L636 assume 1 == ~t8_pc~0; 34943#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 34944#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 35257#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35142#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 34888#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 34889#L655 assume !(1 == ~t9_pc~0); 34919#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 34920#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 34803#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 34804#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 35153#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35154#L674 assume 1 == ~t10_pc~0; 34307#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 34308#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 34934#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 34935#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 34879#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 34880#L1119 assume !(1 == ~M_E~0); 34407#L1119-2 assume !(1 == ~T1_E~0); 34408#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 34224#L1129-1 assume !(1 == ~T3_E~0); 34225#L1134-1 assume !(1 == ~T4_E~0); 35064#L1139-1 assume !(1 == ~T5_E~0); 34751#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 34752#L1149-1 assume !(1 == ~T7_E~0); 34401#L1154-1 assume !(1 == ~T8_E~0); 34402#L1159-1 assume !(1 == ~T9_E~0); 34484#L1164-1 assume !(1 == ~T10_E~0); 35563#L1169-1 assume !(1 == ~E_1~0); 35559#L1174-1 assume !(1 == ~E_2~0); 35558#L1179-1 assume !(1 == ~E_3~0); 35556#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 35554#L1189-1 assume !(1 == ~E_5~0); 35552#L1194-1 assume !(1 == ~E_6~0); 35551#L1199-1 assume !(1 == ~E_7~0); 35533#L1204-1 assume !(1 == ~E_8~0); 35521#L1209-1 assume !(1 == ~E_9~0); 35512#L1214-1 assume !(1 == ~E_10~0); 35504#L1219-1 assume { :end_inline_reset_delta_events } true; 35498#L1520-2 [2023-11-29 02:54:25,916 INFO L750 eck$LassoCheckResult]: Loop: 35498#L1520-2 assume !false; 35493#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 35491#L981-1 assume !false; 35490#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35481#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35478#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35477#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 35475#L836 assume !(0 != eval_~tmp~0#1); 35474#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 35473#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 35472#L1006-3 assume !(0 == ~M_E~0); 35471#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 35469#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 35470#L1016-3 assume !(0 == ~T3_E~0); 36980#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 36943#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 36851#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 36849#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 36847#L1041-3 assume !(0 == ~T8_E~0); 36845#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 36843#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 36841#L1056-3 assume !(0 == ~E_1~0); 36839#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 36837#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 36832#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 36826#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 36820#L1081-3 assume !(0 == ~E_6~0); 36815#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 36810#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 36805#L1096-3 assume 0 == ~E_9~0;~E_9~0 := 1; 36799#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 36793#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 36787#L484-33 assume 1 == ~m_pc~0; 36781#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 36776#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 36772#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 36767#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 36761#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 36757#L503-33 assume 1 == ~t1_pc~0; 36752#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 36748#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 36743#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 36736#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 36729#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 36724#L522-33 assume 1 == ~t2_pc~0; 36718#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 36713#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 36708#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 36701#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 36694#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 36689#L541-33 assume 1 == ~t3_pc~0; 36683#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 36678#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 36673#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 36666#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 36659#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 36654#L560-33 assume !(1 == ~t4_pc~0); 36648#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 36644#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 36640#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 36634#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 36269#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 36266#L579-33 assume 1 == ~t5_pc~0; 36263#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 36261#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 36259#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 36257#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 36255#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 36252#L598-33 assume !(1 == ~t6_pc~0); 36249#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 36247#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 36245#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 36243#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 36241#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 36238#L617-33 assume 1 == ~t7_pc~0; 36208#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 36206#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 36203#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 36201#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 36198#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 36196#L636-33 assume !(1 == ~t8_pc~0); 36193#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 36191#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 36190#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 35938#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 35936#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 35933#L655-33 assume 1 == ~t9_pc~0; 35929#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 35927#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 35925#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 35923#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 35920#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 35918#L674-33 assume 1 == ~t10_pc~0; 35913#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 35911#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 35908#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 35684#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 35681#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 35677#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 35673#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 35669#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 35467#L1129-3 assume !(1 == ~T3_E~0); 35662#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 35659#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 35656#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 35653#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 35650#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 35647#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 35643#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 35639#L1169-3 assume !(1 == ~E_1~0); 35637#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 35635#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 35633#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 35631#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 35628#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 35626#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 35625#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 35623#L1209-3 assume !(1 == ~E_9~0); 35621#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 35619#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35617#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35605#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35603#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 35600#L1539 assume !(0 == start_simulation_~tmp~3#1); 35598#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 35597#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 35584#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 35550#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 35532#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 35520#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 35511#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 35503#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 35498#L1520-2 [2023-11-29 02:54:25,916 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:25,916 INFO L85 PathProgramCache]: Analyzing trace with hash 642257269, now seen corresponding path program 1 times [2023-11-29 02:54:25,917 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:25,917 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1874660759] [2023-11-29 02:54:25,917 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:25,917 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:25,936 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:26,003 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:26,004 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:26,004 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1874660759] [2023-11-29 02:54:26,004 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1874660759] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:26,004 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:26,004 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:26,005 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1485937583] [2023-11-29 02:54:26,005 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:26,005 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:26,006 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:26,006 INFO L85 PathProgramCache]: Analyzing trace with hash -539525330, now seen corresponding path program 1 times [2023-11-29 02:54:26,006 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:26,006 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [718208440] [2023-11-29 02:54:26,006 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:26,006 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:26,023 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:26,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:26,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:26,066 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [718208440] [2023-11-29 02:54:26,066 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [718208440] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:26,066 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:26,066 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:26,066 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [224641460] [2023-11-29 02:54:26,066 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:26,067 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:26,067 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:26,067 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 02:54:26,067 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 02:54:26,067 INFO L87 Difference]: Start difference. First operand 4632 states and 6825 transitions. cyclomatic complexity: 2197 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:26,287 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:26,287 INFO L93 Difference]: Finished difference Result 8784 states and 12922 transitions. [2023-11-29 02:54:26,288 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 8784 states and 12922 transitions. [2023-11-29 02:54:26,330 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8580 [2023-11-29 02:54:26,376 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 8784 states to 8784 states and 12922 transitions. [2023-11-29 02:54:26,376 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 8784 [2023-11-29 02:54:26,385 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 8784 [2023-11-29 02:54:26,385 INFO L73 IsDeterministic]: Start isDeterministic. Operand 8784 states and 12922 transitions. [2023-11-29 02:54:26,400 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:26,400 INFO L218 hiAutomatonCegarLoop]: Abstraction has 8784 states and 12922 transitions. [2023-11-29 02:54:26,411 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 8784 states and 12922 transitions. [2023-11-29 02:54:26,548 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 8784 to 8780. [2023-11-29 02:54:26,563 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 8780 states, 8780 states have (on average 1.4712984054669704) internal successors, (12918), 8779 states have internal predecessors, (12918), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:26,579 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 8780 states to 8780 states and 12918 transitions. [2023-11-29 02:54:26,580 INFO L240 hiAutomatonCegarLoop]: Abstraction has 8780 states and 12918 transitions. [2023-11-29 02:54:26,580 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 02:54:26,580 INFO L428 stractBuchiCegarLoop]: Abstraction has 8780 states and 12918 transitions. [2023-11-29 02:54:26,581 INFO L335 stractBuchiCegarLoop]: ======== Iteration 13 ============ [2023-11-29 02:54:26,581 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 8780 states and 12918 transitions. [2023-11-29 02:54:26,604 INFO L131 ngComponentsAnalysis]: Automaton has 8 accepting balls. 8580 [2023-11-29 02:54:26,604 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:26,605 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:26,606 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:26,606 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:26,607 INFO L748 eck$LassoCheckResult]: Stem: 47932#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 47933#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 48803#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 48804#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 48883#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 48875#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 48876#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 48100#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 47844#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 47845#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 48771#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 48772#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 48753#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 48754#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 48795#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 47893#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 47894#L1006 assume !(0 == ~M_E~0); 47747#L1006-2 assume !(0 == ~T1_E~0); 47748#L1011-1 assume !(0 == ~T2_E~0); 48822#L1016-1 assume !(0 == ~T3_E~0); 48841#L1021-1 assume !(0 == ~T4_E~0); 47623#L1026-1 assume !(0 == ~T5_E~0); 47624#L1031-1 assume !(0 == ~T6_E~0); 48524#L1036-1 assume !(0 == ~T7_E~0); 48521#L1041-1 assume !(0 == ~T8_E~0); 48522#L1046-1 assume !(0 == ~T9_E~0); 47923#L1051-1 assume !(0 == ~T10_E~0); 47924#L1056-1 assume !(0 == ~E_1~0); 48653#L1061-1 assume !(0 == ~E_2~0); 47848#L1066-1 assume !(0 == ~E_3~0); 47849#L1071-1 assume !(0 == ~E_4~0); 48628#L1076-1 assume !(0 == ~E_5~0); 47755#L1081-1 assume !(0 == ~E_6~0); 47756#L1086-1 assume !(0 == ~E_7~0); 48074#L1091-1 assume !(0 == ~E_8~0); 48811#L1096-1 assume !(0 == ~E_9~0); 48812#L1101-1 assume !(0 == ~E_10~0); 48146#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 48147#L484 assume !(1 == ~m_pc~0); 47805#L484-2 is_master_triggered_~__retres1~0#1 := 0; 47804#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 48434#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 48725#L1245 assume !(0 != activate_threads_~tmp~1#1); 48726#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 48511#L503 assume 1 == ~t1_pc~0; 48512#L504 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 48530#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 47664#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 47665#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 47660#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 47661#L522 assume !(1 == ~t2_pc~0); 48474#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 47859#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 47860#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 48140#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 48773#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 48850#L541 assume 1 == ~t3_pc~0; 48416#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 48213#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 47607#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 47608#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 48480#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 48481#L560 assume !(1 == ~t4_pc~0); 47739#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 47738#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 47771#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 47621#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 47622#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 47904#L579 assume 1 == ~t5_pc~0; 47572#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 47573#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 47686#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 48730#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 48839#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 48860#L598 assume 1 == ~t6_pc~0; 47989#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 47990#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 48115#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 48116#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 48558#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 48502#L617 assume !(1 == ~t7_pc~0); 47965#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 47964#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 48887#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 48786#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 48180#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 48181#L636 assume 1 == ~t8_pc~0; 48368#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 48369#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 48685#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 48567#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 48312#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 48313#L655 assume !(1 == ~t9_pc~0); 48341#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 48342#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 48223#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 48224#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 48579#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 48580#L674 assume 1 == ~t10_pc~0; 47732#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 47733#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 48356#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 48357#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 48303#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 48304#L1119 assume !(1 == ~M_E~0); 47831#L1119-2 assume !(1 == ~T1_E~0); 47832#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 47650#L1129-1 assume !(1 == ~T3_E~0); 47651#L1134-1 assume !(1 == ~T4_E~0); 47948#L1139-1 assume !(1 == ~T5_E~0); 47949#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 48176#L1149-1 assume !(1 == ~T7_E~0); 47825#L1154-1 assume !(1 == ~T8_E~0); 47826#L1159-1 assume !(1 == ~T9_E~0); 47907#L1164-1 assume !(1 == ~T10_E~0); 48889#L1169-1 assume !(1 == ~E_1~0); 49018#L1174-1 assume !(1 == ~E_2~0); 48972#L1179-1 assume !(1 == ~E_3~0); 48970#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 48968#L1189-1 assume !(1 == ~E_5~0); 48967#L1194-1 assume !(1 == ~E_6~0); 48965#L1199-1 assume !(1 == ~E_7~0); 48963#L1204-1 assume !(1 == ~E_8~0); 48949#L1209-1 assume !(1 == ~E_9~0); 48938#L1214-1 assume !(1 == ~E_10~0); 48930#L1219-1 assume { :end_inline_reset_delta_events } true; 48924#L1520-2 [2023-11-29 02:54:26,607 INFO L750 eck$LassoCheckResult]: Loop: 48924#L1520-2 assume !false; 48919#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 48917#L981-1 assume !false; 48916#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48907#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48904#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48903#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 48901#L836 assume !(0 != eval_~tmp~0#1); 48900#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 48899#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 48898#L1006-3 assume !(0 == ~M_E~0); 48897#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 48895#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 48896#L1016-3 assume !(0 == ~T3_E~0); 49813#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 49804#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 49797#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 49790#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 49781#L1041-3 assume !(0 == ~T8_E~0); 49774#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 49766#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 49758#L1056-3 assume !(0 == ~E_1~0); 49751#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 49744#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 49734#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 49727#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 49719#L1081-3 assume !(0 == ~E_6~0); 49710#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 49703#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 49696#L1096-3 assume !(0 == ~E_9~0); 49686#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 49679#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 49671#L484-33 assume 1 == ~m_pc~0; 49661#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 49654#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 49647#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 49637#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 49630#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 49622#L503-33 assume 1 == ~t1_pc~0; 49612#L504-11 assume 1 == ~E_1~0;is_transmit1_triggered_~__retres1~1#1 := 1; 49605#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 49598#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 49588#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 49581#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 49573#L522-33 assume 1 == ~t2_pc~0; 49563#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 49556#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 49549#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 49539#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 49532#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 49524#L541-33 assume 1 == ~t3_pc~0; 49514#L542-11 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 49507#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 49501#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 49456#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 49454#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 49452#L560-33 assume !(1 == ~t4_pc~0); 49449#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 49447#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 49444#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 49442#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 49440#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 49438#L579-33 assume 1 == ~t5_pc~0; 49433#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 49431#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 49429#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 49427#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 49425#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 49422#L598-33 assume !(1 == ~t6_pc~0); 49419#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 49417#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 49415#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 49413#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 49411#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 49410#L617-33 assume 1 == ~t7_pc~0; 49406#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 49404#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 49402#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 49400#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 49398#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 49396#L636-33 assume !(1 == ~t8_pc~0); 49394#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 49391#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 49389#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 49387#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 49385#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 49383#L655-33 assume 1 == ~t9_pc~0; 49379#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 49377#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 49375#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 49373#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 49371#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 49368#L674-33 assume 1 == ~t10_pc~0; 49342#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 49335#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 49328#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 49321#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 49314#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 49307#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 49300#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 49293#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 48893#L1129-3 assume !(1 == ~T3_E~0); 49282#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 49278#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 49273#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 49267#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 49262#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 49257#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 49252#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 49246#L1169-3 assume !(1 == ~E_1~0); 49243#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 49239#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 49236#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 49233#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 49230#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 49227#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 49224#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 49219#L1209-3 assume !(1 == ~E_9~0); 49217#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 49215#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 49211#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 49198#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 49196#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 49194#L1539 assume !(0 == start_simulation_~tmp~3#1); 49191#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 48991#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 48977#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 48975#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 48961#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 48946#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 48937#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 48929#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 48924#L1520-2 [2023-11-29 02:54:26,607 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:26,607 INFO L85 PathProgramCache]: Analyzing trace with hash -1298324745, now seen corresponding path program 1 times [2023-11-29 02:54:26,608 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:26,608 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [370099598] [2023-11-29 02:54:26,608 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:26,608 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:26,619 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:26,654 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:26,654 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:26,654 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [370099598] [2023-11-29 02:54:26,654 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [370099598] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:26,655 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:26,655 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:54:26,655 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1989069244] [2023-11-29 02:54:26,655 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:26,655 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:26,656 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:26,656 INFO L85 PathProgramCache]: Analyzing trace with hash 1722047920, now seen corresponding path program 1 times [2023-11-29 02:54:26,656 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:26,656 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1658092223] [2023-11-29 02:54:26,656 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:26,657 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:26,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:26,695 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:26,695 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:26,695 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1658092223] [2023-11-29 02:54:26,695 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1658092223] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:26,695 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:26,695 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:26,696 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [468356637] [2023-11-29 02:54:26,696 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:26,696 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:26,696 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:26,697 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:26,697 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:26,697 INFO L87 Difference]: Start difference. First operand 8780 states and 12918 transitions. cyclomatic complexity: 4146 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:26,833 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:26,833 INFO L93 Difference]: Finished difference Result 16639 states and 24352 transitions. [2023-11-29 02:54:26,833 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 16639 states and 24352 transitions. [2023-11-29 02:54:26,883 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16424 [2023-11-29 02:54:27,000 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 16639 states to 16639 states and 24352 transitions. [2023-11-29 02:54:27,000 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 16639 [2023-11-29 02:54:27,015 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 16639 [2023-11-29 02:54:27,015 INFO L73 IsDeterministic]: Start isDeterministic. Operand 16639 states and 24352 transitions. [2023-11-29 02:54:27,035 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:27,035 INFO L218 hiAutomatonCegarLoop]: Abstraction has 16639 states and 24352 transitions. [2023-11-29 02:54:27,054 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 16639 states and 24352 transitions. [2023-11-29 02:54:27,243 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 16639 to 16623. [2023-11-29 02:54:27,269 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 16623 states, 16623 states have (on average 1.4639956686518678) internal successors, (24336), 16622 states have internal predecessors, (24336), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:27,389 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 16623 states to 16623 states and 24336 transitions. [2023-11-29 02:54:27,389 INFO L240 hiAutomatonCegarLoop]: Abstraction has 16623 states and 24336 transitions. [2023-11-29 02:54:27,389 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:27,390 INFO L428 stractBuchiCegarLoop]: Abstraction has 16623 states and 24336 transitions. [2023-11-29 02:54:27,390 INFO L335 stractBuchiCegarLoop]: ======== Iteration 14 ============ [2023-11-29 02:54:27,390 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 16623 states and 24336 transitions. [2023-11-29 02:54:27,443 INFO L131 ngComponentsAnalysis]: Automaton has 16 accepting balls. 16408 [2023-11-29 02:54:27,444 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:27,444 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:27,446 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:27,446 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:27,447 INFO L748 eck$LassoCheckResult]: Stem: 73361#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 73362#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 74253#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 74254#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 74357#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 74347#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 74348#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 73530#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 73271#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 73272#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 74218#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 74219#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 74199#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 74200#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 74245#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 73323#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 73324#L1006 assume !(0 == ~M_E~0); 73174#L1006-2 assume !(0 == ~T1_E~0); 73175#L1011-1 assume !(0 == ~T2_E~0); 74273#L1016-1 assume !(0 == ~T3_E~0); 74292#L1021-1 assume !(0 == ~T4_E~0); 73051#L1026-1 assume !(0 == ~T5_E~0); 73052#L1031-1 assume !(0 == ~T6_E~0); 73952#L1036-1 assume !(0 == ~T7_E~0); 73948#L1041-1 assume !(0 == ~T8_E~0); 73949#L1046-1 assume !(0 == ~T9_E~0); 73352#L1051-1 assume !(0 == ~T10_E~0); 73353#L1056-1 assume !(0 == ~E_1~0); 74086#L1061-1 assume !(0 == ~E_2~0); 73275#L1066-1 assume !(0 == ~E_3~0); 73276#L1071-1 assume !(0 == ~E_4~0); 74061#L1076-1 assume !(0 == ~E_5~0); 73181#L1081-1 assume !(0 == ~E_6~0); 73182#L1086-1 assume !(0 == ~E_7~0); 73502#L1091-1 assume !(0 == ~E_8~0); 74264#L1096-1 assume !(0 == ~E_9~0); 74265#L1101-1 assume !(0 == ~E_10~0); 73573#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 73574#L484 assume !(1 == ~m_pc~0); 73232#L484-2 is_master_triggered_~__retres1~0#1 := 0; 73231#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 73862#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 74170#L1245 assume !(0 != activate_threads_~tmp~1#1); 74171#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 73939#L503 assume !(1 == ~t1_pc~0); 73940#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 74121#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 73092#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 73093#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 73086#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 73087#L522 assume !(1 == ~t2_pc~0); 73901#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 73286#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 73287#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 73568#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 74220#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 74304#L541 assume 1 == ~t3_pc~0; 73843#L542 assume 1 == ~E_3~0;is_transmit3_triggered_~__retres1~3#1 := 1; 73640#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 73035#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 73036#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 73907#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 73908#L560 assume !(1 == ~t4_pc~0); 73168#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 73167#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 73197#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 73047#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 73048#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 73332#L579 assume 1 == ~t5_pc~0; 72998#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 72999#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 73112#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 74175#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 74291#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 74328#L598 assume 1 == ~t6_pc~0; 73416#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 73417#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 73545#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 73546#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 73986#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 73930#L617 assume !(1 == ~t7_pc~0); 73392#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 73391#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 74365#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 74235#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 73608#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 73609#L636 assume 1 == ~t8_pc~0; 73792#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 73793#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 74122#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 73995#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 73738#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 73739#L655 assume !(1 == ~t9_pc~0); 73769#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 73770#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 73654#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 73655#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 74005#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 74006#L674 assume 1 == ~t10_pc~0; 73159#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 73160#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 73783#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 73784#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 73729#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 73730#L1119 assume !(1 == ~M_E~0); 73258#L1119-2 assume !(1 == ~T1_E~0); 73259#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 73076#L1129-1 assume !(1 == ~T3_E~0); 73077#L1134-1 assume !(1 == ~T4_E~0); 84233#L1139-1 assume !(1 == ~T5_E~0); 84231#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 84229#L1149-1 assume !(1 == ~T7_E~0); 84227#L1154-1 assume !(1 == ~T8_E~0); 73335#L1159-1 assume !(1 == ~T9_E~0); 73336#L1164-1 assume !(1 == ~T10_E~0); 73757#L1169-1 assume !(1 == ~E_1~0); 73758#L1174-1 assume !(1 == ~E_2~0); 86381#L1179-1 assume !(1 == ~E_3~0); 86379#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 86377#L1189-1 assume !(1 == ~E_5~0); 86375#L1194-1 assume !(1 == ~E_6~0); 86372#L1199-1 assume !(1 == ~E_7~0); 86370#L1204-1 assume !(1 == ~E_8~0); 86252#L1209-1 assume !(1 == ~E_9~0); 86240#L1214-1 assume !(1 == ~E_10~0); 86230#L1219-1 assume { :end_inline_reset_delta_events } true; 86223#L1520-2 [2023-11-29 02:54:27,447 INFO L750 eck$LassoCheckResult]: Loop: 86223#L1520-2 assume !false; 86217#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 86214#L981-1 assume !false; 86213#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 86203#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 86198#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 86196#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 86193#L836 assume !(0 != eval_~tmp~0#1); 86194#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 88270#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 88268#L1006-3 assume !(0 == ~M_E~0); 88266#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 88264#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 88261#L1016-3 assume !(0 == ~T3_E~0); 88259#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 88257#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 88255#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 88253#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 88251#L1041-3 assume !(0 == ~T8_E~0); 88248#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 88246#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 88244#L1056-3 assume !(0 == ~E_1~0); 88242#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 88240#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 88238#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 88235#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 88233#L1081-3 assume !(0 == ~E_6~0); 88231#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 88229#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 88227#L1096-3 assume !(0 == ~E_9~0); 88225#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 88222#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 88220#L484-33 assume 1 == ~m_pc~0; 88217#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 88215#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 88213#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 88212#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 88211#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 88208#L503-33 assume !(1 == ~t1_pc~0); 88206#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 88204#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 88203#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 88175#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 88167#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 88145#L522-33 assume !(1 == ~t2_pc~0); 87121#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 87116#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 87114#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 87112#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 87111#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 87108#L541-33 assume !(1 == ~t3_pc~0); 87104#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 87099#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 87095#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 87091#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 87087#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 87082#L560-33 assume !(1 == ~t4_pc~0); 87079#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 87077#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 87076#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 87075#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 87074#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 87073#L579-33 assume !(1 == ~t5_pc~0); 87072#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 87070#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 87069#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 87068#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 87067#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 87066#L598-33 assume 1 == ~t6_pc~0; 87065#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 87052#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 87050#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 87048#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 87045#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 87043#L617-33 assume !(1 == ~t7_pc~0); 87041#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 87038#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 87036#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 87034#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 87032#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 87030#L636-33 assume !(1 == ~t8_pc~0); 87027#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 87025#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 87023#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 87021#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 87019#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 87017#L655-33 assume !(1 == ~t9_pc~0); 87015#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 87012#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 87010#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 87008#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 87006#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 87004#L674-33 assume 1 == ~t10_pc~0; 87001#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 86999#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 86997#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 86995#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 86993#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 86991#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 86988#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 86986#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 74373#L1129-3 assume !(1 == ~T3_E~0); 74352#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 86982#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 86980#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 86978#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 86976#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 86974#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 86972#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 86970#L1169-3 assume !(1 == ~E_1~0); 83080#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 86966#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 86964#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 86962#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 86960#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 86958#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 86956#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 86732#L1209-3 assume !(1 == ~E_9~0); 86730#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 86728#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 86726#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 86714#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 86712#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 86708#L1539 assume !(0 == start_simulation_~tmp~3#1); 86705#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 86703#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 86689#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 86685#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 86350#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 86249#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 86239#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 86229#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 86223#L1520-2 [2023-11-29 02:54:27,447 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:27,448 INFO L85 PathProgramCache]: Analyzing trace with hash 1011813846, now seen corresponding path program 1 times [2023-11-29 02:54:27,448 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:27,448 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1238326978] [2023-11-29 02:54:27,448 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:27,448 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:27,463 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:27,516 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:27,516 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:27,516 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1238326978] [2023-11-29 02:54:27,516 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1238326978] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:27,516 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:27,517 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:54:27,517 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1450083415] [2023-11-29 02:54:27,517 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:27,517 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:27,518 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:27,518 INFO L85 PathProgramCache]: Analyzing trace with hash -1035405429, now seen corresponding path program 1 times [2023-11-29 02:54:27,518 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:27,518 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1278187658] [2023-11-29 02:54:27,519 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:27,519 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:27,536 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:27,674 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:27,675 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:27,675 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1278187658] [2023-11-29 02:54:27,675 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1278187658] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:27,675 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:27,676 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:54:27,676 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2100586292] [2023-11-29 02:54:27,676 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:27,677 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:27,677 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:27,677 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:27,678 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:27,678 INFO L87 Difference]: Start difference. First operand 16623 states and 24336 transitions. cyclomatic complexity: 7729 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:28,013 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:28,013 INFO L93 Difference]: Finished difference Result 31606 states and 46055 transitions. [2023-11-29 02:54:28,014 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 31606 states and 46055 transitions. [2023-11-29 02:54:28,148 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31360 [2023-11-29 02:54:28,338 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 31606 states to 31606 states and 46055 transitions. [2023-11-29 02:54:28,338 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 31606 [2023-11-29 02:54:28,359 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 31606 [2023-11-29 02:54:28,359 INFO L73 IsDeterministic]: Start isDeterministic. Operand 31606 states and 46055 transitions. [2023-11-29 02:54:28,376 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:28,377 INFO L218 hiAutomatonCegarLoop]: Abstraction has 31606 states and 46055 transitions. [2023-11-29 02:54:28,400 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 31606 states and 46055 transitions. [2023-11-29 02:54:28,695 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 31606 to 31574. [2023-11-29 02:54:28,730 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 31574 states, 31574 states have (on average 1.4576233609932223) internal successors, (46023), 31573 states have internal predecessors, (46023), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:28,791 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 31574 states to 31574 states and 46023 transitions. [2023-11-29 02:54:28,791 INFO L240 hiAutomatonCegarLoop]: Abstraction has 31574 states and 46023 transitions. [2023-11-29 02:54:28,791 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:28,792 INFO L428 stractBuchiCegarLoop]: Abstraction has 31574 states and 46023 transitions. [2023-11-29 02:54:28,792 INFO L335 stractBuchiCegarLoop]: ======== Iteration 15 ============ [2023-11-29 02:54:28,792 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 31574 states and 46023 transitions. [2023-11-29 02:54:28,864 INFO L131 ngComponentsAnalysis]: Automaton has 32 accepting balls. 31328 [2023-11-29 02:54:28,865 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:28,865 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:28,866 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:28,866 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:28,867 INFO L748 eck$LassoCheckResult]: Stem: 121598#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 121599#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 122507#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 122508#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 122614#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 122606#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 122607#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 121767#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 121509#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 121510#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 122467#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 122468#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 122447#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 122448#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 122497#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 121559#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 121560#L1006 assume !(0 == ~M_E~0); 121411#L1006-2 assume !(0 == ~T1_E~0); 121412#L1011-1 assume !(0 == ~T2_E~0); 122533#L1016-1 assume !(0 == ~T3_E~0); 122556#L1021-1 assume !(0 == ~T4_E~0); 121287#L1026-1 assume !(0 == ~T5_E~0); 121288#L1031-1 assume !(0 == ~T6_E~0); 122190#L1036-1 assume !(0 == ~T7_E~0); 122187#L1041-1 assume !(0 == ~T8_E~0); 122188#L1046-1 assume !(0 == ~T9_E~0); 121589#L1051-1 assume !(0 == ~T10_E~0); 121590#L1056-1 assume !(0 == ~E_1~0); 122331#L1061-1 assume !(0 == ~E_2~0); 121513#L1066-1 assume !(0 == ~E_3~0); 121514#L1071-1 assume !(0 == ~E_4~0); 122306#L1076-1 assume !(0 == ~E_5~0); 121419#L1081-1 assume !(0 == ~E_6~0); 121420#L1086-1 assume !(0 == ~E_7~0); 121741#L1091-1 assume !(0 == ~E_8~0); 122519#L1096-1 assume !(0 == ~E_9~0); 122520#L1101-1 assume !(0 == ~E_10~0); 121812#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 121813#L484 assume !(1 == ~m_pc~0); 121469#L484-2 is_master_triggered_~__retres1~0#1 := 0; 121468#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 122101#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 122412#L1245 assume !(0 != activate_threads_~tmp~1#1); 122413#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 122178#L503 assume !(1 == ~t1_pc~0); 122179#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 122361#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 121328#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 121329#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 121324#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 121325#L522 assume !(1 == ~t2_pc~0); 122141#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 121524#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 121525#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 121807#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 122469#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 122567#L541 assume !(1 == ~t3_pc~0); 121878#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 121879#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 121271#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 121272#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 122147#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 122148#L560 assume !(1 == ~t4_pc~0); 121403#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 121402#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 121435#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 121285#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 121286#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 121570#L579 assume 1 == ~t5_pc~0; 121236#L580 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 121237#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 121350#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 122417#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 122554#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 122586#L598 assume 1 == ~t6_pc~0; 121653#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 121654#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 121782#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 121783#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 122225#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 122169#L617 assume !(1 == ~t7_pc~0); 121629#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 121628#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 122618#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 122482#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 121846#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 121847#L636 assume 1 == ~t8_pc~0; 122034#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 122035#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 122362#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 122236#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 121979#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 121980#L655 assume !(1 == ~t9_pc~0); 122009#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 122010#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 121889#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 121890#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 122249#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 122250#L674 assume 1 == ~t10_pc~0; 121396#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 121397#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 122024#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 122025#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 121970#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 121971#L1119 assume !(1 == ~M_E~0); 121495#L1119-2 assume !(1 == ~T1_E~0); 121496#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 121314#L1129-1 assume !(1 == ~T3_E~0); 121315#L1134-1 assume !(1 == ~T4_E~0); 131815#L1139-1 assume !(1 == ~T5_E~0); 131813#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 131811#L1149-1 assume !(1 == ~T7_E~0); 131809#L1154-1 assume !(1 == ~T8_E~0); 131807#L1159-1 assume !(1 == ~T9_E~0); 131805#L1164-1 assume !(1 == ~T10_E~0); 131802#L1169-1 assume !(1 == ~E_1~0); 131800#L1174-1 assume !(1 == ~E_2~0); 131798#L1179-1 assume !(1 == ~E_3~0); 131796#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 131794#L1189-1 assume !(1 == ~E_5~0); 131792#L1194-1 assume !(1 == ~E_6~0); 131789#L1199-1 assume !(1 == ~E_7~0); 131787#L1204-1 assume !(1 == ~E_8~0); 131048#L1209-1 assume !(1 == ~E_9~0); 131044#L1214-1 assume !(1 == ~E_10~0); 129090#L1219-1 assume { :end_inline_reset_delta_events } true; 128252#L1520-2 [2023-11-29 02:54:28,867 INFO L750 eck$LassoCheckResult]: Loop: 128252#L1520-2 assume !false; 127836#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 127834#L981-1 assume !false; 127833#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 127289#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 127285#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 126986#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 126983#L836 assume !(0 != eval_~tmp~0#1); 126984#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 134817#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 134816#L1006-3 assume !(0 == ~M_E~0); 134815#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 134814#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 134813#L1016-3 assume !(0 == ~T3_E~0); 134812#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 134811#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 134810#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 134809#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 134808#L1041-3 assume !(0 == ~T8_E~0); 134807#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 134806#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 134805#L1056-3 assume !(0 == ~E_1~0); 134804#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 134803#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 134801#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 134798#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 134796#L1081-3 assume !(0 == ~E_6~0); 134794#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 134792#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 134790#L1096-3 assume !(0 == ~E_9~0); 134788#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 134786#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 134784#L484-33 assume !(1 == ~m_pc~0); 134782#L484-35 is_master_triggered_~__retres1~0#1 := 0; 134779#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 134777#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 134775#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 134772#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 134770#L503-33 assume !(1 == ~t1_pc~0); 134768#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 134766#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 134764#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 134762#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 134760#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 134758#L522-33 assume 1 == ~t2_pc~0; 134755#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 134753#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 134751#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 134749#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 134746#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 134744#L541-33 assume !(1 == ~t3_pc~0); 134742#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 134740#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 134738#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 134736#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 134733#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 134731#L560-33 assume !(1 == ~t4_pc~0); 134728#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 134726#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 134724#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 134722#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 134719#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 134717#L579-33 assume 1 == ~t5_pc~0; 134714#L580-11 assume 1 == ~E_5~0;is_transmit5_triggered_~__retres1~5#1 := 1; 134712#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 134710#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 134708#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 134705#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 134703#L598-33 assume !(1 == ~t6_pc~0); 134700#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 134698#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 134696#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 134694#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 134691#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 134689#L617-33 assume 1 == ~t7_pc~0; 134686#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 134684#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 134682#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 134680#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 134677#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 134675#L636-33 assume !(1 == ~t8_pc~0); 134672#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 134670#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 134668#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 134666#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 134663#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 134661#L655-33 assume 1 == ~t9_pc~0; 134658#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 134656#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 134654#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 134653#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 134649#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 134647#L674-33 assume 1 == ~t10_pc~0; 134644#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 134643#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 134640#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 134636#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 134632#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 134628#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 134624#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 134620#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 124268#L1129-3 assume !(1 == ~T3_E~0); 133510#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 133224#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 133222#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 133219#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 133217#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 133215#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 133213#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 133205#L1169-3 assume !(1 == ~E_1~0); 132937#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 132935#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 132933#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 132931#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 132929#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 132926#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 132924#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 132548#L1209-3 assume !(1 == ~E_9~0); 132546#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 132545#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 131855#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 131096#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 131091#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 131087#L1539 assume !(0 == start_simulation_~tmp~3#1); 131084#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 131081#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 131070#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 131069#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 131068#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 129100#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 129096#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 129089#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 128252#L1520-2 [2023-11-29 02:54:28,867 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:28,867 INFO L85 PathProgramCache]: Analyzing trace with hash 1918570293, now seen corresponding path program 1 times [2023-11-29 02:54:28,868 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:28,868 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1972118013] [2023-11-29 02:54:28,868 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:28,868 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:28,881 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:28,918 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:28,918 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:28,918 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1972118013] [2023-11-29 02:54:28,918 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1972118013] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:28,918 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:28,918 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:54:28,919 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1435845419] [2023-11-29 02:54:28,919 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:28,919 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:28,919 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:28,919 INFO L85 PathProgramCache]: Analyzing trace with hash -992842227, now seen corresponding path program 1 times [2023-11-29 02:54:28,920 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:28,920 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1331009094] [2023-11-29 02:54:28,920 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:28,920 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:28,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:29,026 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:29,027 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:29,027 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1331009094] [2023-11-29 02:54:29,027 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1331009094] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:29,027 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:29,028 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:29,028 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [390820936] [2023-11-29 02:54:29,028 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:29,029 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:29,029 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:29,029 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:29,029 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:29,030 INFO L87 Difference]: Start difference. First operand 31574 states and 46023 transitions. cyclomatic complexity: 14481 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:29,403 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:29,403 INFO L93 Difference]: Finished difference Result 60133 states and 87304 transitions. [2023-11-29 02:54:29,403 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60133 states and 87304 transitions. [2023-11-29 02:54:29,654 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59776 [2023-11-29 02:54:29,831 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60133 states to 60133 states and 87304 transitions. [2023-11-29 02:54:29,832 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60133 [2023-11-29 02:54:30,053 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60133 [2023-11-29 02:54:30,053 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60133 states and 87304 transitions. [2023-11-29 02:54:30,079 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:30,079 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60133 states and 87304 transitions. [2023-11-29 02:54:30,112 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60133 states and 87304 transitions. [2023-11-29 02:54:30,675 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60133 to 60069. [2023-11-29 02:54:30,736 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60069 states, 60069 states have (on average 1.4523298207061879) internal successors, (87240), 60068 states have internal predecessors, (87240), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:30,872 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60069 states to 60069 states and 87240 transitions. [2023-11-29 02:54:30,872 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60069 states and 87240 transitions. [2023-11-29 02:54:30,873 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:30,873 INFO L428 stractBuchiCegarLoop]: Abstraction has 60069 states and 87240 transitions. [2023-11-29 02:54:30,873 INFO L335 stractBuchiCegarLoop]: ======== Iteration 16 ============ [2023-11-29 02:54:30,874 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60069 states and 87240 transitions. [2023-11-29 02:54:31,182 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 59712 [2023-11-29 02:54:31,182 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:31,182 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:31,185 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:31,185 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:31,185 INFO L748 eck$LassoCheckResult]: Stem: 213312#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 213313#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 214245#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 214246#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 214358#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 214350#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 214351#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 213486#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 213221#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 213222#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 214206#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 214207#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 214180#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 214181#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 214237#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 213272#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 213273#L1006 assume !(0 == ~M_E~0); 213122#L1006-2 assume !(0 == ~T1_E~0); 213123#L1011-1 assume !(0 == ~T2_E~0); 214276#L1016-1 assume !(0 == ~T3_E~0); 214297#L1021-1 assume !(0 == ~T4_E~0); 212997#L1026-1 assume !(0 == ~T5_E~0); 212998#L1031-1 assume !(0 == ~T6_E~0); 213921#L1036-1 assume !(0 == ~T7_E~0); 213917#L1041-1 assume !(0 == ~T8_E~0); 213918#L1046-1 assume !(0 == ~T9_E~0); 213303#L1051-1 assume !(0 == ~T10_E~0); 213304#L1056-1 assume !(0 == ~E_1~0); 214062#L1061-1 assume !(0 == ~E_2~0); 213225#L1066-1 assume !(0 == ~E_3~0); 213226#L1071-1 assume !(0 == ~E_4~0); 214037#L1076-1 assume !(0 == ~E_5~0); 213130#L1081-1 assume !(0 == ~E_6~0); 213131#L1086-1 assume !(0 == ~E_7~0); 213460#L1091-1 assume !(0 == ~E_8~0); 214259#L1096-1 assume !(0 == ~E_9~0); 214260#L1101-1 assume !(0 == ~E_10~0); 213534#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 213535#L484 assume !(1 == ~m_pc~0); 213182#L484-2 is_master_triggered_~__retres1~0#1 := 0; 213181#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 213830#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 214146#L1245 assume !(0 != activate_threads_~tmp~1#1); 214147#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 213908#L503 assume !(1 == ~t1_pc~0); 213909#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 214095#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 213038#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 213039#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 213034#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 213035#L522 assume !(1 == ~t2_pc~0); 213870#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 213238#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 213239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 213528#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 214208#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 214309#L541 assume !(1 == ~t3_pc~0); 213600#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 213601#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 212981#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 212982#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 213876#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 213877#L560 assume !(1 == ~t4_pc~0); 213114#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 213113#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 213146#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 212995#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 212996#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 213283#L579 assume !(1 == ~t5_pc~0); 213284#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 213060#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 213061#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 214153#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 214295#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 214330#L598 assume 1 == ~t6_pc~0; 213372#L599 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 213373#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 213502#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 213503#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 213959#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 213899#L617 assume !(1 == ~t7_pc~0); 213348#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 213347#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 214364#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 214222#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 213568#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 213569#L636 assume 1 == ~t8_pc~0; 213757#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 213758#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 214096#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 213969#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 213703#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 213704#L655 assume !(1 == ~t9_pc~0); 213731#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 213732#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 213612#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 213613#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 213983#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 213984#L674 assume 1 == ~t10_pc~0; 213107#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 213108#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 213746#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 213747#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 213694#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 213695#L1119 assume !(1 == ~M_E~0); 213208#L1119-2 assume !(1 == ~T1_E~0); 213209#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 213024#L1129-1 assume !(1 == ~T3_E~0); 213025#L1134-1 assume !(1 == ~T4_E~0); 213331#L1139-1 assume !(1 == ~T5_E~0); 213332#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 213564#L1149-1 assume !(1 == ~T7_E~0); 213202#L1154-1 assume !(1 == ~T8_E~0); 213203#L1159-1 assume !(1 == ~T9_E~0); 242061#L1164-1 assume !(1 == ~T10_E~0); 213722#L1169-1 assume !(1 == ~E_1~0); 213618#L1174-1 assume !(1 == ~E_2~0); 213386#L1179-1 assume !(1 == ~E_3~0); 213276#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 213277#L1189-1 assume !(1 == ~E_5~0); 213328#L1194-1 assume !(1 == ~E_6~0); 213440#L1199-1 assume !(1 == ~E_7~0); 213398#L1204-1 assume !(1 == ~E_8~0); 213399#L1209-1 assume !(1 == ~E_9~0); 213980#L1214-1 assume !(1 == ~E_10~0); 213981#L1219-1 assume { :end_inline_reset_delta_events } true; 214370#L1520-2 [2023-11-29 02:54:31,186 INFO L750 eck$LassoCheckResult]: Loop: 214370#L1520-2 assume !false; 250651#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 250648#L981-1 assume !false; 250645#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 250621#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 250617#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 250614#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 250612#L836 assume !(0 != eval_~tmp~0#1); 250613#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 257052#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 257050#L1006-3 assume !(0 == ~M_E~0); 257047#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 257045#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 257043#L1016-3 assume !(0 == ~T3_E~0); 257041#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 257039#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 257037#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 257035#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 257033#L1041-3 assume !(0 == ~T8_E~0); 257032#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 257031#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 257029#L1056-3 assume !(0 == ~E_1~0); 257027#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 257025#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 257023#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 257021#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 257019#L1081-3 assume !(0 == ~E_6~0); 257017#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 257016#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 257014#L1096-3 assume !(0 == ~E_9~0); 257012#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 257010#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 257008#L484-33 assume !(1 == ~m_pc~0); 257006#L484-35 is_master_triggered_~__retres1~0#1 := 0; 257003#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 257001#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 257000#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 256999#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 256998#L503-33 assume !(1 == ~t1_pc~0); 256997#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 256996#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 256995#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 256994#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 256993#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 256992#L522-33 assume !(1 == ~t2_pc~0); 256991#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 256989#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 256988#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 256987#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 256986#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 256985#L541-33 assume !(1 == ~t3_pc~0); 256984#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 256983#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 256982#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 256981#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 256980#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 256979#L560-33 assume 1 == ~t4_pc~0; 256978#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 256976#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 256975#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 256974#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 256973#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 256972#L579-33 assume !(1 == ~t5_pc~0); 256970#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 256967#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 256965#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 256963#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 256961#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 256959#L598-33 assume 1 == ~t6_pc~0; 256957#L599-11 assume 1 == ~E_6~0;is_transmit6_triggered_~__retres1~6#1 := 1; 256954#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 256952#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 256950#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 256948#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 256946#L617-33 assume !(1 == ~t7_pc~0); 256944#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 256940#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 256938#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 256936#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 256934#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 256932#L636-33 assume 1 == ~t8_pc~0; 256930#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 256927#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 256925#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 256923#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 256921#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 256919#L655-33 assume !(1 == ~t9_pc~0); 256917#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 256913#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 256911#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 256909#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 256907#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 256905#L674-33 assume !(1 == ~t10_pc~0); 256903#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 256900#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 256898#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 256896#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 256894#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 256892#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 256890#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 256887#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 243376#L1129-3 assume !(1 == ~T3_E~0); 248958#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 256883#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 256881#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 256879#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 256876#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 256874#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 256872#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 256870#L1169-3 assume !(1 == ~E_1~0); 255494#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 256867#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 256864#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 256862#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 256860#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 256858#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 256856#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 256854#L1209-3 assume !(1 == ~E_9~0); 256277#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 256850#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 256848#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 256836#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 256834#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 256831#L1539 assume !(0 == start_simulation_~tmp~3#1); 256827#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 256825#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 256813#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 256811#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 256809#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 256808#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 256804#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 256802#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 214370#L1520-2 [2023-11-29 02:54:31,186 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:31,186 INFO L85 PathProgramCache]: Analyzing trace with hash 776922900, now seen corresponding path program 1 times [2023-11-29 02:54:31,186 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:31,187 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [185090580] [2023-11-29 02:54:31,187 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:31,187 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:31,204 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:31,250 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:31,251 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:31,251 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [185090580] [2023-11-29 02:54:31,251 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [185090580] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:31,251 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:31,251 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:54:31,251 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1395302222] [2023-11-29 02:54:31,251 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:31,252 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:31,252 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:31,252 INFO L85 PathProgramCache]: Analyzing trace with hash -1016020725, now seen corresponding path program 1 times [2023-11-29 02:54:31,252 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:31,252 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1029806542] [2023-11-29 02:54:31,252 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:31,252 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:31,269 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:31,327 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:31,327 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:31,327 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1029806542] [2023-11-29 02:54:31,327 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1029806542] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:31,327 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:31,327 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:54:31,327 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [48046810] [2023-11-29 02:54:31,328 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:31,328 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:31,328 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:31,328 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:31,328 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:31,329 INFO L87 Difference]: Start difference. First operand 60069 states and 87240 transitions. cyclomatic complexity: 27235 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:32,009 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:32,009 INFO L93 Difference]: Finished difference Result 114372 states and 165517 transitions. [2023-11-29 02:54:32,009 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 114372 states and 165517 transitions. [2023-11-29 02:54:32,512 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 113728 [2023-11-29 02:54:32,840 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 114372 states to 114372 states and 165517 transitions. [2023-11-29 02:54:32,841 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 114372 [2023-11-29 02:54:32,879 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 114372 [2023-11-29 02:54:32,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 114372 states and 165517 transitions. [2023-11-29 02:54:32,917 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:32,917 INFO L218 hiAutomatonCegarLoop]: Abstraction has 114372 states and 165517 transitions. [2023-11-29 02:54:32,967 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 114372 states and 165517 transitions. [2023-11-29 02:54:33,945 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 114372 to 114244. [2023-11-29 02:54:34,027 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 114244 states, 114244 states have (on average 1.447682153986205) internal successors, (165389), 114243 states have internal predecessors, (165389), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:34,273 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 114244 states to 114244 states and 165389 transitions. [2023-11-29 02:54:34,274 INFO L240 hiAutomatonCegarLoop]: Abstraction has 114244 states and 165389 transitions. [2023-11-29 02:54:34,274 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:34,275 INFO L428 stractBuchiCegarLoop]: Abstraction has 114244 states and 165389 transitions. [2023-11-29 02:54:34,275 INFO L335 stractBuchiCegarLoop]: ======== Iteration 17 ============ [2023-11-29 02:54:34,275 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 114244 states and 165389 transitions. [2023-11-29 02:54:34,687 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 113600 [2023-11-29 02:54:34,688 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:34,688 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:34,690 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:34,690 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:34,690 INFO L748 eck$LassoCheckResult]: Stem: 387766#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 387767#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 388696#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 388697#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 388803#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 388796#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 388797#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 387930#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 387675#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 387676#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 388659#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 388660#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 388639#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 388640#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 388686#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 387726#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 387727#L1006 assume !(0 == ~M_E~0); 387576#L1006-2 assume !(0 == ~T1_E~0); 387577#L1011-1 assume !(0 == ~T2_E~0); 388727#L1016-1 assume !(0 == ~T3_E~0); 388748#L1021-1 assume !(0 == ~T4_E~0); 387448#L1026-1 assume !(0 == ~T5_E~0); 387449#L1031-1 assume !(0 == ~T6_E~0); 388367#L1036-1 assume !(0 == ~T7_E~0); 388363#L1041-1 assume !(0 == ~T8_E~0); 388364#L1046-1 assume !(0 == ~T9_E~0); 387757#L1051-1 assume !(0 == ~T10_E~0); 387758#L1056-1 assume !(0 == ~E_1~0); 388507#L1061-1 assume !(0 == ~E_2~0); 387679#L1066-1 assume !(0 == ~E_3~0); 387680#L1071-1 assume !(0 == ~E_4~0); 388478#L1076-1 assume !(0 == ~E_5~0); 387583#L1081-1 assume !(0 == ~E_6~0); 387584#L1086-1 assume !(0 == ~E_7~0); 387904#L1091-1 assume !(0 == ~E_8~0); 388706#L1096-1 assume !(0 == ~E_9~0); 388707#L1101-1 assume !(0 == ~E_10~0); 387978#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 387979#L484 assume !(1 == ~m_pc~0); 387635#L484-2 is_master_triggered_~__retres1~0#1 := 0; 387634#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 388271#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 388598#L1245 assume !(0 != activate_threads_~tmp~1#1); 388599#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 388354#L503 assume !(1 == ~t1_pc~0); 388355#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 388543#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 387489#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 387490#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 387485#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 387486#L522 assume !(1 == ~t2_pc~0); 388313#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 387690#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 387691#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 387972#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 388661#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 388760#L541 assume !(1 == ~t3_pc~0); 388045#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 388046#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 387432#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 387433#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 388319#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 388320#L560 assume !(1 == ~t4_pc~0); 387568#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 387567#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 387599#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 387446#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 387447#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 387737#L579 assume !(1 == ~t5_pc~0); 387738#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 387511#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 387512#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 388603#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 388746#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 388779#L598 assume !(1 == ~t6_pc~0); 388522#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 388140#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 387945#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 387946#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 388403#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 388345#L617 assume !(1 == ~t7_pc~0); 387798#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 387797#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 388810#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 388676#L1301 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 388012#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 388013#L636 assume 1 == ~t8_pc~0; 388202#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 388203#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 388544#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 388411#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 388147#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 388148#L655 assume !(1 == ~t9_pc~0); 388176#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 388177#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 388056#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 388057#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 388422#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 388423#L674 assume 1 == ~t10_pc~0; 387561#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 387562#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 388191#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 388192#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 388137#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 388138#L1119 assume !(1 == ~M_E~0); 387661#L1119-2 assume !(1 == ~T1_E~0); 387662#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 387475#L1129-1 assume !(1 == ~T3_E~0); 387476#L1134-1 assume !(1 == ~T4_E~0); 451329#L1139-1 assume !(1 == ~T5_E~0); 451327#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 451325#L1149-1 assume !(1 == ~T7_E~0); 451322#L1154-1 assume !(1 == ~T8_E~0); 451320#L1159-1 assume !(1 == ~T9_E~0); 451318#L1164-1 assume !(1 == ~T10_E~0); 451316#L1169-1 assume !(1 == ~E_1~0); 451314#L1174-1 assume !(1 == ~E_2~0); 451312#L1179-1 assume !(1 == ~E_3~0); 451310#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 451308#L1189-1 assume !(1 == ~E_5~0); 451306#L1194-1 assume !(1 == ~E_6~0); 451303#L1199-1 assume !(1 == ~E_7~0); 387842#L1204-1 assume !(1 == ~E_8~0); 387843#L1209-1 assume !(1 == ~E_9~0); 388792#L1214-1 assume !(1 == ~E_10~0); 474210#L1219-1 assume { :end_inline_reset_delta_events } true; 474206#L1520-2 [2023-11-29 02:54:34,691 INFO L750 eck$LassoCheckResult]: Loop: 474206#L1520-2 assume !false; 473223#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 473219#L981-1 assume !false; 473217#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 473205#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 473200#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 473198#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 473195#L836 assume !(0 != eval_~tmp~0#1); 473196#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 474617#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 474615#L1006-3 assume !(0 == ~M_E~0); 474613#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 474611#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 474609#L1016-3 assume !(0 == ~T3_E~0); 474607#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 474605#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 474603#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 474601#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 474599#L1041-3 assume !(0 == ~T8_E~0); 474597#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 474595#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 474592#L1056-3 assume !(0 == ~E_1~0); 474590#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 474588#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 474586#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 474584#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 474582#L1081-3 assume !(0 == ~E_6~0); 474579#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 474577#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 474575#L1096-3 assume !(0 == ~E_9~0); 474573#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 474571#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 474569#L484-33 assume !(1 == ~m_pc~0); 474566#L484-35 is_master_triggered_~__retres1~0#1 := 0; 474563#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 474561#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 474559#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 474557#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 474555#L503-33 assume !(1 == ~t1_pc~0); 474552#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 474550#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 474548#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 474546#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 474544#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 474543#L522-33 assume !(1 == ~t2_pc~0); 474539#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 474536#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 474534#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 474533#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 474530#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 474529#L541-33 assume !(1 == ~t3_pc~0); 474528#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 474525#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 474521#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 474517#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 474512#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 474510#L560-33 assume 1 == ~t4_pc~0; 474508#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 474506#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 474505#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 474504#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 474503#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 474502#L579-33 assume !(1 == ~t5_pc~0); 474501#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 474500#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 474499#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 474498#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 474486#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 474484#L598-33 assume !(1 == ~t6_pc~0); 474482#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 474480#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 474478#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 474476#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 474474#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 474472#L617-33 assume !(1 == ~t7_pc~0); 474470#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 474467#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 474465#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 474463#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 474461#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 474459#L636-33 assume 1 == ~t8_pc~0; 474457#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 474454#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 474452#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 474450#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 474448#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 474446#L655-33 assume !(1 == ~t9_pc~0); 474444#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 474441#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 474439#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 474437#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 474435#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 474433#L674-33 assume !(1 == ~t10_pc~0); 474431#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 474428#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 474426#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 474423#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 474421#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 474419#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 474417#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 474415#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 417805#L1129-3 assume !(1 == ~T3_E~0); 443071#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 474411#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 474409#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 474407#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 474405#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 474403#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 474400#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 474274#L1169-3 assume !(1 == ~E_1~0); 474272#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 474270#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 474268#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 474266#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 474264#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 474261#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 474259#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 474257#L1209-3 assume !(1 == ~E_9~0); 473706#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 474254#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 474252#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 474239#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 474237#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 474234#L1539 assume !(0 == start_simulation_~tmp~3#1); 474231#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 474229#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 474218#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 474217#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 474216#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 474215#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 474214#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 474209#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 474206#L1520-2 [2023-11-29 02:54:34,691 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:34,691 INFO L85 PathProgramCache]: Analyzing trace with hash 75354675, now seen corresponding path program 1 times [2023-11-29 02:54:34,691 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:34,691 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2070259355] [2023-11-29 02:54:34,692 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:34,692 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:34,707 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:34,765 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:34,765 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:34,765 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2070259355] [2023-11-29 02:54:34,765 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2070259355] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:34,765 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:34,766 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:54:34,766 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [401544918] [2023-11-29 02:54:34,766 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:34,766 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:34,766 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:34,767 INFO L85 PathProgramCache]: Analyzing trace with hash -311102038, now seen corresponding path program 1 times [2023-11-29 02:54:34,767 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:34,767 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1480471753] [2023-11-29 02:54:34,767 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:34,767 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:34,783 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:34,836 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:34,837 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:34,837 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1480471753] [2023-11-29 02:54:34,837 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1480471753] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:34,837 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:34,837 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:54:34,837 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [708239457] [2023-11-29 02:54:34,837 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:34,838 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:34,838 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:34,838 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:54:34,838 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:54:34,839 INFO L87 Difference]: Start difference. First operand 114244 states and 165389 transitions. cyclomatic complexity: 51273 Second operand has 5 states, 5 states have (on average 25.2) internal successors, (126), 5 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:35,849 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:35,849 INFO L93 Difference]: Finished difference Result 250312 states and 359488 transitions. [2023-11-29 02:54:35,849 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 250312 states and 359488 transitions. [2023-11-29 02:54:36,984 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 249088 [2023-11-29 02:54:37,691 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 250312 states to 250312 states and 359488 transitions. [2023-11-29 02:54:37,691 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 250312 [2023-11-29 02:54:37,787 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 250312 [2023-11-29 02:54:37,787 INFO L73 IsDeterministic]: Start isDeterministic. Operand 250312 states and 359488 transitions. [2023-11-29 02:54:37,913 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:37,914 INFO L218 hiAutomatonCegarLoop]: Abstraction has 250312 states and 359488 transitions. [2023-11-29 02:54:38,030 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 250312 states and 359488 transitions. [2023-11-29 02:54:39,471 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 250312 to 117703. [2023-11-29 02:54:39,523 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 117703 states, 117703 states have (on average 1.4345258829426608) internal successors, (168848), 117702 states have internal predecessors, (168848), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:39,731 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 117703 states to 117703 states and 168848 transitions. [2023-11-29 02:54:39,732 INFO L240 hiAutomatonCegarLoop]: Abstraction has 117703 states and 168848 transitions. [2023-11-29 02:54:39,732 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:54:39,732 INFO L428 stractBuchiCegarLoop]: Abstraction has 117703 states and 168848 transitions. [2023-11-29 02:54:39,732 INFO L335 stractBuchiCegarLoop]: ======== Iteration 18 ============ [2023-11-29 02:54:39,732 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 117703 states and 168848 transitions. [2023-11-29 02:54:39,972 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 117056 [2023-11-29 02:54:39,972 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:39,972 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:39,974 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:39,974 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:39,975 INFO L748 eck$LassoCheckResult]: Stem: 752336#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 752337#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 753289#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 753290#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 753410#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 753391#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 753392#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 752506#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 752245#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 752246#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 753252#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 753253#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 753227#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 753228#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 753280#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 752298#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 752299#L1006 assume !(0 == ~M_E~0); 752146#L1006-2 assume !(0 == ~T1_E~0); 752147#L1011-1 assume !(0 == ~T2_E~0); 753316#L1016-1 assume !(0 == ~T3_E~0); 753344#L1021-1 assume !(0 == ~T4_E~0); 752021#L1026-1 assume !(0 == ~T5_E~0); 752022#L1031-1 assume !(0 == ~T6_E~0); 752950#L1036-1 assume !(0 == ~T7_E~0); 752945#L1041-1 assume !(0 == ~T8_E~0); 752946#L1046-1 assume !(0 == ~T9_E~0); 752327#L1051-1 assume !(0 == ~T10_E~0); 752328#L1056-1 assume !(0 == ~E_1~0); 753094#L1061-1 assume !(0 == ~E_2~0); 752247#L1066-1 assume !(0 == ~E_3~0); 752248#L1071-1 assume !(0 == ~E_4~0); 753066#L1076-1 assume !(0 == ~E_5~0); 752151#L1081-1 assume !(0 == ~E_6~0); 752152#L1086-1 assume !(0 == ~E_7~0); 752480#L1091-1 assume !(0 == ~E_8~0); 753301#L1096-1 assume !(0 == ~E_9~0); 753302#L1101-1 assume !(0 == ~E_10~0); 752554#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 752555#L484 assume !(1 == ~m_pc~0); 752204#L484-2 is_master_triggered_~__retres1~0#1 := 0; 752203#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 752858#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 753185#L1245 assume !(0 != activate_threads_~tmp~1#1); 753186#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 752935#L503 assume !(1 == ~t1_pc~0); 752936#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 753137#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 752062#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 752063#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 752058#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 752059#L522 assume !(1 == ~t2_pc~0); 752901#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 752264#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 752265#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 752550#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 753254#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 753355#L541 assume !(1 == ~t3_pc~0); 752620#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 752621#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 752005#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 752006#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 752911#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 752912#L560 assume !(1 == ~t4_pc~0); 752138#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 752137#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 752167#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 752017#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 752018#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 752309#L579 assume !(1 == ~t5_pc~0); 752310#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 752082#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 752083#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 753191#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 753343#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 753373#L598 assume !(1 == ~t6_pc~0); 753109#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 752730#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 752524#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 752525#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 752983#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 752926#L617 assume !(1 == ~t7_pc~0); 752369#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 752806#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 753416#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 753268#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 752591#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 752592#L636 assume 1 == ~t8_pc~0; 752788#L637 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 752789#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 753138#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 752996#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 752736#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 752737#L655 assume !(1 == ~t9_pc~0); 752767#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 752768#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 752636#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 752637#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 753005#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 753006#L674 assume 1 == ~t10_pc~0; 752129#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 752130#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 752779#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 752780#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 752724#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 752725#L1119 assume !(1 == ~M_E~0); 752228#L1119-2 assume !(1 == ~T1_E~0); 752229#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 752046#L1129-1 assume !(1 == ~T3_E~0); 752047#L1134-1 assume !(1 == ~T4_E~0); 752354#L1139-1 assume !(1 == ~T5_E~0); 752355#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 752587#L1149-1 assume !(1 == ~T7_E~0); 752222#L1154-1 assume !(1 == ~T8_E~0); 752223#L1159-1 assume !(1 == ~T9_E~0); 752311#L1164-1 assume !(1 == ~T10_E~0); 752754#L1169-1 assume !(1 == ~E_1~0); 752639#L1174-1 assume !(1 == ~E_2~0); 752405#L1179-1 assume !(1 == ~E_3~0); 752300#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 752301#L1189-1 assume !(1 == ~E_5~0); 752352#L1194-1 assume !(1 == ~E_6~0); 752457#L1199-1 assume !(1 == ~E_7~0); 752415#L1204-1 assume !(1 == ~E_8~0); 752416#L1209-1 assume !(1 == ~E_9~0); 753385#L1214-1 assume !(1 == ~E_10~0); 784230#L1219-1 assume { :end_inline_reset_delta_events } true; 784219#L1520-2 [2023-11-29 02:54:39,975 INFO L750 eck$LassoCheckResult]: Loop: 784219#L1520-2 assume !false; 784129#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 784118#L981-1 assume !false; 784112#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 784077#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 784073#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 784071#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 784068#L836 assume !(0 != eval_~tmp~0#1); 784069#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 785977#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 785976#L1006-3 assume !(0 == ~M_E~0); 785975#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 785974#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 785973#L1016-3 assume !(0 == ~T3_E~0); 785972#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 785971#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 785970#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 785969#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 785968#L1041-3 assume !(0 == ~T8_E~0); 785967#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 785966#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 785965#L1056-3 assume !(0 == ~E_1~0); 785964#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 785963#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 785962#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 785961#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 785960#L1081-3 assume !(0 == ~E_6~0); 785959#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 785958#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 785957#L1096-3 assume !(0 == ~E_9~0); 785956#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 785955#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 785954#L484-33 assume !(1 == ~m_pc~0); 785953#L484-35 is_master_triggered_~__retres1~0#1 := 0; 785951#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 785950#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 785949#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 785948#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 785947#L503-33 assume !(1 == ~t1_pc~0); 785946#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 785945#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 785944#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 785943#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 785942#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 785941#L522-33 assume 1 == ~t2_pc~0; 785939#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 785938#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 785937#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 785936#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 785935#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 785934#L541-33 assume !(1 == ~t3_pc~0); 785933#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 785932#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 785931#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 785930#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 785929#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 785928#L560-33 assume 1 == ~t4_pc~0; 785927#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 785925#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 785924#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 785923#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 785922#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 785921#L579-33 assume !(1 == ~t5_pc~0); 785920#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 785919#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 785918#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 785917#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 785916#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 785915#L598-33 assume !(1 == ~t6_pc~0); 785914#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 785913#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 785912#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 785911#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 785910#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 785909#L617-33 assume 1 == ~t7_pc~0; 785907#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 785905#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 785903#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 785901#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 784650#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 784648#L636-33 assume 1 == ~t8_pc~0; 784646#L637-11 assume 1 == ~E_8~0;is_transmit8_triggered_~__retres1~8#1 := 1; 784642#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 784640#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 784638#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 784636#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 784634#L655-33 assume !(1 == ~t9_pc~0); 784632#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 784628#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 784626#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 784624#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 784622#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 784620#L674-33 assume !(1 == ~t10_pc~0); 784618#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 784614#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 784612#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 784592#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 784407#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 784402#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 784397#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 784392#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 776347#L1129-3 assume !(1 == ~T3_E~0); 784379#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 784374#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 784369#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 784361#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 784355#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 784350#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 784345#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 784339#L1169-3 assume !(1 == ~E_1~0); 784335#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 784331#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 784321#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 784305#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 784301#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 784299#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 784297#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 784295#L1209-3 assume !(1 == ~E_9~0); 776275#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 784292#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 784290#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 784278#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 784276#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 784274#L1539 assume !(0 == start_simulation_~tmp~3#1); 784272#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 784271#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 784260#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 784258#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 784252#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 784244#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 784236#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 784229#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 784219#L1520-2 [2023-11-29 02:54:39,975 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:39,975 INFO L85 PathProgramCache]: Analyzing trace with hash 323501169, now seen corresponding path program 1 times [2023-11-29 02:54:39,975 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:39,975 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [768854048] [2023-11-29 02:54:39,976 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:39,976 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:39,987 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:40,017 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:40,017 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:40,017 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [768854048] [2023-11-29 02:54:40,017 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [768854048] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:40,017 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:40,018 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:54:40,018 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [660723594] [2023-11-29 02:54:40,018 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:40,018 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:40,018 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:40,019 INFO L85 PathProgramCache]: Analyzing trace with hash -371648980, now seen corresponding path program 1 times [2023-11-29 02:54:40,019 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:40,019 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2083424588] [2023-11-29 02:54:40,019 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:40,019 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:40,031 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:40,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:40,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:40,074 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2083424588] [2023-11-29 02:54:40,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2083424588] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:40,074 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:40,074 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:54:40,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [223767162] [2023-11-29 02:54:40,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:40,075 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:40,075 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:40,076 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:40,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:40,076 INFO L87 Difference]: Start difference. First operand 117703 states and 168848 transitions. cyclomatic complexity: 51273 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:40,972 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:40,972 INFO L93 Difference]: Finished difference Result 228870 states and 326877 transitions. [2023-11-29 02:54:40,973 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 228870 states and 326877 transitions. [2023-11-29 02:54:42,039 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 227520 [2023-11-29 02:54:42,563 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 228870 states to 228870 states and 326877 transitions. [2023-11-29 02:54:42,563 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 228870 [2023-11-29 02:54:42,680 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 228870 [2023-11-29 02:54:42,680 INFO L73 IsDeterministic]: Start isDeterministic. Operand 228870 states and 326877 transitions. [2023-11-29 02:54:42,777 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:42,777 INFO L218 hiAutomatonCegarLoop]: Abstraction has 228870 states and 326877 transitions. [2023-11-29 02:54:42,895 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 228870 states and 326877 transitions. [2023-11-29 02:54:44,570 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 228870 to 228614. [2023-11-29 02:54:44,690 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 228614 states, 228614 states have (on average 1.4287007794798219) internal successors, (326621), 228613 states have internal predecessors, (326621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:45,085 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228614 states to 228614 states and 326621 transitions. [2023-11-29 02:54:45,085 INFO L240 hiAutomatonCegarLoop]: Abstraction has 228614 states and 326621 transitions. [2023-11-29 02:54:45,086 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:45,086 INFO L428 stractBuchiCegarLoop]: Abstraction has 228614 states and 326621 transitions. [2023-11-29 02:54:45,086 INFO L335 stractBuchiCegarLoop]: ======== Iteration 19 ============ [2023-11-29 02:54:45,086 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 228614 states and 326621 transitions. [2023-11-29 02:54:45,954 INFO L131 ngComponentsAnalysis]: Automaton has 256 accepting balls. 227264 [2023-11-29 02:54:45,954 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:45,954 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:45,956 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:45,956 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:45,956 INFO L748 eck$LassoCheckResult]: Stem: 1098917#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1098918#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1099908#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1099909#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1100057#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 1100045#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1100046#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1099082#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1098823#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1098824#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1099859#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1099860#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1099836#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1099837#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1099896#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1098877#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1098878#L1006 assume !(0 == ~M_E~0); 1098724#L1006-2 assume !(0 == ~T1_E~0); 1098725#L1011-1 assume !(0 == ~T2_E~0); 1099948#L1016-1 assume !(0 == ~T3_E~0); 1099977#L1021-1 assume !(0 == ~T4_E~0); 1098602#L1026-1 assume !(0 == ~T5_E~0); 1098603#L1031-1 assume !(0 == ~T6_E~0); 1099534#L1036-1 assume !(0 == ~T7_E~0); 1099531#L1041-1 assume !(0 == ~T8_E~0); 1099532#L1046-1 assume !(0 == ~T9_E~0); 1098908#L1051-1 assume !(0 == ~T10_E~0); 1098909#L1056-1 assume !(0 == ~E_1~0); 1099684#L1061-1 assume !(0 == ~E_2~0); 1098827#L1066-1 assume !(0 == ~E_3~0); 1098828#L1071-1 assume !(0 == ~E_4~0); 1099657#L1076-1 assume !(0 == ~E_5~0); 1098731#L1081-1 assume !(0 == ~E_6~0); 1098732#L1086-1 assume !(0 == ~E_7~0); 1099056#L1091-1 assume !(0 == ~E_8~0); 1099926#L1096-1 assume !(0 == ~E_9~0); 1099927#L1101-1 assume !(0 == ~E_10~0); 1099130#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1099131#L484 assume !(1 == ~m_pc~0); 1098783#L484-2 is_master_triggered_~__retres1~0#1 := 0; 1098782#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1099439#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1099787#L1245 assume !(0 != activate_threads_~tmp~1#1); 1099788#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1099522#L503 assume !(1 == ~t1_pc~0); 1099523#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1099724#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1098642#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1098643#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 1098636#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1098637#L522 assume !(1 == ~t2_pc~0); 1099486#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1098839#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1098840#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1099125#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 1099861#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1099991#L541 assume !(1 == ~t3_pc~0); 1099198#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1099199#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1098586#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1098587#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 1099492#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1099493#L560 assume !(1 == ~t4_pc~0); 1098718#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1098717#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1098747#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1098598#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 1098599#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1098886#L579 assume !(1 == ~t5_pc~0); 1098887#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1098661#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1098662#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1099796#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 1099975#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1100017#L598 assume !(1 == ~t6_pc~0); 1099699#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1099305#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1099098#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1099099#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 1099572#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1099513#L617 assume !(1 == ~t7_pc~0); 1098949#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1099384#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1100072#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1099882#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 1099165#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1099166#L636 assume !(1 == ~t8_pc~0); 1099569#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1099780#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1099725#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1099584#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 1099312#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1099313#L655 assume !(1 == ~t9_pc~0); 1099344#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1099345#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1099213#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1099214#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 1099596#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1099597#L674 assume 1 == ~t10_pc~0; 1098709#L675 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1098710#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1099359#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1099360#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 1099302#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1099303#L1119 assume !(1 == ~M_E~0); 1098809#L1119-2 assume !(1 == ~T1_E~0); 1098810#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1098626#L1129-1 assume !(1 == ~T3_E~0); 1098627#L1134-1 assume !(1 == ~T4_E~0); 1098934#L1139-1 assume !(1 == ~T5_E~0); 1098935#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1099161#L1149-1 assume !(1 == ~T7_E~0); 1098803#L1154-1 assume !(1 == ~T8_E~0); 1098804#L1159-1 assume !(1 == ~T9_E~0); 1098890#L1164-1 assume !(1 == ~T10_E~0); 1099333#L1169-1 assume !(1 == ~E_1~0); 1099215#L1174-1 assume !(1 == ~E_2~0); 1098985#L1179-1 assume !(1 == ~E_3~0); 1098879#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1098880#L1189-1 assume !(1 == ~E_5~0); 1098931#L1194-1 assume !(1 == ~E_6~0); 1099036#L1199-1 assume !(1 == ~E_7~0); 1098996#L1204-1 assume !(1 == ~E_8~0); 1098997#L1209-1 assume !(1 == ~E_9~0); 1100034#L1214-1 assume !(1 == ~E_10~0); 1195759#L1219-1 assume { :end_inline_reset_delta_events } true; 1195756#L1520-2 [2023-11-29 02:54:45,957 INFO L750 eck$LassoCheckResult]: Loop: 1195756#L1520-2 assume !false; 1195379#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1195376#L981-1 assume !false; 1195374#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1195350#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1195346#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1195344#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1195340#L836 assume !(0 != eval_~tmp~0#1); 1195341#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1196018#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1196016#L1006-3 assume !(0 == ~M_E~0); 1196014#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1196012#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1196010#L1016-3 assume !(0 == ~T3_E~0); 1196008#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1196006#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1196004#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1196001#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1195999#L1041-3 assume !(0 == ~T8_E~0); 1195997#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1195995#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1195993#L1056-3 assume !(0 == ~E_1~0); 1195991#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1195989#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1195987#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1195985#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1195983#L1081-3 assume !(0 == ~E_6~0); 1195981#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1195979#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1195977#L1096-3 assume !(0 == ~E_9~0); 1195975#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1195973#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1195971#L484-33 assume 1 == ~m_pc~0; 1195968#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 1195966#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1195963#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1195961#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 1195959#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1195956#L503-33 assume !(1 == ~t1_pc~0); 1195954#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1195952#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1195950#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1195948#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1195946#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1195944#L522-33 assume !(1 == ~t2_pc~0); 1195942#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1195939#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1195936#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1195934#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1195932#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1195930#L541-33 assume !(1 == ~t3_pc~0); 1195928#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1195926#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1195923#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1195921#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1195919#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1195917#L560-33 assume !(1 == ~t4_pc~0); 1195914#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 1195912#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1195910#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1195908#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1195907#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1195906#L579-33 assume !(1 == ~t5_pc~0); 1195904#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1195902#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1195900#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1195898#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1195896#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1195894#L598-33 assume !(1 == ~t6_pc~0); 1195892#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1195891#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1195889#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1195887#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1195885#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1195883#L617-33 assume !(1 == ~t7_pc~0); 1195879#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1195877#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1195875#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1195874#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 1195872#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1195871#L636-33 assume !(1 == ~t8_pc~0); 1195870#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1195869#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1195868#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1195867#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1195866#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1195865#L655-33 assume 1 == ~t9_pc~0; 1195863#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 1195862#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1195861#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1195860#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 1195859#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1195858#L674-33 assume 1 == ~t10_pc~0; 1195856#L675-11 assume 1 == ~E_10~0;is_transmit10_triggered_~__retres1~10#1 := 1; 1195855#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1195854#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1195852#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1195849#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1195847#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1195845#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1195843#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1166306#L1129-3 assume !(1 == ~T3_E~0); 1195124#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1195839#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1195837#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1195835#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1195833#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1195831#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1195829#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1195826#L1169-3 assume !(1 == ~E_1~0); 1167652#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1195823#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1195821#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1195819#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1195817#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1195815#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1195813#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1195811#L1209-3 assume !(1 == ~E_9~0); 1194372#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1195808#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1195806#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1195793#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1195791#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1195788#L1539 assume !(0 == start_simulation_~tmp~3#1); 1195785#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1195783#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1195771#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1195769#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1195767#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1195765#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1195763#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1195758#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 1195756#L1520-2 [2023-11-29 02:54:45,957 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:45,957 INFO L85 PathProgramCache]: Analyzing trace with hash 723492368, now seen corresponding path program 1 times [2023-11-29 02:54:45,957 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:45,957 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [756920729] [2023-11-29 02:54:45,957 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:45,958 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:45,969 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:46,013 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:46,013 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:46,014 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [756920729] [2023-11-29 02:54:46,014 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [756920729] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:46,014 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:46,014 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:54:46,014 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1863886426] [2023-11-29 02:54:46,014 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:46,015 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:46,015 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:46,015 INFO L85 PathProgramCache]: Analyzing trace with hash 1853537033, now seen corresponding path program 1 times [2023-11-29 02:54:46,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:46,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1696295525] [2023-11-29 02:54:46,016 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:46,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:46,029 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:46,058 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:46,058 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:46,059 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1696295525] [2023-11-29 02:54:46,059 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1696295525] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:46,059 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:46,059 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:54:46,059 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [200254486] [2023-11-29 02:54:46,059 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:46,060 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:46,060 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:46,060 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:46,060 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:46,060 INFO L87 Difference]: Start difference. First operand 228614 states and 326621 transitions. cyclomatic complexity: 98263 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:47,697 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:47,698 INFO L93 Difference]: Finished difference Result 454533 states and 645946 transitions. [2023-11-29 02:54:47,698 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 454533 states and 645946 transitions. [2023-11-29 02:54:49,691 INFO L131 ngComponentsAnalysis]: Automaton has 512 accepting balls. 451520 [2023-11-29 02:54:50,786 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 454533 states to 454533 states and 645946 transitions. [2023-11-29 02:54:50,786 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 454533 [2023-11-29 02:54:50,928 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 454533 [2023-11-29 02:54:50,929 INFO L73 IsDeterministic]: Start isDeterministic. Operand 454533 states and 645946 transitions. [2023-11-29 02:54:51,044 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:54:51,044 INFO L218 hiAutomatonCegarLoop]: Abstraction has 454533 states and 645946 transitions. [2023-11-29 02:54:51,223 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 454533 states and 645946 transitions. [2023-11-29 02:54:54,515 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 454533 to 453509. [2023-11-29 02:54:54,735 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 453509 states, 453509 states have (on average 1.421506519165) internal successors, (644666), 453508 states have internal predecessors, (644666), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:56,287 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 453509 states to 453509 states and 644666 transitions. [2023-11-29 02:54:56,287 INFO L240 hiAutomatonCegarLoop]: Abstraction has 453509 states and 644666 transitions. [2023-11-29 02:54:56,287 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:54:56,288 INFO L428 stractBuchiCegarLoop]: Abstraction has 453509 states and 644666 transitions. [2023-11-29 02:54:56,288 INFO L335 stractBuchiCegarLoop]: ======== Iteration 20 ============ [2023-11-29 02:54:56,288 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 453509 states and 644666 transitions. [2023-11-29 02:54:57,650 INFO L131 ngComponentsAnalysis]: Automaton has 512 accepting balls. 451008 [2023-11-29 02:54:57,650 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:54:57,650 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:54:57,652 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:57,652 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:54:57,652 INFO L748 eck$LassoCheckResult]: Stem: 1782072#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 1782073#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 1783019#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 1783020#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 1783134#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 1783123#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 1783124#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 1782241#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 1781977#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 1781978#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 1782982#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 1782983#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 1782959#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 1782960#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 1783010#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 1782030#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 1782031#L1006 assume !(0 == ~M_E~0); 1781877#L1006-2 assume !(0 == ~T1_E~0); 1781878#L1011-1 assume !(0 == ~T2_E~0); 1783049#L1016-1 assume !(0 == ~T3_E~0); 1783073#L1021-1 assume !(0 == ~T4_E~0); 1781754#L1026-1 assume !(0 == ~T5_E~0); 1781755#L1031-1 assume !(0 == ~T6_E~0); 1782685#L1036-1 assume !(0 == ~T7_E~0); 1782682#L1041-1 assume !(0 == ~T8_E~0); 1782683#L1046-1 assume !(0 == ~T9_E~0); 1782063#L1051-1 assume !(0 == ~T10_E~0); 1782064#L1056-1 assume !(0 == ~E_1~0); 1782832#L1061-1 assume !(0 == ~E_2~0); 1781981#L1066-1 assume !(0 == ~E_3~0); 1781982#L1071-1 assume !(0 == ~E_4~0); 1782806#L1076-1 assume !(0 == ~E_5~0); 1781885#L1081-1 assume !(0 == ~E_6~0); 1781886#L1086-1 assume !(0 == ~E_7~0); 1782215#L1091-1 assume !(0 == ~E_8~0); 1783033#L1096-1 assume !(0 == ~E_9~0); 1783034#L1101-1 assume !(0 == ~E_10~0); 1782290#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1782291#L484 assume !(1 == ~m_pc~0); 1781937#L484-2 is_master_triggered_~__retres1~0#1 := 0; 1781936#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1782593#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1782918#L1245 assume !(0 != activate_threads_~tmp~1#1); 1782919#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1782673#L503 assume !(1 == ~t1_pc~0); 1782674#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 1782868#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1781794#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1781795#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 1781790#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1781791#L522 assume !(1 == ~t2_pc~0); 1782635#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 1781995#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1781996#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1782284#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 1782984#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1783088#L541 assume !(1 == ~t3_pc~0); 1782356#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 1782357#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1781738#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1781739#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 1782641#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1782642#L560 assume !(1 == ~t4_pc~0); 1781869#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 1781868#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1781901#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1781752#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 1781753#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1782041#L579 assume !(1 == ~t5_pc~0); 1782042#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 1781816#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1781817#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1782924#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 1783071#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1783108#L598 assume !(1 == ~t6_pc~0); 1782844#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 1782455#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1782257#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1782258#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 1782720#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1782662#L617 assume !(1 == ~t7_pc~0); 1782107#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 1782533#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1783142#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1782997#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 1782324#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1782325#L636 assume !(1 == ~t8_pc~0); 1782717#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 1782911#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1782869#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1782731#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 1782462#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1782463#L655 assume !(1 == ~t9_pc~0); 1782490#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 1782491#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1782367#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1782368#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 1782747#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1782748#L674 assume !(1 == ~t10_pc~0); 1782413#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 1782414#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1782505#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1782506#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 1782452#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1782453#L1119 assume !(1 == ~M_E~0); 1781963#L1119-2 assume !(1 == ~T1_E~0); 1781964#L1124-1 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1781780#L1129-1 assume !(1 == ~T3_E~0); 1781781#L1134-1 assume !(1 == ~T4_E~0); 1782088#L1139-1 assume !(1 == ~T5_E~0); 1782089#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1782320#L1149-1 assume !(1 == ~T7_E~0); 1781957#L1154-1 assume !(1 == ~T8_E~0); 1781958#L1159-1 assume !(1 == ~T9_E~0); 1782045#L1164-1 assume !(1 == ~T10_E~0); 1782481#L1169-1 assume !(1 == ~E_1~0); 1782373#L1174-1 assume !(1 == ~E_2~0); 1782142#L1179-1 assume !(1 == ~E_3~0); 1782034#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 1782035#L1189-1 assume !(1 == ~E_5~0); 1782086#L1194-1 assume !(1 == ~E_6~0); 1782194#L1199-1 assume !(1 == ~E_7~0); 1782154#L1204-1 assume !(1 == ~E_8~0); 1782155#L1209-1 assume !(1 == ~E_9~0); 1783115#L1214-1 assume !(1 == ~E_10~0); 1926699#L1219-1 assume { :end_inline_reset_delta_events } true; 1926696#L1520-2 [2023-11-29 02:54:57,653 INFO L750 eck$LassoCheckResult]: Loop: 1926696#L1520-2 assume !false; 1926531#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 1926528#L981-1 assume !false; 1926525#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1926504#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1926500#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1926498#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 1926494#L836 assume !(0 != eval_~tmp~0#1); 1926495#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 1927188#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 1927186#L1006-3 assume !(0 == ~M_E~0); 1927184#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 1927182#L1011-3 assume 0 == ~T2_E~0;~T2_E~0 := 1; 1927180#L1016-3 assume !(0 == ~T3_E~0); 1927178#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 1927175#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 1927173#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 1927171#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 1927168#L1041-3 assume !(0 == ~T8_E~0); 1927166#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 1927164#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 1927162#L1056-3 assume !(0 == ~E_1~0); 1927160#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 1927158#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 1927156#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 1927154#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 1927152#L1081-3 assume !(0 == ~E_6~0); 1927149#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 1927147#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 1927145#L1096-3 assume !(0 == ~E_9~0); 1927143#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 1927141#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 1927139#L484-33 assume !(1 == ~m_pc~0); 1927137#L484-35 is_master_triggered_~__retres1~0#1 := 0; 1927134#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 1927132#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 1927130#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 1927128#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 1927127#L503-33 assume !(1 == ~t1_pc~0); 1927123#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 1927121#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 1927119#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 1927116#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 1927115#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 1927114#L522-33 assume !(1 == ~t2_pc~0); 1927113#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 1927109#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 1927104#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 1927102#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 1927100#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 1927099#L541-33 assume !(1 == ~t3_pc~0); 1927098#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 1927097#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 1927096#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 1927095#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 1927094#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 1927093#L560-33 assume 1 == ~t4_pc~0; 1927092#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 1927090#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 1927089#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 1927077#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 1927075#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 1927073#L579-33 assume !(1 == ~t5_pc~0); 1927070#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 1927068#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 1927066#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 1927064#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 1927062#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 1927060#L598-33 assume !(1 == ~t6_pc~0); 1927058#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 1927056#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 1927054#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 1927052#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 1927050#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 1927048#L617-33 assume !(1 == ~t7_pc~0); 1927044#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 1927042#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 1927040#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 1927038#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 1927035#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 1927033#L636-33 assume !(1 == ~t8_pc~0); 1927031#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 1927029#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 1927027#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 1927025#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 1927023#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 1927021#L655-33 assume !(1 == ~t9_pc~0); 1927019#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 1927016#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 1927013#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 1927011#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 1927009#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 1927007#L674-33 assume !(1 == ~t10_pc~0); 1927005#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 1927003#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 1927001#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 1926999#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 1926997#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 1926995#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 1926993#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 1926991#L1124-3 assume 1 == ~T2_E~0;~T2_E~0 := 2; 1895797#L1129-3 assume !(1 == ~T3_E~0); 1926876#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 1926874#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 1926871#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 1926869#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 1926867#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 1926865#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 1926863#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 1926769#L1169-3 assume !(1 == ~E_1~0); 1926767#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 1926765#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 1926763#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 1926761#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 1926759#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 1926757#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 1926754#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 1926752#L1209-3 assume !(1 == ~E_9~0); 1918971#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 1926748#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1926746#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1926734#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1926732#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 1926729#L1539 assume !(0 == start_simulation_~tmp~3#1); 1926726#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 1926724#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 1926712#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 1926710#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 1926707#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 1926705#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 1926703#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 1926698#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 1926696#L1520-2 [2023-11-29 02:54:57,653 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:57,653 INFO L85 PathProgramCache]: Analyzing trace with hash 415053359, now seen corresponding path program 1 times [2023-11-29 02:54:57,653 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:57,653 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [905522245] [2023-11-29 02:54:57,654 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:57,654 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:57,670 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:57,719 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:57,719 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:57,719 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [905522245] [2023-11-29 02:54:57,720 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [905522245] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:57,720 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:57,720 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:54:57,720 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1538538934] [2023-11-29 02:54:57,720 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:57,720 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:54:57,721 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:54:57,721 INFO L85 PathProgramCache]: Analyzing trace with hash -136651257, now seen corresponding path program 1 times [2023-11-29 02:54:57,721 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:54:57,721 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1055362539] [2023-11-29 02:54:57,721 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:54:57,721 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:54:57,736 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:54:57,783 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:54:57,783 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:54:57,784 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1055362539] [2023-11-29 02:54:57,784 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1055362539] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:54:57,784 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:54:57,784 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:54:57,784 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1800033705] [2023-11-29 02:54:57,784 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:54:57,784 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:54:57,785 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:54:57,785 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:54:57,785 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:54:57,785 INFO L87 Difference]: Start difference. First operand 453509 states and 644666 transitions. cyclomatic complexity: 191669 Second operand has 3 states, 3 states have (on average 42.0) internal successors, (126), 2 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:54:59,374 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:54:59,374 INFO L93 Difference]: Finished difference Result 453492 states and 643543 transitions. [2023-11-29 02:54:59,374 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 453492 states and 643543 transitions. [2023-11-29 02:55:01,404 INFO L131 ngComponentsAnalysis]: Automaton has 512 accepting balls. 451008 [2023-11-29 02:55:02,300 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 453492 states to 453492 states and 643543 transitions. [2023-11-29 02:55:02,300 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 453492 [2023-11-29 02:55:02,893 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 453492 [2023-11-29 02:55:02,894 INFO L73 IsDeterministic]: Start isDeterministic. Operand 453492 states and 643543 transitions. [2023-11-29 02:55:03,001 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:03,002 INFO L218 hiAutomatonCegarLoop]: Abstraction has 453492 states and 643543 transitions. [2023-11-29 02:55:03,202 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 453492 states and 643543 transitions. [2023-11-29 02:55:04,352 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 453492 to 60630. [2023-11-29 02:55:04,386 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60630 states, 60630 states have (on average 1.4142503711034142) internal successors, (85746), 60629 states have internal predecessors, (85746), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:04,824 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60630 states to 60630 states and 85746 transitions. [2023-11-29 02:55:04,824 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60630 states and 85746 transitions. [2023-11-29 02:55:04,824 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:55:04,825 INFO L428 stractBuchiCegarLoop]: Abstraction has 60630 states and 85746 transitions. [2023-11-29 02:55:04,825 INFO L335 stractBuchiCegarLoop]: ======== Iteration 21 ============ [2023-11-29 02:55:04,825 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60630 states and 85746 transitions. [2023-11-29 02:55:04,937 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 60208 [2023-11-29 02:55:04,937 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:04,937 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:04,938 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:04,939 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:04,939 INFO L748 eck$LassoCheckResult]: Stem: 2689075#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 2689076#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2690023#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2690024#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2690145#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 2690135#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2690136#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2689237#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2688984#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2688985#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2689980#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2689981#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2689951#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2689952#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2690015#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2689035#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2689036#L1006 assume !(0 == ~M_E~0); 2688886#L1006-2 assume !(0 == ~T1_E~0); 2688887#L1011-1 assume !(0 == ~T2_E~0); 2690053#L1016-1 assume !(0 == ~T3_E~0); 2690075#L1021-1 assume !(0 == ~T4_E~0); 2688764#L1026-1 assume !(0 == ~T5_E~0); 2688765#L1031-1 assume !(0 == ~T6_E~0); 2689674#L1036-1 assume !(0 == ~T7_E~0); 2689671#L1041-1 assume !(0 == ~T8_E~0); 2689672#L1046-1 assume !(0 == ~T9_E~0); 2689066#L1051-1 assume !(0 == ~T10_E~0); 2689067#L1056-1 assume !(0 == ~E_1~0); 2689827#L1061-1 assume !(0 == ~E_2~0); 2688988#L1066-1 assume !(0 == ~E_3~0); 2688989#L1071-1 assume !(0 == ~E_4~0); 2689796#L1076-1 assume !(0 == ~E_5~0); 2688893#L1081-1 assume !(0 == ~E_6~0); 2688894#L1086-1 assume !(0 == ~E_7~0); 2689211#L1091-1 assume !(0 == ~E_8~0); 2690039#L1096-1 assume !(0 == ~E_9~0); 2690040#L1101-1 assume !(0 == ~E_10~0); 2689284#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2689285#L484 assume !(1 == ~m_pc~0); 2688944#L484-2 is_master_triggered_~__retres1~0#1 := 0; 2688943#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2689585#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2689916#L1245 assume !(0 != activate_threads_~tmp~1#1); 2689917#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2689662#L503 assume !(1 == ~t1_pc~0); 2689663#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2689864#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2688805#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2688806#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 2688801#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2688802#L522 assume !(1 == ~t2_pc~0); 2689624#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2689002#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2689003#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2689278#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 2689982#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2690091#L541 assume !(1 == ~t3_pc~0); 2689351#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2689352#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2688748#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2688749#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 2689630#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2689631#L560 assume !(1 == ~t4_pc~0); 2688878#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2688877#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2688909#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2688762#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 2688763#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2689046#L579 assume !(1 == ~t5_pc~0); 2689047#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2688827#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2688828#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2689921#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 2690073#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2690122#L598 assume !(1 == ~t6_pc~0); 2689844#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2689451#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2689253#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2689254#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 2689712#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2689653#L617 assume !(1 == ~t7_pc~0); 2689106#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2689529#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2690157#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2690001#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 2689318#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2689319#L636 assume !(1 == ~t8_pc~0); 2689709#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2689909#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2689863#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2689720#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 2689458#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2689459#L655 assume !(1 == ~t9_pc~0); 2689488#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2689489#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2689362#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2689363#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 2689731#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2689732#L674 assume !(1 == ~t10_pc~0); 2689408#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2689409#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2689504#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2689505#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 2689448#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2689449#L1119 assume !(1 == ~M_E~0); 2688970#L1119-2 assume !(1 == ~T1_E~0); 2688971#L1124-1 assume !(1 == ~T2_E~0); 2688791#L1129-1 assume !(1 == ~T3_E~0); 2688792#L1134-1 assume !(1 == ~T4_E~0); 2689091#L1139-1 assume !(1 == ~T5_E~0); 2689092#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2689314#L1149-1 assume !(1 == ~T7_E~0); 2688964#L1154-1 assume !(1 == ~T8_E~0); 2688965#L1159-1 assume !(1 == ~T9_E~0); 2689050#L1164-1 assume !(1 == ~T10_E~0); 2689479#L1169-1 assume !(1 == ~E_1~0); 2689368#L1174-1 assume !(1 == ~E_2~0); 2689139#L1179-1 assume !(1 == ~E_3~0); 2689039#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2689040#L1189-1 assume !(1 == ~E_5~0); 2689089#L1194-1 assume !(1 == ~E_6~0); 2689191#L1199-1 assume !(1 == ~E_7~0); 2689151#L1204-1 assume !(1 == ~E_8~0); 2689152#L1209-1 assume !(1 == ~E_9~0); 2689728#L1214-1 assume !(1 == ~E_10~0); 2689729#L1219-1 assume { :end_inline_reset_delta_events } true; 2690163#L1520-2 [2023-11-29 02:55:04,939 INFO L750 eck$LassoCheckResult]: Loop: 2690163#L1520-2 assume !false; 2706509#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2706505#L981-1 assume !false; 2706503#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2697142#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2697138#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2697136#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2697133#L836 assume !(0 != eval_~tmp~0#1); 2697134#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2706985#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2706984#L1006-3 assume !(0 == ~M_E~0); 2706983#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2706982#L1011-3 assume !(0 == ~T2_E~0); 2706981#L1016-3 assume !(0 == ~T3_E~0); 2706980#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2706979#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2706977#L1031-3 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2706974#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2706972#L1041-3 assume !(0 == ~T8_E~0); 2706970#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2706968#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2706966#L1056-3 assume !(0 == ~E_1~0); 2706964#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2706962#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2706960#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2706958#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2706956#L1081-3 assume !(0 == ~E_6~0); 2706954#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2706952#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2706949#L1096-3 assume !(0 == ~E_9~0); 2706947#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2706945#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2706943#L484-33 assume !(1 == ~m_pc~0); 2706941#L484-35 is_master_triggered_~__retres1~0#1 := 0; 2706938#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2706935#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2706933#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 2706931#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2706929#L503-33 assume !(1 == ~t1_pc~0); 2706927#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2706925#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2706922#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2706920#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2706918#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2706916#L522-33 assume 1 == ~t2_pc~0; 2706913#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2706911#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2706909#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2706907#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2706905#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2706903#L541-33 assume !(1 == ~t3_pc~0); 2706901#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2706899#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2706897#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2706895#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2706893#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2706891#L560-33 assume 1 == ~t4_pc~0; 2706889#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 2706886#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2706883#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2706881#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2706879#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2706876#L579-33 assume !(1 == ~t5_pc~0); 2706874#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2706872#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2706870#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2706868#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2706866#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2706864#L598-33 assume !(1 == ~t6_pc~0); 2706862#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2706860#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2706857#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2706855#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2706853#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2706851#L617-33 assume !(1 == ~t7_pc~0); 2706847#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2706845#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2706843#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2706841#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 2706838#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2706836#L636-33 assume !(1 == ~t8_pc~0); 2706834#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2706833#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2706829#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2706827#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2706825#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2706824#L655-33 assume !(1 == ~t9_pc~0); 2706821#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 2706819#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2706818#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2706815#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 2706811#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2706807#L674-33 assume !(1 == ~t10_pc~0); 2706806#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 2706804#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2706800#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2706796#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2706792#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2706788#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2706784#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2706779#L1124-3 assume !(1 == ~T2_E~0); 2706777#L1129-3 assume !(1 == ~T3_E~0); 2706775#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2706774#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2706773#L1144-3 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2706772#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2706771#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2706770#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2706769#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2706768#L1169-3 assume !(1 == ~E_1~0); 2706767#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2706766#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2706765#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2706764#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2706763#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2706762#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2706761#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2706760#L1209-3 assume !(1 == ~E_9~0); 2706759#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2706758#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2706757#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2706746#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2706734#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2706731#L1539 assume !(0 == start_simulation_~tmp~3#1); 2706728#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2706725#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2706711#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2706708#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2706705#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2706704#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2706703#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2706702#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 2690163#L1520-2 [2023-11-29 02:55:04,939 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:04,940 INFO L85 PathProgramCache]: Analyzing trace with hash -402595091, now seen corresponding path program 1 times [2023-11-29 02:55:04,940 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:04,940 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [610586530] [2023-11-29 02:55:04,940 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:04,940 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:04,954 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:05,012 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:05,012 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:05,012 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [610586530] [2023-11-29 02:55:05,012 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [610586530] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:05,013 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:05,013 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:55:05,013 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1108883743] [2023-11-29 02:55:05,013 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:05,013 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:55:05,014 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:05,014 INFO L85 PathProgramCache]: Analyzing trace with hash 2138246116, now seen corresponding path program 1 times [2023-11-29 02:55:05,014 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:05,014 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1884017766] [2023-11-29 02:55:05,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:05,015 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:05,028 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:05,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:05,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:05,074 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1884017766] [2023-11-29 02:55:05,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1884017766] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:05,074 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:05,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:55:05,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [982771821] [2023-11-29 02:55:05,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:05,075 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:05,075 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:05,076 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 02:55:05,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 02:55:05,076 INFO L87 Difference]: Start difference. First operand 60630 states and 85746 transitions. cyclomatic complexity: 25180 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:05,432 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:05,432 INFO L93 Difference]: Finished difference Result 127573 states and 180421 transitions. [2023-11-29 02:55:05,433 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 127573 states and 180421 transitions. [2023-11-29 02:55:05,827 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 126752 [2023-11-29 02:55:06,076 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 127573 states to 127573 states and 180421 transitions. [2023-11-29 02:55:06,076 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 127573 [2023-11-29 02:55:06,136 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 127573 [2023-11-29 02:55:06,137 INFO L73 IsDeterministic]: Start isDeterministic. Operand 127573 states and 180421 transitions. [2023-11-29 02:55:06,558 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:06,558 INFO L218 hiAutomatonCegarLoop]: Abstraction has 127573 states and 180421 transitions. [2023-11-29 02:55:06,617 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 127573 states and 180421 transitions. [2023-11-29 02:55:07,212 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 127573 to 67062. [2023-11-29 02:55:07,251 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67062 states, 67062 states have (on average 1.41612239420238) internal successors, (94968), 67061 states have internal predecessors, (94968), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:07,376 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67062 states to 67062 states and 94968 transitions. [2023-11-29 02:55:07,376 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67062 states and 94968 transitions. [2023-11-29 02:55:07,377 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 02:55:07,377 INFO L428 stractBuchiCegarLoop]: Abstraction has 67062 states and 94968 transitions. [2023-11-29 02:55:07,377 INFO L335 stractBuchiCegarLoop]: ======== Iteration 22 ============ [2023-11-29 02:55:07,377 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67062 states and 94968 transitions. [2023-11-29 02:55:07,534 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 66544 [2023-11-29 02:55:07,534 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:07,534 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:07,535 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:07,535 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:07,536 INFO L748 eck$LassoCheckResult]: Stem: 2877289#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 2877290#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 2878229#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 2878230#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 2878357#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 2878348#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 2878349#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 2877454#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 2877199#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 2877200#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 2878191#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 2878192#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 2878165#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 2878166#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 2878220#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 2877248#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 2877249#L1006 assume !(0 == ~M_E~0); 2877098#L1006-2 assume !(0 == ~T1_E~0); 2877099#L1011-1 assume !(0 == ~T2_E~0); 2878259#L1016-1 assume !(0 == ~T3_E~0); 2878288#L1021-1 assume !(0 == ~T4_E~0); 2876980#L1026-1 assume !(0 == ~T5_E~0); 2876981#L1031-1 assume 0 == ~T6_E~0;~T6_E~0 := 1; 2878392#L1036-1 assume !(0 == ~T7_E~0); 2877890#L1041-1 assume !(0 == ~T8_E~0); 2877891#L1046-1 assume !(0 == ~T9_E~0); 2877280#L1051-1 assume !(0 == ~T10_E~0); 2877281#L1056-1 assume !(0 == ~E_1~0); 2878032#L1061-1 assume !(0 == ~E_2~0); 2878089#L1066-1 assume !(0 == ~E_3~0); 2878313#L1071-1 assume !(0 == ~E_4~0); 2878006#L1076-1 assume !(0 == ~E_5~0); 2878007#L1081-1 assume !(0 == ~E_6~0); 2878451#L1086-1 assume !(0 == ~E_7~0); 2878317#L1091-1 assume !(0 == ~E_8~0); 2878240#L1096-1 assume !(0 == ~E_9~0); 2878241#L1101-1 assume !(0 == ~E_10~0); 2877501#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2877502#L484 assume !(1 == ~m_pc~0); 2878449#L484-2 is_master_triggered_~__retres1~0#1 := 0; 2878447#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2878446#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2878445#L1245 assume !(0 != activate_threads_~tmp~1#1); 2878382#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2878383#L503 assume !(1 == ~t1_pc~0); 2878444#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 2878443#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2877020#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2877021#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 2877638#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2878441#L522 assume !(1 == ~t2_pc~0); 2877843#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 2877844#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2877495#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2877496#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 2878193#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2878301#L541 assume !(1 == ~t3_pc~0); 2878302#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 2878439#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2878438#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2877924#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 2877925#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2878437#L560 assume !(1 == ~t4_pc~0); 2877090#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 2877089#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2877121#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2877122#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 2878434#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2877259#L579 assume !(1 == ~t5_pc~0); 2877260#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 2877041#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2877042#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2878125#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 2878286#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2878401#L598 assume !(1 == ~t6_pc~0); 2878043#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 2877673#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2877674#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2878427#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 2877930#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2877931#L617 assume !(1 == ~t7_pc~0); 2877749#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 2877750#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2878373#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2878207#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 2878208#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2877927#L636 assume !(1 == ~t8_pc~0); 2877928#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 2878420#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2878419#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2877939#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 2877681#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2877682#L655 assume !(1 == ~t9_pc~0); 2877710#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 2877711#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2878414#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2878289#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 2878290#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2878413#L674 assume !(1 == ~t10_pc~0); 2878412#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 2878305#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2877726#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2877727#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 2877670#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2877671#L1119 assume !(1 == ~M_E~0); 2877185#L1119-2 assume !(1 == ~T1_E~0); 2877186#L1124-1 assume !(1 == ~T2_E~0); 2877591#L1129-1 assume !(1 == ~T3_E~0); 2877860#L1134-1 assume !(1 == ~T4_E~0); 2877305#L1139-1 assume !(1 == ~T5_E~0); 2877306#L1144-1 assume 1 == ~T6_E~0;~T6_E~0 := 2; 2877532#L1149-1 assume !(1 == ~T7_E~0); 2877179#L1154-1 assume !(1 == ~T8_E~0); 2877180#L1159-1 assume !(1 == ~T9_E~0); 2877263#L1164-1 assume !(1 == ~T10_E~0); 2877701#L1169-1 assume !(1 == ~E_1~0); 2877585#L1174-1 assume !(1 == ~E_2~0); 2877355#L1179-1 assume !(1 == ~E_3~0); 2877252#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 2877253#L1189-1 assume !(1 == ~E_5~0); 2877303#L1194-1 assume !(1 == ~E_6~0); 2877408#L1199-1 assume !(1 == ~E_7~0); 2877367#L1204-1 assume !(1 == ~E_8~0); 2877368#L1209-1 assume !(1 == ~E_9~0); 2877950#L1214-1 assume !(1 == ~E_10~0); 2877951#L1219-1 assume { :end_inline_reset_delta_events } true; 2878387#L1520-2 [2023-11-29 02:55:07,536 INFO L750 eck$LassoCheckResult]: Loop: 2878387#L1520-2 assume !false; 2885116#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 2885112#L981-1 assume !false; 2885110#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2885091#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2885086#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2885084#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 2885081#L836 assume !(0 != eval_~tmp~0#1); 2885082#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 2894951#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 2894949#L1006-3 assume !(0 == ~M_E~0); 2894947#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 2894945#L1011-3 assume !(0 == ~T2_E~0); 2894943#L1016-3 assume !(0 == ~T3_E~0); 2894941#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 2894939#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 2894936#L1031-3 assume !(0 == ~T6_E~0); 2894937#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 2895146#L1041-3 assume !(0 == ~T8_E~0); 2895145#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 2895144#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 2895143#L1056-3 assume !(0 == ~E_1~0); 2895142#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 2895141#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 2895140#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 2895139#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 2895138#L1081-3 assume !(0 == ~E_6~0); 2895137#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 2895135#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 2895133#L1096-3 assume !(0 == ~E_9~0); 2895131#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 2895128#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 2895126#L484-33 assume !(1 == ~m_pc~0); 2895124#L484-35 is_master_triggered_~__retres1~0#1 := 0; 2895121#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 2895119#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 2895117#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 2895114#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 2895112#L503-33 assume !(1 == ~t1_pc~0); 2895110#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 2895108#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 2895106#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 2895104#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 2895101#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 2895099#L522-33 assume 1 == ~t2_pc~0; 2895096#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 2895094#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 2895092#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 2895090#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 2895088#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 2895086#L541-33 assume !(1 == ~t3_pc~0); 2895084#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 2895082#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 2895080#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 2895078#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 2895075#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 2895073#L560-33 assume !(1 == ~t4_pc~0); 2895070#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 2895068#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 2895066#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 2895064#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 2895061#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 2895059#L579-33 assume !(1 == ~t5_pc~0); 2895057#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 2895055#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 2895053#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 2895051#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 2895049#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 2895047#L598-33 assume !(1 == ~t6_pc~0); 2895045#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 2895043#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 2895041#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 2895037#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 2895035#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 2895033#L617-33 assume !(1 == ~t7_pc~0); 2895029#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 2895026#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 2895024#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 2895022#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 2895018#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 2895016#L636-33 assume !(1 == ~t8_pc~0); 2895014#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 2895012#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 2895010#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 2895008#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 2895005#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 2895003#L655-33 assume 1 == ~t9_pc~0; 2895000#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 2894998#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 2894996#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 2894994#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 2894992#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 2894990#L674-33 assume !(1 == ~t10_pc~0); 2894988#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 2894986#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 2894984#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 2894983#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 2894982#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 2894981#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 2894979#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 2894976#L1124-3 assume !(1 == ~T2_E~0); 2894974#L1129-3 assume !(1 == ~T3_E~0); 2894972#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 2894970#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 2894840#L1144-3 assume !(1 == ~T6_E~0); 2894837#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 2894835#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 2894833#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 2894831#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 2894829#L1169-3 assume !(1 == ~E_1~0); 2894827#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 2894825#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 2894823#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 2894820#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 2894818#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 2894816#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 2894814#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 2894812#L1209-3 assume !(1 == ~E_9~0); 2894810#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 2894808#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2885349#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2885337#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2885335#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 2885332#L1539 assume !(0 == start_simulation_~tmp~3#1); 2885329#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 2885327#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 2885315#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 2885313#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 2885311#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 2885310#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 2885306#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 2885304#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 2878387#L1520-2 [2023-11-29 02:55:07,536 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:07,536 INFO L85 PathProgramCache]: Analyzing trace with hash -1791889105, now seen corresponding path program 1 times [2023-11-29 02:55:07,537 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:07,537 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [540487398] [2023-11-29 02:55:07,537 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:07,537 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:07,549 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:07,593 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:07,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:07,595 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [540487398] [2023-11-29 02:55:07,595 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [540487398] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:07,595 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:07,595 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:55:07,595 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2124718000] [2023-11-29 02:55:07,595 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:07,596 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:55:07,596 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:07,596 INFO L85 PathProgramCache]: Analyzing trace with hash -1611714784, now seen corresponding path program 1 times [2023-11-29 02:55:07,596 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:07,596 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1377752123] [2023-11-29 02:55:07,597 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:07,597 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:07,609 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:07,635 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:07,635 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:07,635 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1377752123] [2023-11-29 02:55:07,635 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1377752123] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:07,635 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:07,635 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:55:07,636 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1901337700] [2023-11-29 02:55:07,636 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:07,636 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:07,636 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:07,636 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 02:55:07,637 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 02:55:07,637 INFO L87 Difference]: Start difference. First operand 67062 states and 94968 transitions. cyclomatic complexity: 27970 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:07,826 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:07,827 INFO L93 Difference]: Finished difference Result 60630 states and 85552 transitions. [2023-11-29 02:55:07,827 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 60630 states and 85552 transitions. [2023-11-29 02:55:08,313 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 60208 [2023-11-29 02:55:08,417 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 60630 states to 60630 states and 85552 transitions. [2023-11-29 02:55:08,417 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 60630 [2023-11-29 02:55:08,439 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 60630 [2023-11-29 02:55:08,439 INFO L73 IsDeterministic]: Start isDeterministic. Operand 60630 states and 85552 transitions. [2023-11-29 02:55:08,457 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:08,457 INFO L218 hiAutomatonCegarLoop]: Abstraction has 60630 states and 85552 transitions. [2023-11-29 02:55:08,480 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 60630 states and 85552 transitions. [2023-11-29 02:55:08,764 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 60630 to 60630. [2023-11-29 02:55:08,797 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60630 states, 60630 states have (on average 1.4110506349991754) internal successors, (85552), 60629 states have internal predecessors, (85552), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:08,884 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60630 states to 60630 states and 85552 transitions. [2023-11-29 02:55:08,884 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60630 states and 85552 transitions. [2023-11-29 02:55:08,885 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:55:08,885 INFO L428 stractBuchiCegarLoop]: Abstraction has 60630 states and 85552 transitions. [2023-11-29 02:55:08,885 INFO L335 stractBuchiCegarLoop]: ======== Iteration 23 ============ [2023-11-29 02:55:08,885 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60630 states and 85552 transitions. [2023-11-29 02:55:09,012 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 60208 [2023-11-29 02:55:09,012 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:09,012 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:09,014 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:09,014 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:09,014 INFO L748 eck$LassoCheckResult]: Stem: 3004992#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 3004993#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3005931#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3005932#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3006047#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3006038#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3006039#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3005161#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3004900#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3004901#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3005894#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3005895#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3005870#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3005871#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3005922#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3004950#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3004951#L1006 assume !(0 == ~M_E~0); 3004799#L1006-2 assume !(0 == ~T1_E~0); 3004800#L1011-1 assume !(0 == ~T2_E~0); 3005962#L1016-1 assume !(0 == ~T3_E~0); 3005990#L1021-1 assume !(0 == ~T4_E~0); 3004681#L1026-1 assume !(0 == ~T5_E~0); 3004682#L1031-1 assume !(0 == ~T6_E~0); 3005598#L1036-1 assume !(0 == ~T7_E~0); 3005595#L1041-1 assume !(0 == ~T8_E~0); 3005596#L1046-1 assume !(0 == ~T9_E~0); 3004983#L1051-1 assume !(0 == ~T10_E~0); 3004984#L1056-1 assume !(0 == ~E_1~0); 3005739#L1061-1 assume !(0 == ~E_2~0); 3004904#L1066-1 assume !(0 == ~E_3~0); 3004905#L1071-1 assume !(0 == ~E_4~0); 3005713#L1076-1 assume !(0 == ~E_5~0); 3004807#L1081-1 assume !(0 == ~E_6~0); 3004808#L1086-1 assume !(0 == ~E_7~0); 3005135#L1091-1 assume !(0 == ~E_8~0); 3005943#L1096-1 assume !(0 == ~E_9~0); 3005944#L1101-1 assume !(0 == ~E_10~0); 3005209#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3005210#L484 assume !(1 == ~m_pc~0); 3004859#L484-2 is_master_triggered_~__retres1~0#1 := 0; 3004858#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3005508#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3005831#L1245 assume !(0 != activate_threads_~tmp~1#1); 3005832#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3005586#L503 assume !(1 == ~t1_pc~0); 3005587#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3005776#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3004721#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3004722#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 3004717#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3004718#L522 assume !(1 == ~t2_pc~0); 3005548#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3004917#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3004918#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3005203#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3005893#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3006003#L541 assume !(1 == ~t3_pc~0); 3005277#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3005278#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3004665#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3004666#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3005554#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3005555#L560 assume !(1 == ~t4_pc~0); 3004791#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3004790#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3004822#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3004679#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 3004680#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3004961#L579 assume !(1 == ~t5_pc~0); 3004962#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3004742#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3004743#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3005836#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3005987#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3006024#L598 assume !(1 == ~t6_pc~0); 3005750#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3005378#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3005178#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3005179#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3005635#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3005576#L617 assume !(1 == ~t7_pc~0); 3005027#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3005454#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3006053#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3005908#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 3005245#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3005246#L636 assume !(1 == ~t8_pc~0); 3005632#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3005825#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3005777#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3005644#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3005385#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3005386#L655 assume !(1 == ~t9_pc~0); 3005414#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3005415#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3005289#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3005290#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3005655#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3005656#L674 assume !(1 == ~t10_pc~0); 3005334#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3005335#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3005429#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3005430#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3005375#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3005376#L1119 assume !(1 == ~M_E~0); 3004885#L1119-2 assume !(1 == ~T1_E~0); 3004886#L1124-1 assume !(1 == ~T2_E~0); 3004707#L1129-1 assume !(1 == ~T3_E~0); 3004708#L1134-1 assume !(1 == ~T4_E~0); 3005008#L1139-1 assume !(1 == ~T5_E~0); 3005009#L1144-1 assume !(1 == ~T6_E~0); 3005241#L1149-1 assume !(1 == ~T7_E~0); 3004879#L1154-1 assume !(1 == ~T8_E~0); 3004880#L1159-1 assume !(1 == ~T9_E~0); 3004965#L1164-1 assume !(1 == ~T10_E~0); 3005405#L1169-1 assume !(1 == ~E_1~0); 3005295#L1174-1 assume !(1 == ~E_2~0); 3005062#L1179-1 assume !(1 == ~E_3~0); 3004954#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3004955#L1189-1 assume !(1 == ~E_5~0); 3005006#L1194-1 assume !(1 == ~E_6~0); 3005114#L1199-1 assume !(1 == ~E_7~0); 3005074#L1204-1 assume !(1 == ~E_8~0); 3005075#L1209-1 assume !(1 == ~E_9~0); 3005653#L1214-1 assume !(1 == ~E_10~0); 3005654#L1219-1 assume { :end_inline_reset_delta_events } true; 3006057#L1520-2 [2023-11-29 02:55:09,014 INFO L750 eck$LassoCheckResult]: Loop: 3006057#L1520-2 assume !false; 3012348#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3012345#L981-1 assume !false; 3012342#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3012319#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3012315#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3012313#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3012310#L836 assume !(0 != eval_~tmp~0#1); 3012311#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3063934#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3063932#L1006-3 assume !(0 == ~M_E~0); 3063930#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3063928#L1011-3 assume !(0 == ~T2_E~0); 3063926#L1016-3 assume !(0 == ~T3_E~0); 3063923#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3063921#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3063847#L1031-3 assume !(0 == ~T6_E~0); 3063843#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3063841#L1041-3 assume !(0 == ~T8_E~0); 3063840#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3063839#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3063838#L1056-3 assume !(0 == ~E_1~0); 3063836#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3063835#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3063834#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3063833#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3063831#L1081-3 assume !(0 == ~E_6~0); 3063829#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3063828#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3063827#L1096-3 assume !(0 == ~E_9~0); 3063826#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3063825#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3063824#L484-33 assume 1 == ~m_pc~0; 3063822#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3063820#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3063818#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3063816#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 3063814#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3063812#L503-33 assume !(1 == ~t1_pc~0); 3063809#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3063807#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3063805#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3063803#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3063801#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3063799#L522-33 assume 1 == ~t2_pc~0; 3063796#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3063794#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3063792#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3063790#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3063788#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3063786#L541-33 assume !(1 == ~t3_pc~0); 3063783#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3063781#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3063779#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3063777#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3063775#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3063773#L560-33 assume 1 == ~t4_pc~0; 3063770#L561-11 assume 1 == ~E_4~0;is_transmit4_triggered_~__retres1~4#1 := 1; 3063767#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3063765#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3063763#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3063761#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3063759#L579-33 assume !(1 == ~t5_pc~0); 3063757#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3063755#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3063753#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3063751#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3063749#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3063747#L598-33 assume !(1 == ~t6_pc~0); 3063744#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3063742#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3063740#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3063737#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3063735#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3063733#L617-33 assume 1 == ~t7_pc~0; 3063731#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3063732#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3063837#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3063722#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3063720#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3063718#L636-33 assume !(1 == ~t8_pc~0); 3063717#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3063714#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3063712#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3063710#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3063708#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3063706#L655-33 assume !(1 == ~t9_pc~0); 3063704#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 3063701#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3063699#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3063697#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 3063695#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3063693#L674-33 assume !(1 == ~t10_pc~0); 3063691#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 3063689#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3063687#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3063685#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3063683#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3063681#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3063679#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3063677#L1124-3 assume !(1 == ~T2_E~0); 3063675#L1129-3 assume !(1 == ~T3_E~0); 3063673#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3063671#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3063669#L1144-3 assume !(1 == ~T6_E~0); 3063667#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3063665#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3063663#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3063661#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3063659#L1169-3 assume !(1 == ~E_1~0); 3063657#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3063644#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3063641#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3063638#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3063634#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3062419#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3062407#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3062405#L1209-3 assume !(1 == ~E_9~0); 3061473#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3012598#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3012595#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3012583#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3012581#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3012578#L1539 assume !(0 == start_simulation_~tmp~3#1); 3012575#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3012573#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3012561#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3012559#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3012557#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3012555#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3012553#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3012552#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 3006057#L1520-2 [2023-11-29 02:55:09,015 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:09,015 INFO L85 PathProgramCache]: Analyzing trace with hash -1423663445, now seen corresponding path program 1 times [2023-11-29 02:55:09,015 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:09,015 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1435517416] [2023-11-29 02:55:09,015 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:09,016 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:09,024 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:09,065 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:09,065 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:09,065 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1435517416] [2023-11-29 02:55:09,065 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1435517416] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:09,065 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:09,065 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:55:09,065 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1749632275] [2023-11-29 02:55:09,065 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:09,066 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:55:09,066 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:09,066 INFO L85 PathProgramCache]: Analyzing trace with hash -1730152156, now seen corresponding path program 1 times [2023-11-29 02:55:09,066 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:09,066 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [50235953] [2023-11-29 02:55:09,066 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:09,067 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:09,075 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:09,107 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:09,108 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:09,108 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [50235953] [2023-11-29 02:55:09,108 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [50235953] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:09,108 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:09,108 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:55:09,108 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [297030651] [2023-11-29 02:55:09,108 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:09,109 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:09,109 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:09,109 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 02:55:09,109 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 02:55:09,109 INFO L87 Difference]: Start difference. First operand 60630 states and 85552 transitions. cyclomatic complexity: 24986 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:09,721 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:09,722 INFO L93 Difference]: Finished difference Result 126682 states and 177590 transitions. [2023-11-29 02:55:09,722 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 126682 states and 177590 transitions. [2023-11-29 02:55:10,057 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 125776 [2023-11-29 02:55:10,251 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 126682 states to 126682 states and 177590 transitions. [2023-11-29 02:55:10,251 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 126682 [2023-11-29 02:55:10,292 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 126682 [2023-11-29 02:55:10,292 INFO L73 IsDeterministic]: Start isDeterministic. Operand 126682 states and 177590 transitions. [2023-11-29 02:55:10,326 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:10,326 INFO L218 hiAutomatonCegarLoop]: Abstraction has 126682 states and 177590 transitions. [2023-11-29 02:55:10,377 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 126682 states and 177590 transitions. [2023-11-29 02:55:11,134 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 126682 to 67062. [2023-11-29 02:55:11,160 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 67062 states, 67062 states have (on average 1.4046255703677195) internal successors, (94197), 67061 states have internal predecessors, (94197), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:11,253 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 67062 states to 67062 states and 94197 transitions. [2023-11-29 02:55:11,253 INFO L240 hiAutomatonCegarLoop]: Abstraction has 67062 states and 94197 transitions. [2023-11-29 02:55:11,254 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 02:55:11,254 INFO L428 stractBuchiCegarLoop]: Abstraction has 67062 states and 94197 transitions. [2023-11-29 02:55:11,254 INFO L335 stractBuchiCegarLoop]: ======== Iteration 24 ============ [2023-11-29 02:55:11,254 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 67062 states and 94197 transitions. [2023-11-29 02:55:11,380 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 66544 [2023-11-29 02:55:11,380 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:11,380 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:11,381 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:11,381 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:11,382 INFO L748 eck$LassoCheckResult]: Stem: 3192314#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 3192315#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3193281#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3193282#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3193398#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3193387#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3193388#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3192483#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3192221#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3192222#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3193239#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3193240#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3193214#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3193215#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3193270#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3192274#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3192275#L1006 assume !(0 == ~M_E~0); 3192123#L1006-2 assume !(0 == ~T1_E~0); 3192124#L1011-1 assume !(0 == ~T2_E~0); 3193306#L1016-1 assume !(0 == ~T3_E~0); 3193327#L1021-1 assume !(0 == ~T4_E~0); 3192007#L1026-1 assume !(0 == ~T5_E~0); 3192008#L1031-1 assume !(0 == ~T6_E~0); 3192928#L1036-1 assume !(0 == ~T7_E~0); 3192924#L1041-1 assume !(0 == ~T8_E~0); 3192925#L1046-1 assume !(0 == ~T9_E~0); 3192305#L1051-1 assume !(0 == ~T10_E~0); 3192306#L1056-1 assume !(0 == ~E_1~0); 3193072#L1061-1 assume !(0 == ~E_2~0); 3192225#L1066-1 assume !(0 == ~E_3~0); 3192226#L1071-1 assume 0 == ~E_4~0;~E_4~0 := 1; 3193350#L1076-1 assume !(0 == ~E_5~0); 3192130#L1081-1 assume !(0 == ~E_6~0); 3192131#L1086-1 assume !(0 == ~E_7~0); 3192457#L1091-1 assume !(0 == ~E_8~0); 3193521#L1096-1 assume !(0 == ~E_9~0); 3193404#L1101-1 assume !(0 == ~E_10~0); 3193405#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3193368#L484 assume !(1 == ~m_pc~0); 3192180#L484-2 is_master_triggered_~__retres1~0#1 := 0; 3192179#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3192836#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3193164#L1245 assume !(0 != activate_threads_~tmp~1#1); 3193165#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3192916#L503 assume !(1 == ~t1_pc~0); 3192917#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3193175#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3192047#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3192048#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 3192041#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3192042#L522 assume !(1 == ~t2_pc~0); 3193252#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3192238#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3192239#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3193513#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3193418#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3193419#L541 assume !(1 == ~t3_pc~0); 3192597#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3192598#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3193191#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3192959#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3192960#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3193511#L560 assume !(1 == ~t4_pc~0); 3193509#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3193508#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3193507#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3193506#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 3193505#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3193504#L579 assume !(1 == ~t5_pc~0); 3193503#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3193502#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3193501#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3193500#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3193499#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3193498#L598 assume !(1 == ~t6_pc~0); 3193497#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3193496#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3193495#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3193494#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3193493#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3193492#L617 assume !(1 == ~t7_pc~0); 3193490#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3193488#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3193486#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3193484#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 3193483#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3193482#L636 assume !(1 == ~t8_pc~0); 3193481#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3193480#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3193479#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3193478#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3193477#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3193476#L655 assume !(1 == ~t9_pc~0); 3193474#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3193473#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3193472#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3193471#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3193470#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3193469#L674 assume !(1 == ~t10_pc~0); 3193468#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3193467#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3193466#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3193465#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3193464#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3193463#L1119 assume !(1 == ~M_E~0); 3193462#L1119-2 assume !(1 == ~T1_E~0); 3193461#L1124-1 assume !(1 == ~T2_E~0); 3193460#L1129-1 assume !(1 == ~T3_E~0); 3193459#L1134-1 assume !(1 == ~T4_E~0); 3193458#L1139-1 assume !(1 == ~T5_E~0); 3193457#L1144-1 assume !(1 == ~T6_E~0); 3193456#L1149-1 assume !(1 == ~T7_E~0); 3193455#L1154-1 assume !(1 == ~T8_E~0); 3193454#L1159-1 assume !(1 == ~T9_E~0); 3193453#L1164-1 assume !(1 == ~T10_E~0); 3193452#L1169-1 assume !(1 == ~E_1~0); 3193451#L1174-1 assume !(1 == ~E_2~0); 3193450#L1179-1 assume !(1 == ~E_3~0); 3193449#L1184-1 assume 1 == ~E_4~0;~E_4~0 := 2; 3192277#L1189-1 assume !(1 == ~E_5~0); 3192329#L1194-1 assume !(1 == ~E_6~0); 3192436#L1199-1 assume !(1 == ~E_7~0); 3192394#L1204-1 assume !(1 == ~E_8~0); 3192395#L1209-1 assume !(1 == ~E_9~0); 3192984#L1214-1 assume !(1 == ~E_10~0); 3192985#L1219-1 assume { :end_inline_reset_delta_events } true; 3193426#L1520-2 [2023-11-29 02:55:11,382 INFO L750 eck$LassoCheckResult]: Loop: 3193426#L1520-2 assume !false; 3202813#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3202810#L981-1 assume !false; 3202807#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3202785#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3202781#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3202779#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3202775#L836 assume !(0 != eval_~tmp~0#1); 3202776#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3203382#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3203380#L1006-3 assume !(0 == ~M_E~0); 3203377#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3203375#L1011-3 assume !(0 == ~T2_E~0); 3203373#L1016-3 assume !(0 == ~T3_E~0); 3203371#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3203369#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3203367#L1031-3 assume !(0 == ~T6_E~0); 3203364#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3203362#L1041-3 assume !(0 == ~T8_E~0); 3203360#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3203357#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3203355#L1056-3 assume !(0 == ~E_1~0); 3203353#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3203350#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3203347#L1071-3 assume 0 == ~E_4~0;~E_4~0 := 1; 3203346#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3203345#L1081-3 assume !(0 == ~E_6~0); 3203344#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3203343#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3203342#L1096-3 assume !(0 == ~E_9~0); 3203341#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3203340#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3203339#L484-33 assume 1 == ~m_pc~0; 3203337#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3203336#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3203335#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3203334#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 3203333#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3203332#L503-33 assume !(1 == ~t1_pc~0); 3203331#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3203330#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3203329#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3203328#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3203327#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3203326#L522-33 assume 1 == ~t2_pc~0; 3203324#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 3203323#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3203322#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3203321#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3203320#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3203319#L541-33 assume !(1 == ~t3_pc~0); 3203318#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3203317#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3203316#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3203315#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3203314#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3203313#L560-33 assume !(1 == ~t4_pc~0); 3203310#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 3203309#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3203308#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3203307#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3203306#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3203305#L579-33 assume !(1 == ~t5_pc~0); 3203304#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3203303#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3203302#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3203301#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3203300#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3203299#L598-33 assume !(1 == ~t6_pc~0); 3203298#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3203297#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3203296#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3203295#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3203294#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3203293#L617-33 assume 1 == ~t7_pc~0; 3203291#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 3203289#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3203287#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3203285#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 3203284#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3203283#L636-33 assume !(1 == ~t8_pc~0); 3203282#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3203281#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3203280#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3203279#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3203278#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3203277#L655-33 assume 1 == ~t9_pc~0; 3203275#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3203274#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3203273#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3203272#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 3203271#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3203270#L674-33 assume !(1 == ~t10_pc~0); 3203269#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 3203268#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3203267#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3203266#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3203265#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3203264#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3203263#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3203262#L1124-3 assume !(1 == ~T2_E~0); 3203261#L1129-3 assume !(1 == ~T3_E~0); 3203260#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3203259#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3203258#L1144-3 assume !(1 == ~T6_E~0); 3203257#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3203256#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3203255#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3203254#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3203253#L1169-3 assume !(1 == ~E_1~0); 3203252#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3203251#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3203249#L1184-3 assume 1 == ~E_4~0;~E_4~0 := 2; 3203247#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3203245#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3203243#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3203241#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3203239#L1209-3 assume !(1 == ~E_9~0); 3203238#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3203235#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3203233#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3203221#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3203219#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3203216#L1539 assume !(0 == start_simulation_~tmp~3#1); 3203213#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3203211#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3203199#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3203197#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3203195#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3203193#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3203191#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3203189#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 3193426#L1520-2 [2023-11-29 02:55:11,382 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:11,382 INFO L85 PathProgramCache]: Analyzing trace with hash -366932243, now seen corresponding path program 1 times [2023-11-29 02:55:11,383 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:11,383 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2098331392] [2023-11-29 02:55:11,383 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:11,383 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:11,391 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:11,421 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:11,422 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:11,422 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [2098331392] [2023-11-29 02:55:11,422 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [2098331392] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:11,422 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:11,422 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:55:11,422 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [244684295] [2023-11-29 02:55:11,422 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:11,423 INFO L753 eck$LassoCheckResult]: stem already infeasible [2023-11-29 02:55:11,423 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:11,423 INFO L85 PathProgramCache]: Analyzing trace with hash -343029532, now seen corresponding path program 1 times [2023-11-29 02:55:11,423 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:11,423 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1090013412] [2023-11-29 02:55:11,423 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:11,423 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:11,432 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:11,448 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:11,449 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:11,449 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1090013412] [2023-11-29 02:55:11,449 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1090013412] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:11,449 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:11,449 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:55:11,449 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2105366229] [2023-11-29 02:55:11,449 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:11,449 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:11,450 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:11,450 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 4 interpolants. [2023-11-29 02:55:11,450 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=5, Invalid=7, Unknown=0, NotChecked=0, Total=12 [2023-11-29 02:55:11,450 INFO L87 Difference]: Start difference. First operand 67062 states and 94197 transitions. cyclomatic complexity: 27199 Second operand has 4 states, 4 states have (on average 31.5) internal successors, (126), 3 states have internal predecessors, (126), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:11,722 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:11,722 INFO L93 Difference]: Finished difference Result 89846 states and 125917 transitions. [2023-11-29 02:55:11,723 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 89846 states and 125917 transitions. [2023-11-29 02:55:11,970 INFO L131 ngComponentsAnalysis]: Automaton has 96 accepting balls. 89264 [2023-11-29 02:55:12,128 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 89846 states to 89846 states and 125917 transitions. [2023-11-29 02:55:12,129 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 89846 [2023-11-29 02:55:12,169 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 89846 [2023-11-29 02:55:12,169 INFO L73 IsDeterministic]: Start isDeterministic. Operand 89846 states and 125917 transitions. [2023-11-29 02:55:12,202 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:12,202 INFO L218 hiAutomatonCegarLoop]: Abstraction has 89846 states and 125917 transitions. [2023-11-29 02:55:12,244 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 89846 states and 125917 transitions. [2023-11-29 02:55:13,131 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 89846 to 60630. [2023-11-29 02:55:13,164 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 60630 states, 60630 states have (on average 1.398334158007587) internal successors, (84781), 60629 states have internal predecessors, (84781), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:13,277 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 60630 states to 60630 states and 84781 transitions. [2023-11-29 02:55:13,277 INFO L240 hiAutomatonCegarLoop]: Abstraction has 60630 states and 84781 transitions. [2023-11-29 02:55:13,278 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 4 states. [2023-11-29 02:55:13,278 INFO L428 stractBuchiCegarLoop]: Abstraction has 60630 states and 84781 transitions. [2023-11-29 02:55:13,278 INFO L335 stractBuchiCegarLoop]: ======== Iteration 25 ============ [2023-11-29 02:55:13,278 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 60630 states and 84781 transitions. [2023-11-29 02:55:13,429 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 60208 [2023-11-29 02:55:13,429 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:13,429 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:13,430 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:13,430 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:13,431 INFO L748 eck$LassoCheckResult]: Stem: 3349231#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 3349232#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3350158#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3350159#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3350272#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3350262#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3350263#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3349399#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3349141#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3349142#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3350119#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3350120#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3350096#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3350097#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3350149#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3349191#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3349192#L1006 assume !(0 == ~M_E~0); 3349043#L1006-2 assume !(0 == ~T1_E~0); 3349044#L1011-1 assume !(0 == ~T2_E~0); 3350185#L1016-1 assume !(0 == ~T3_E~0); 3350207#L1021-1 assume !(0 == ~T4_E~0); 3348925#L1026-1 assume !(0 == ~T5_E~0); 3348926#L1031-1 assume !(0 == ~T6_E~0); 3349834#L1036-1 assume !(0 == ~T7_E~0); 3349829#L1041-1 assume !(0 == ~T8_E~0); 3349830#L1046-1 assume !(0 == ~T9_E~0); 3349222#L1051-1 assume !(0 == ~T10_E~0); 3349223#L1056-1 assume !(0 == ~E_1~0); 3349975#L1061-1 assume !(0 == ~E_2~0); 3349143#L1066-1 assume !(0 == ~E_3~0); 3349144#L1071-1 assume !(0 == ~E_4~0); 3349948#L1076-1 assume !(0 == ~E_5~0); 3349048#L1081-1 assume !(0 == ~E_6~0); 3349049#L1086-1 assume !(0 == ~E_7~0); 3349373#L1091-1 assume !(0 == ~E_8~0); 3350172#L1096-1 assume !(0 == ~E_9~0); 3350173#L1101-1 assume !(0 == ~E_10~0); 3349445#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3349446#L484 assume !(1 == ~m_pc~0); 3349101#L484-2 is_master_triggered_~__retres1~0#1 := 0; 3349100#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3349745#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3350062#L1245 assume !(0 != activate_threads_~tmp~1#1); 3350063#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3349821#L503 assume !(1 == ~t1_pc~0); 3349822#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3350017#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3348965#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3348966#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 3348961#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3348962#L522 assume !(1 == ~t2_pc~0); 3349784#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3349159#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3349160#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3349441#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3350121#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3350221#L541 assume !(1 == ~t3_pc~0); 3349511#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3349512#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3348909#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3348910#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3349794#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3349795#L560 assume !(1 == ~t4_pc~0); 3349034#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3349692#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3349064#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3348921#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 3348922#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3349202#L579 assume !(1 == ~t5_pc~0); 3349203#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3348984#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3348985#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3350068#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3350206#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3350243#L598 assume !(1 == ~t6_pc~0); 3349989#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3349615#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3349417#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3349418#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3349871#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3349812#L617 assume !(1 == ~t7_pc~0); 3349262#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3349687#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3350279#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3350136#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 3349482#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3349483#L636 assume !(1 == ~t8_pc~0); 3349867#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3350055#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3350016#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3349882#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3349621#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3349622#L655 assume !(1 == ~t9_pc~0); 3349651#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3349652#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3349526#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3349527#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3349892#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3349893#L674 assume !(1 == ~t10_pc~0); 3349568#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3349569#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3349663#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3349664#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3349609#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3349610#L1119 assume !(1 == ~M_E~0); 3349125#L1119-2 assume !(1 == ~T1_E~0); 3349126#L1124-1 assume !(1 == ~T2_E~0); 3348949#L1129-1 assume !(1 == ~T3_E~0); 3348950#L1134-1 assume !(1 == ~T4_E~0); 3349248#L1139-1 assume !(1 == ~T5_E~0); 3349249#L1144-1 assume !(1 == ~T6_E~0); 3349478#L1149-1 assume !(1 == ~T7_E~0); 3349119#L1154-1 assume !(1 == ~T8_E~0); 3349120#L1159-1 assume !(1 == ~T9_E~0); 3349204#L1164-1 assume !(1 == ~T10_E~0); 3349639#L1169-1 assume !(1 == ~E_1~0); 3349529#L1174-1 assume !(1 == ~E_2~0); 3349300#L1179-1 assume !(1 == ~E_3~0); 3349193#L1184-1 assume !(1 == ~E_4~0); 3349194#L1189-1 assume !(1 == ~E_5~0); 3349246#L1194-1 assume !(1 == ~E_6~0); 3349351#L1199-1 assume !(1 == ~E_7~0); 3349310#L1204-1 assume !(1 == ~E_8~0); 3349311#L1209-1 assume !(1 == ~E_9~0); 3349890#L1214-1 assume !(1 == ~E_10~0); 3349891#L1219-1 assume { :end_inline_reset_delta_events } true; 3350289#L1520-2 [2023-11-29 02:55:13,431 INFO L750 eck$LassoCheckResult]: Loop: 3350289#L1520-2 assume !false; 3354304#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3354301#L981-1 assume !false; 3354299#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3354135#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3354132#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3354128#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3354123#L836 assume !(0 != eval_~tmp~0#1); 3354124#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3362045#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3362043#L1006-3 assume !(0 == ~M_E~0); 3362040#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3362038#L1011-3 assume !(0 == ~T2_E~0); 3362036#L1016-3 assume !(0 == ~T3_E~0); 3362034#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3362032#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3362030#L1031-3 assume !(0 == ~T6_E~0); 3362028#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3362026#L1041-3 assume !(0 == ~T8_E~0); 3362024#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3362022#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3362020#L1056-3 assume !(0 == ~E_1~0); 3362018#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3362016#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3362014#L1071-3 assume !(0 == ~E_4~0); 3362012#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3362010#L1081-3 assume !(0 == ~E_6~0); 3362008#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3362006#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3362003#L1096-3 assume !(0 == ~E_9~0); 3362001#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3361999#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3361997#L484-33 assume !(1 == ~m_pc~0); 3361995#L484-35 is_master_triggered_~__retres1~0#1 := 0; 3361992#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3361990#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3361988#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 3361986#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3361984#L503-33 assume !(1 == ~t1_pc~0); 3361982#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3361978#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3361976#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3361974#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3361972#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3361969#L522-33 assume !(1 == ~t2_pc~0); 3361967#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3361964#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3361962#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3361960#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3361958#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3361956#L541-33 assume !(1 == ~t3_pc~0); 3361954#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3361952#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3361949#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3361947#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3361945#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3361943#L560-33 assume !(1 == ~t4_pc~0); 3361940#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 3361938#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3361935#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3361933#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3361931#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3361929#L579-33 assume !(1 == ~t5_pc~0); 3361927#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3361926#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3361925#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3361921#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3361919#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3361917#L598-33 assume !(1 == ~t6_pc~0); 3361916#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3361913#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3361912#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3361911#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3361910#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3361909#L617-33 assume !(1 == ~t7_pc~0); 3361907#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 3363409#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3363407#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3361900#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 3361897#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3361895#L636-33 assume !(1 == ~t8_pc~0); 3361893#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3361891#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3361889#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3361887#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3361885#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3361882#L655-33 assume 1 == ~t9_pc~0; 3361879#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3361877#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3361874#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3361872#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 3361870#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3361868#L674-33 assume !(1 == ~t10_pc~0); 3361866#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 3361864#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3361862#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3361860#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3361858#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3361857#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3361854#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3361852#L1124-3 assume !(1 == ~T2_E~0); 3361850#L1129-3 assume !(1 == ~T3_E~0); 3361848#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3361846#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3361844#L1144-3 assume !(1 == ~T6_E~0); 3361841#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3361839#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3361837#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3361835#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3361833#L1169-3 assume !(1 == ~E_1~0); 3361832#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3361831#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3361827#L1184-3 assume !(1 == ~E_4~0); 3361825#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3361823#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3361820#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3361544#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3361501#L1209-3 assume !(1 == ~E_9~0); 3361290#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3360768#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3354697#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3354685#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3354683#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3354680#L1539 assume !(0 == start_simulation_~tmp~3#1); 3354677#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3354675#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3354662#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3354660#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3354658#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3354656#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3354654#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3354652#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 3350289#L1520-2 [2023-11-29 02:55:13,431 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:13,431 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 1 times [2023-11-29 02:55:13,431 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:13,432 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1523733537] [2023-11-29 02:55:13,432 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:13,432 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:13,445 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:13,446 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:55:13,458 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:13,552 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:55:13,553 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:13,553 INFO L85 PathProgramCache]: Analyzing trace with hash 1094633019, now seen corresponding path program 1 times [2023-11-29 02:55:13,553 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:13,554 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [882426401] [2023-11-29 02:55:13,554 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:13,554 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:13,571 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:13,601 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:13,601 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:13,602 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [882426401] [2023-11-29 02:55:13,602 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [882426401] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:13,602 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:13,602 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:55:13,602 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1860388291] [2023-11-29 02:55:13,602 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:13,603 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:13,603 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:13,603 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:55:13,603 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:55:13,604 INFO L87 Difference]: Start difference. First operand 60630 states and 84781 transitions. cyclomatic complexity: 24215 Second operand has 3 states, 3 states have (on average 44.0) internal successors, (132), 3 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:13,969 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:13,969 INFO L93 Difference]: Finished difference Result 111892 states and 155485 transitions. [2023-11-29 02:55:13,969 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 111892 states and 155485 transitions. [2023-11-29 02:55:14,713 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 111152 [2023-11-29 02:55:14,911 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 111892 states to 111892 states and 155485 transitions. [2023-11-29 02:55:14,911 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 111892 [2023-11-29 02:55:14,950 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 111892 [2023-11-29 02:55:14,950 INFO L73 IsDeterministic]: Start isDeterministic. Operand 111892 states and 155485 transitions. [2023-11-29 02:55:14,981 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:14,981 INFO L218 hiAutomatonCegarLoop]: Abstraction has 111892 states and 155485 transitions. [2023-11-29 02:55:15,028 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 111892 states and 155485 transitions. [2023-11-29 02:55:15,642 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 111892 to 111860. [2023-11-29 02:55:15,702 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 111860 states, 111860 states have (on average 1.3897103522259968) internal successors, (155453), 111859 states have internal predecessors, (155453), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:16,208 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 111860 states to 111860 states and 155453 transitions. [2023-11-29 02:55:16,208 INFO L240 hiAutomatonCegarLoop]: Abstraction has 111860 states and 155453 transitions. [2023-11-29 02:55:16,208 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:55:16,209 INFO L428 stractBuchiCegarLoop]: Abstraction has 111860 states and 155453 transitions. [2023-11-29 02:55:16,209 INFO L335 stractBuchiCegarLoop]: ======== Iteration 26 ============ [2023-11-29 02:55:16,209 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 111860 states and 155453 transitions. [2023-11-29 02:55:16,422 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 111120 [2023-11-29 02:55:16,422 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:16,422 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:16,424 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:16,424 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:16,424 INFO L748 eck$LassoCheckResult]: Stem: 3521761#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 3521762#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3522700#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3522701#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3522827#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3522817#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3522818#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3521923#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3521670#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3521671#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3522667#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3522668#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3522646#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3522647#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3522693#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3521719#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3521720#L1006 assume !(0 == ~M_E~0); 3521570#L1006-2 assume !(0 == ~T1_E~0); 3521571#L1011-1 assume !(0 == ~T2_E~0); 3522730#L1016-1 assume !(0 == ~T3_E~0); 3522757#L1021-1 assume !(0 == ~T4_E~0); 3521452#L1026-1 assume !(0 == ~T5_E~0); 3521453#L1031-1 assume !(0 == ~T6_E~0); 3522363#L1036-1 assume !(0 == ~T7_E~0); 3522360#L1041-1 assume !(0 == ~T8_E~0); 3522361#L1046-1 assume !(0 == ~T9_E~0); 3521752#L1051-1 assume !(0 == ~T10_E~0); 3521753#L1056-1 assume !(0 == ~E_1~0); 3522508#L1061-1 assume !(0 == ~E_2~0); 3521674#L1066-1 assume !(0 == ~E_3~0); 3521675#L1071-1 assume !(0 == ~E_4~0); 3522483#L1076-1 assume !(0 == ~E_5~0); 3521578#L1081-1 assume !(0 == ~E_6~0); 3521579#L1086-1 assume !(0 == ~E_7~0); 3521897#L1091-1 assume !(0 == ~E_8~0); 3522710#L1096-1 assume !(0 == ~E_9~0); 3522711#L1101-1 assume !(0 == ~E_10~0); 3521972#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3521973#L484 assume !(1 == ~m_pc~0); 3521629#L484-2 is_master_triggered_~__retres1~0#1 := 0; 3521628#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3522274#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3522604#L1245 assume !(0 != activate_threads_~tmp~1#1); 3522605#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3522352#L503 assume !(1 == ~t1_pc~0); 3522353#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3522545#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3521492#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3521493#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 3521488#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3521489#L522 assume !(1 == ~t2_pc~0); 3522316#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3521685#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3521686#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3521967#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3522669#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3522774#L541 assume !(1 == ~t3_pc~0); 3522039#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3522040#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3521436#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3521437#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3522322#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3522323#L560 assume !(1 == ~t4_pc~0); 3521562#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3522223#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3521594#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3521450#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 3521451#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3521730#L579 assume !(1 == ~t5_pc~0); 3521731#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3521513#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3521514#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3522609#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3522755#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3522794#L598 assume !(1 == ~t6_pc~0); 3522522#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3522141#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3521940#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3521941#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3522401#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3522343#L617 assume !(1 == ~t7_pc~0); 3521792#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3522218#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3522830#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3522683#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 3522007#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3522008#L636 assume !(1 == ~t8_pc~0); 3522397#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3522597#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3522546#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3522409#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3522148#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3522149#L655 assume !(1 == ~t9_pc~0); 3522178#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3522580#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3522050#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3522051#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3522421#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3522422#L674 assume !(1 == ~t10_pc~0); 3522098#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3522099#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3522872#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3522853#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3522138#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3522139#L1119 assume !(1 == ~M_E~0); 3521655#L1119-2 assume !(1 == ~T1_E~0); 3521656#L1124-1 assume !(1 == ~T2_E~0); 3522062#L1129-1 assume !(1 == ~T3_E~0); 3522333#L1134-1 assume !(1 == ~T4_E~0); 3521777#L1139-1 assume !(1 == ~T5_E~0); 3521778#L1144-1 assume !(1 == ~T6_E~0); 3522842#L1149-1 assume !(1 == ~T7_E~0); 3521649#L1154-1 assume !(1 == ~T8_E~0); 3521650#L1159-1 assume !(1 == ~T9_E~0); 3521734#L1164-1 assume !(1 == ~T10_E~0); 3522864#L1169-1 assume !(1 == ~E_1~0); 3522863#L1174-1 assume !(1 == ~E_2~0); 3522862#L1179-1 assume !(1 == ~E_3~0); 3522861#L1184-1 assume !(1 == ~E_4~0); 3522860#L1189-1 assume !(1 == ~E_5~0); 3522859#L1194-1 assume !(1 == ~E_6~0); 3522858#L1199-1 assume !(1 == ~E_7~0); 3522857#L1204-1 assume !(1 == ~E_8~0); 3522855#L1209-1 assume !(1 == ~E_9~0); 3522419#L1214-1 assume !(1 == ~E_10~0); 3522420#L1219-1 assume { :end_inline_reset_delta_events } true; 3522839#L1520-2 [2023-11-29 02:55:16,424 INFO L750 eck$LassoCheckResult]: Loop: 3522839#L1520-2 assume !false; 3532018#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3532015#L981-1 assume !false; 3532013#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3531992#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3531988#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3531986#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3531983#L836 assume !(0 != eval_~tmp~0#1); 3531984#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3533201#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3533199#L1006-3 assume !(0 == ~M_E~0); 3533197#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3533195#L1011-3 assume !(0 == ~T2_E~0); 3533193#L1016-3 assume !(0 == ~T3_E~0); 3533191#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3533189#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3533187#L1031-3 assume !(0 == ~T6_E~0); 3533185#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3533182#L1041-3 assume !(0 == ~T8_E~0); 3533180#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3533178#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3533176#L1056-3 assume !(0 == ~E_1~0); 3533174#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3533172#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3533170#L1071-3 assume !(0 == ~E_4~0); 3533168#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3533166#L1081-3 assume !(0 == ~E_6~0); 3533164#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3533162#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3533161#L1096-3 assume !(0 == ~E_9~0); 3533158#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3533156#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3533154#L484-33 assume !(1 == ~m_pc~0); 3533152#L484-35 is_master_triggered_~__retres1~0#1 := 0; 3533149#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3533147#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3533145#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 3533143#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3533141#L503-33 assume !(1 == ~t1_pc~0); 3533139#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3533137#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3533135#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3533133#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3533131#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3533129#L522-33 assume !(1 == ~t2_pc~0); 3533127#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3533124#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3533122#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3533120#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3533117#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3533115#L541-33 assume !(1 == ~t3_pc~0); 3533113#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3533110#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3533108#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3533106#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3533104#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3533102#L560-33 assume !(1 == ~t4_pc~0); 3533099#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 3533097#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3533095#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3533091#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3533089#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3533087#L579-33 assume !(1 == ~t5_pc~0); 3533085#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3533083#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3533081#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3533079#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3533077#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3533075#L598-33 assume !(1 == ~t6_pc~0); 3533073#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3533071#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3533069#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3533068#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3533067#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3533066#L617-33 assume !(1 == ~t7_pc~0); 3533063#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 3533061#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3533060#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3533059#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 3533056#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3533054#L636-33 assume !(1 == ~t8_pc~0); 3533052#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3533050#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3533048#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3533046#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3533044#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3533042#L655-33 assume 1 == ~t9_pc~0; 3533041#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 3532328#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3532326#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3532322#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 3532320#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3532318#L674-33 assume !(1 == ~t10_pc~0); 3532316#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 3532314#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3532312#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3532310#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3532308#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3532306#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3532304#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3532302#L1124-3 assume !(1 == ~T2_E~0); 3532300#L1129-3 assume !(1 == ~T3_E~0); 3532298#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3532296#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3532294#L1144-3 assume !(1 == ~T6_E~0); 3532292#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3532290#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3532288#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3532286#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3532284#L1169-3 assume !(1 == ~E_1~0); 3532282#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3532280#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3532278#L1184-3 assume !(1 == ~E_4~0); 3532276#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3532274#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3532272#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3532270#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3532268#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 3532265#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3532263#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3532261#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3532248#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3532246#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3532244#L1539 assume !(0 == start_simulation_~tmp~3#1); 3532242#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3532238#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3532226#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3532224#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3532221#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3532220#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3532219#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3532217#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 3522839#L1520-2 [2023-11-29 02:55:16,424 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:16,425 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 2 times [2023-11-29 02:55:16,425 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:16,425 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [63820017] [2023-11-29 02:55:16,425 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:16,425 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:16,436 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:16,436 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:55:16,444 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:16,496 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:55:16,497 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:16,497 INFO L85 PathProgramCache]: Analyzing trace with hash -1920470599, now seen corresponding path program 1 times [2023-11-29 02:55:16,497 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:16,497 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1008032008] [2023-11-29 02:55:16,497 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:16,497 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:16,511 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:16,558 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:16,558 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:16,558 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1008032008] [2023-11-29 02:55:16,559 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1008032008] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:16,559 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:16,559 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:55:16,559 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [824147925] [2023-11-29 02:55:16,559 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:16,559 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:16,559 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:16,560 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:55:16,560 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:55:16,560 INFO L87 Difference]: Start difference. First operand 111860 states and 155453 transitions. cyclomatic complexity: 43657 Second operand has 5 states, 5 states have (on average 26.4) internal successors, (132), 5 states have internal predecessors, (132), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:17,141 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:17,141 INFO L93 Difference]: Finished difference Result 207172 states and 285389 transitions. [2023-11-29 02:55:17,141 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 207172 states and 285389 transitions. [2023-11-29 02:55:18,142 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 205856 [2023-11-29 02:55:18,515 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 207172 states to 207172 states and 285389 transitions. [2023-11-29 02:55:18,515 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 207172 [2023-11-29 02:55:18,613 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 207172 [2023-11-29 02:55:18,614 INFO L73 IsDeterministic]: Start isDeterministic. Operand 207172 states and 285389 transitions. [2023-11-29 02:55:18,684 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:18,685 INFO L218 hiAutomatonCegarLoop]: Abstraction has 207172 states and 285389 transitions. [2023-11-29 02:55:18,788 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 207172 states and 285389 transitions. [2023-11-29 02:55:19,911 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 207172 to 112244. [2023-11-29 02:55:19,970 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 112244 states, 112244 states have (on average 1.3883771070168562) internal successors, (155837), 112243 states have internal predecessors, (155837), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:20,135 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 112244 states to 112244 states and 155837 transitions. [2023-11-29 02:55:20,135 INFO L240 hiAutomatonCegarLoop]: Abstraction has 112244 states and 155837 transitions. [2023-11-29 02:55:20,136 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 9 states. [2023-11-29 02:55:20,136 INFO L428 stractBuchiCegarLoop]: Abstraction has 112244 states and 155837 transitions. [2023-11-29 02:55:20,136 INFO L335 stractBuchiCegarLoop]: ======== Iteration 27 ============ [2023-11-29 02:55:20,136 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 112244 states and 155837 transitions. [2023-11-29 02:55:20,388 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 111504 [2023-11-29 02:55:20,388 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:20,388 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:20,389 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:20,389 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:20,390 INFO L748 eck$LassoCheckResult]: Stem: 3840811#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 3840812#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 3841825#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 3841826#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 3841984#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 3841972#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 3841973#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 3840980#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 3840722#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 3840723#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 3841778#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 3841779#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 3841751#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 3841752#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 3841813#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 3840773#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 3840774#L1006 assume !(0 == ~M_E~0); 3840624#L1006-2 assume !(0 == ~T1_E~0); 3840625#L1011-1 assume !(0 == ~T2_E~0); 3841863#L1016-1 assume !(0 == ~T3_E~0); 3841897#L1021-1 assume !(0 == ~T4_E~0); 3840502#L1026-1 assume !(0 == ~T5_E~0); 3840503#L1031-1 assume !(0 == ~T6_E~0); 3841433#L1036-1 assume !(0 == ~T7_E~0); 3841428#L1041-1 assume !(0 == ~T8_E~0); 3841429#L1046-1 assume !(0 == ~T9_E~0); 3840802#L1051-1 assume !(0 == ~T10_E~0); 3840803#L1056-1 assume !(0 == ~E_1~0); 3841596#L1061-1 assume !(0 == ~E_2~0); 3840724#L1066-1 assume !(0 == ~E_3~0); 3840725#L1071-1 assume !(0 == ~E_4~0); 3841565#L1076-1 assume !(0 == ~E_5~0); 3840629#L1081-1 assume !(0 == ~E_6~0); 3840630#L1086-1 assume !(0 == ~E_7~0); 3840954#L1091-1 assume !(0 == ~E_8~0); 3841838#L1096-1 assume !(0 == ~E_9~0); 3841839#L1101-1 assume !(0 == ~E_10~0); 3841026#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3841027#L484 assume !(1 == ~m_pc~0); 3840682#L484-2 is_master_triggered_~__retres1~0#1 := 0; 3840681#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3841335#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3841698#L1245 assume !(0 != activate_threads_~tmp~1#1); 3841699#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3841419#L503 assume !(1 == ~t1_pc~0); 3841420#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 3841641#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3840542#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3840543#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 3840538#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3840539#L522 assume !(1 == ~t2_pc~0); 3841381#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 3840741#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3840742#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3841021#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 3841777#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3841912#L541 assume !(1 == ~t3_pc~0); 3841093#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 3841094#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3840486#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3840487#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 3841391#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3841392#L560 assume !(1 == ~t4_pc~0); 3840615#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 3841280#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3840644#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3840498#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 3840499#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3840784#L579 assume !(1 == ~t5_pc~0); 3840785#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 3840561#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3840562#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3841705#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 3841896#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3841938#L598 assume !(1 == ~t6_pc~0); 3841611#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 3841202#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3840996#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3840997#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 3841474#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3841410#L617 assume !(1 == ~t7_pc~0); 3840847#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 3841277#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3841992#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3841797#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 3841064#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3841065#L636 assume !(1 == ~t8_pc~0); 3841470#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 3841689#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3841642#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3841487#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 3841208#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3841209#L655 assume !(1 == ~t9_pc~0); 3841238#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 3841672#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3841109#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3841110#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 3841498#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3841499#L674 assume !(1 == ~t10_pc~0); 3841152#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 3841153#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3842057#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3842038#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 3841196#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3841197#L1119 assume !(1 == ~M_E~0); 3840706#L1119-2 assume !(1 == ~T1_E~0); 3840707#L1124-1 assume !(1 == ~T2_E~0); 3841120#L1129-1 assume !(1 == ~T3_E~0); 3841399#L1134-1 assume !(1 == ~T4_E~0); 3840829#L1139-1 assume !(1 == ~T5_E~0); 3840830#L1144-1 assume !(1 == ~T6_E~0); 3842020#L1149-1 assume !(1 == ~T7_E~0); 3840700#L1154-1 assume !(1 == ~T8_E~0); 3840701#L1159-1 assume !(1 == ~T9_E~0); 3840786#L1164-1 assume !(1 == ~T10_E~0); 3842049#L1169-1 assume !(1 == ~E_1~0); 3842048#L1174-1 assume !(1 == ~E_2~0); 3842047#L1179-1 assume !(1 == ~E_3~0); 3842046#L1184-1 assume !(1 == ~E_4~0); 3842045#L1189-1 assume !(1 == ~E_5~0); 3842044#L1194-1 assume !(1 == ~E_6~0); 3842043#L1199-1 assume !(1 == ~E_7~0); 3842042#L1204-1 assume !(1 == ~E_8~0); 3842040#L1209-1 assume !(1 == ~E_9~0); 3841496#L1214-1 assume !(1 == ~E_10~0); 3841497#L1219-1 assume { :end_inline_reset_delta_events } true; 3842009#L1520-2 [2023-11-29 02:55:20,390 INFO L750 eck$LassoCheckResult]: Loop: 3842009#L1520-2 assume !false; 3885341#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 3885339#L981-1 assume !false; 3885291#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3885225#L764 assume !(0 == ~m_st~0); 3885226#L768 assume !(0 == ~t1_st~0); 3885232#L772 assume !(0 == ~t2_st~0); 3885223#L776 assume !(0 == ~t3_st~0); 3885224#L780 assume !(0 == ~t4_st~0); 3885231#L784 assume !(0 == ~t5_st~0); 3885234#L788 assume !(0 == ~t6_st~0); 3885229#L792 assume !(0 == ~t7_st~0); 3885230#L796 assume !(0 == ~t8_st~0); 3885233#L800 assume !(0 == ~t9_st~0); 3885227#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 3885228#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3851719#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 3851720#L836 assume !(0 != eval_~tmp~0#1); 3885663#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 3885661#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 3885659#L1006-3 assume !(0 == ~M_E~0); 3885657#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 3885655#L1011-3 assume !(0 == ~T2_E~0); 3885653#L1016-3 assume !(0 == ~T3_E~0); 3885651#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 3885649#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 3885647#L1031-3 assume !(0 == ~T6_E~0); 3885645#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 3885643#L1041-3 assume !(0 == ~T8_E~0); 3885641#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 3885639#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 3885637#L1056-3 assume !(0 == ~E_1~0); 3885635#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 3885633#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 3885631#L1071-3 assume !(0 == ~E_4~0); 3885629#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 3885627#L1081-3 assume !(0 == ~E_6~0); 3885625#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 3885623#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 3885621#L1096-3 assume !(0 == ~E_9~0); 3885619#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 3885617#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 3885615#L484-33 assume 1 == ~m_pc~0; 3885611#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 3885609#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 3885607#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 3885605#L1245-33 assume !(0 != activate_threads_~tmp~1#1); 3885603#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 3885601#L503-33 assume !(1 == ~t1_pc~0); 3885599#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 3885597#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 3885595#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 3885593#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 3885591#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 3885589#L522-33 assume !(1 == ~t2_pc~0); 3885586#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 3885583#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 3885581#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 3885579#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 3885577#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 3885575#L541-33 assume !(1 == ~t3_pc~0); 3885573#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 3885571#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 3885569#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 3885567#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 3885565#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 3885562#L560-33 assume !(1 == ~t4_pc~0); 3885559#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 3885557#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 3885555#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 3885553#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 3885551#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 3885549#L579-33 assume !(1 == ~t5_pc~0); 3885547#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 3885545#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 3885543#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 3885541#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 3885539#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 3885537#L598-33 assume !(1 == ~t6_pc~0); 3885535#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 3885533#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 3885531#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 3885529#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 3885527#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 3885525#L617-33 assume !(1 == ~t7_pc~0); 3885522#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 3885518#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 3885514#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 3885510#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 3885507#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 3885505#L636-33 assume !(1 == ~t8_pc~0); 3885503#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 3885501#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 3885499#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 3885497#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 3885495#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 3885493#L655-33 assume !(1 == ~t9_pc~0); 3885489#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 3885487#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 3885485#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 3885483#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 3885481#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 3885479#L674-33 assume !(1 == ~t10_pc~0); 3885477#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 3885475#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 3885473#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 3885471#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 3885469#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 3885467#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 3885465#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 3885463#L1124-3 assume !(1 == ~T2_E~0); 3885461#L1129-3 assume !(1 == ~T3_E~0); 3885459#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 3885457#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 3885455#L1144-3 assume !(1 == ~T6_E~0); 3885453#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 3885451#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 3885449#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 3885447#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 3885445#L1169-3 assume !(1 == ~E_1~0); 3885443#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 3885441#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 3885439#L1184-3 assume !(1 == ~E_4~0); 3885437#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 3885435#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 3885433#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 3885431#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 3885429#L1209-3 assume !(1 == ~E_9~0); 3885428#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 3885427#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3885426#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3885414#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3885412#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 3885409#L1539 assume !(0 == start_simulation_~tmp~3#1); 3885407#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 3885406#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 3885392#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 3885390#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 3885388#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 3885385#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 3885384#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 3885383#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 3842009#L1520-2 [2023-11-29 02:55:20,390 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:20,390 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 3 times [2023-11-29 02:55:20,391 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:20,391 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1338771975] [2023-11-29 02:55:20,391 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:20,391 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:20,401 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:20,401 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:55:20,406 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:20,439 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:55:20,440 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:20,440 INFO L85 PathProgramCache]: Analyzing trace with hash 700319872, now seen corresponding path program 1 times [2023-11-29 02:55:20,440 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:20,440 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [789744884] [2023-11-29 02:55:20,441 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:20,441 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:20,449 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:20,472 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:20,472 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:20,472 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [789744884] [2023-11-29 02:55:20,472 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [789744884] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:20,472 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:20,472 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:55:20,472 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1858453947] [2023-11-29 02:55:20,472 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:20,473 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:20,473 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:20,473 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:55:20,473 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:55:20,473 INFO L87 Difference]: Start difference. First operand 112244 states and 155837 transitions. cyclomatic complexity: 43657 Second operand has 3 states, 3 states have (on average 47.333333333333336) internal successors, (142), 3 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:21,270 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:21,270 INFO L93 Difference]: Finished difference Result 216004 states and 296973 transitions. [2023-11-29 02:55:21,271 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 216004 states and 296973 transitions. [2023-11-29 02:55:21,887 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 214688 [2023-11-29 02:55:22,236 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 216004 states to 216004 states and 296973 transitions. [2023-11-29 02:55:22,236 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 216004 [2023-11-29 02:55:22,311 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 216004 [2023-11-29 02:55:22,311 INFO L73 IsDeterministic]: Start isDeterministic. Operand 216004 states and 296973 transitions. [2023-11-29 02:55:22,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:22,369 INFO L218 hiAutomatonCegarLoop]: Abstraction has 216004 states and 296973 transitions. [2023-11-29 02:55:22,457 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 216004 states and 296973 transitions. [2023-11-29 02:55:24,104 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 216004 to 206532. [2023-11-29 02:55:24,185 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 206532 states, 206532 states have (on average 1.3780963724749675) internal successors, (284621), 206531 states have internal predecessors, (284621), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:24,518 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 206532 states to 206532 states and 284621 transitions. [2023-11-29 02:55:24,519 INFO L240 hiAutomatonCegarLoop]: Abstraction has 206532 states and 284621 transitions. [2023-11-29 02:55:24,519 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:55:24,519 INFO L428 stractBuchiCegarLoop]: Abstraction has 206532 states and 284621 transitions. [2023-11-29 02:55:24,520 INFO L335 stractBuchiCegarLoop]: ======== Iteration 28 ============ [2023-11-29 02:55:24,520 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 206532 states and 284621 transitions. [2023-11-29 02:55:24,977 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 205216 [2023-11-29 02:55:24,977 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:24,977 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:24,979 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:24,979 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:24,979 INFO L748 eck$LassoCheckResult]: Stem: 4169065#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 4169066#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4170005#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4170006#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4170118#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 4170109#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4170110#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4169229#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4168973#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4168974#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4169967#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4169968#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4169945#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4169946#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4169996#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4169023#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4169024#L1006 assume !(0 == ~M_E~0); 4168875#L1006-2 assume !(0 == ~T1_E~0); 4168876#L1011-1 assume !(0 == ~T2_E~0); 4170035#L1016-1 assume !(0 == ~T3_E~0); 4170059#L1021-1 assume !(0 == ~T4_E~0); 4168756#L1026-1 assume !(0 == ~T5_E~0); 4168757#L1031-1 assume !(0 == ~T6_E~0); 4169671#L1036-1 assume !(0 == ~T7_E~0); 4169667#L1041-1 assume !(0 == ~T8_E~0); 4169668#L1046-1 assume !(0 == ~T9_E~0); 4169056#L1051-1 assume !(0 == ~T10_E~0); 4169057#L1056-1 assume !(0 == ~E_1~0); 4169811#L1061-1 assume !(0 == ~E_2~0); 4168977#L1066-1 assume !(0 == ~E_3~0); 4168978#L1071-1 assume !(0 == ~E_4~0); 4169784#L1076-1 assume !(0 == ~E_5~0); 4168883#L1081-1 assume !(0 == ~E_6~0); 4168884#L1086-1 assume !(0 == ~E_7~0); 4169203#L1091-1 assume !(0 == ~E_8~0); 4170015#L1096-1 assume !(0 == ~E_9~0); 4170016#L1101-1 assume !(0 == ~E_10~0); 4169275#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4169276#L484 assume !(1 == ~m_pc~0); 4168933#L484-2 is_master_triggered_~__retres1~0#1 := 0; 4168932#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4169578#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4169906#L1245 assume !(0 != activate_threads_~tmp~1#1); 4169907#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4169658#L503 assume !(1 == ~t1_pc~0); 4169659#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4169849#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4168796#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4168797#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 4168792#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4168793#L522 assume !(1 == ~t2_pc~0); 4169621#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4168988#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4168989#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4169270#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 4169966#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4170073#L541 assume !(1 == ~t3_pc~0); 4169342#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4169343#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4168739#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4168740#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 4169627#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4169628#L560 assume !(1 == ~t4_pc~0); 4168867#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4169527#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4168899#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4168754#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 4168755#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4169034#L579 assume !(1 == ~t5_pc~0); 4169035#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4168818#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4168819#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4169913#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 4170057#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4170091#L598 assume !(1 == ~t6_pc~0); 4169822#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4169445#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4169245#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4169246#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 4169712#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4169648#L617 assume !(1 == ~t7_pc~0); 4169098#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4169522#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4170121#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4169984#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 4169310#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4169311#L636 assume !(1 == ~t8_pc~0); 4169708#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4169898#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4169850#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4169720#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 4169452#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4169453#L655 assume !(1 == ~t9_pc~0); 4169482#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4169882#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4169353#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4169354#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 4169732#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4169733#L674 assume !(1 == ~t10_pc~0); 4169401#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4169402#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4170161#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4170142#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 4169442#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4169443#L1119 assume !(1 == ~M_E~0); 4168959#L1119-2 assume !(1 == ~T1_E~0); 4168960#L1124-1 assume !(1 == ~T2_E~0); 4169366#L1129-1 assume !(1 == ~T3_E~0); 4169638#L1134-1 assume !(1 == ~T4_E~0); 4169081#L1139-1 assume !(1 == ~T5_E~0); 4169082#L1144-1 assume !(1 == ~T6_E~0); 4170133#L1149-1 assume !(1 == ~T7_E~0); 4168953#L1154-1 assume !(1 == ~T8_E~0); 4168954#L1159-1 assume !(1 == ~T9_E~0); 4169038#L1164-1 assume !(1 == ~T10_E~0); 4170153#L1169-1 assume !(1 == ~E_1~0); 4170152#L1174-1 assume !(1 == ~E_2~0); 4170151#L1179-1 assume !(1 == ~E_3~0); 4170150#L1184-1 assume !(1 == ~E_4~0); 4170149#L1189-1 assume !(1 == ~E_5~0); 4170148#L1194-1 assume !(1 == ~E_6~0); 4170147#L1199-1 assume !(1 == ~E_7~0); 4170146#L1204-1 assume !(1 == ~E_8~0); 4170144#L1209-1 assume !(1 == ~E_9~0); 4169730#L1214-1 assume !(1 == ~E_10~0); 4169731#L1219-1 assume { :end_inline_reset_delta_events } true; 4170126#L1520-2 [2023-11-29 02:55:24,979 INFO L750 eck$LassoCheckResult]: Loop: 4170126#L1520-2 assume !false; 4175260#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4175257#L981-1 assume !false; 4175256#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4175251#L764 assume !(0 == ~m_st~0); 4175252#L768 assume !(0 == ~t1_st~0); 4179355#L772 assume !(0 == ~t2_st~0); 4179353#L776 assume !(0 == ~t3_st~0); 4179351#L780 assume !(0 == ~t4_st~0); 4179349#L784 assume !(0 == ~t5_st~0); 4179347#L788 assume !(0 == ~t6_st~0); 4179345#L792 assume !(0 == ~t7_st~0); 4179343#L796 assume !(0 == ~t8_st~0); 4179341#L800 assume !(0 == ~t9_st~0); 4179338#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 4179335#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4179333#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4179330#L836 assume !(0 != eval_~tmp~0#1); 4179328#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4179326#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4179324#L1006-3 assume !(0 == ~M_E~0); 4179322#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4179320#L1011-3 assume !(0 == ~T2_E~0); 4179318#L1016-3 assume !(0 == ~T3_E~0); 4179316#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4179314#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4179313#L1031-3 assume !(0 == ~T6_E~0); 4179310#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4179308#L1041-3 assume !(0 == ~T8_E~0); 4179306#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4179304#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4179302#L1056-3 assume !(0 == ~E_1~0); 4179300#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4179298#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4179296#L1071-3 assume !(0 == ~E_4~0); 4179294#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4179292#L1081-3 assume !(0 == ~E_6~0); 4179290#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4179288#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4179286#L1096-3 assume !(0 == ~E_9~0); 4179284#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4179282#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4179280#L484-33 assume !(1 == ~m_pc~0); 4179278#L484-35 is_master_triggered_~__retres1~0#1 := 0; 4179275#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4179273#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4179269#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4179267#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4179265#L503-33 assume !(1 == ~t1_pc~0); 4179262#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 4179260#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4179258#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4179256#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4179254#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4179252#L522-33 assume !(1 == ~t2_pc~0); 4179250#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 4179247#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4179243#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4179241#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4179239#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4179237#L541-33 assume !(1 == ~t3_pc~0); 4179235#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 4179233#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4179231#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4179229#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4179227#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4179225#L560-33 assume !(1 == ~t4_pc~0); 4179222#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 4179220#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4179218#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4179216#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4179214#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4179212#L579-33 assume !(1 == ~t5_pc~0); 4179210#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 4179208#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4179206#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4179204#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4179202#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4179200#L598-33 assume !(1 == ~t6_pc~0); 4179198#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 4179196#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4179194#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4179192#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4179190#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4179188#L617-33 assume 1 == ~t7_pc~0; 4179186#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 4179187#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4179912#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4179176#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 4179174#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4179173#L636-33 assume !(1 == ~t8_pc~0); 4179172#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 4179171#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4179170#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4179169#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4179168#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4179166#L655-33 assume 1 == ~t9_pc~0; 4179165#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4175913#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4175911#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4175909#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 4175907#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4175905#L674-33 assume !(1 == ~t10_pc~0); 4175903#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 4175901#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4175899#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4175897#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4175895#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4175893#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4175891#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4175889#L1124-3 assume !(1 == ~T2_E~0); 4175887#L1129-3 assume !(1 == ~T3_E~0); 4175885#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4175881#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4175879#L1144-3 assume !(1 == ~T6_E~0); 4175877#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4175875#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4175872#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4175870#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4175868#L1169-3 assume !(1 == ~E_1~0); 4175866#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4175864#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4175862#L1184-3 assume !(1 == ~E_4~0); 4175860#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4175858#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4175857#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4175853#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4175851#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4175848#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4175846#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4175843#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4175841#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4175839#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 4175836#L1539 assume !(0 == start_simulation_~tmp~3#1); 4175833#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4175830#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4175828#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4175826#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 4175824#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4175823#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4175821#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 4175819#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 4170126#L1520-2 [2023-11-29 02:55:24,980 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:24,980 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 4 times [2023-11-29 02:55:24,980 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:24,980 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [285212861] [2023-11-29 02:55:24,980 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:24,980 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:24,991 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:24,991 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:55:24,999 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:25,040 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:55:25,041 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:25,041 INFO L85 PathProgramCache]: Analyzing trace with hash -687476253, now seen corresponding path program 1 times [2023-11-29 02:55:25,041 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:25,041 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1102768593] [2023-11-29 02:55:25,041 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:25,041 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:25,053 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:25,105 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:25,106 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:25,106 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1102768593] [2023-11-29 02:55:25,106 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1102768593] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:25,106 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:25,106 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:55:25,106 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1339714656] [2023-11-29 02:55:25,106 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:25,107 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:25,107 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:25,107 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:55:25,107 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:55:25,108 INFO L87 Difference]: Start difference. First operand 206532 states and 284621 transitions. cyclomatic complexity: 78153 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:26,645 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:26,646 INFO L93 Difference]: Finished difference Result 385286 states and 526991 transitions. [2023-11-29 02:55:26,646 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 385286 states and 526991 transitions. [2023-11-29 02:55:28,225 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 382816 [2023-11-29 02:55:28,788 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 385286 states to 385286 states and 526991 transitions. [2023-11-29 02:55:28,788 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 385286 [2023-11-29 02:55:28,901 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 385286 [2023-11-29 02:55:28,901 INFO L73 IsDeterministic]: Start isDeterministic. Operand 385286 states and 526991 transitions. [2023-11-29 02:55:29,396 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:29,396 INFO L218 hiAutomatonCegarLoop]: Abstraction has 385286 states and 526991 transitions. [2023-11-29 02:55:29,532 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 385286 states and 526991 transitions. [2023-11-29 02:55:31,184 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 385286 to 209604. [2023-11-29 02:55:31,297 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 209604 states, 209604 states have (on average 1.3719394668040685) internal successors, (287564), 209603 states have internal predecessors, (287564), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:31,629 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 209604 states to 209604 states and 287564 transitions. [2023-11-29 02:55:31,629 INFO L240 hiAutomatonCegarLoop]: Abstraction has 209604 states and 287564 transitions. [2023-11-29 02:55:31,629 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 6 states. [2023-11-29 02:55:31,630 INFO L428 stractBuchiCegarLoop]: Abstraction has 209604 states and 287564 transitions. [2023-11-29 02:55:31,630 INFO L335 stractBuchiCegarLoop]: ======== Iteration 29 ============ [2023-11-29 02:55:31,630 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 209604 states and 287564 transitions. [2023-11-29 02:55:32,487 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 208288 [2023-11-29 02:55:32,487 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:32,487 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:32,489 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:32,489 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:32,490 INFO L748 eck$LassoCheckResult]: Stem: 4760894#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 4760895#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 4761866#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 4761867#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 4762002#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 4761992#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 4761993#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 4761059#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 4760808#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 4760809#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 4761830#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 4761831#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 4761808#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 4761809#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 4761858#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 4760854#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 4760855#L1006 assume !(0 == ~M_E~0); 4760709#L1006-2 assume !(0 == ~T1_E~0); 4760710#L1011-1 assume !(0 == ~T2_E~0); 4761898#L1016-1 assume !(0 == ~T3_E~0); 4761927#L1021-1 assume !(0 == ~T4_E~0); 4760586#L1026-1 assume !(0 == ~T5_E~0); 4760587#L1031-1 assume !(0 == ~T6_E~0); 4761510#L1036-1 assume !(0 == ~T7_E~0); 4761504#L1041-1 assume !(0 == ~T8_E~0); 4761505#L1046-1 assume !(0 == ~T9_E~0); 4760885#L1051-1 assume !(0 == ~T10_E~0); 4760886#L1056-1 assume !(0 == ~E_1~0); 4761669#L1061-1 assume !(0 == ~E_2~0); 4760810#L1066-1 assume !(0 == ~E_3~0); 4760811#L1071-1 assume !(0 == ~E_4~0); 4761639#L1076-1 assume !(0 == ~E_5~0); 4760715#L1081-1 assume !(0 == ~E_6~0); 4760716#L1086-1 assume !(0 == ~E_7~0); 4761033#L1091-1 assume !(0 == ~E_8~0); 4761883#L1096-1 assume !(0 == ~E_9~0); 4761884#L1101-1 assume !(0 == ~E_10~0); 4761105#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4761106#L484 assume !(1 == ~m_pc~0); 4760768#L484-2 is_master_triggered_~__retres1~0#1 := 0; 4760767#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4761413#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4761771#L1245 assume !(0 != activate_threads_~tmp~1#1); 4761772#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4761496#L503 assume !(1 == ~t1_pc~0); 4761497#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 4761710#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4760627#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4760628#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 4760625#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4760626#L522 assume !(1 == ~t2_pc~0); 4761457#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 4760822#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4760823#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4761101#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 4761832#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4761948#L541 assume !(1 == ~t3_pc~0); 4761172#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 4761173#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4760571#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4760572#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 4761463#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4761464#L560 assume !(1 == ~t4_pc~0); 4760701#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 4761360#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4760731#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4760584#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 4760585#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4760867#L579 assume !(1 == ~t5_pc~0); 4760868#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 4760651#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4760652#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4761776#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 4761926#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4761969#L598 assume !(1 == ~t6_pc~0); 4761686#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 4761278#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4761073#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4761074#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 4761548#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4761487#L617 assume !(1 == ~t7_pc~0); 4760925#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 4761357#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4762005#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4761845#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 4761140#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4761141#L636 assume !(1 == ~t8_pc~0); 4761545#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 4761763#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4761711#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4761561#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 4761285#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4761286#L655 assume !(1 == ~t9_pc~0); 4761316#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 4761744#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4761185#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4761186#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 4762060#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4762075#L674 assume !(1 == ~t10_pc~0); 4761232#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 4761233#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4762074#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4762057#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 4761273#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4761274#L1119 assume !(1 == ~M_E~0); 4760792#L1119-2 assume !(1 == ~T1_E~0); 4760793#L1124-1 assume !(1 == ~T2_E~0); 4760613#L1129-1 assume !(1 == ~T3_E~0); 4760614#L1134-1 assume !(1 == ~T4_E~0); 4762070#L1139-1 assume !(1 == ~T5_E~0); 4761134#L1144-1 assume !(1 == ~T6_E~0); 4761135#L1149-1 assume !(1 == ~T7_E~0); 4762069#L1154-1 assume !(1 == ~T8_E~0); 4760869#L1159-1 assume !(1 == ~T9_E~0); 4760870#L1164-1 assume !(1 == ~T10_E~0); 4762068#L1169-1 assume !(1 == ~E_1~0); 4762067#L1174-1 assume !(1 == ~E_2~0); 4762066#L1179-1 assume !(1 == ~E_3~0); 4760858#L1184-1 assume !(1 == ~E_4~0); 4760859#L1189-1 assume !(1 == ~E_5~0); 4760909#L1194-1 assume !(1 == ~E_6~0); 4761010#L1199-1 assume !(1 == ~E_7~0); 4760970#L1204-1 assume !(1 == ~E_8~0); 4760971#L1209-1 assume !(1 == ~E_9~0); 4761570#L1214-1 assume !(1 == ~E_10~0); 4761571#L1219-1 assume { :end_inline_reset_delta_events } true; 4762023#L1520-2 [2023-11-29 02:55:32,491 INFO L750 eck$LassoCheckResult]: Loop: 4762023#L1520-2 assume !false; 4785068#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 4785065#L981-1 assume !false; 4785063#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4785060#L764 assume !(0 == ~m_st~0); 4785061#L768 assume !(0 == ~t1_st~0); 4928427#L772 assume !(0 == ~t2_st~0); 4928418#L776 assume !(0 == ~t3_st~0); 4928409#L780 assume !(0 == ~t4_st~0); 4928402#L784 assume !(0 == ~t5_st~0); 4928394#L788 assume !(0 == ~t6_st~0); 4928387#L792 assume !(0 == ~t7_st~0); 4928271#L796 assume !(0 == ~t8_st~0); 4928269#L800 assume !(0 == ~t9_st~0); 4928266#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 4928264#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4928262#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 4928260#L836 assume !(0 != eval_~tmp~0#1); 4928258#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 4928256#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 4928254#L1006-3 assume !(0 == ~M_E~0); 4928252#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 4928250#L1011-3 assume !(0 == ~T2_E~0); 4928248#L1016-3 assume !(0 == ~T3_E~0); 4928246#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 4928244#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 4928242#L1031-3 assume !(0 == ~T6_E~0); 4928240#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 4928238#L1041-3 assume !(0 == ~T8_E~0); 4928236#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 4928234#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 4928232#L1056-3 assume !(0 == ~E_1~0); 4928230#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 4928228#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 4928226#L1071-3 assume !(0 == ~E_4~0); 4928224#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 4928214#L1081-3 assume !(0 == ~E_6~0); 4927748#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 4912879#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 4912877#L1096-3 assume !(0 == ~E_9~0); 4912875#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 4912872#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 4912870#L484-33 assume 1 == ~m_pc~0; 4912867#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 4912865#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 4912863#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 4912861#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 4912862#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 4926015#L503-33 assume !(1 == ~t1_pc~0); 4926013#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 4926011#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 4926009#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 4926008#L1253-33 assume 0 != activate_threads_~tmp___0~0#1;~t1_st~0 := 0; 4926005#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 4926003#L522-33 assume !(1 == ~t2_pc~0); 4926001#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 4925998#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 4925996#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 4925994#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 4925992#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 4925989#L541-33 assume !(1 == ~t3_pc~0); 4925987#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 4925985#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 4925983#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 4925981#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 4925979#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 4925977#L560-33 assume !(1 == ~t4_pc~0); 4925974#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 4925972#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 4911588#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 4911586#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 4911584#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 4911581#L579-33 assume !(1 == ~t5_pc~0); 4911579#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 4911577#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 4911575#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 4911573#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 4911571#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 4911570#L598-33 assume !(1 == ~t6_pc~0); 4911568#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 4911566#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 4911403#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 4911402#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 4911401#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 4808815#L617-33 assume !(1 == ~t7_pc~0); 4808811#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 4808809#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 4808807#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 4808805#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 4808802#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 4808799#L636-33 assume !(1 == ~t8_pc~0); 4808797#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 4808795#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 4808793#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 4808791#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 4808790#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 4808789#L655-33 assume 1 == ~t9_pc~0; 4808787#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 4808788#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 4928111#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 4928109#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 4928106#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 4928104#L674-33 assume !(1 == ~t10_pc~0); 4928102#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 4928099#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 4928097#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 4928095#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 4928093#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 4928091#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 4928089#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 4928087#L1124-3 assume !(1 == ~T2_E~0); 4928085#L1129-3 assume !(1 == ~T3_E~0); 4928083#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 4928081#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 4928079#L1144-3 assume !(1 == ~T6_E~0); 4928075#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 4928073#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 4928071#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 4928069#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 4928066#L1169-3 assume !(1 == ~E_1~0); 4928064#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 4928062#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 4928060#L1184-3 assume !(1 == ~E_4~0); 4928058#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 4928056#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 4928054#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 4927850#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 4808756#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 4808753#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 4808751#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4808748#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4808746#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4808744#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 4808741#L1539 assume !(0 == start_simulation_~tmp~3#1); 4808739#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 4808736#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 4808734#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 4808733#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 4808732#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 4808730#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 4791627#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 4791625#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 4762023#L1520-2 [2023-11-29 02:55:32,491 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:32,491 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 5 times [2023-11-29 02:55:32,492 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:32,492 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2118326164] [2023-11-29 02:55:32,492 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:32,492 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:32,506 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:32,506 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:55:32,516 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:32,570 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:55:32,571 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:32,571 INFO L85 PathProgramCache]: Analyzing trace with hash -198194269, now seen corresponding path program 1 times [2023-11-29 02:55:32,572 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:32,572 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [472334993] [2023-11-29 02:55:32,572 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:32,572 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:32,592 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:32,679 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:32,680 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:32,680 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [472334993] [2023-11-29 02:55:32,680 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [472334993] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:32,680 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:32,681 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:55:32,681 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1584437773] [2023-11-29 02:55:32,681 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:32,681 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:32,682 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:32,682 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:55:32,682 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:55:32,682 INFO L87 Difference]: Start difference. First operand 209604 states and 287564 transitions. cyclomatic complexity: 78024 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:33,695 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:33,695 INFO L93 Difference]: Finished difference Result 391492 states and 530187 transitions. [2023-11-29 02:55:33,695 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 391492 states and 530187 transitions. [2023-11-29 02:55:35,169 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 389728 [2023-11-29 02:55:36,085 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 391492 states to 391492 states and 530187 transitions. [2023-11-29 02:55:36,085 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 391492 [2023-11-29 02:55:36,179 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 391492 [2023-11-29 02:55:36,179 INFO L73 IsDeterministic]: Start isDeterministic. Operand 391492 states and 530187 transitions. [2023-11-29 02:55:36,258 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:36,259 INFO L218 hiAutomatonCegarLoop]: Abstraction has 391492 states and 530187 transitions. [2023-11-29 02:55:36,383 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 391492 states and 530187 transitions. [2023-11-29 02:55:37,964 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 391492 to 212964. [2023-11-29 02:55:38,079 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 212964 states, 212964 states have (on average 1.3614085009672996) internal successors, (289931), 212963 states have internal predecessors, (289931), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:38,423 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 212964 states to 212964 states and 289931 transitions. [2023-11-29 02:55:38,423 INFO L240 hiAutomatonCegarLoop]: Abstraction has 212964 states and 289931 transitions. [2023-11-29 02:55:38,423 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:55:38,424 INFO L428 stractBuchiCegarLoop]: Abstraction has 212964 states and 289931 transitions. [2023-11-29 02:55:38,424 INFO L335 stractBuchiCegarLoop]: ======== Iteration 30 ============ [2023-11-29 02:55:38,424 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 212964 states and 289931 transitions. [2023-11-29 02:55:39,266 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 211648 [2023-11-29 02:55:39,266 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:39,266 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:39,268 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:39,268 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:39,268 INFO L748 eck$LassoCheckResult]: Stem: 5362002#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 5362003#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 5363000#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 5363001#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 5363135#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 5363125#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 5363126#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 5362172#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 5361914#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 5361915#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 5362958#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 5362959#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 5362928#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 5362929#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 5362989#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 5361962#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 5361963#L1006 assume !(0 == ~M_E~0); 5361818#L1006-2 assume !(0 == ~T1_E~0); 5361819#L1011-1 assume !(0 == ~T2_E~0); 5363030#L1016-1 assume !(0 == ~T3_E~0); 5363061#L1021-1 assume !(0 == ~T4_E~0); 5361694#L1026-1 assume !(0 == ~T5_E~0); 5361695#L1031-1 assume !(0 == ~T6_E~0); 5362618#L1036-1 assume !(0 == ~T7_E~0); 5362613#L1041-1 assume !(0 == ~T8_E~0); 5362614#L1046-1 assume !(0 == ~T9_E~0); 5361993#L1051-1 assume !(0 == ~T10_E~0); 5361994#L1056-1 assume !(0 == ~E_1~0); 5362774#L1061-1 assume !(0 == ~E_2~0); 5361916#L1066-1 assume !(0 == ~E_3~0); 5361917#L1071-1 assume !(0 == ~E_4~0); 5362745#L1076-1 assume !(0 == ~E_5~0); 5361823#L1081-1 assume !(0 == ~E_6~0); 5361824#L1086-1 assume !(0 == ~E_7~0); 5362146#L1091-1 assume !(0 == ~E_8~0); 5363013#L1096-1 assume !(0 == ~E_9~0); 5363014#L1101-1 assume !(0 == ~E_10~0); 5362217#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5362218#L484 assume !(1 == ~m_pc~0); 5361874#L484-2 is_master_triggered_~__retres1~0#1 := 0; 5361873#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5362522#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5362879#L1245 assume !(0 != activate_threads_~tmp~1#1); 5362880#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5362605#L503 assume !(1 == ~t1_pc~0); 5362606#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 5362814#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5361736#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5361737#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 5361732#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5361733#L522 assume !(1 == ~t2_pc~0); 5362567#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 5361928#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5361929#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5362213#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 5362957#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5363081#L541 assume !(1 == ~t3_pc~0); 5362284#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 5362285#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5361679#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5361680#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 5362573#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5362574#L560 assume !(1 == ~t4_pc~0); 5361809#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 5362470#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5361838#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5361692#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 5361693#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5361973#L579 assume !(1 == ~t5_pc~0); 5361974#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 5361757#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5361758#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5362885#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 5363060#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5363103#L598 assume !(1 == ~t6_pc~0); 5362788#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 5362392#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5362187#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5362188#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 5362655#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5362596#L617 assume !(1 == ~t7_pc~0); 5362036#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 5362465#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5363141#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5362976#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 5362252#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5362253#L636 assume !(1 == ~t8_pc~0); 5362652#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 5362869#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5362815#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5362666#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 5362398#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5362399#L655 assume !(1 == ~t9_pc~0); 5362427#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 5362850#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5362295#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5362296#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 5363184#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5363196#L674 assume !(1 == ~t10_pc~0); 5362346#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 5362347#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5363195#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5363173#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 5362385#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5362386#L1119 assume !(1 == ~M_E~0); 5361898#L1119-2 assume !(1 == ~T1_E~0); 5361899#L1124-1 assume !(1 == ~T2_E~0); 5362312#L1129-1 assume !(1 == ~T3_E~0); 5362585#L1134-1 assume !(1 == ~T4_E~0); 5362020#L1139-1 assume !(1 == ~T5_E~0); 5362021#L1144-1 assume !(1 == ~T6_E~0); 5363161#L1149-1 assume !(1 == ~T7_E~0); 5361892#L1154-1 assume !(1 == ~T8_E~0); 5361893#L1159-1 assume !(1 == ~T9_E~0); 5361975#L1164-1 assume !(1 == ~T10_E~0); 5363187#L1169-1 assume !(1 == ~E_1~0); 5363185#L1174-1 assume !(1 == ~E_2~0); 5363183#L1179-1 assume !(1 == ~E_3~0); 5363182#L1184-1 assume !(1 == ~E_4~0); 5363181#L1189-1 assume !(1 == ~E_5~0); 5363180#L1194-1 assume !(1 == ~E_6~0); 5363179#L1199-1 assume !(1 == ~E_7~0); 5363178#L1204-1 assume !(1 == ~E_8~0); 5363176#L1209-1 assume !(1 == ~E_9~0); 5362673#L1214-1 assume !(1 == ~E_10~0); 5362674#L1219-1 assume { :end_inline_reset_delta_events } true; 5363151#L1520-2 [2023-11-29 02:55:39,268 INFO L750 eck$LassoCheckResult]: Loop: 5363151#L1520-2 assume !false; 5368905#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 5368902#L981-1 assume !false; 5368901#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5368899#L764 assume !(0 == ~m_st~0); 5368900#L768 assume !(0 == ~t1_st~0); 5373360#L772 assume !(0 == ~t2_st~0); 5373358#L776 assume !(0 == ~t3_st~0); 5373356#L780 assume !(0 == ~t4_st~0); 5373354#L784 assume !(0 == ~t5_st~0); 5373351#L788 assume !(0 == ~t6_st~0); 5373349#L792 assume !(0 == ~t7_st~0); 5373347#L796 assume !(0 == ~t8_st~0); 5373345#L800 assume !(0 == ~t9_st~0); 5373342#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 5373340#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5373338#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 5373336#L836 assume !(0 != eval_~tmp~0#1); 5373334#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 5373332#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 5373330#L1006-3 assume !(0 == ~M_E~0); 5373327#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 5373325#L1011-3 assume !(0 == ~T2_E~0); 5373323#L1016-3 assume !(0 == ~T3_E~0); 5373321#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 5373319#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 5373317#L1031-3 assume !(0 == ~T6_E~0); 5373315#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 5373313#L1041-3 assume !(0 == ~T8_E~0); 5373311#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 5373309#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 5373307#L1056-3 assume !(0 == ~E_1~0); 5373305#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 5373303#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 5373301#L1071-3 assume !(0 == ~E_4~0); 5373299#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 5373297#L1081-3 assume !(0 == ~E_6~0); 5373295#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 5373293#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 5373291#L1096-3 assume !(0 == ~E_9~0); 5373288#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 5373286#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 5373284#L484-33 assume 1 == ~m_pc~0; 5373281#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 5373278#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 5373276#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 5373273#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 5373271#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 5373269#L503-33 assume !(1 == ~t1_pc~0); 5373267#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 5373265#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 5373263#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 5373260#L1253-33 assume !(0 != activate_threads_~tmp___0~0#1); 5373258#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 5373256#L522-33 assume !(1 == ~t2_pc~0); 5373253#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 5373250#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 5373248#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 5373246#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 5373244#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 5373242#L541-33 assume !(1 == ~t3_pc~0); 5373240#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 5373238#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 5373236#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 5369085#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 5369082#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 5369080#L560-33 assume !(1 == ~t4_pc~0); 5369077#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 5369075#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 5369073#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 5369071#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 5369069#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 5369067#L579-33 assume !(1 == ~t5_pc~0); 5369065#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 5369063#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 5369061#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 5369059#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 5369057#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 5369055#L598-33 assume !(1 == ~t6_pc~0); 5369053#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 5369051#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 5369049#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 5369047#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 5369045#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 5369042#L617-33 assume !(1 == ~t7_pc~0); 5369040#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 5373036#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 5373034#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 5369031#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 5369028#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 5369026#L636-33 assume !(1 == ~t8_pc~0); 5369024#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 5369022#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 5369020#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 5369016#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 5369014#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 5369012#L655-33 assume !(1 == ~t9_pc~0); 5369008#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 5369006#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 5369004#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 5369002#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 5369000#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 5368998#L674-33 assume !(1 == ~t10_pc~0); 5368996#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 5368994#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 5368992#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 5368990#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 5368988#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 5368986#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 5368984#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 5368982#L1124-3 assume !(1 == ~T2_E~0); 5368980#L1129-3 assume !(1 == ~T3_E~0); 5368978#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 5368976#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 5368974#L1144-3 assume !(1 == ~T6_E~0); 5368972#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 5368970#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 5368968#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 5368966#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 5368964#L1169-3 assume !(1 == ~E_1~0); 5368962#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 5368960#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 5368958#L1184-3 assume !(1 == ~E_4~0); 5368956#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 5368954#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 5368951#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 5368949#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 5368946#L1209-3 assume !(1 == ~E_9~0); 5368944#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 5368942#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5368939#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5368937#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5368935#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 5368932#L1539 assume !(0 == start_simulation_~tmp~3#1); 5368930#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 5368925#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 5368923#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 5368921#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 5368918#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 5368917#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 5368915#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 5368914#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 5363151#L1520-2 [2023-11-29 02:55:39,269 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:39,269 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 6 times [2023-11-29 02:55:39,269 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:39,269 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1016305985] [2023-11-29 02:55:39,269 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:39,269 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:39,284 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:39,284 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:55:39,293 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:39,332 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:55:39,333 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:39,333 INFO L85 PathProgramCache]: Analyzing trace with hash -660852992, now seen corresponding path program 1 times [2023-11-29 02:55:39,333 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:39,333 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [93283356] [2023-11-29 02:55:39,333 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:39,333 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:39,349 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:39,414 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:39,414 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:39,414 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [93283356] [2023-11-29 02:55:39,414 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [93283356] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:39,414 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:39,414 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:55:39,415 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [339350651] [2023-11-29 02:55:39,415 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:39,415 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:39,415 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:39,416 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:55:39,416 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:55:39,416 INFO L87 Difference]: Start difference. First operand 212964 states and 289931 transitions. cyclomatic complexity: 77031 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:40,999 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:41,000 INFO L93 Difference]: Finished difference Result 545683 states and 731096 transitions. [2023-11-29 02:55:41,000 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 545683 states and 731096 transitions. [2023-11-29 02:55:42,970 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 543040 [2023-11-29 02:55:44,126 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 545683 states to 545683 states and 731096 transitions. [2023-11-29 02:55:44,126 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 545683 [2023-11-29 02:55:44,258 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 545683 [2023-11-29 02:55:44,258 INFO L73 IsDeterministic]: Start isDeterministic. Operand 545683 states and 731096 transitions. [2023-11-29 02:55:44,371 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:44,371 INFO L218 hiAutomatonCegarLoop]: Abstraction has 545683 states and 731096 transitions. [2023-11-29 02:55:44,545 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 545683 states and 731096 transitions. [2023-11-29 02:55:46,486 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 545683 to 219303. [2023-11-29 02:55:46,602 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 219303 states, 219303 states have (on average 1.3509619111457665) internal successors, (296270), 219302 states have internal predecessors, (296270), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:47,585 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 219303 states to 219303 states and 296270 transitions. [2023-11-29 02:55:47,585 INFO L240 hiAutomatonCegarLoop]: Abstraction has 219303 states and 296270 transitions. [2023-11-29 02:55:47,586 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:55:47,586 INFO L428 stractBuchiCegarLoop]: Abstraction has 219303 states and 296270 transitions. [2023-11-29 02:55:47,586 INFO L335 stractBuchiCegarLoop]: ======== Iteration 31 ============ [2023-11-29 02:55:47,586 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 219303 states and 296270 transitions. [2023-11-29 02:55:48,064 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 217984 [2023-11-29 02:55:48,064 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:48,064 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:48,066 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:48,066 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:48,066 INFO L748 eck$LassoCheckResult]: Stem: 6120662#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 6120663#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6121654#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6121655#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6121792#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 6121777#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6121778#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6120831#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6120573#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6120574#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6121607#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6121608#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6121584#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6121585#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6121645#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 6120622#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6120623#L1006 assume !(0 == ~M_E~0); 6120474#L1006-2 assume !(0 == ~T1_E~0); 6120475#L1011-1 assume !(0 == ~T2_E~0); 6121680#L1016-1 assume !(0 == ~T3_E~0); 6121705#L1021-1 assume !(0 == ~T4_E~0); 6120352#L1026-1 assume !(0 == ~T5_E~0); 6120353#L1031-1 assume !(0 == ~T6_E~0); 6121279#L1036-1 assume !(0 == ~T7_E~0); 6121276#L1041-1 assume !(0 == ~T8_E~0); 6121277#L1046-1 assume !(0 == ~T9_E~0); 6120653#L1051-1 assume !(0 == ~T10_E~0); 6120654#L1056-1 assume !(0 == ~E_1~0); 6121438#L1061-1 assume !(0 == ~E_2~0); 6120577#L1066-1 assume !(0 == ~E_3~0); 6120578#L1071-1 assume !(0 == ~E_4~0); 6121411#L1076-1 assume !(0 == ~E_5~0); 6120483#L1081-1 assume !(0 == ~E_6~0); 6120484#L1086-1 assume !(0 == ~E_7~0); 6120805#L1091-1 assume !(0 == ~E_8~0); 6121669#L1096-1 assume !(0 == ~E_9~0); 6121670#L1101-1 assume !(0 == ~E_10~0); 6120878#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6120879#L484 assume !(1 == ~m_pc~0); 6120533#L484-2 is_master_triggered_~__retres1~0#1 := 0; 6120532#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6121182#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6121540#L1245 assume !(0 != activate_threads_~tmp~1#1); 6121541#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6121268#L503 assume !(1 == ~t1_pc~0); 6121269#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6121473#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6120393#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6120394#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 6120389#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6120390#L522 assume !(1 == ~t2_pc~0); 6121228#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6120588#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6120589#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6121609#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 6121610#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6121721#L541 assume !(1 == ~t3_pc~0); 6120943#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6120944#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6120335#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6120336#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 6121234#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6121235#L560 assume !(1 == ~t4_pc~0); 6120466#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6121131#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6120499#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6120350#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 6120351#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6120633#L579 assume !(1 == ~t5_pc~0); 6120634#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6120417#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6120418#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6121546#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 6121703#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6121750#L598 assume !(1 == ~t6_pc~0); 6121450#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6121046#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6120846#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6120847#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 6121320#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6121258#L617 assume !(1 == ~t7_pc~0); 6120695#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6121123#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6121806#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6121627#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 6120911#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6120912#L636 assume !(1 == ~t8_pc~0); 6121317#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6121530#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6121474#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6121329#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 6121054#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6121055#L655 assume !(1 == ~t9_pc~0); 6121084#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6121512#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6121767#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6121706#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 6121707#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6121854#L674 assume !(1 == ~t10_pc~0); 6121853#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6121724#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6121099#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6121100#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 6121851#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6121850#L1119 assume !(1 == ~M_E~0); 6121848#L1119-2 assume !(1 == ~T1_E~0); 6121847#L1124-1 assume !(1 == ~T2_E~0); 6120379#L1129-1 assume !(1 == ~T3_E~0); 6120380#L1134-1 assume !(1 == ~T4_E~0); 6121846#L1139-1 assume !(1 == ~T5_E~0); 6121845#L1144-1 assume !(1 == ~T6_E~0); 6121844#L1149-1 assume !(1 == ~T7_E~0); 6121843#L1154-1 assume !(1 == ~T8_E~0); 6121842#L1159-1 assume !(1 == ~T9_E~0); 6121841#L1164-1 assume !(1 == ~T10_E~0); 6121840#L1169-1 assume !(1 == ~E_1~0); 6121839#L1174-1 assume !(1 == ~E_2~0); 6121838#L1179-1 assume !(1 == ~E_3~0); 6121837#L1184-1 assume !(1 == ~E_4~0); 6121836#L1189-1 assume !(1 == ~E_5~0); 6121835#L1194-1 assume !(1 == ~E_6~0); 6121834#L1199-1 assume !(1 == ~E_7~0); 6121833#L1204-1 assume !(1 == ~E_8~0); 6121832#L1209-1 assume !(1 == ~E_9~0); 6121342#L1214-1 assume !(1 == ~E_10~0); 6121343#L1219-1 assume { :end_inline_reset_delta_events } true; 6121813#L1520-2 [2023-11-29 02:55:48,066 INFO L750 eck$LassoCheckResult]: Loop: 6121813#L1520-2 assume !false; 6179719#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6179717#L981-1 assume !false; 6179716#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6179714#L764 assume !(0 == ~m_st~0); 6179715#L768 assume !(0 == ~t1_st~0); 6190492#L772 assume !(0 == ~t2_st~0); 6190491#L776 assume !(0 == ~t3_st~0); 6190490#L780 assume !(0 == ~t4_st~0); 6190489#L784 assume !(0 == ~t5_st~0); 6190488#L788 assume !(0 == ~t6_st~0); 6190487#L792 assume !(0 == ~t7_st~0); 6190486#L796 assume !(0 == ~t8_st~0); 6190485#L800 assume !(0 == ~t9_st~0); 6190483#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 6190482#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6190481#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6190480#L836 assume !(0 != eval_~tmp~0#1); 6190479#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6190478#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6190477#L1006-3 assume !(0 == ~M_E~0); 6190476#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6190475#L1011-3 assume !(0 == ~T2_E~0); 6190474#L1016-3 assume !(0 == ~T3_E~0); 6190473#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6190472#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6190471#L1031-3 assume !(0 == ~T6_E~0); 6190470#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6190469#L1041-3 assume !(0 == ~T8_E~0); 6190468#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6190467#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6190466#L1056-3 assume !(0 == ~E_1~0); 6190465#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6190464#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6190463#L1071-3 assume !(0 == ~E_4~0); 6190462#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6190461#L1081-3 assume !(0 == ~E_6~0); 6190460#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6190459#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6190458#L1096-3 assume !(0 == ~E_9~0); 6190457#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6190456#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6190455#L484-33 assume !(1 == ~m_pc~0); 6190454#L484-35 is_master_triggered_~__retres1~0#1 := 0; 6190452#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6190451#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6190449#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6190448#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6190447#L503-33 assume !(1 == ~t1_pc~0); 6190446#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 6190445#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6190444#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6190443#L1253-33 assume !(0 != activate_threads_~tmp___0~0#1); 6190442#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6190441#L522-33 assume !(1 == ~t2_pc~0); 6190440#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 6190438#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6190436#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6190434#L1261-33 assume !(0 != activate_threads_~tmp___1~0#1); 6190430#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6190428#L541-33 assume !(1 == ~t3_pc~0); 6190426#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 6190424#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6190422#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6190420#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6190418#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6180242#L560-33 assume !(1 == ~t4_pc~0); 6179954#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 6179952#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6179950#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6179948#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6179946#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6179944#L579-33 assume !(1 == ~t5_pc~0); 6179942#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 6179940#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6179939#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6179936#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6179934#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6179932#L598-33 assume !(1 == ~t6_pc~0); 6179930#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 6179928#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6179926#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6179924#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6179922#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6179920#L617-33 assume 1 == ~t7_pc~0; 6179918#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 6179919#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6179980#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6179909#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 6179906#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6179904#L636-33 assume !(1 == ~t8_pc~0); 6179902#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 6179900#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6179898#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6179895#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6179893#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6179891#L655-33 assume 1 == ~t9_pc~0; 6179890#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 6179887#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6179885#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6179883#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 6179880#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6179878#L674-33 assume !(1 == ~t10_pc~0); 6179876#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 6179874#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6179872#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6179870#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6179868#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6179866#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6179864#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6179862#L1124-3 assume !(1 == ~T2_E~0); 6179860#L1129-3 assume !(1 == ~T3_E~0); 6179857#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6179854#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6179851#L1144-3 assume !(1 == ~T6_E~0); 6179848#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6179845#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6179842#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6179839#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6179836#L1169-3 assume !(1 == ~E_1~0); 6179833#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6179830#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6179827#L1184-3 assume !(1 == ~E_4~0); 6179824#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6179821#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6179818#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6179815#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6179812#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 6179809#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6179807#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6179803#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6179798#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6179793#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 6179785#L1539 assume !(0 == start_simulation_~tmp~3#1); 6179777#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6179769#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6179760#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6179753#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 6179745#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6179738#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6179732#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 6179726#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 6121813#L1520-2 [2023-11-29 02:55:48,067 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:48,067 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 7 times [2023-11-29 02:55:48,067 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:48,067 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [848400935] [2023-11-29 02:55:48,067 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:48,068 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:48,082 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:48,082 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:55:48,091 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:48,133 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:55:48,134 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:48,134 INFO L85 PathProgramCache]: Analyzing trace with hash -937690463, now seen corresponding path program 1 times [2023-11-29 02:55:48,134 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:48,134 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [27565556] [2023-11-29 02:55:48,134 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:48,134 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:48,152 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:48,241 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:48,241 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:48,242 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [27565556] [2023-11-29 02:55:48,242 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [27565556] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:48,242 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:48,242 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:55:48,242 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [691913382] [2023-11-29 02:55:48,242 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:48,243 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:48,243 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:48,243 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:55:48,243 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:55:48,244 INFO L87 Difference]: Start difference. First operand 219303 states and 296270 transitions. cyclomatic complexity: 77031 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:49,890 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:49,890 INFO L93 Difference]: Finished difference Result 497078 states and 662289 transitions. [2023-11-29 02:55:49,890 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 497078 states and 662289 transitions. [2023-11-29 02:55:51,921 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 494400 [2023-11-29 02:55:52,733 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 497078 states to 497078 states and 662289 transitions. [2023-11-29 02:55:52,733 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 497078 [2023-11-29 02:55:53,280 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 497078 [2023-11-29 02:55:53,281 INFO L73 IsDeterministic]: Start isDeterministic. Operand 497078 states and 662289 transitions. [2023-11-29 02:55:53,433 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:55:53,433 INFO L218 hiAutomatonCegarLoop]: Abstraction has 497078 states and 662289 transitions. [2023-11-29 02:55:53,611 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 497078 states and 662289 transitions. [2023-11-29 02:55:55,530 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 497078 to 225258. [2023-11-29 02:55:55,651 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 225258 states, 225258 states have (on average 1.3416837581795098) internal successors, (302225), 225257 states have internal predecessors, (302225), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:56,041 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 225258 states to 225258 states and 302225 transitions. [2023-11-29 02:55:56,041 INFO L240 hiAutomatonCegarLoop]: Abstraction has 225258 states and 302225 transitions. [2023-11-29 02:55:56,041 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:55:56,042 INFO L428 stractBuchiCegarLoop]: Abstraction has 225258 states and 302225 transitions. [2023-11-29 02:55:56,042 INFO L335 stractBuchiCegarLoop]: ======== Iteration 32 ============ [2023-11-29 02:55:56,042 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 225258 states and 302225 transitions. [2023-11-29 02:55:56,964 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 223936 [2023-11-29 02:55:56,965 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:55:56,965 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:55:56,966 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:56,966 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:55:56,966 INFO L748 eck$LassoCheckResult]: Stem: 6837057#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 6837058#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 6838074#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 6838075#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 6838222#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 6838208#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 6838209#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 6837226#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 6836962#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 6836963#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 6838028#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 6838029#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 6837998#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 6837999#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 6838062#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 6837015#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 6837016#L1006 assume !(0 == ~M_E~0); 6836866#L1006-2 assume !(0 == ~T1_E~0); 6836867#L1011-1 assume !(0 == ~T2_E~0); 6838111#L1016-1 assume !(0 == ~T3_E~0); 6838143#L1021-1 assume !(0 == ~T4_E~0); 6836744#L1026-1 assume !(0 == ~T5_E~0); 6836745#L1031-1 assume !(0 == ~T6_E~0); 6837678#L1036-1 assume !(0 == ~T7_E~0); 6837675#L1041-1 assume !(0 == ~T8_E~0); 6837676#L1046-1 assume !(0 == ~T9_E~0); 6837048#L1051-1 assume !(0 == ~T10_E~0); 6837049#L1056-1 assume !(0 == ~E_1~0); 6837836#L1061-1 assume !(0 == ~E_2~0); 6836966#L1066-1 assume !(0 == ~E_3~0); 6836967#L1071-1 assume !(0 == ~E_4~0); 6837803#L1076-1 assume !(0 == ~E_5~0); 6836873#L1081-1 assume !(0 == ~E_6~0); 6836874#L1086-1 assume !(0 == ~E_7~0); 6837200#L1091-1 assume !(0 == ~E_8~0); 6838089#L1096-1 assume !(0 == ~E_9~0); 6838090#L1101-1 assume !(0 == ~E_10~0); 6837278#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6837279#L484 assume !(1 == ~m_pc~0); 6836922#L484-2 is_master_triggered_~__retres1~0#1 := 0; 6837391#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6837588#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6837946#L1245 assume !(0 != activate_threads_~tmp~1#1); 6837947#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6837667#L503 assume !(1 == ~t1_pc~0); 6837668#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 6837877#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6836784#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6836785#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 6836780#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6836781#L522 assume !(1 == ~t2_pc~0); 6837628#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 6837629#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6837272#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6837273#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 6838027#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6838161#L541 assume !(1 == ~t3_pc~0); 6837345#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 6837346#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6836728#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6836729#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 6837635#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6837636#L560 assume !(1 == ~t4_pc~0); 6836858#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 6837532#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6836888#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6836742#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 6836743#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6837026#L579 assume !(1 == ~t5_pc~0); 6837027#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 6836806#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6836807#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6837954#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 6838141#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6838184#L598 assume !(1 == ~t6_pc~0); 6837851#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 6837447#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6837242#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6837243#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 6837718#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6837658#L617 assume !(1 == ~t7_pc~0); 6837090#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 6837526#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6838230#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6838048#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 6837312#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6837313#L636 assume !(1 == ~t8_pc~0); 6837715#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 6837936#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6837878#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6837728#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 6837456#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6837457#L655 assume !(1 == ~t9_pc~0); 6837486#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 6837917#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6838286#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6838144#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 6838145#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6838285#L674 assume !(1 == ~t10_pc~0); 6838284#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 6838282#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6838280#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6838279#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 6838278#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6838277#L1119 assume !(1 == ~M_E~0); 6838276#L1119-2 assume !(1 == ~T1_E~0); 6838275#L1124-1 assume !(1 == ~T2_E~0); 6838274#L1129-1 assume !(1 == ~T3_E~0); 6838273#L1134-1 assume !(1 == ~T4_E~0); 6838272#L1139-1 assume !(1 == ~T5_E~0); 6838271#L1144-1 assume !(1 == ~T6_E~0); 6838270#L1149-1 assume !(1 == ~T7_E~0); 6838269#L1154-1 assume !(1 == ~T8_E~0); 6838268#L1159-1 assume !(1 == ~T9_E~0); 6838267#L1164-1 assume !(1 == ~T10_E~0); 6838266#L1169-1 assume !(1 == ~E_1~0); 6838265#L1174-1 assume !(1 == ~E_2~0); 6838264#L1179-1 assume !(1 == ~E_3~0); 6838262#L1184-1 assume !(1 == ~E_4~0); 6838261#L1189-1 assume !(1 == ~E_5~0); 6838260#L1194-1 assume !(1 == ~E_6~0); 6838259#L1199-1 assume !(1 == ~E_7~0); 6838258#L1204-1 assume !(1 == ~E_8~0); 6838257#L1209-1 assume !(1 == ~E_9~0); 6837739#L1214-1 assume !(1 == ~E_10~0); 6837740#L1219-1 assume { :end_inline_reset_delta_events } true; 6838241#L1520-2 [2023-11-29 02:55:56,966 INFO L750 eck$LassoCheckResult]: Loop: 6838241#L1520-2 assume !false; 6924622#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 6924619#L981-1 assume !false; 6924617#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6924612#L764 assume !(0 == ~m_st~0); 6924613#L768 assume !(0 == ~t1_st~0); 6928559#L772 assume !(0 == ~t2_st~0); 6928557#L776 assume !(0 == ~t3_st~0); 6928555#L780 assume !(0 == ~t4_st~0); 6928553#L784 assume !(0 == ~t5_st~0); 6928551#L788 assume !(0 == ~t6_st~0); 6928549#L792 assume !(0 == ~t7_st~0); 6928547#L796 assume !(0 == ~t8_st~0); 6928545#L800 assume !(0 == ~t9_st~0); 6928541#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 6928539#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6928537#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 6928534#L836 assume !(0 != eval_~tmp~0#1); 6928532#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 6928530#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 6928528#L1006-3 assume !(0 == ~M_E~0); 6928526#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 6928524#L1011-3 assume !(0 == ~T2_E~0); 6928522#L1016-3 assume !(0 == ~T3_E~0); 6928520#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 6928518#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 6928516#L1031-3 assume !(0 == ~T6_E~0); 6928514#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 6928512#L1041-3 assume !(0 == ~T8_E~0); 6928510#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 6928508#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 6928506#L1056-3 assume !(0 == ~E_1~0); 6928504#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 6928502#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 6928500#L1071-3 assume !(0 == ~E_4~0); 6928498#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 6928496#L1081-3 assume !(0 == ~E_6~0); 6928494#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 6928492#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 6928490#L1096-3 assume !(0 == ~E_9~0); 6928488#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 6928486#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 6928484#L484-33 assume 1 == ~m_pc~0; 6928480#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 6928478#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 6928476#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 6928472#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 6928470#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 6928468#L503-33 assume !(1 == ~t1_pc~0); 6928466#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 6928464#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 6928462#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 6928460#L1253-33 assume !(0 != activate_threads_~tmp___0~0#1); 6928458#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 6928456#L522-33 assume !(1 == ~t2_pc~0); 6928453#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 6928449#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 6928445#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 6928441#L1261-33 assume !(0 != activate_threads_~tmp___1~0#1); 6928438#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 6928436#L541-33 assume !(1 == ~t3_pc~0); 6928434#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 6928432#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 6928430#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 6928428#L1269-33 assume 0 != activate_threads_~tmp___2~0#1;~t3_st~0 := 0; 6928426#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 6928423#L560-33 assume !(1 == ~t4_pc~0); 6928420#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 6928418#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 6928416#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 6928414#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 6928412#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 6928410#L579-33 assume !(1 == ~t5_pc~0); 6928408#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 6928406#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 6928404#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 6928402#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 6928400#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 6928398#L598-33 assume !(1 == ~t6_pc~0); 6928396#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 6928394#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 6928392#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 6928390#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 6928388#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 6928386#L617-33 assume !(1 == ~t7_pc~0); 6928383#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 6928379#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 6928375#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 6928371#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 6928368#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 6928366#L636-33 assume !(1 == ~t8_pc~0); 6928364#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 6928362#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 6928360#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 6928358#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 6928356#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 6928354#L655-33 assume !(1 == ~t9_pc~0); 6928350#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 6928347#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 6928344#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 6928341#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 6928339#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 6928337#L674-33 assume !(1 == ~t10_pc~0); 6928335#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 6928333#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 6928331#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 6928329#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 6928327#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 6928325#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 6928323#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 6928321#L1124-3 assume !(1 == ~T2_E~0); 6928319#L1129-3 assume !(1 == ~T3_E~0); 6928317#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 6928315#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 6928313#L1144-3 assume !(1 == ~T6_E~0); 6928311#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 6928309#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 6928307#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 6928305#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 6928303#L1169-3 assume !(1 == ~E_1~0); 6928301#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 6928299#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 6928297#L1184-3 assume !(1 == ~E_4~0); 6928295#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 6928293#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 6928291#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 6928289#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 6928287#L1209-3 assume !(1 == ~E_9~0); 6928286#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 6928285#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6928283#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6928282#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6928281#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 6928279#L1539 assume !(0 == start_simulation_~tmp~3#1); 6928276#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 6928273#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 6928271#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 6928269#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 6928266#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 6928264#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 6928263#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 6928261#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 6838241#L1520-2 [2023-11-29 02:55:56,967 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:56,967 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 8 times [2023-11-29 02:55:56,967 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:56,967 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1060350063] [2023-11-29 02:55:56,967 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:56,967 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:56,974 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:56,975 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:55:56,980 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:55:57,003 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:55:57,004 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:55:57,004 INFO L85 PathProgramCache]: Analyzing trace with hash 1754983358, now seen corresponding path program 1 times [2023-11-29 02:55:57,004 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:55:57,004 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1998893226] [2023-11-29 02:55:57,004 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:55:57,004 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:55:57,014 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:55:57,074 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:55:57,074 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:55:57,074 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1998893226] [2023-11-29 02:55:57,074 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1998893226] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:55:57,075 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:55:57,075 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:55:57,075 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1259761753] [2023-11-29 02:55:57,075 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:55:57,075 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:55:57,075 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:55:57,076 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:55:57,076 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:55:57,076 INFO L87 Difference]: Start difference. First operand 225258 states and 302225 transitions. cyclomatic complexity: 77031 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:55:58,615 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:55:58,615 INFO L93 Difference]: Finished difference Result 400362 states and 532064 transitions. [2023-11-29 02:55:58,615 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 400362 states and 532064 transitions. [2023-11-29 02:55:59,891 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 398528 [2023-11-29 02:56:00,975 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 400362 states to 400362 states and 532064 transitions. [2023-11-29 02:56:00,975 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 400362 [2023-11-29 02:56:01,096 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 400362 [2023-11-29 02:56:01,096 INFO L73 IsDeterministic]: Start isDeterministic. Operand 400362 states and 532064 transitions. [2023-11-29 02:56:01,189 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:56:01,189 INFO L218 hiAutomatonCegarLoop]: Abstraction has 400362 states and 532064 transitions. [2023-11-29 02:56:01,322 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 400362 states and 532064 transitions. [2023-11-29 02:56:03,373 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 400362 to 228618. [2023-11-29 02:56:03,457 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 228618 states, 228618 states have (on average 1.332318540097455) internal successors, (304592), 228617 states have internal predecessors, (304592), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:03,901 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 228618 states to 228618 states and 304592 transitions. [2023-11-29 02:56:03,901 INFO L240 hiAutomatonCegarLoop]: Abstraction has 228618 states and 304592 transitions. [2023-11-29 02:56:03,901 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:56:03,901 INFO L428 stractBuchiCegarLoop]: Abstraction has 228618 states and 304592 transitions. [2023-11-29 02:56:03,902 INFO L335 stractBuchiCegarLoop]: ======== Iteration 33 ============ [2023-11-29 02:56:03,902 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 228618 states and 304592 transitions. [2023-11-29 02:56:04,365 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 227296 [2023-11-29 02:56:04,365 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:56:04,365 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:56:04,366 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:04,367 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:04,367 INFO L748 eck$LassoCheckResult]: Stem: 7462690#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 7462691#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 7463708#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7463709#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7463854#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 7463843#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7463844#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7462858#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7462600#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7462601#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7463652#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7463653#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7463624#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7463625#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7463696#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 7462650#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7462651#L1006 assume !(0 == ~M_E~0); 7462499#L1006-2 assume !(0 == ~T1_E~0); 7462500#L1011-1 assume !(0 == ~T2_E~0); 7463738#L1016-1 assume !(0 == ~T3_E~0); 7463768#L1021-1 assume !(0 == ~T4_E~0); 7462377#L1026-1 assume !(0 == ~T5_E~0); 7462378#L1031-1 assume !(0 == ~T6_E~0); 7463316#L1036-1 assume !(0 == ~T7_E~0); 7463311#L1041-1 assume !(0 == ~T8_E~0); 7463312#L1046-1 assume !(0 == ~T9_E~0); 7462681#L1051-1 assume !(0 == ~T10_E~0); 7462682#L1056-1 assume !(0 == ~E_1~0); 7463467#L1061-1 assume !(0 == ~E_2~0); 7462602#L1066-1 assume !(0 == ~E_3~0); 7462603#L1071-1 assume !(0 == ~E_4~0); 7463440#L1076-1 assume !(0 == ~E_5~0); 7462505#L1081-1 assume !(0 == ~E_6~0); 7462506#L1086-1 assume !(0 == ~E_7~0); 7462832#L1091-1 assume !(0 == ~E_8~0); 7463718#L1096-1 assume !(0 == ~E_9~0); 7463719#L1101-1 assume !(0 == ~E_10~0); 7462906#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7462907#L484 assume !(1 == ~m_pc~0); 7462559#L484-2 is_master_triggered_~__retres1~0#1 := 0; 7463024#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7463218#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7463575#L1245 assume !(0 != activate_threads_~tmp~1#1); 7463576#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7463303#L503 assume !(1 == ~t1_pc~0); 7463304#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7463509#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7462420#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7462421#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 7462416#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7462417#L522 assume !(1 == ~t2_pc~0); 7463263#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7463264#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7462901#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7462902#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 7463654#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7463789#L541 assume !(1 == ~t3_pc~0); 7462973#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7462974#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7462363#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7462364#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 7463273#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7463274#L560 assume !(1 == ~t4_pc~0); 7462491#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7463160#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7462521#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7462375#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 7462376#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7462661#L579 assume !(1 == ~t5_pc~0); 7462662#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7462441#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7462442#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7463581#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 7463767#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7463814#L598 assume !(1 == ~t6_pc~0); 7463485#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7463082#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7462875#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7462876#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 7463355#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7463294#L617 assume !(1 == ~t7_pc~0); 7462723#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7463157#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7463865#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7463675#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 7462941#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7462942#L636 assume !(1 == ~t8_pc~0); 7463352#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7463564#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7463510#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7463367#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 7463089#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7463090#L655 assume !(1 == ~t9_pc~0); 7463120#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 7463545#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7462986#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7462987#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 7463376#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7463377#L674 assume !(1 == ~t10_pc~0); 7463731#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7463792#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7463133#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7463134#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 7463913#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7463912#L1119 assume !(1 == ~M_E~0); 7463911#L1119-2 assume !(1 == ~T1_E~0); 7463910#L1124-1 assume !(1 == ~T2_E~0); 7462404#L1129-1 assume !(1 == ~T3_E~0); 7462405#L1134-1 assume !(1 == ~T4_E~0); 7463909#L1139-1 assume !(1 == ~T5_E~0); 7462935#L1144-1 assume !(1 == ~T6_E~0); 7462936#L1149-1 assume !(1 == ~T7_E~0); 7463908#L1154-1 assume !(1 == ~T8_E~0); 7463907#L1159-1 assume !(1 == ~T9_E~0); 7463906#L1164-1 assume !(1 == ~T10_E~0); 7463108#L1169-1 assume !(1 == ~E_1~0); 7463109#L1174-1 assume !(1 == ~E_2~0); 7463905#L1179-1 assume !(1 == ~E_3~0); 7463904#L1184-1 assume !(1 == ~E_4~0); 7463903#L1189-1 assume !(1 == ~E_5~0); 7463902#L1194-1 assume !(1 == ~E_6~0); 7463901#L1199-1 assume !(1 == ~E_7~0); 7463899#L1204-1 assume !(1 == ~E_8~0); 7463897#L1209-1 assume !(1 == ~E_9~0); 7463374#L1214-1 assume !(1 == ~E_10~0); 7463375#L1219-1 assume { :end_inline_reset_delta_events } true; 7463877#L1520-2 [2023-11-29 02:56:04,367 INFO L750 eck$LassoCheckResult]: Loop: 7463877#L1520-2 assume !false; 7503454#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 7503451#L981-1 assume !false; 7503449#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 7503446#L764 assume !(0 == ~m_st~0); 7503447#L768 assume !(0 == ~t1_st~0); 7504719#L772 assume !(0 == ~t2_st~0); 7504717#L776 assume !(0 == ~t3_st~0); 7504715#L780 assume !(0 == ~t4_st~0); 7504713#L784 assume !(0 == ~t5_st~0); 7504710#L788 assume !(0 == ~t6_st~0); 7504708#L792 assume !(0 == ~t7_st~0); 7504706#L796 assume !(0 == ~t8_st~0); 7504704#L800 assume !(0 == ~t9_st~0); 7504701#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 7504699#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 7504697#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 7504695#L836 assume !(0 != eval_~tmp~0#1); 7504694#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 7504691#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 7504689#L1006-3 assume !(0 == ~M_E~0); 7504687#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 7504685#L1011-3 assume !(0 == ~T2_E~0); 7504683#L1016-3 assume !(0 == ~T3_E~0); 7504681#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 7504679#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 7504677#L1031-3 assume !(0 == ~T6_E~0); 7504675#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 7504673#L1041-3 assume !(0 == ~T8_E~0); 7504671#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 7504669#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 7504667#L1056-3 assume !(0 == ~E_1~0); 7504665#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 7504663#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 7504661#L1071-3 assume !(0 == ~E_4~0); 7504659#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 7504657#L1081-3 assume !(0 == ~E_6~0); 7504655#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 7504652#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 7504650#L1096-3 assume !(0 == ~E_9~0); 7504648#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 7504645#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7504643#L484-33 assume 1 == ~m_pc~0; 7504640#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 7504638#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7504636#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7504634#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 7504632#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7504630#L503-33 assume !(1 == ~t1_pc~0); 7504627#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 7504625#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7504623#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7504621#L1253-33 assume !(0 != activate_threads_~tmp___0~0#1); 7504618#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7504616#L522-33 assume 1 == ~t2_pc~0; 7504614#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 7504615#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7504998#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7504605#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 7504603#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7504601#L541-33 assume !(1 == ~t3_pc~0); 7504599#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 7504598#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7504596#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7504594#L1269-33 assume !(0 != activate_threads_~tmp___2~0#1); 7504593#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7504590#L560-33 assume !(1 == ~t4_pc~0); 7504587#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 7504585#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7504583#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7504582#L1277-33 assume 0 != activate_threads_~tmp___3~0#1;~t4_st~0 := 0; 7504580#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7504578#L579-33 assume !(1 == ~t5_pc~0); 7504576#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 7504574#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7504572#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7504570#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 7504568#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7504566#L598-33 assume !(1 == ~t6_pc~0); 7504563#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 7504561#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7504559#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7504556#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 7504554#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7504552#L617-33 assume 1 == ~t7_pc~0; 7504550#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 7504551#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7505015#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7504541#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 7504539#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7504537#L636-33 assume !(1 == ~t8_pc~0); 7504535#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 7504533#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7504531#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7504529#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 7504527#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7504525#L655-33 assume !(1 == ~t9_pc~0); 7504522#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 7504520#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7504518#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7504516#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 7504514#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7504512#L674-33 assume !(1 == ~t10_pc~0); 7504510#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 7504508#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7504506#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7504504#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 7504502#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7504499#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 7504497#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 7504495#L1124-3 assume !(1 == ~T2_E~0); 7504493#L1129-3 assume !(1 == ~T3_E~0); 7504491#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 7504489#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 7504487#L1144-3 assume !(1 == ~T6_E~0); 7504485#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 7504483#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 7504481#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 7504479#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 7504475#L1169-3 assume !(1 == ~E_1~0); 7504473#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 7504471#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 7504469#L1184-3 assume !(1 == ~E_4~0); 7504466#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 7504464#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 7504462#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 7504460#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 7503952#L1209-3 assume !(1 == ~E_9~0); 7503950#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 7503949#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 7503947#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7503946#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 7503942#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 7503939#L1539 assume !(0 == start_simulation_~tmp~3#1); 7503936#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 7503933#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 7503928#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 7503926#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 7503924#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 7503922#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 7503920#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 7503918#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 7463877#L1520-2 [2023-11-29 02:56:04,367 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:04,367 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 9 times [2023-11-29 02:56:04,367 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:04,368 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [402972415] [2023-11-29 02:56:04,368 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:04,368 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:04,376 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:04,376 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:56:04,383 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:04,407 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:56:04,407 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:04,407 INFO L85 PathProgramCache]: Analyzing trace with hash -758385278, now seen corresponding path program 1 times [2023-11-29 02:56:04,408 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:04,408 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [473605318] [2023-11-29 02:56:04,408 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:04,408 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:04,418 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:56:04,462 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:56:04,462 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:56:04,463 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [473605318] [2023-11-29 02:56:04,463 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [473605318] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:56:04,463 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:56:04,463 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:56:04,463 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [375022720] [2023-11-29 02:56:04,463 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:56:04,464 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:56:04,464 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:56:04,464 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:56:04,464 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:56:04,465 INFO L87 Difference]: Start difference. First operand 228618 states and 304592 transitions. cyclomatic complexity: 76038 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:05,696 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:56:05,696 INFO L93 Difference]: Finished difference Result 294378 states and 389471 transitions. [2023-11-29 02:56:05,696 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 294378 states and 389471 transitions. [2023-11-29 02:56:06,579 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 292544 [2023-11-29 02:56:07,447 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 294378 states to 294378 states and 389471 transitions. [2023-11-29 02:56:07,447 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 294378 [2023-11-29 02:56:07,535 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 294378 [2023-11-29 02:56:07,536 INFO L73 IsDeterministic]: Start isDeterministic. Operand 294378 states and 389471 transitions. [2023-11-29 02:56:07,607 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:56:07,607 INFO L218 hiAutomatonCegarLoop]: Abstraction has 294378 states and 389471 transitions. [2023-11-29 02:56:07,718 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 294378 states and 389471 transitions. [2023-11-29 02:56:09,204 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 294378 to 229002. [2023-11-29 02:56:09,325 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 229002 states, 229002 states have (on average 1.323093248093903) internal successors, (302991), 229001 states have internal predecessors, (302991), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:09,675 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 229002 states to 229002 states and 302991 transitions. [2023-11-29 02:56:09,675 INFO L240 hiAutomatonCegarLoop]: Abstraction has 229002 states and 302991 transitions. [2023-11-29 02:56:09,676 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:56:09,676 INFO L428 stractBuchiCegarLoop]: Abstraction has 229002 states and 302991 transitions. [2023-11-29 02:56:09,676 INFO L335 stractBuchiCegarLoop]: ======== Iteration 34 ============ [2023-11-29 02:56:09,676 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 229002 states and 302991 transitions. [2023-11-29 02:56:10,496 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 227680 [2023-11-29 02:56:10,496 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:56:10,496 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:56:10,497 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:10,497 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:10,497 INFO L748 eck$LassoCheckResult]: Stem: 7985701#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 7985702#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 7986735#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 7986736#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 7986895#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 7986880#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 7986881#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 7985874#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 7985609#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 7985610#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 7986678#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 7986679#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 7986652#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 7986653#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 7986719#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 7985661#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 7985662#L1006 assume !(0 == ~M_E~0); 7985509#L1006-2 assume !(0 == ~T1_E~0); 7985510#L1011-1 assume !(0 == ~T2_E~0); 7986769#L1016-1 assume !(0 == ~T3_E~0); 7986805#L1021-1 assume !(0 == ~T4_E~0); 7985385#L1026-1 assume !(0 == ~T5_E~0); 7985386#L1031-1 assume !(0 == ~T6_E~0); 7986340#L1036-1 assume !(0 == ~T7_E~0); 7986335#L1041-1 assume !(0 == ~T8_E~0); 7986336#L1046-1 assume !(0 == ~T9_E~0); 7985692#L1051-1 assume !(0 == ~T10_E~0); 7985693#L1056-1 assume !(0 == ~E_1~0); 7986496#L1061-1 assume !(0 == ~E_2~0); 7985611#L1066-1 assume !(0 == ~E_3~0); 7985612#L1071-1 assume !(0 == ~E_4~0); 7986468#L1076-1 assume !(0 == ~E_5~0); 7985514#L1081-1 assume !(0 == ~E_6~0); 7985515#L1086-1 assume !(0 == ~E_7~0); 7985848#L1091-1 assume !(0 == ~E_8~0); 7986749#L1096-1 assume !(0 == ~E_9~0); 7986750#L1101-1 assume !(0 == ~E_10~0); 7985925#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 7985926#L484 assume !(1 == ~m_pc~0); 7985567#L484-2 is_master_triggered_~__retres1~0#1 := 0; 7986048#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 7986243#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 7986604#L1245 assume !(0 != activate_threads_~tmp~1#1); 7986605#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 7986327#L503 assume !(1 == ~t1_pc~0); 7986328#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 7986543#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 7985428#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 7985429#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 7985424#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 7985425#L522 assume !(1 == ~t2_pc~0); 7986287#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 7986288#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 7985919#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 7985920#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 7986680#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 7986822#L541 assume !(1 == ~t3_pc~0); 7985993#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 7985994#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 7985371#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 7985372#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 7986300#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 7986301#L560 assume !(1 == ~t4_pc~0); 7985501#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 7986185#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 7985530#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 7985383#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 7985384#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 7985672#L579 assume !(1 == ~t5_pc~0); 7985673#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 7985449#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 7985450#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 7986611#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 7986804#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 7986852#L598 assume !(1 == ~t6_pc~0); 7986513#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 7986107#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 7985890#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 7985891#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 7986378#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 7986318#L617 assume !(1 == ~t7_pc~0); 7985737#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 7986182#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 7986905#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 7986699#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 7985962#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 7985963#L636 assume !(1 == ~t8_pc~0); 7986374#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 7986597#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 7986544#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 7986390#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 7986113#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 7986114#L655 assume !(1 == ~t9_pc~0); 7986145#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 7986577#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 7986007#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 7986008#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 7986401#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 7986402#L674 assume !(1 == ~t10_pc~0); 7986761#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 7986825#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 7986157#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 7986158#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 7986965#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 7986964#L1119 assume !(1 == ~M_E~0); 7986963#L1119-2 assume !(1 == ~T1_E~0); 7986962#L1124-1 assume !(1 == ~T2_E~0); 7985412#L1129-1 assume !(1 == ~T3_E~0); 7985413#L1134-1 assume !(1 == ~T4_E~0); 7986961#L1139-1 assume !(1 == ~T5_E~0); 7985957#L1144-1 assume !(1 == ~T6_E~0); 7985958#L1149-1 assume !(1 == ~T7_E~0); 7986960#L1154-1 assume !(1 == ~T8_E~0); 7986959#L1159-1 assume !(1 == ~T9_E~0); 7986958#L1164-1 assume !(1 == ~T10_E~0); 7986131#L1169-1 assume !(1 == ~E_1~0); 7986132#L1174-1 assume !(1 == ~E_2~0); 7986957#L1179-1 assume !(1 == ~E_3~0); 7986956#L1184-1 assume !(1 == ~E_4~0); 7986955#L1189-1 assume !(1 == ~E_5~0); 7986954#L1194-1 assume !(1 == ~E_6~0); 7986953#L1199-1 assume !(1 == ~E_7~0); 7986951#L1204-1 assume !(1 == ~E_8~0); 7986949#L1209-1 assume !(1 == ~E_9~0); 7986399#L1214-1 assume !(1 == ~E_10~0); 7986400#L1219-1 assume { :end_inline_reset_delta_events } true; 7986920#L1520-2 [2023-11-29 02:56:10,498 INFO L750 eck$LassoCheckResult]: Loop: 7986920#L1520-2 assume !false; 8004676#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8004671#L981-1 assume !false; 8004667#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8004662#L764 assume !(0 == ~m_st~0); 8004663#L768 assume !(0 == ~t1_st~0); 8005242#L772 assume !(0 == ~t2_st~0); 8005240#L776 assume !(0 == ~t3_st~0); 8005238#L780 assume !(0 == ~t4_st~0); 8005236#L784 assume !(0 == ~t5_st~0); 8005234#L788 assume !(0 == ~t6_st~0); 8005232#L792 assume !(0 == ~t7_st~0); 8005230#L796 assume !(0 == ~t8_st~0); 8005228#L800 assume !(0 == ~t9_st~0); 8005225#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 8005222#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8005220#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8005218#L836 assume !(0 != eval_~tmp~0#1); 8005217#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8005216#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8005214#L1006-3 assume !(0 == ~M_E~0); 8005213#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8005212#L1011-3 assume !(0 == ~T2_E~0); 8005211#L1016-3 assume !(0 == ~T3_E~0); 8005210#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8005209#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8005207#L1031-3 assume !(0 == ~T6_E~0); 8005206#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8005205#L1041-3 assume !(0 == ~T8_E~0); 8005203#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8005202#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8005201#L1056-3 assume !(0 == ~E_1~0); 8005200#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8005199#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8005198#L1071-3 assume !(0 == ~E_4~0); 8005196#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8005195#L1081-3 assume !(0 == ~E_6~0); 8005194#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8005192#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8005190#L1096-3 assume !(0 == ~E_9~0); 8005188#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8005186#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8005184#L484-33 assume 1 == ~m_pc~0; 8005181#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8005179#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8005177#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8005174#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8005172#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8005169#L503-33 assume !(1 == ~t1_pc~0); 8005167#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 8005165#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8005162#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8005160#L1253-33 assume !(0 != activate_threads_~tmp___0~0#1); 8005158#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8005156#L522-33 assume 1 == ~t2_pc~0; 8005154#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 8005155#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8005197#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8005145#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 8005143#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8005141#L541-33 assume !(1 == ~t3_pc~0); 8005139#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 8005137#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8005135#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8005133#L1269-33 assume !(0 != activate_threads_~tmp___2~0#1); 8005131#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8005129#L560-33 assume !(1 == ~t4_pc~0); 8005126#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 8005124#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8005122#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8005120#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 8005118#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8005116#L579-33 assume !(1 == ~t5_pc~0); 8005114#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 8005112#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8005110#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8005108#L1285-33 assume 0 != activate_threads_~tmp___4~0#1;~t5_st~0 := 0; 8005105#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8005103#L598-33 assume !(1 == ~t6_pc~0); 8005101#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 8005098#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8005096#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8005094#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8005092#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8005090#L617-33 assume !(1 == ~t7_pc~0); 8005086#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 8005084#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8005082#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8005078#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 8005075#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8005073#L636-33 assume !(1 == ~t8_pc~0); 8005071#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 8005068#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8005066#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8005064#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8005062#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8005060#L655-33 assume 1 == ~t9_pc~0; 8005059#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8004871#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8004868#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8004866#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8004863#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8004861#L674-33 assume !(1 == ~t10_pc~0); 8004859#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 8004857#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8004854#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8004852#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8004850#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8004848#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8004846#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8004844#L1124-3 assume !(1 == ~T2_E~0); 8004841#L1129-3 assume !(1 == ~T3_E~0); 8004839#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8004837#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8004834#L1144-3 assume !(1 == ~T6_E~0); 8004832#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8004830#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8004828#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8004826#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8004824#L1169-3 assume !(1 == ~E_1~0); 8004822#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8004820#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8004816#L1184-3 assume !(1 == ~E_4~0); 8004814#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8004812#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8004810#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8004808#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8004806#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 8004803#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8004800#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8004797#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8004795#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8004793#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 8004790#L1539 assume !(0 == start_simulation_~tmp~3#1); 8004788#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8004783#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8004781#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8004779#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 8004778#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8004775#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8004774#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8004772#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 7986920#L1520-2 [2023-11-29 02:56:10,498 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:10,498 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 10 times [2023-11-29 02:56:10,498 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:10,498 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1989541109] [2023-11-29 02:56:10,498 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:10,499 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:10,508 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:10,508 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:56:10,515 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:10,539 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:56:10,539 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:10,539 INFO L85 PathProgramCache]: Analyzing trace with hash 1392609086, now seen corresponding path program 1 times [2023-11-29 02:56:10,539 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:10,539 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1928152362] [2023-11-29 02:56:10,539 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:10,539 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:10,550 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:56:10,592 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:56:10,593 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:56:10,593 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1928152362] [2023-11-29 02:56:10,593 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1928152362] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:56:10,593 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:56:10,593 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:56:10,593 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [779434008] [2023-11-29 02:56:10,593 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:56:10,594 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:56:10,594 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:56:10,594 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:56:10,594 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:56:10,594 INFO L87 Difference]: Start difference. First operand 229002 states and 302991 transitions. cyclomatic complexity: 74053 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:11,955 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:56:11,955 INFO L93 Difference]: Finished difference Result 390858 states and 513198 transitions. [2023-11-29 02:56:11,956 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 390858 states and 513198 transitions. [2023-11-29 02:56:13,020 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 389088 [2023-11-29 02:56:14,096 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 390858 states to 390858 states and 513198 transitions. [2023-11-29 02:56:14,097 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 390858 [2023-11-29 02:56:14,255 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 390858 [2023-11-29 02:56:14,255 INFO L73 IsDeterministic]: Start isDeterministic. Operand 390858 states and 513198 transitions. [2023-11-29 02:56:14,369 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:56:14,369 INFO L218 hiAutomatonCegarLoop]: Abstraction has 390858 states and 513198 transitions. [2023-11-29 02:56:14,533 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 390858 states and 513198 transitions. [2023-11-29 02:56:16,191 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 390858 to 232362. [2023-11-29 02:56:16,312 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 232362 states, 232362 states have (on average 1.3141477522142175) internal successors, (305358), 232361 states have internal predecessors, (305358), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:17,403 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 232362 states to 232362 states and 305358 transitions. [2023-11-29 02:56:17,403 INFO L240 hiAutomatonCegarLoop]: Abstraction has 232362 states and 305358 transitions. [2023-11-29 02:56:17,404 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:56:17,404 INFO L428 stractBuchiCegarLoop]: Abstraction has 232362 states and 305358 transitions. [2023-11-29 02:56:17,404 INFO L335 stractBuchiCegarLoop]: ======== Iteration 35 ============ [2023-11-29 02:56:17,404 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 232362 states and 305358 transitions. [2023-11-29 02:56:17,898 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 231040 [2023-11-29 02:56:17,899 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:56:17,899 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:56:17,900 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:17,900 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:17,900 INFO L748 eck$LassoCheckResult]: Stem: 8605571#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 8605572#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 8606588#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 8606589#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 8606714#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 8606702#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 8606703#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 8605743#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 8605478#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 8605479#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 8606540#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 8606541#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 8606511#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 8606512#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 8606578#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 8605534#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 8605535#L1006 assume !(0 == ~M_E~0); 8605379#L1006-2 assume !(0 == ~T1_E~0); 8605380#L1011-1 assume !(0 == ~T2_E~0); 8606620#L1016-1 assume !(0 == ~T3_E~0); 8606644#L1021-1 assume !(0 == ~T4_E~0); 8605259#L1026-1 assume !(0 == ~T5_E~0); 8605260#L1031-1 assume !(0 == ~T6_E~0); 8606196#L1036-1 assume !(0 == ~T7_E~0); 8606191#L1041-1 assume !(0 == ~T8_E~0); 8606192#L1046-1 assume !(0 == ~T9_E~0); 8605562#L1051-1 assume !(0 == ~T10_E~0); 8605563#L1056-1 assume !(0 == ~E_1~0); 8606358#L1061-1 assume !(0 == ~E_2~0); 8605480#L1066-1 assume !(0 == ~E_3~0); 8605481#L1071-1 assume !(0 == ~E_4~0); 8606328#L1076-1 assume !(0 == ~E_5~0); 8605384#L1081-1 assume !(0 == ~E_6~0); 8605385#L1086-1 assume !(0 == ~E_7~0); 8605717#L1091-1 assume !(0 == ~E_8~0); 8606603#L1096-1 assume !(0 == ~E_9~0); 8606604#L1101-1 assume !(0 == ~E_10~0); 8605791#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8605792#L484 assume !(1 == ~m_pc~0); 8605436#L484-2 is_master_triggered_~__retres1~0#1 := 0; 8605908#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8606094#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8606464#L1245 assume !(0 != activate_threads_~tmp~1#1); 8606465#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8606182#L503 assume !(1 == ~t1_pc~0); 8606183#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 8606411#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8605299#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8605300#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 8605295#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8605296#L522 assume !(1 == ~t2_pc~0); 8606137#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 8606138#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8605786#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8605787#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 8606542#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8606662#L541 assume !(1 == ~t3_pc~0); 8605859#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 8605860#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8605243#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8605244#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 8606150#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8606151#L560 assume !(1 == ~t4_pc~0); 8605371#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 8606041#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8605399#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8605255#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 8605256#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8605545#L579 assume !(1 == ~t5_pc~0); 8605546#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 8605320#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8605321#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8606472#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 8606643#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8606687#L598 assume !(1 == ~t6_pc~0); 8606375#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 8605963#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8605760#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8605761#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 8606236#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8606173#L617 assume !(1 == ~t7_pc~0); 8605603#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 8606038#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8606723#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8606562#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 8605828#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8605829#L636 assume !(1 == ~t8_pc~0); 8606232#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 8606456#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8606412#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8606253#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 8605969#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8605970#L655 assume !(1 == ~t9_pc~0); 8605999#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 8606441#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8605875#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8605876#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 8606262#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8606263#L674 assume !(1 == ~t10_pc~0); 8606612#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 8606665#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8606011#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8606012#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 8606779#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8606778#L1119 assume !(1 == ~M_E~0); 8606777#L1119-2 assume !(1 == ~T1_E~0); 8606776#L1124-1 assume !(1 == ~T2_E~0); 8605283#L1129-1 assume !(1 == ~T3_E~0); 8605284#L1134-1 assume !(1 == ~T4_E~0); 8606775#L1139-1 assume !(1 == ~T5_E~0); 8605823#L1144-1 assume !(1 == ~T6_E~0); 8605824#L1149-1 assume !(1 == ~T7_E~0); 8606774#L1154-1 assume !(1 == ~T8_E~0); 8606773#L1159-1 assume !(1 == ~T9_E~0); 8606772#L1164-1 assume !(1 == ~T10_E~0); 8605986#L1169-1 assume !(1 == ~E_1~0); 8605987#L1174-1 assume !(1 == ~E_2~0); 8606771#L1179-1 assume !(1 == ~E_3~0); 8606770#L1184-1 assume !(1 == ~E_4~0); 8606769#L1189-1 assume !(1 == ~E_5~0); 8606768#L1194-1 assume !(1 == ~E_6~0); 8606767#L1199-1 assume !(1 == ~E_7~0); 8606765#L1204-1 assume !(1 == ~E_8~0); 8606763#L1209-1 assume !(1 == ~E_9~0); 8606260#L1214-1 assume !(1 == ~E_10~0); 8606261#L1219-1 assume { :end_inline_reset_delta_events } true; 8606741#L1520-2 [2023-11-29 02:56:17,901 INFO L750 eck$LassoCheckResult]: Loop: 8606741#L1520-2 assume !false; 8629478#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 8629154#L981-1 assume !false; 8629475#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8629472#L764 assume !(0 == ~m_st~0); 8629473#L768 assume !(0 == ~t1_st~0); 8699567#L772 assume !(0 == ~t2_st~0); 8699563#L776 assume !(0 == ~t3_st~0); 8699561#L780 assume !(0 == ~t4_st~0); 8699559#L784 assume !(0 == ~t5_st~0); 8699557#L788 assume !(0 == ~t6_st~0); 8699556#L792 assume !(0 == ~t7_st~0); 8699554#L796 assume !(0 == ~t8_st~0); 8699552#L800 assume !(0 == ~t9_st~0); 8699549#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 8699547#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8699545#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 8699543#L836 assume !(0 != eval_~tmp~0#1); 8699541#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 8699539#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 8699536#L1006-3 assume !(0 == ~M_E~0); 8699534#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 8699532#L1011-3 assume !(0 == ~T2_E~0); 8699530#L1016-3 assume !(0 == ~T3_E~0); 8699528#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 8699526#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 8699524#L1031-3 assume !(0 == ~T6_E~0); 8699522#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 8699520#L1041-3 assume !(0 == ~T8_E~0); 8699518#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 8699516#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 8699514#L1056-3 assume !(0 == ~E_1~0); 8699512#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 8699510#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 8699508#L1071-3 assume !(0 == ~E_4~0); 8699506#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 8699504#L1081-3 assume !(0 == ~E_6~0); 8699502#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 8699500#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 8699498#L1096-3 assume !(0 == ~E_9~0); 8699496#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 8699494#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 8699492#L484-33 assume 1 == ~m_pc~0; 8699489#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 8699487#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 8699485#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 8699483#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 8699481#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 8699479#L503-33 assume !(1 == ~t1_pc~0); 8699476#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 8699474#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 8699472#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 8699470#L1253-33 assume !(0 != activate_threads_~tmp___0~0#1); 8699468#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 8699466#L522-33 assume !(1 == ~t2_pc~0); 8699462#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 8699460#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 8699458#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 8699456#L1261-33 assume !(0 != activate_threads_~tmp___1~0#1); 8699453#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 8699451#L541-33 assume !(1 == ~t3_pc~0); 8699448#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 8699446#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 8699444#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 8699443#L1269-33 assume !(0 != activate_threads_~tmp___2~0#1); 8699442#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 8699441#L560-33 assume !(1 == ~t4_pc~0); 8699439#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 8699437#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 8699436#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 8699435#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 8699433#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 8699432#L579-33 assume !(1 == ~t5_pc~0); 8699431#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 8699430#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 8699429#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 8699427#L1285-33 assume !(0 != activate_threads_~tmp___4~0#1); 8699425#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 8699423#L598-33 assume !(1 == ~t6_pc~0); 8699422#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 8699420#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 8699418#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 8699416#L1293-33 assume 0 != activate_threads_~tmp___5~0#1;~t6_st~0 := 0; 8699414#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 8699412#L617-33 assume !(1 == ~t7_pc~0); 8699408#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 8699404#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 8699402#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 8699400#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 8699397#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 8699394#L636-33 assume !(1 == ~t8_pc~0); 8699392#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 8699390#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 8699388#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 8699386#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 8699384#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 8699382#L655-33 assume 1 == ~t9_pc~0; 8699380#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 8699381#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 8714362#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 8714359#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 8714356#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 8714354#L674-33 assume !(1 == ~t10_pc~0); 8714352#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 8714348#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 8714341#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 8714336#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 8714331#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 8714325#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 8714322#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 8714319#L1124-3 assume !(1 == ~T2_E~0); 8714316#L1129-3 assume !(1 == ~T3_E~0); 8714313#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 8714310#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 8714307#L1144-3 assume !(1 == ~T6_E~0); 8712209#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 8712208#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 8699677#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 8699669#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 8699662#L1169-3 assume !(1 == ~E_1~0); 8699656#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 8699650#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 8699644#L1184-3 assume !(1 == ~E_4~0); 8699637#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 8699631#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 8699625#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 8696171#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 8629519#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 8629516#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 8629514#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8629511#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8629507#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8629505#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 8629502#L1539 assume !(0 == start_simulation_~tmp~3#1); 8629499#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 8629495#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 8629493#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 8629491#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 8629488#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 8629486#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 8629484#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 8629482#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 8606741#L1520-2 [2023-11-29 02:56:17,901 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:17,901 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 11 times [2023-11-29 02:56:17,901 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:17,901 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [996295901] [2023-11-29 02:56:17,901 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:17,901 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:17,909 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:17,909 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:56:17,915 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:17,938 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:56:17,938 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:17,938 INFO L85 PathProgramCache]: Analyzing trace with hash -16294951, now seen corresponding path program 1 times [2023-11-29 02:56:17,938 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:17,939 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [988257970] [2023-11-29 02:56:17,939 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:17,939 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:17,949 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:56:18,022 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:56:18,023 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:56:18,023 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [988257970] [2023-11-29 02:56:18,023 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [988257970] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:56:18,023 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:56:18,023 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:56:18,024 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [2071561028] [2023-11-29 02:56:18,024 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:56:18,024 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:56:18,024 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:56:18,025 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:56:18,025 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:56:18,026 INFO L87 Difference]: Start difference. First operand 232362 states and 305358 transitions. cyclomatic complexity: 73060 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:19,385 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:56:19,385 INFO L93 Difference]: Finished difference Result 388682 states and 507197 transitions. [2023-11-29 02:56:19,385 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 388682 states and 507197 transitions. [2023-11-29 02:56:21,001 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 386912 [2023-11-29 02:56:21,667 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 388682 states to 388682 states and 507197 transitions. [2023-11-29 02:56:21,668 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 388682 [2023-11-29 02:56:21,825 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 388682 [2023-11-29 02:56:21,825 INFO L73 IsDeterministic]: Start isDeterministic. Operand 388682 states and 507197 transitions. [2023-11-29 02:56:21,939 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:56:21,939 INFO L218 hiAutomatonCegarLoop]: Abstraction has 388682 states and 507197 transitions. [2023-11-29 02:56:22,104 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 388682 states and 507197 transitions. [2023-11-29 02:56:24,199 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 388682 to 235722. [2023-11-29 02:56:24,286 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 235722 states, 235722 states have (on average 1.3054572759436964) internal successors, (307725), 235721 states have internal predecessors, (307725), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:24,708 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 235722 states to 235722 states and 307725 transitions. [2023-11-29 02:56:24,708 INFO L240 hiAutomatonCegarLoop]: Abstraction has 235722 states and 307725 transitions. [2023-11-29 02:56:24,709 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:56:24,709 INFO L428 stractBuchiCegarLoop]: Abstraction has 235722 states and 307725 transitions. [2023-11-29 02:56:24,709 INFO L335 stractBuchiCegarLoop]: ======== Iteration 36 ============ [2023-11-29 02:56:24,709 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 235722 states and 307725 transitions. [2023-11-29 02:56:25,174 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 234400 [2023-11-29 02:56:25,174 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:56:25,174 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:56:25,175 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:25,175 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:25,176 INFO L748 eck$LassoCheckResult]: Stem: 9226623#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 9226624#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9227658#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9227659#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9227824#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 9227812#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9227813#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9226799#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9226535#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9226536#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9227608#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9227609#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 9227580#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 9227581#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9227647#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 9226586#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9226587#L1006 assume !(0 == ~M_E~0); 9226437#L1006-2 assume !(0 == ~T1_E~0); 9226438#L1011-1 assume !(0 == ~T2_E~0); 9227697#L1016-1 assume !(0 == ~T3_E~0); 9227731#L1021-1 assume !(0 == ~T4_E~0); 9226315#L1026-1 assume !(0 == ~T5_E~0); 9226316#L1031-1 assume !(0 == ~T6_E~0); 9227261#L1036-1 assume !(0 == ~T7_E~0); 9227256#L1041-1 assume !(0 == ~T8_E~0); 9227257#L1046-1 assume !(0 == ~T9_E~0); 9226614#L1051-1 assume !(0 == ~T10_E~0); 9226615#L1056-1 assume !(0 == ~E_1~0); 9227423#L1061-1 assume !(0 == ~E_2~0); 9226537#L1066-1 assume !(0 == ~E_3~0); 9226538#L1071-1 assume !(0 == ~E_4~0); 9227392#L1076-1 assume !(0 == ~E_5~0); 9226443#L1081-1 assume !(0 == ~E_6~0); 9226444#L1086-1 assume !(0 == ~E_7~0); 9226773#L1091-1 assume !(0 == ~E_8~0); 9227674#L1096-1 assume !(0 == ~E_9~0); 9227675#L1101-1 assume !(0 == ~E_10~0); 9226844#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9226845#L484 assume !(1 == ~m_pc~0); 9226495#L484-2 is_master_triggered_~__retres1~0#1 := 0; 9226962#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9227159#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9227529#L1245 assume !(0 != activate_threads_~tmp~1#1); 9227530#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9227248#L503 assume !(1 == ~t1_pc~0); 9227249#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9227469#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9226356#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9226357#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 9226352#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9226353#L522 assume !(1 == ~t2_pc~0); 9227205#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9227206#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9226839#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9226840#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 9227610#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9227758#L541 assume !(1 == ~t3_pc~0); 9226913#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9226914#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9226299#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9226300#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 9227217#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9227218#L560 assume !(1 == ~t4_pc~0); 9226428#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9227103#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9226458#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9226311#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 9226312#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9226597#L579 assume !(1 == ~t5_pc~0); 9226598#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9226376#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9226377#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9227537#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 9227730#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9227782#L598 assume !(1 == ~t6_pc~0); 9227437#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9227020#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9226816#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9226817#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 9227305#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9227237#L617 assume !(1 == ~t7_pc~0); 9226658#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9227097#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9227831#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9227628#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 9226882#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9226883#L636 assume !(1 == ~t8_pc~0); 9227300#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9227521#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9227470#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9227317#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 9227026#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9227027#L655 assume !(1 == ~t9_pc~0); 9227057#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9227499#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9226928#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9226929#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 9227327#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9227328#L674 assume !(1 == ~t10_pc~0); 9227686#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9227760#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9227069#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9227070#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 9227884#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9227883#L1119 assume !(1 == ~M_E~0); 9227882#L1119-2 assume !(1 == ~T1_E~0); 9227881#L1124-1 assume !(1 == ~T2_E~0); 9226340#L1129-1 assume !(1 == ~T3_E~0); 9226341#L1134-1 assume !(1 == ~T4_E~0); 9227880#L1139-1 assume !(1 == ~T5_E~0); 9226876#L1144-1 assume !(1 == ~T6_E~0); 9226877#L1149-1 assume !(1 == ~T7_E~0); 9227879#L1154-1 assume !(1 == ~T8_E~0); 9227878#L1159-1 assume !(1 == ~T9_E~0); 9227877#L1164-1 assume !(1 == ~T10_E~0); 9227044#L1169-1 assume !(1 == ~E_1~0); 9227045#L1174-1 assume !(1 == ~E_2~0); 9227876#L1179-1 assume !(1 == ~E_3~0); 9227875#L1184-1 assume !(1 == ~E_4~0); 9227874#L1189-1 assume !(1 == ~E_5~0); 9227873#L1194-1 assume !(1 == ~E_6~0); 9227872#L1199-1 assume !(1 == ~E_7~0); 9227870#L1204-1 assume !(1 == ~E_8~0); 9227868#L1209-1 assume !(1 == ~E_9~0); 9227325#L1214-1 assume !(1 == ~E_10~0); 9227326#L1219-1 assume { :end_inline_reset_delta_events } true; 9227843#L1520-2 [2023-11-29 02:56:25,176 INFO L750 eck$LassoCheckResult]: Loop: 9227843#L1520-2 assume !false; 9272371#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9272368#L981-1 assume !false; 9272366#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9272363#L764 assume !(0 == ~m_st~0); 9272364#L768 assume !(0 == ~t1_st~0); 9273172#L772 assume !(0 == ~t2_st~0); 9273170#L776 assume !(0 == ~t3_st~0); 9273168#L780 assume !(0 == ~t4_st~0); 9273166#L784 assume !(0 == ~t5_st~0); 9273164#L788 assume !(0 == ~t6_st~0); 9273162#L792 assume !(0 == ~t7_st~0); 9273160#L796 assume !(0 == ~t8_st~0); 9273158#L800 assume !(0 == ~t9_st~0); 9273155#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 9273153#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9273151#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9273148#L836 assume !(0 != eval_~tmp~0#1); 9273146#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9273145#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9273144#L1006-3 assume !(0 == ~M_E~0); 9273142#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9273141#L1011-3 assume !(0 == ~T2_E~0); 9273140#L1016-3 assume !(0 == ~T3_E~0); 9273139#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9273138#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9273137#L1031-3 assume !(0 == ~T6_E~0); 9273135#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9273134#L1041-3 assume !(0 == ~T8_E~0); 9273133#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9273132#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9273130#L1056-3 assume !(0 == ~E_1~0); 9273129#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9273128#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9273127#L1071-3 assume !(0 == ~E_4~0); 9273126#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9273124#L1081-3 assume !(0 == ~E_6~0); 9273123#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9273122#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9273121#L1096-3 assume !(0 == ~E_9~0); 9273120#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9273118#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9273116#L484-33 assume 1 == ~m_pc~0; 9273114#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9273112#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9273110#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9273107#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9273105#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9273103#L503-33 assume !(1 == ~t1_pc~0); 9273101#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9273099#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9273097#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9273094#L1253-33 assume !(0 != activate_threads_~tmp___0~0#1); 9273092#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9273090#L522-33 assume !(1 == ~t2_pc~0); 9273086#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 9273084#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9273082#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9273080#L1261-33 assume !(0 != activate_threads_~tmp___1~0#1); 9273077#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9273075#L541-33 assume !(1 == ~t3_pc~0); 9273073#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 9273071#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9273069#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9273067#L1269-33 assume !(0 != activate_threads_~tmp___2~0#1); 9273065#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9273063#L560-33 assume !(1 == ~t4_pc~0); 9273060#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 9273058#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9273056#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9273054#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 9273052#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9273050#L579-33 assume !(1 == ~t5_pc~0); 9273048#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 9273046#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9273044#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9273042#L1285-33 assume !(0 != activate_threads_~tmp___4~0#1); 9273040#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9273038#L598-33 assume !(1 == ~t6_pc~0); 9273036#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 9273034#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9273031#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9273029#L1293-33 assume !(0 != activate_threads_~tmp___5~0#1); 9273027#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9273024#L617-33 assume !(1 == ~t7_pc~0); 9273020#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 9273018#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9273016#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9273014#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 9273011#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9273009#L636-33 assume !(1 == ~t8_pc~0); 9273007#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 9273003#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9273001#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9272999#L1309-33 assume 0 != activate_threads_~tmp___7~0#1;~t8_st~0 := 0; 9272997#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9272994#L655-33 assume !(1 == ~t9_pc~0); 9272991#L655-35 is_transmit9_triggered_~__retres1~9#1 := 0; 9272989#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9272987#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9272985#L1317-33 assume !(0 != activate_threads_~tmp___8~0#1); 9272983#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9272981#L674-33 assume !(1 == ~t10_pc~0); 9272979#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 9272976#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9272974#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9272972#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9272970#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9272968#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9272966#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9272964#L1124-3 assume !(1 == ~T2_E~0); 9272962#L1129-3 assume !(1 == ~T3_E~0); 9272960#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9272958#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9272956#L1144-3 assume !(1 == ~T6_E~0); 9272954#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9272952#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9272950#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9272948#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9272946#L1169-3 assume !(1 == ~E_1~0); 9272944#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9272942#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9272938#L1184-3 assume !(1 == ~E_4~0); 9272936#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9272934#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9272932#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9272929#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9272830#L1209-3 assume !(1 == ~E_9~0); 9272828#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9272826#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9272823#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 9272821#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9272819#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 9272816#L1539 assume !(0 == start_simulation_~tmp~3#1); 9272813#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9272810#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 9272808#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9272806#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 9272803#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9272801#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9272799#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 9272796#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 9227843#L1520-2 [2023-11-29 02:56:25,176 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:25,176 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 12 times [2023-11-29 02:56:25,176 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:25,176 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [534482438] [2023-11-29 02:56:25,176 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:25,176 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:25,183 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:25,183 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:56:25,188 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:25,209 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:56:25,209 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:25,209 INFO L85 PathProgramCache]: Analyzing trace with hash 2140774326, now seen corresponding path program 1 times [2023-11-29 02:56:25,209 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:25,210 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1770268596] [2023-11-29 02:56:25,210 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:25,210 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:25,220 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:56:25,276 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:56:25,276 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:56:25,276 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1770268596] [2023-11-29 02:56:25,277 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1770268596] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:56:25,277 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:56:25,277 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:56:25,277 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [414363568] [2023-11-29 02:56:25,277 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:56:25,277 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:56:25,277 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:56:25,278 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:56:25,278 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:56:25,278 INFO L87 Difference]: Start difference. First operand 235722 states and 307725 transitions. cyclomatic complexity: 72067 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:26,633 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:56:26,633 INFO L93 Difference]: Finished difference Result 372042 states and 482572 transitions. [2023-11-29 02:56:26,633 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 372042 states and 482572 transitions. [2023-11-29 02:56:28,067 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 370272 [2023-11-29 02:56:28,597 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 372042 states to 372042 states and 482572 transitions. [2023-11-29 02:56:28,597 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 372042 [2023-11-29 02:56:28,706 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 372042 [2023-11-29 02:56:28,706 INFO L73 IsDeterministic]: Start isDeterministic. Operand 372042 states and 482572 transitions. [2023-11-29 02:56:28,795 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:56:28,796 INFO L218 hiAutomatonCegarLoop]: Abstraction has 372042 states and 482572 transitions. [2023-11-29 02:56:28,929 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 372042 states and 482572 transitions. [2023-11-29 02:56:30,872 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 372042 to 238986. [2023-11-29 02:56:30,962 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 238986 states, 238986 states have (on average 1.2969964767810667) internal successors, (309964), 238985 states have internal predecessors, (309964), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:31,338 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 238986 states to 238986 states and 309964 transitions. [2023-11-29 02:56:31,338 INFO L240 hiAutomatonCegarLoop]: Abstraction has 238986 states and 309964 transitions. [2023-11-29 02:56:31,339 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:56:31,339 INFO L428 stractBuchiCegarLoop]: Abstraction has 238986 states and 309964 transitions. [2023-11-29 02:56:31,339 INFO L335 stractBuchiCegarLoop]: ======== Iteration 37 ============ [2023-11-29 02:56:31,339 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 238986 states and 309964 transitions. [2023-11-29 02:56:31,871 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 237664 [2023-11-29 02:56:31,871 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:56:31,871 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:56:31,872 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:31,872 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:31,872 INFO L748 eck$LassoCheckResult]: Stem: 9834401#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 9834402#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 9835435#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 9835436#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 9835574#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 9835566#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 9835567#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 9834568#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 9834309#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 9834310#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 9835388#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 9835389#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 9835360#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 9835361#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 9835425#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 9834359#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 9834360#L1006 assume !(0 == ~M_E~0); 9834209#L1006-2 assume !(0 == ~T1_E~0); 9834210#L1011-1 assume !(0 == ~T2_E~0); 9835471#L1016-1 assume !(0 == ~T3_E~0); 9835498#L1021-1 assume !(0 == ~T4_E~0); 9834088#L1026-1 assume !(0 == ~T5_E~0); 9834089#L1031-1 assume !(0 == ~T6_E~0); 9835038#L1036-1 assume !(0 == ~T7_E~0); 9835035#L1041-1 assume !(0 == ~T8_E~0); 9835036#L1046-1 assume !(0 == ~T9_E~0); 9834392#L1051-1 assume !(0 == ~T10_E~0); 9834393#L1056-1 assume !(0 == ~E_1~0); 9835197#L1061-1 assume !(0 == ~E_2~0); 9834313#L1066-1 assume !(0 == ~E_3~0); 9834314#L1071-1 assume !(0 == ~E_4~0); 9835167#L1076-1 assume !(0 == ~E_5~0); 9834216#L1081-1 assume !(0 == ~E_6~0); 9834217#L1086-1 assume !(0 == ~E_7~0); 9834542#L1091-1 assume !(0 == ~E_8~0); 9835449#L1096-1 assume !(0 == ~E_9~0); 9835450#L1101-1 assume !(0 == ~E_10~0); 9834620#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9834621#L484 assume !(1 == ~m_pc~0); 9834269#L484-2 is_master_triggered_~__retres1~0#1 := 0; 9834735#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9834937#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9835316#L1245 assume !(0 != activate_threads_~tmp~1#1); 9835317#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9835027#L503 assume !(1 == ~t1_pc~0); 9835028#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 9835244#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9834128#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9834129#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 9834124#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9834125#L522 assume !(1 == ~t2_pc~0); 9834981#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 9834982#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9834613#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9834614#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 9835390#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9835515#L541 assume !(1 == ~t3_pc~0); 9834688#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 9834689#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9834074#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9834075#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 9834990#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9834991#L560 assume !(1 == ~t4_pc~0); 9834201#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 9834881#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9834232#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9834086#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 9834087#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9834370#L579 assume !(1 == ~t5_pc~0); 9834371#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 9834151#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9834152#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9835321#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 9835496#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9835540#L598 assume !(1 == ~t6_pc~0); 9835213#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 9834793#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9834586#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9834587#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 9835078#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9835016#L617 assume !(1 == ~t7_pc~0); 9834434#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 9834874#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9835586#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9835410#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 9834653#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9834654#L636 assume !(1 == ~t8_pc~0); 9835075#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 9835306#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9835245#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9835086#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 9834801#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9834802#L655 assume !(1 == ~t9_pc~0); 9834830#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 9835286#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9834699#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9834700#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 9835098#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9835099#L674 assume !(1 == ~t10_pc~0); 9835463#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 9835517#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9834844#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9834845#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 9835645#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9835644#L1119 assume !(1 == ~M_E~0); 9835643#L1119-2 assume !(1 == ~T1_E~0); 9835642#L1124-1 assume !(1 == ~T2_E~0); 9834114#L1129-1 assume !(1 == ~T3_E~0); 9834115#L1134-1 assume !(1 == ~T4_E~0); 9835640#L1139-1 assume !(1 == ~T5_E~0); 9835639#L1144-1 assume !(1 == ~T6_E~0); 9835638#L1149-1 assume !(1 == ~T7_E~0); 9835637#L1154-1 assume !(1 == ~T8_E~0); 9835636#L1159-1 assume !(1 == ~T9_E~0); 9835635#L1164-1 assume !(1 == ~T10_E~0); 9834820#L1169-1 assume !(1 == ~E_1~0); 9834821#L1174-1 assume !(1 == ~E_2~0); 9835634#L1179-1 assume !(1 == ~E_3~0); 9835633#L1184-1 assume !(1 == ~E_4~0); 9835632#L1189-1 assume !(1 == ~E_5~0); 9835631#L1194-1 assume !(1 == ~E_6~0); 9835630#L1199-1 assume !(1 == ~E_7~0); 9835629#L1204-1 assume !(1 == ~E_8~0); 9835626#L1209-1 assume !(1 == ~E_9~0); 9835096#L1214-1 assume !(1 == ~E_10~0); 9835097#L1219-1 assume { :end_inline_reset_delta_events } true; 9835598#L1520-2 [2023-11-29 02:56:31,873 INFO L750 eck$LassoCheckResult]: Loop: 9835598#L1520-2 assume !false; 9845523#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 9845518#L981-1 assume !false; 9845516#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9845513#L764 assume !(0 == ~m_st~0); 9845514#L768 assume !(0 == ~t1_st~0); 9846238#L772 assume !(0 == ~t2_st~0); 9846234#L776 assume !(0 == ~t3_st~0); 9846233#L780 assume !(0 == ~t4_st~0); 9846231#L784 assume !(0 == ~t5_st~0); 9846227#L788 assume !(0 == ~t6_st~0); 9846223#L792 assume !(0 == ~t7_st~0); 9846220#L796 assume !(0 == ~t8_st~0); 9846217#L800 assume !(0 == ~t9_st~0); 9846214#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 9846211#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9846209#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 9846206#L836 assume !(0 != eval_~tmp~0#1); 9846203#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 9846201#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 9846199#L1006-3 assume !(0 == ~M_E~0); 9846198#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 9846197#L1011-3 assume !(0 == ~T2_E~0); 9846195#L1016-3 assume !(0 == ~T3_E~0); 9846193#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 9846192#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 9846191#L1031-3 assume !(0 == ~T6_E~0); 9846189#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 9846186#L1041-3 assume !(0 == ~T8_E~0); 9846184#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 9846182#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 9846177#L1056-3 assume !(0 == ~E_1~0); 9846175#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 9846173#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 9846171#L1071-3 assume !(0 == ~E_4~0); 9846169#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 9846167#L1081-3 assume !(0 == ~E_6~0); 9846165#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 9846163#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 9846162#L1096-3 assume !(0 == ~E_9~0); 9846158#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 9846156#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 9846154#L484-33 assume 1 == ~m_pc~0; 9846151#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 9846148#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 9846146#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 9846143#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 9846141#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 9846139#L503-33 assume !(1 == ~t1_pc~0); 9846137#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 9846135#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 9846133#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 9846130#L1253-33 assume !(0 != activate_threads_~tmp___0~0#1); 9846128#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 9846126#L522-33 assume 1 == ~t2_pc~0; 9846124#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 9846125#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 9846878#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 9846115#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 9846113#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 9846111#L541-33 assume !(1 == ~t3_pc~0); 9846109#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 9846107#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 9846105#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 9846103#L1269-33 assume !(0 != activate_threads_~tmp___2~0#1); 9846101#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 9846099#L560-33 assume !(1 == ~t4_pc~0); 9846096#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 9846094#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 9846092#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 9846088#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 9846086#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 9846084#L579-33 assume !(1 == ~t5_pc~0); 9846082#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 9846079#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 9846077#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 9846075#L1285-33 assume !(0 != activate_threads_~tmp___4~0#1); 9846073#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 9846071#L598-33 assume !(1 == ~t6_pc~0); 9846069#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 9846067#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 9846065#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 9846064#L1293-33 assume !(0 != activate_threads_~tmp___5~0#1); 9846060#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 9846058#L617-33 assume !(1 == ~t7_pc~0); 9846054#L617-35 is_transmit7_triggered_~__retres1~7#1 := 0; 9846052#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 9846050#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 9846048#L1301-33 assume !(0 != activate_threads_~tmp___6~0#1); 9846045#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 9846043#L636-33 assume !(1 == ~t8_pc~0); 9846041#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 9846039#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 9846037#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 9846035#L1309-33 assume !(0 != activate_threads_~tmp___7~0#1); 9846034#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 9846033#L655-33 assume 1 == ~t9_pc~0; 9846032#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 9845627#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 9845625#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 9845621#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 9845618#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 9845616#L674-33 assume !(1 == ~t10_pc~0); 9845614#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 9845612#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 9845610#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 9845608#L1325-33 assume 0 != activate_threads_~tmp___9~0#1;~t10_st~0 := 0; 9845606#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 9845604#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 9845602#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 9845600#L1124-3 assume !(1 == ~T2_E~0); 9845598#L1129-3 assume !(1 == ~T3_E~0); 9845596#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 9845594#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 9845592#L1144-3 assume !(1 == ~T6_E~0); 9845590#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 9845588#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 9845586#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 9845584#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 9845582#L1169-3 assume !(1 == ~E_1~0); 9845580#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 9845578#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 9845576#L1184-3 assume !(1 == ~E_4~0); 9845574#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 9845572#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 9845570#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 9845568#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 9845566#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 9845563#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 9845561#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9845558#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 9845555#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9845553#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 9845551#L1539 assume !(0 == start_simulation_~tmp~3#1); 9845546#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 9845543#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 9845541#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 9845540#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 9845537#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 9845536#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 9845535#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 9845532#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 9835598#L1520-2 [2023-11-29 02:56:31,873 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:31,873 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 13 times [2023-11-29 02:56:31,873 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:31,873 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [2079647396] [2023-11-29 02:56:31,873 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:31,873 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:31,880 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:31,880 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:56:31,886 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:31,908 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:56:31,908 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:31,908 INFO L85 PathProgramCache]: Analyzing trace with hash -1493339656, now seen corresponding path program 1 times [2023-11-29 02:56:31,909 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:31,909 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [138743819] [2023-11-29 02:56:31,909 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:31,909 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:31,918 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:56:31,959 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:56:31,959 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:56:31,960 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [138743819] [2023-11-29 02:56:31,960 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [138743819] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:56:31,960 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:56:31,960 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [5] imperfect sequences [] total 5 [2023-11-29 02:56:31,960 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [252474357] [2023-11-29 02:56:31,960 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:56:31,961 INFO L765 eck$LassoCheckResult]: loop already infeasible [2023-11-29 02:56:31,961 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:56:31,961 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 5 interpolants. [2023-11-29 02:56:31,961 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=7, Invalid=13, Unknown=0, NotChecked=0, Total=20 [2023-11-29 02:56:31,961 INFO L87 Difference]: Start difference. First operand 238986 states and 309964 transitions. cyclomatic complexity: 71042 Second operand has 5 states, 5 states have (on average 28.4) internal successors, (142), 5 states have internal predecessors, (142), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:33,329 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:56:33,329 INFO L93 Difference]: Finished difference Result 357034 states and 460170 transitions. [2023-11-29 02:56:33,329 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 357034 states and 460170 transitions. [2023-11-29 02:56:34,837 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 355136 [2023-11-29 02:56:35,314 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 357034 states to 357034 states and 460170 transitions. [2023-11-29 02:56:35,315 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 357034 [2023-11-29 02:56:35,423 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 357034 [2023-11-29 02:56:35,423 INFO L73 IsDeterministic]: Start isDeterministic. Operand 357034 states and 460170 transitions. [2023-11-29 02:56:35,509 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is deterministic. [2023-11-29 02:56:35,509 INFO L218 hiAutomatonCegarLoop]: Abstraction has 357034 states and 460170 transitions. [2023-11-29 02:56:35,643 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 357034 states and 460170 transitions. [2023-11-29 02:56:37,551 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 357034 to 242346. [2023-11-29 02:56:37,656 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 242346 states, 242346 states have (on average 1.2882490323751992) internal successors, (312202), 242345 states have internal predecessors, (312202), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:38,032 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 242346 states to 242346 states and 312202 transitions. [2023-11-29 02:56:38,032 INFO L240 hiAutomatonCegarLoop]: Abstraction has 242346 states and 312202 transitions. [2023-11-29 02:56:38,032 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 7 states. [2023-11-29 02:56:38,033 INFO L428 stractBuchiCegarLoop]: Abstraction has 242346 states and 312202 transitions. [2023-11-29 02:56:38,033 INFO L335 stractBuchiCegarLoop]: ======== Iteration 38 ============ [2023-11-29 02:56:38,033 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 242346 states and 312202 transitions. [2023-11-29 02:56:38,560 INFO L131 ngComponentsAnalysis]: Automaton has 64 accepting balls. 241024 [2023-11-29 02:56:38,560 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:56:38,560 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:56:38,561 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:38,561 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:56:38,561 INFO L748 eck$LassoCheckResult]: Stem: 10430434#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 10430435#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 10431465#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 10431466#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 10431604#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 10431595#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 10431596#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 10430600#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 10430342#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 10430343#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 10431416#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 10431417#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 10431389#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 10431390#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 10431453#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 10430392#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 10430393#L1006 assume !(0 == ~M_E~0); 10430241#L1006-2 assume !(0 == ~T1_E~0); 10430242#L1011-1 assume !(0 == ~T2_E~0); 10431498#L1016-1 assume !(0 == ~T3_E~0); 10431532#L1021-1 assume !(0 == ~T4_E~0); 10430120#L1026-1 assume !(0 == ~T5_E~0); 10430121#L1031-1 assume !(0 == ~T6_E~0); 10431066#L1036-1 assume !(0 == ~T7_E~0); 10431063#L1041-1 assume !(0 == ~T8_E~0); 10431064#L1046-1 assume !(0 == ~T9_E~0); 10430425#L1051-1 assume !(0 == ~T10_E~0); 10430426#L1056-1 assume !(0 == ~E_1~0); 10431235#L1061-1 assume !(0 == ~E_2~0); 10430346#L1066-1 assume !(0 == ~E_3~0); 10430347#L1071-1 assume !(0 == ~E_4~0); 10431204#L1076-1 assume !(0 == ~E_5~0); 10430248#L1081-1 assume !(0 == ~E_6~0); 10430249#L1086-1 assume !(0 == ~E_7~0); 10430574#L1091-1 assume !(0 == ~E_8~0); 10431481#L1096-1 assume !(0 == ~E_9~0); 10431482#L1101-1 assume !(0 == ~E_10~0); 10430650#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10430651#L484 assume !(1 == ~m_pc~0); 10430300#L484-2 is_master_triggered_~__retres1~0#1 := 0; 10430766#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10430968#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10431343#L1245 assume !(0 != activate_threads_~tmp~1#1); 10431344#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10431054#L503 assume !(1 == ~t1_pc~0); 10431055#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 10431278#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10430160#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10430161#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 10430156#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10430157#L522 assume !(1 == ~t2_pc~0); 10431014#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 10431015#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10430644#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10430645#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 10431418#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10431552#L541 assume !(1 == ~t3_pc~0); 10430716#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 10430717#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10430104#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10430105#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 10431021#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10431022#L560 assume !(1 == ~t4_pc~0); 10430233#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 10430910#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10430264#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10430118#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 10430119#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10430403#L579 assume !(1 == ~t5_pc~0); 10430404#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 10430183#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10430184#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10431350#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 10431529#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10431571#L598 assume !(1 == ~t6_pc~0); 10431250#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 10430823#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10430617#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10430618#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 10431106#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10431045#L617 assume !(1 == ~t7_pc~0); 10430465#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 10430902#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10431617#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10431438#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 10430683#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10430684#L636 assume !(1 == ~t8_pc~0); 10431103#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 10431334#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10431279#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10431116#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 10430830#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10430831#L655 assume !(1 == ~t9_pc~0); 10430860#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 10431317#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10430727#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10430728#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 10431132#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10431133#L674 assume !(1 == ~t10_pc~0); 10431489#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 10431555#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10430874#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10430875#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 10431673#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10431672#L1119 assume !(1 == ~M_E~0); 10431671#L1119-2 assume !(1 == ~T1_E~0); 10431670#L1124-1 assume !(1 == ~T2_E~0); 10430146#L1129-1 assume !(1 == ~T3_E~0); 10430147#L1134-1 assume !(1 == ~T4_E~0); 10431668#L1139-1 assume !(1 == ~T5_E~0); 10431667#L1144-1 assume !(1 == ~T6_E~0); 10431666#L1149-1 assume !(1 == ~T7_E~0); 10431665#L1154-1 assume !(1 == ~T8_E~0); 10431664#L1159-1 assume !(1 == ~T9_E~0); 10431663#L1164-1 assume !(1 == ~T10_E~0); 10430850#L1169-1 assume !(1 == ~E_1~0); 10430851#L1174-1 assume !(1 == ~E_2~0); 10431662#L1179-1 assume !(1 == ~E_3~0); 10431661#L1184-1 assume !(1 == ~E_4~0); 10431660#L1189-1 assume !(1 == ~E_5~0); 10431659#L1194-1 assume !(1 == ~E_6~0); 10431658#L1199-1 assume !(1 == ~E_7~0); 10431657#L1204-1 assume !(1 == ~E_8~0); 10431654#L1209-1 assume !(1 == ~E_9~0); 10431130#L1214-1 assume !(1 == ~E_10~0); 10431131#L1219-1 assume { :end_inline_reset_delta_events } true; 10431629#L1520-2 [2023-11-29 02:56:38,562 INFO L750 eck$LassoCheckResult]: Loop: 10431629#L1520-2 assume !false; 10446716#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 10446713#L981-1 assume !false; 10446711#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 10446708#L764 assume !(0 == ~m_st~0); 10446709#L768 assume !(0 == ~t1_st~0); 10447466#L772 assume !(0 == ~t2_st~0); 10447464#L776 assume !(0 == ~t3_st~0); 10447462#L780 assume !(0 == ~t4_st~0); 10447460#L784 assume !(0 == ~t5_st~0); 10447456#L788 assume !(0 == ~t6_st~0); 10447454#L792 assume !(0 == ~t7_st~0); 10447452#L796 assume !(0 == ~t8_st~0); 10447450#L800 assume !(0 == ~t9_st~0); 10447447#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 10447445#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10447443#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 10447441#L836 assume !(0 != eval_~tmp~0#1); 10447439#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 10447437#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 10447435#L1006-3 assume !(0 == ~M_E~0); 10447433#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 10447431#L1011-3 assume !(0 == ~T2_E~0); 10447429#L1016-3 assume !(0 == ~T3_E~0); 10447427#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 10447425#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 10447423#L1031-3 assume !(0 == ~T6_E~0); 10447421#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 10447419#L1041-3 assume !(0 == ~T8_E~0); 10447417#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 10447415#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 10447413#L1056-3 assume !(0 == ~E_1~0); 10447411#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 10447409#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 10447407#L1071-3 assume !(0 == ~E_4~0); 10447405#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 10447403#L1081-3 assume !(0 == ~E_6~0); 10447401#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 10447399#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 10447397#L1096-3 assume !(0 == ~E_9~0); 10447395#L1101-3 assume 0 == ~E_10~0;~E_10~0 := 1; 10447392#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 10447390#L484-33 assume 1 == ~m_pc~0; 10447388#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 10447387#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 10447385#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 10447383#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 10447382#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 10447381#L503-33 assume !(1 == ~t1_pc~0); 10447380#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 10447379#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 10447377#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 10447376#L1253-33 assume !(0 != activate_threads_~tmp___0~0#1); 10447375#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 10447373#L522-33 assume !(1 == ~t2_pc~0); 10447372#L522-35 is_transmit2_triggered_~__retres1~2#1 := 0; 10467984#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 10467982#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 10447127#L1261-33 assume !(0 != activate_threads_~tmp___1~0#1); 10447124#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 10447122#L541-33 assume !(1 == ~t3_pc~0); 10447120#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 10447118#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 10447116#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 10447114#L1269-33 assume !(0 != activate_threads_~tmp___2~0#1); 10447112#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 10447110#L560-33 assume !(1 == ~t4_pc~0); 10447107#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 10447105#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 10447103#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 10447101#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 10447099#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 10447097#L579-33 assume !(1 == ~t5_pc~0); 10447094#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 10447092#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 10447090#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 10447087#L1285-33 assume !(0 != activate_threads_~tmp___4~0#1); 10447085#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 10447083#L598-33 assume !(1 == ~t6_pc~0); 10447081#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 10447079#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 10447077#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 10447075#L1293-33 assume !(0 != activate_threads_~tmp___5~0#1); 10447073#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 10447069#L617-33 assume 1 == ~t7_pc~0; 10447067#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 10447068#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 10447378#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 10447057#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 10447055#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 10447053#L636-33 assume !(1 == ~t8_pc~0); 10447051#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 10447049#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 10447047#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 10447045#L1309-33 assume !(0 != activate_threads_~tmp___7~0#1); 10447043#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 10447040#L655-33 assume 1 == ~t9_pc~0; 10447039#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 10446968#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 10446966#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 10446964#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 10446961#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 10446959#L674-33 assume !(1 == ~t10_pc~0); 10446957#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 10446955#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 10446953#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 10446951#L1325-33 assume !(0 != activate_threads_~tmp___9~0#1); 10446949#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 10446946#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 10446944#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 10446942#L1124-3 assume !(1 == ~T2_E~0); 10446939#L1129-3 assume !(1 == ~T3_E~0); 10446937#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 10446935#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 10446933#L1144-3 assume !(1 == ~T6_E~0); 10446931#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 10446929#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 10446927#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 10446925#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 10446923#L1169-3 assume !(1 == ~E_1~0); 10446921#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 10446919#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 10446917#L1184-3 assume !(1 == ~E_4~0); 10446915#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 10446913#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 10446911#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 10446909#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 10446907#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 10446904#L1214-3 assume 1 == ~E_10~0;~E_10~0 := 2; 10446902#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 10446899#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10446897#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10446895#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 10446892#L1539 assume !(0 == start_simulation_~tmp~3#1); 10446889#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 10446886#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 10446884#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 10446881#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 10446879#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 10446877#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 10446875#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 10446873#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 10431629#L1520-2 [2023-11-29 02:56:38,562 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:38,562 INFO L85 PathProgramCache]: Analyzing trace with hash 2061957225, now seen corresponding path program 14 times [2023-11-29 02:56:38,562 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:38,562 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1039713127] [2023-11-29 02:56:38,562 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:38,563 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:38,572 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:38,572 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:56:38,579 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:38,614 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:56:38,614 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:38,615 INFO L85 PathProgramCache]: Analyzing trace with hash 1995952630, now seen corresponding path program 1 times [2023-11-29 02:56:38,615 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:38,615 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1911384514] [2023-11-29 02:56:38,615 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:38,615 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:39,020 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:39,020 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:56:39,030 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:56:39,128 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:56:39,128 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:39,129 INFO L85 PathProgramCache]: Analyzing trace with hash 1491170398, now seen corresponding path program 1 times [2023-11-29 02:56:39,129 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:56:39,129 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1828112128] [2023-11-29 02:56:39,129 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:56:39,129 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:56:39,145 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:56:39,226 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:56:39,226 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:56:39,226 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [1828112128] [2023-11-29 02:56:39,226 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [1828112128] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:56:39,226 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:56:39,227 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [3] imperfect sequences [] total 3 [2023-11-29 02:56:39,227 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [1723061318] [2023-11-29 02:56:39,227 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:56:41,914 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 02:56:41,915 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 02:56:41,915 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 02:56:41,915 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 02:56:41,915 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-29 02:56:41,915 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:41,915 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 02:56:41,916 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 02:56:41,916 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.10.cil.c_Iteration38_Loop [2023-11-29 02:56:41,916 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 02:56:41,916 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 02:56:41,944 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,953 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,956 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,958 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,959 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,962 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,963 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,965 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,968 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,970 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,972 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,973 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,975 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,977 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,979 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,981 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,983 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,988 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,989 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,994 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,997 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:41,999 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,002 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,003 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,004 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,006 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,007 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,009 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,011 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,014 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,015 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,019 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,020 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,022 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,023 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,024 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,026 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,028 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,030 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,032 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,034 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,036 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,039 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,043 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,044 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,046 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,047 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,050 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,051 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,053 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,054 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,055 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,057 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,058 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,064 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,066 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,067 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,069 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,071 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,072 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,074 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,077 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,080 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,081 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,083 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,085 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,087 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,090 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,091 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,094 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,096 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,098 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,099 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,103 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,104 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,107 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,109 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,111 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,113 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,117 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,119 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,121 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,125 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,127 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,129 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,130 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,132 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,134 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,136 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,137 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,139 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,143 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,144 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,146 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,147 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,149 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,151 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,153 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,155 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,156 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,158 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,160 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,162 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,166 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,169 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,173 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,174 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,177 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,179 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,180 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,182 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,183 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,187 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,188 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,189 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,190 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,192 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,193 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,194 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,197 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,199 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,201 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:42,799 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 02:56:42,800 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-29 02:56:42,801 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:42,802 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:42,803 INFO L229 MonitoredProcess]: Starting monitored process 2 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:42,804 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Waiting until timeout for monitored process [2023-11-29 02:56:42,805 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:42,805 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:42,828 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:42,828 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:42,831 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (2)] Forceful destruction successful, exit code 0 [2023-11-29 02:56:42,832 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:42,832 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:42,833 INFO L229 MonitoredProcess]: Starting monitored process 3 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:42,835 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Waiting until timeout for monitored process [2023-11-29 02:56:42,835 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:42,835 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:42,847 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:42,847 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Honda state: {ULTIMATE.start_exists_runnable_thread_#res#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:42,850 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (3)] Ended with exit code 0 [2023-11-29 02:56:42,851 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:42,851 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:42,851 INFO L229 MonitoredProcess]: Starting monitored process 4 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:42,852 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Waiting until timeout for monitored process [2023-11-29 02:56:42,854 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:42,854 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:42,867 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:42,867 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret17#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret17#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:42,869 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (4)] Ended with exit code 0 [2023-11-29 02:56:42,869 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:42,869 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:42,870 INFO L229 MonitoredProcess]: Starting monitored process 5 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:42,871 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Waiting until timeout for monitored process [2023-11-29 02:56:42,872 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:42,872 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:42,884 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:42,884 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_2~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:42,887 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (5)] Ended with exit code 0 [2023-11-29 02:56:42,887 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:42,887 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:42,888 INFO L229 MonitoredProcess]: Starting monitored process 6 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:42,889 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Waiting until timeout for monitored process [2023-11-29 02:56:42,899 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:42,899 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:42,917 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:42,917 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_pc~0=4} Honda state: {~t4_pc~0=4} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:42,919 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (6)] Ended with exit code 0 [2023-11-29 02:56:42,919 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:42,920 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:42,920 INFO L229 MonitoredProcess]: Starting monitored process 7 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:42,922 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Waiting until timeout for monitored process [2023-11-29 02:56:42,923 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:42,923 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:42,936 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:42,937 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_#t~nondet7#1=0} Honda state: {ULTIMATE.start_eval_#t~nondet7#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:42,943 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (7)] Ended with exit code 0 [2023-11-29 02:56:42,944 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:42,944 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:42,945 INFO L229 MonitoredProcess]: Starting monitored process 8 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:42,947 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Waiting until timeout for monitored process [2023-11-29 02:56:42,948 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:42,948 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:42,961 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:42,961 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit9_triggered_~__retres1~9#1=0} Honda state: {ULTIMATE.start_is_transmit9_triggered_~__retres1~9#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:42,964 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (8)] Ended with exit code 0 [2023-11-29 02:56:42,964 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:42,964 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:42,965 INFO L229 MonitoredProcess]: Starting monitored process 9 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:42,966 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Waiting until timeout for monitored process [2023-11-29 02:56:42,967 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:42,967 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:42,979 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:42,979 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Honda state: {ULTIMATE.start_start_simulation_~tmp~3#1=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:42,982 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (9)] Forceful destruction successful, exit code 0 [2023-11-29 02:56:42,982 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:42,982 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:42,983 INFO L229 MonitoredProcess]: Starting monitored process 10 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:42,984 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Waiting until timeout for monitored process [2023-11-29 02:56:42,985 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:42,986 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:42,997 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:42,997 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit10_triggered_~__retres1~10#1=0} Honda state: {ULTIMATE.start_is_transmit10_triggered_~__retres1~10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:42,999 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (10)] Ended with exit code 0 [2023-11-29 02:56:42,999 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:43,000 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:43,000 INFO L229 MonitoredProcess]: Starting monitored process 11 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:43,001 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Waiting until timeout for monitored process [2023-11-29 02:56:43,002 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:43,003 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:43,014 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:43,014 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit6_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit6_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:43,016 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (11)] Ended with exit code 0 [2023-11-29 02:56:43,016 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:43,016 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:43,017 INFO L229 MonitoredProcess]: Starting monitored process 12 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:43,018 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Waiting until timeout for monitored process [2023-11-29 02:56:43,019 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:43,019 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:43,030 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:43,030 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret26#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret26#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:43,032 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (12)] Forceful destruction successful, exit code 0 [2023-11-29 02:56:43,033 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:43,033 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:43,033 INFO L229 MonitoredProcess]: Starting monitored process 13 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:43,034 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Waiting until timeout for monitored process [2023-11-29 02:56:43,036 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:43,036 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:43,053 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:43,053 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t1_st~0=-1} Honda state: {~t1_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:43,055 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (13)] Forceful destruction successful, exit code 0 [2023-11-29 02:56:43,055 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:43,056 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:43,056 INFO L229 MonitoredProcess]: Starting monitored process 14 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:43,057 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Waiting until timeout for monitored process [2023-11-29 02:56:43,058 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:43,058 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:43,070 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:43,070 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit10_triggered_#res#1=0} Honda state: {ULTIMATE.start_is_transmit10_triggered_#res#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:43,073 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (14)] Ended with exit code 0 [2023-11-29 02:56:43,073 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:43,073 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:43,074 INFO L229 MonitoredProcess]: Starting monitored process 15 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:43,075 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Waiting until timeout for monitored process [2023-11-29 02:56:43,076 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:43,076 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:43,087 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:43,088 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Honda state: {ULTIMATE.start_activate_threads_~tmp~1#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:43,090 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (15)] Ended with exit code 0 [2023-11-29 02:56:43,090 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:43,090 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:43,091 INFO L229 MonitoredProcess]: Starting monitored process 16 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:43,091 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Waiting until timeout for monitored process [2023-11-29 02:56:43,093 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:43,093 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:43,104 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:43,104 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_eval_~tmp_ndt_9~0#1=0} Honda state: {ULTIMATE.start_eval_~tmp_ndt_9~0#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:43,106 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (16)] Ended with exit code 0 [2023-11-29 02:56:43,106 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:43,107 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:43,107 INFO L229 MonitoredProcess]: Starting monitored process 17 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:43,108 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Waiting until timeout for monitored process [2023-11-29 02:56:43,109 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:43,110 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:43,121 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:56:43,121 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t7_pc~0=1} Honda state: {~t7_pc~0=1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:56:43,123 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (17)] Ended with exit code 0 [2023-11-29 02:56:43,123 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:43,123 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:43,124 INFO L229 MonitoredProcess]: Starting monitored process 18 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:43,125 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Waiting until timeout for monitored process [2023-11-29 02:56:43,126 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:56:43,126 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:43,140 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (18)] Ended with exit code 0 [2023-11-29 02:56:43,140 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:43,140 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:43,141 INFO L229 MonitoredProcess]: Starting monitored process 19 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:43,141 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Waiting until timeout for monitored process [2023-11-29 02:56:43,143 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-29 02:56:43,143 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:56:43,156 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-29 02:56:43,158 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (19)] Ended with exit code 0 [2023-11-29 02:56:43,163 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 02:56:43,163 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 02:56:43,163 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 02:56:43,163 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 02:56:43,163 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-29 02:56:43,163 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:43,163 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 02:56:43,163 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 02:56:43,163 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.10.cil.c_Iteration38_Loop [2023-11-29 02:56:43,163 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 02:56:43,163 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 02:56:43,170 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,172 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,175 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,177 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,179 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,182 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,184 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,185 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,187 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,190 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,192 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,194 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,197 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,199 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,201 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,203 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,205 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,209 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,212 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,215 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,217 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,218 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,222 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,224 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,226 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,227 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,229 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,231 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,234 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,236 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,239 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,241 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,242 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,244 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,245 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,247 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,249 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,250 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,252 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,254 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,258 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,261 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,263 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,265 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,266 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,270 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,271 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,273 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,275 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,277 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,279 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,280 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,282 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,285 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,287 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,289 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,291 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,293 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,295 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,299 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,301 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,306 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,308 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,310 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,312 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,314 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,317 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,322 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,327 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,328 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,331 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,334 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,337 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,339 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,345 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,347 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,350 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,352 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,355 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,359 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,362 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,364 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,366 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,371 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,373 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,375 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,377 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,379 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,381 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,383 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,386 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,387 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,389 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,393 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,394 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,396 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,606 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,608 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,609 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,610 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,613 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,616 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,618 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,621 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,623 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,624 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,628 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,629 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,630 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,632 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,637 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,638 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,642 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,645 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,649 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,651 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:43,653 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:56:44,247 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 02:56:44,252 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-29 02:56:44,253 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,254 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,254 INFO L229 MonitoredProcess]: Starting monitored process 20 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,260 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Waiting until timeout for monitored process [2023-11-29 02:56:44,260 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,270 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,271 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,271 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,272 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 02:56:44,272 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,273 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 02:56:44,274 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,276 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,279 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (20)] Ended with exit code 0 [2023-11-29 02:56:44,279 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,280 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,280 INFO L229 MonitoredProcess]: Starting monitored process 21 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,281 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Waiting until timeout for monitored process [2023-11-29 02:56:44,283 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,292 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,292 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,292 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,292 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,293 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,293 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,293 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,295 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,302 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (21)] Ended with exit code 0 [2023-11-29 02:56:44,302 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,302 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,303 INFO L229 MonitoredProcess]: Starting monitored process 22 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,304 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Waiting until timeout for monitored process [2023-11-29 02:56:44,305 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,315 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,315 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,315 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,315 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,315 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,316 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,316 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,317 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,320 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (22)] Ended with exit code 0 [2023-11-29 02:56:44,320 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,321 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,321 INFO L229 MonitoredProcess]: Starting monitored process 23 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,322 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Waiting until timeout for monitored process [2023-11-29 02:56:44,323 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,333 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,333 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,333 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,333 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,333 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,334 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,334 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,335 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,337 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (23)] Forceful destruction successful, exit code 0 [2023-11-29 02:56:44,337 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,337 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,338 INFO L229 MonitoredProcess]: Starting monitored process 24 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,340 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Waiting until timeout for monitored process [2023-11-29 02:56:44,340 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,350 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,350 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,350 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,350 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 02:56:44,350 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,351 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 02:56:44,351 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,353 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,355 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (24)] Forceful destruction successful, exit code 0 [2023-11-29 02:56:44,355 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,355 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,356 INFO L229 MonitoredProcess]: Starting monitored process 25 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,357 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Waiting until timeout for monitored process [2023-11-29 02:56:44,358 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,368 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,368 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,368 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,368 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,368 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,368 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,368 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,370 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,373 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (25)] Forceful destruction successful, exit code 0 [2023-11-29 02:56:44,373 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,373 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,374 INFO L229 MonitoredProcess]: Starting monitored process 26 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,375 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Waiting until timeout for monitored process [2023-11-29 02:56:44,376 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,385 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,385 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,385 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,386 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,386 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,386 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,386 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,387 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,389 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (26)] Ended with exit code 0 [2023-11-29 02:56:44,390 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,390 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,390 INFO L229 MonitoredProcess]: Starting monitored process 27 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,391 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Waiting until timeout for monitored process [2023-11-29 02:56:44,392 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,404 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,404 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,404 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,404 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,405 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,405 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,405 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,406 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,409 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (27)] Ended with exit code 0 [2023-11-29 02:56:44,409 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,409 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,410 INFO L229 MonitoredProcess]: Starting monitored process 28 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,411 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Waiting until timeout for monitored process [2023-11-29 02:56:44,412 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,422 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,422 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,422 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,422 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,422 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,423 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,423 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,424 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,426 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (28)] Forceful destruction successful, exit code 0 [2023-11-29 02:56:44,426 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,426 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,427 INFO L229 MonitoredProcess]: Starting monitored process 29 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,428 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Waiting until timeout for monitored process [2023-11-29 02:56:44,429 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,439 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,439 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,439 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,439 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,439 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,439 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,439 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,441 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,443 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (29)] Ended with exit code 0 [2023-11-29 02:56:44,443 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,443 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,444 INFO L229 MonitoredProcess]: Starting monitored process 30 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,445 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Waiting until timeout for monitored process [2023-11-29 02:56:44,446 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,455 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,456 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,456 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,456 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,456 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,456 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,456 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,457 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,460 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (30)] Ended with exit code 0 [2023-11-29 02:56:44,460 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,460 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,461 INFO L229 MonitoredProcess]: Starting monitored process 31 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,461 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Waiting until timeout for monitored process [2023-11-29 02:56:44,463 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,472 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,473 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,473 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,473 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 02:56:44,473 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,474 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 02:56:44,474 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,475 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,478 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (31)] Ended with exit code 0 [2023-11-29 02:56:44,478 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,479 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,479 INFO L229 MonitoredProcess]: Starting monitored process 32 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,480 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Waiting until timeout for monitored process [2023-11-29 02:56:44,481 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,491 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,491 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,491 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,491 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,491 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,492 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,492 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,494 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,496 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (32)] Ended with exit code 0 [2023-11-29 02:56:44,496 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,496 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,497 INFO L229 MonitoredProcess]: Starting monitored process 33 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,497 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Waiting until timeout for monitored process [2023-11-29 02:56:44,498 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,508 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,508 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,508 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,508 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,508 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,509 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,509 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,510 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,512 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (33)] Ended with exit code 0 [2023-11-29 02:56:44,512 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,513 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,513 INFO L229 MonitoredProcess]: Starting monitored process 34 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,514 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Waiting until timeout for monitored process [2023-11-29 02:56:44,515 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,525 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,525 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,525 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,525 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,526 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,526 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,526 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,527 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,529 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (34)] Ended with exit code 0 [2023-11-29 02:56:44,529 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,529 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,530 INFO L229 MonitoredProcess]: Starting monitored process 35 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,531 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Waiting until timeout for monitored process [2023-11-29 02:56:44,532 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,542 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,542 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,542 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,542 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,542 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,543 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,543 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,544 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:56:44,546 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (35)] Ended with exit code 0 [2023-11-29 02:56:44,546 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,546 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,547 INFO L229 MonitoredProcess]: Starting monitored process 36 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,548 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Waiting until timeout for monitored process [2023-11-29 02:56:44,549 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:56:44,558 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:56:44,559 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:56:44,559 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:56:44,559 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:56:44,559 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:56:44,559 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:56:44,559 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:56:44,562 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-29 02:56:44,564 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-29 02:56:44,564 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-29 02:56:44,566 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:56:44,566 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:56:44,599 INFO L229 MonitoredProcess]: Starting monitored process 37 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:56:44,600 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Waiting until timeout for monitored process [2023-11-29 02:56:44,601 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-29 02:56:44,601 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-29 02:56:44,601 INFO L513 LassoAnalysis]: Proved termination. [2023-11-29 02:56:44,602 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~E_10~0) = -1*~E_10~0 + 1 Supporting invariants [] [2023-11-29 02:56:44,604 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (36)] Forceful destruction successful, exit code 0 [2023-11-29 02:56:44,606 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-29 02:56:44,623 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:56:44,705 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:56:44,708 INFO L262 TraceCheckSpWp]: Trace formula consists of 353 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-29 02:56:44,712 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 02:56:44,932 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:56:44,934 INFO L262 TraceCheckSpWp]: Trace formula consists of 307 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-29 02:56:44,939 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 02:56:45,323 INFO L134 CoverageAnalysis]: Checked inductivity of 0 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:56:45,329 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-29 02:56:45,330 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 242346 states and 312202 transitions. cyclomatic complexity: 69920 Second operand has 5 states, 5 states have (on average 53.6) internal successors, (268), 5 states have internal predecessors, (268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:46,955 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (37)] Ended with exit code 0 [2023-11-29 02:56:47,555 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 242346 states and 312202 transitions. cyclomatic complexity: 69920. Second operand has 5 states, 5 states have (on average 53.6) internal successors, (268), 5 states have internal predecessors, (268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 679084 states and 877453 transitions. Complement of second has 5 states. [2023-11-29 02:56:47,558 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-29 02:56:47,558 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 53.6) internal successors, (268), 5 states have internal predecessors, (268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:47,561 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1728 transitions. [2023-11-29 02:56:47,562 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1728 transitions. Stem has 126 letters. Loop has 142 letters. [2023-11-29 02:56:47,567 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 02:56:47,567 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1728 transitions. Stem has 268 letters. Loop has 142 letters. [2023-11-29 02:56:47,568 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 02:56:47,568 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1728 transitions. Stem has 126 letters. Loop has 284 letters. [2023-11-29 02:56:47,571 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 02:56:47,571 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 679084 states and 877453 transitions. [2023-11-29 02:56:50,051 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 457600 [2023-11-29 02:56:51,680 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 679084 states to 678828 states and 877197 transitions. [2023-11-29 02:56:51,680 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 460331 [2023-11-29 02:56:51,878 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 460716 [2023-11-29 02:56:51,879 INFO L73 IsDeterministic]: Start isDeterministic. Operand 678828 states and 877197 transitions. [2023-11-29 02:56:51,879 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 02:56:51,879 INFO L218 hiAutomatonCegarLoop]: Abstraction has 678828 states and 877197 transitions. [2023-11-29 02:56:52,174 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 678828 states and 877197 transitions. [2023-11-29 02:56:56,775 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 678828 to 678187. [2023-11-29 02:56:57,266 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 678187 states, 678187 states have (on average 1.2922158637661885) internal successors, (876364), 678186 states have internal predecessors, (876364), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:56:59,580 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678187 states to 678187 states and 876364 transitions. [2023-11-29 02:56:59,580 INFO L240 hiAutomatonCegarLoop]: Abstraction has 678187 states and 876364 transitions. [2023-11-29 02:56:59,580 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:56:59,581 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:56:59,581 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:56:59,581 INFO L87 Difference]: Start difference. First operand 678187 states and 876364 transitions. Second operand has 3 states, 3 states have (on average 89.33333333333333) internal successors, (268), 3 states have internal predecessors, (268), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:57:02,378 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:57:02,378 INFO L93 Difference]: Finished difference Result 711787 states and 915916 transitions. [2023-11-29 02:57:02,378 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 711787 states and 915916 transitions. [2023-11-29 02:57:04,921 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 480000 [2023-11-29 02:57:06,006 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 711787 states to 711787 states and 915916 transitions. [2023-11-29 02:57:06,006 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 482475 [2023-11-29 02:57:06,161 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 482475 [2023-11-29 02:57:06,161 INFO L73 IsDeterministic]: Start isDeterministic. Operand 711787 states and 915916 transitions. [2023-11-29 02:57:06,535 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 02:57:06,535 INFO L218 hiAutomatonCegarLoop]: Abstraction has 711787 states and 915916 transitions. [2023-11-29 02:57:06,811 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 711787 states and 915916 transitions. [2023-11-29 02:57:10,723 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 711787 to 678187. [2023-11-29 02:57:11,016 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 678187 states, 678187 states have (on average 1.2905172172276969) internal successors, (875212), 678186 states have internal predecessors, (875212), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:57:12,906 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 678187 states to 678187 states and 875212 transitions. [2023-11-29 02:57:12,906 INFO L240 hiAutomatonCegarLoop]: Abstraction has 678187 states and 875212 transitions. [2023-11-29 02:57:12,906 INFO L141 InterpolantAutomaton]: Switched to read-only mode: deterministic interpolant automaton has 3 states. [2023-11-29 02:57:12,907 INFO L428 stractBuchiCegarLoop]: Abstraction has 678187 states and 875212 transitions. [2023-11-29 02:57:12,907 INFO L335 stractBuchiCegarLoop]: ======== Iteration 39 ============ [2023-11-29 02:57:12,907 INFO L72 BuchiIsEmpty]: Start buchiIsEmpty. Operand 678187 states and 875212 transitions. [2023-11-29 02:57:14,587 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 457600 [2023-11-29 02:57:14,588 INFO L87 BuchiIsEmpty]: Finished buchiIsEmpty Result is false [2023-11-29 02:57:14,588 INFO L119 BuchiIsEmpty]: Starting construction of run [2023-11-29 02:57:14,589 INFO L148 hiAutomatonCegarLoop]: Counterexample stem histogram [1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:57:14,589 INFO L149 hiAutomatonCegarLoop]: Counterexample loop histogram [2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1] [2023-11-29 02:57:14,590 INFO L748 eck$LassoCheckResult]: Stem: 12742964#$Ultimate##0 assume { :begin_inline_ULTIMATE.init } true;assume 0 == #valid[0];assume 0 < #StackHeapBarrier;call #Ultimate.allocInit(2, 1);call write~init~int#0(48, 1, 0, 1);call write~init~int#0(0, 1, 1, 1);call #Ultimate.allocInit(21, 2);call #Ultimate.allocInit(12, 3);~m_pc~0 := 0;~t1_pc~0 := 0;~t2_pc~0 := 0;~t3_pc~0 := 0;~t4_pc~0 := 0;~t5_pc~0 := 0;~t6_pc~0 := 0;~t7_pc~0 := 0;~t8_pc~0 := 0;~t9_pc~0 := 0;~t10_pc~0 := 0;~m_st~0 := 0;~t1_st~0 := 0;~t2_st~0 := 0;~t3_st~0 := 0;~t4_st~0 := 0;~t5_st~0 := 0;~t6_st~0 := 0;~t7_st~0 := 0;~t8_st~0 := 0;~t9_st~0 := 0;~t10_st~0 := 0;~m_i~0 := 0;~t1_i~0 := 0;~t2_i~0 := 0;~t3_i~0 := 0;~t4_i~0 := 0;~t5_i~0 := 0;~t6_i~0 := 0;~t7_i~0 := 0;~t8_i~0 := 0;~t9_i~0 := 0;~t10_i~0 := 0;~M_E~0 := 2;~T1_E~0 := 2;~T2_E~0 := 2;~T3_E~0 := 2;~T4_E~0 := 2;~T5_E~0 := 2;~T6_E~0 := 2;~T7_E~0 := 2;~T8_E~0 := 2;~T9_E~0 := 2;~T10_E~0 := 2;~E_1~0 := 2;~E_2~0 := 2;~E_3~0 := 2;~E_4~0 := 2;~E_5~0 := 2;~E_6~0 := 2;~E_7~0 := 2;~E_8~0 := 2;~E_9~0 := 2;~E_10~0 := 2; 12742965#L-1 assume { :end_inline_ULTIMATE.init } true;assume { :begin_inline_main } true;havoc main_#res#1;havoc main_~__retres1~12#1;havoc main_~__retres1~12#1;assume { :begin_inline_init_model } true;~m_i~0 := 1;~t1_i~0 := 1;~t2_i~0 := 1;~t3_i~0 := 1;~t4_i~0 := 1;~t5_i~0 := 1;~t6_i~0 := 1;~t7_i~0 := 1;~t8_i~0 := 1;~t9_i~0 := 1;~t10_i~0 := 1; 12744985#init_model_returnLabel#1 assume { :end_inline_init_model } true;assume { :begin_inline_start_simulation } true;havoc start_simulation_#t~ret28#1, start_simulation_#t~ret29#1, start_simulation_~kernel_st~0#1, start_simulation_~tmp~3#1, start_simulation_~tmp___0~1#1;havoc start_simulation_~kernel_st~0#1;havoc start_simulation_~tmp~3#1;havoc start_simulation_~tmp___0~1#1;start_simulation_~kernel_st~0#1 := 0;assume { :begin_inline_update_channels } true; 12744986#update_channels_returnLabel#1 assume { :end_inline_update_channels } true;assume { :begin_inline_init_threads } true; 12745283#L701 assume 1 == ~m_i~0;~m_st~0 := 0; 12745257#L701-2 assume 1 == ~t1_i~0;~t1_st~0 := 0; 12745258#L706-1 assume 1 == ~t2_i~0;~t2_st~0 := 0; 12743282#L711-1 assume 1 == ~t3_i~0;~t3_st~0 := 0; 12742795#L716-1 assume 1 == ~t4_i~0;~t4_st~0 := 0; 12742796#L721-1 assume 1 == ~t5_i~0;~t5_st~0 := 0; 12744880#L726-1 assume 1 == ~t6_i~0;~t6_st~0 := 0; 12744881#L731-1 assume 1 == ~t7_i~0;~t7_st~0 := 0; 12744822#L736-1 assume 1 == ~t8_i~0;~t8_st~0 := 0; 12744823#L741-1 assume 1 == ~t9_i~0;~t9_st~0 := 0; 12744960#L746-1 assume 1 == ~t10_i~0;~t10_st~0 := 0; 12742896#L751-1 assume { :end_inline_init_threads } true;assume { :begin_inline_fire_delta_events } true; 12742897#L1006 assume !(0 == ~M_E~0); 12742620#L1006-2 assume !(0 == ~T1_E~0); 12742621#L1011-1 assume !(0 == ~T2_E~0); 12745047#L1016-1 assume !(0 == ~T3_E~0); 12745118#L1021-1 assume !(0 == ~T4_E~0); 12742398#L1026-1 assume !(0 == ~T5_E~0); 12742399#L1031-1 assume !(0 == ~T6_E~0); 12744160#L1036-1 assume !(0 == ~T7_E~0); 12744153#L1041-1 assume !(0 == ~T8_E~0); 12744154#L1046-1 assume !(0 == ~T9_E~0); 12742948#L1051-1 assume !(0 == ~T10_E~0); 12742949#L1056-1 assume !(0 == ~E_1~0); 12744480#L1061-1 assume !(0 == ~E_2~0); 12742801#L1066-1 assume !(0 == ~E_3~0); 12742802#L1071-1 assume !(0 == ~E_4~0); 12744423#L1076-1 assume !(0 == ~E_5~0); 12742629#L1081-1 assume !(0 == ~E_6~0); 12742630#L1086-1 assume !(0 == ~E_7~0); 12743233#L1091-1 assume !(0 == ~E_8~0); 12745015#L1096-1 assume !(0 == ~E_9~0); 12745016#L1101-1 assume !(0 == ~E_10~0); 12743377#L1106-1 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12743378#L484 assume !(1 == ~m_pc~0); 12742724#L484-2 is_master_triggered_~__retres1~0#1 := 0; 12743604#L495 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12744728#is_master_triggered_returnLabel#1 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12744715#L1245 assume !(0 != activate_threads_~tmp~1#1); 12744716#L1245-2 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12744139#L503 assume !(1 == ~t1_pc~0); 12744140#L503-2 is_transmit1_triggered_~__retres1~1#1 := 0; 12744569#L514 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12742472#is_transmit1_triggered_returnLabel#1 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12742473#L1253 assume !(0 != activate_threads_~tmp___0~0#1); 12742462#L1253-2 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12742463#L522 assume !(1 == ~t2_pc~0); 12744060#L522-2 is_transmit2_triggered_~__retres1~2#1 := 0; 12742825#L533 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12742826#is_transmit2_triggered_returnLabel#1 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12743366#L1261 assume !(0 != activate_threads_~tmp___1~0#1); 12744882#L1261-2 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12745149#L541 assume !(1 == ~t3_pc~0); 12743508#L541-2 is_transmit3_triggered_~__retres1~3#1 := 0; 12743509#L552 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12742370#is_transmit3_triggered_returnLabel#1 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12742371#L1269 assume !(0 != activate_threads_~tmp___2~0#1); 12744072#L1269-2 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12744073#L560 assume !(1 == ~t4_pc~0); 12742609#L560-2 is_transmit4_triggered_~__retres1~4#1 := 0; 12743864#L571 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12742655#is_transmit4_triggered_returnLabel#1 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12742392#L1277 assume !(0 != activate_threads_~tmp___3~0#1); 12742393#L1277-2 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12742914#L579 assume !(1 == ~t5_pc~0); 12742915#L579-2 is_transmit5_triggered_~__retres1~5#1 := 0; 12742508#L590 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12742509#is_transmit5_triggered_returnLabel#1 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12744729#L1285 assume !(0 != activate_threads_~tmp___4~0#1); 12745117#L1285-2 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12745198#L598 assume !(1 == ~t6_pc~0); 12744510#L598-2 is_transmit6_triggered_~__retres1~6#1 := 0; 12743716#L609 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12743320#is_transmit6_triggered_returnLabel#1 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12743321#L1293 assume !(0 != activate_threads_~tmp___5~0#1); 12744236#L1293-2 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12744122#L617 assume !(1 == ~t7_pc~0); 12743020#L617-2 is_transmit7_triggered_~__retres1~7#1 := 0; 12743857#L628 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12745308#is_transmit7_triggered_returnLabel#1 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12744920#L1301 assume !(0 != activate_threads_~tmp___6~0#1); 12743442#L1301-2 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12743443#L636 assume !(1 == ~t8_pc~0); 12744231#L636-2 is_transmit8_triggered_~__retres1~8#1 := 0; 12744696#L647 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12744568#is_transmit8_triggered_returnLabel#1 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12744255#L1309 assume !(0 != activate_threads_~tmp___7~0#1); 12743729#L1309-2 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12743730#L655 assume !(1 == ~t9_pc~0); 12743784#L655-2 is_transmit9_triggered_~__retres1~9#1 := 0; 12744647#L666 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12745414#is_transmit9_triggered_returnLabel#1 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12745411#L1317 assume !(0 != activate_threads_~tmp___8~0#1); 12745412#L1317-2 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12745426#L674 assume !(1 == ~t10_pc~0); 12743626#L674-2 is_transmit10_triggered_~__retres1~10#1 := 0; 12743627#L685 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12743810#is_transmit10_triggered_returnLabel#1 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12743811#L1325 assume !(0 != activate_threads_~tmp___9~0#1); 12743707#L1325-2 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12743708#L1119 assume !(1 == ~M_E~0); 12742766#L1119-2 assume !(1 == ~T1_E~0); 12742767#L1124-1 assume !(1 == ~T2_E~0); 12742444#L1129-1 assume !(1 == ~T3_E~0); 12742445#L1134-1 assume !(1 == ~T4_E~0); 12742996#L1139-1 assume !(1 == ~T5_E~0); 12742997#L1144-1 assume !(1 == ~T6_E~0); 12745361#L1149-1 assume !(1 == ~T7_E~0); 12742756#L1154-1 assume !(1 == ~T8_E~0); 12742757#L1159-1 assume !(1 == ~T9_E~0); 12745339#L1164-1 assume !(1 == ~T10_E~0); 12743763#L1169-1 assume !(1 == ~E_1~0); 12743540#L1174-1 assume !(1 == ~E_2~0); 12743091#L1179-1 assume !(1 == ~E_3~0); 12743092#L1184-1 assume !(1 == ~E_4~0); 12745415#L1189-1 assume !(1 == ~E_5~0); 12745413#L1194-1 assume !(1 == ~E_6~0); 12745379#L1199-1 assume !(1 == ~E_7~0); 12743115#L1204-1 assume !(1 == ~E_8~0); 12743116#L1209-1 assume !(1 == ~E_9~0); 12744275#L1214-1 assume !(1 == ~E_10~0); 12744276#L1219-1 assume { :end_inline_reset_delta_events } true; 12745338#L1520-2 assume !false; 12755367#L1521 [2023-11-29 02:57:14,590 INFO L750 eck$LassoCheckResult]: Loop: 12755367#L1521 start_simulation_~kernel_st~0#1 := 1;assume { :begin_inline_eval } true;havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;havoc eval_~tmp~0#1; 12993096#L981-1 assume !false; 12993094#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12993092#L764 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12993090#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 12993088#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12993086#L836 assume 0 != eval_~tmp~0#1; 12993084#L836-1 assume 0 == ~m_st~0;havoc eval_~tmp_ndt_1~0#1;havoc eval_#t~nondet5#1;eval_~tmp_ndt_1~0#1 := eval_#t~nondet5#1;havoc eval_#t~nondet5#1; 12993072#L844 assume 0 != eval_~tmp_ndt_1~0#1;~m_st~0 := 1;assume { :begin_inline_master } true; 12993073#L95 assume !(0 == ~m_pc~0); 13157430#L98 assume 1 == ~m_pc~0; 13157425#$Ultimate##388 assume !false; 12991345#L115 ~m_pc~0 := 1;~m_st~0 := 2; 12991343#master_returnLabel#1 assume { :end_inline_master } true; 12990250#L844-2 havoc eval_~tmp_ndt_1~0#1; 12990247#L841-1 assume !(0 == ~t1_st~0); 12990242#L855-1 assume !(0 == ~t2_st~0); 12990238#L869-1 assume !(0 == ~t3_st~0); 12990234#L883-1 assume !(0 == ~t4_st~0); 12990230#L897-1 assume !(0 == ~t5_st~0); 12990231#L911-1 assume !(0 == ~t6_st~0); 12994252#L925-1 assume !(0 == ~t7_st~0); 12994253#L939-1 assume !(0 == ~t8_st~0); 12995318#L953-1 assume !(0 == ~t9_st~0); 12995280#L967-1 assume !(0 == ~t10_st~0); 12995275#L981-1 assume !false; 12995273#L832 assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12995271#L764 assume !(0 == ~m_st~0); 12995269#L768 assume !(0 == ~t1_st~0); 12995267#L772 assume !(0 == ~t2_st~0); 12995265#L776 assume !(0 == ~t3_st~0); 12995263#L780 assume !(0 == ~t4_st~0); 12995261#L784 assume !(0 == ~t5_st~0); 12995260#L788 assume !(0 == ~t6_st~0); 12995257#L792 assume !(0 == ~t7_st~0); 12995255#L796 assume !(0 == ~t8_st~0); 12995253#L800 assume !(0 == ~t9_st~0); 12995250#L804 assume !(0 == ~t10_st~0);exists_runnable_thread_~__retres1~11#1 := 0; 12995248#L821 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 12995246#exists_runnable_thread_returnLabel#1 eval_#t~ret4#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;eval_~tmp~0#1 := eval_#t~ret4#1;havoc eval_#t~ret4#1; 12995242#L836 assume !(0 != eval_~tmp~0#1); 12995240#eval_returnLabel#1 havoc eval_#t~ret4#1, eval_#t~nondet5#1, eval_~tmp_ndt_1~0#1, eval_#t~nondet6#1, eval_~tmp_ndt_2~0#1, eval_#t~nondet7#1, eval_~tmp_ndt_3~0#1, eval_#t~nondet8#1, eval_~tmp_ndt_4~0#1, eval_#t~nondet9#1, eval_~tmp_ndt_5~0#1, eval_#t~nondet10#1, eval_~tmp_ndt_6~0#1, eval_#t~nondet11#1, eval_~tmp_ndt_7~0#1, eval_#t~nondet12#1, eval_~tmp_ndt_8~0#1, eval_#t~nondet13#1, eval_~tmp_ndt_9~0#1, eval_#t~nondet14#1, eval_~tmp_ndt_10~0#1, eval_#t~nondet15#1, eval_~tmp_ndt_11~0#1, eval_~tmp~0#1;assume { :end_inline_eval } true;start_simulation_~kernel_st~0#1 := 2;assume { :begin_inline_update_channels } true; 12995238#update_channels_returnLabel#2 assume { :end_inline_update_channels } true;start_simulation_~kernel_st~0#1 := 3;assume { :begin_inline_fire_delta_events } true; 12995236#L1006-3 assume !(0 == ~M_E~0); 12995233#L1006-5 assume 0 == ~T1_E~0;~T1_E~0 := 1; 12995231#L1011-3 assume !(0 == ~T2_E~0); 12995229#L1016-3 assume !(0 == ~T3_E~0); 12995227#L1021-3 assume 0 == ~T4_E~0;~T4_E~0 := 1; 12995225#L1026-3 assume 0 == ~T5_E~0;~T5_E~0 := 1; 12995179#L1031-3 assume !(0 == ~T6_E~0); 12995175#L1036-3 assume 0 == ~T7_E~0;~T7_E~0 := 1; 12995113#L1041-3 assume !(0 == ~T8_E~0); 12995106#L1046-3 assume 0 == ~T9_E~0;~T9_E~0 := 1; 12995098#L1051-3 assume 0 == ~T10_E~0;~T10_E~0 := 1; 12995088#L1056-3 assume !(0 == ~E_1~0); 12995079#L1061-3 assume 0 == ~E_2~0;~E_2~0 := 1; 12995069#L1066-3 assume 0 == ~E_3~0;~E_3~0 := 1; 12995058#L1071-3 assume !(0 == ~E_4~0); 12995050#L1076-3 assume 0 == ~E_5~0;~E_5~0 := 1; 12995042#L1081-3 assume !(0 == ~E_6~0); 12995033#L1086-3 assume 0 == ~E_7~0;~E_7~0 := 1; 12995022#L1091-3 assume 0 == ~E_8~0;~E_8~0 := 1; 12995013#L1096-3 assume !(0 == ~E_9~0); 12995005#L1101-3 assume !(0 == ~E_10~0); 12994997#L1106-3 assume { :end_inline_fire_delta_events } true;assume { :begin_inline_activate_threads } true;havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;havoc activate_threads_~tmp~1#1;havoc activate_threads_~tmp___0~0#1;havoc activate_threads_~tmp___1~0#1;havoc activate_threads_~tmp___2~0#1;havoc activate_threads_~tmp___3~0#1;havoc activate_threads_~tmp___4~0#1;havoc activate_threads_~tmp___5~0#1;havoc activate_threads_~tmp___6~0#1;havoc activate_threads_~tmp___7~0#1;havoc activate_threads_~tmp___8~0#1;havoc activate_threads_~tmp___9~0#1;assume { :begin_inline_is_master_triggered } true;havoc is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;havoc is_master_triggered_~__retres1~0#1; 12994970#L484-33 assume 1 == ~m_pc~0; 12994959#L485-11 assume 1 == ~M_E~0;is_master_triggered_~__retres1~0#1 := 1; 12994951#L495-11 is_master_triggered_#res#1 := is_master_triggered_~__retres1~0#1; 12994943#is_master_triggered_returnLabel#12 activate_threads_#t~ret16#1 := is_master_triggered_#res#1;havoc is_master_triggered_~__retres1~0#1;assume { :end_inline_is_master_triggered } true;activate_threads_~tmp~1#1 := activate_threads_#t~ret16#1;havoc activate_threads_#t~ret16#1; 12994933#L1245-33 assume 0 != activate_threads_~tmp~1#1;~m_st~0 := 0; 12994927#L1245-35 assume { :begin_inline_is_transmit1_triggered } true;havoc is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;havoc is_transmit1_triggered_~__retres1~1#1; 12994920#L503-33 assume !(1 == ~t1_pc~0); 12994913#L503-35 is_transmit1_triggered_~__retres1~1#1 := 0; 12994906#L514-11 is_transmit1_triggered_#res#1 := is_transmit1_triggered_~__retres1~1#1; 12994899#is_transmit1_triggered_returnLabel#12 activate_threads_#t~ret17#1 := is_transmit1_triggered_#res#1;havoc is_transmit1_triggered_~__retres1~1#1;assume { :end_inline_is_transmit1_triggered } true;activate_threads_~tmp___0~0#1 := activate_threads_#t~ret17#1;havoc activate_threads_#t~ret17#1; 12994892#L1253-33 assume !(0 != activate_threads_~tmp___0~0#1); 12994884#L1253-35 assume { :begin_inline_is_transmit2_triggered } true;havoc is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;havoc is_transmit2_triggered_~__retres1~2#1; 12994860#L522-33 assume 1 == ~t2_pc~0; 12994858#L523-11 assume 1 == ~E_2~0;is_transmit2_triggered_~__retres1~2#1 := 1; 12994859#L533-11 is_transmit2_triggered_#res#1 := is_transmit2_triggered_~__retres1~2#1; 12994864#is_transmit2_triggered_returnLabel#12 activate_threads_#t~ret18#1 := is_transmit2_triggered_#res#1;havoc is_transmit2_triggered_~__retres1~2#1;assume { :end_inline_is_transmit2_triggered } true;activate_threads_~tmp___1~0#1 := activate_threads_#t~ret18#1;havoc activate_threads_#t~ret18#1; 12994849#L1261-33 assume 0 != activate_threads_~tmp___1~0#1;~t2_st~0 := 0; 12994847#L1261-35 assume { :begin_inline_is_transmit3_triggered } true;havoc is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;havoc is_transmit3_triggered_~__retres1~3#1; 12994843#L541-33 assume !(1 == ~t3_pc~0); 12994841#L541-35 is_transmit3_triggered_~__retres1~3#1 := 0; 12994839#L552-11 is_transmit3_triggered_#res#1 := is_transmit3_triggered_~__retres1~3#1; 12994837#is_transmit3_triggered_returnLabel#12 activate_threads_#t~ret19#1 := is_transmit3_triggered_#res#1;havoc is_transmit3_triggered_~__retres1~3#1;assume { :end_inline_is_transmit3_triggered } true;activate_threads_~tmp___2~0#1 := activate_threads_#t~ret19#1;havoc activate_threads_#t~ret19#1; 12994834#L1269-33 assume !(0 != activate_threads_~tmp___2~0#1); 12994832#L1269-35 assume { :begin_inline_is_transmit4_triggered } true;havoc is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;havoc is_transmit4_triggered_~__retres1~4#1; 12994830#L560-33 assume !(1 == ~t4_pc~0); 12994826#L560-35 is_transmit4_triggered_~__retres1~4#1 := 0; 12994824#L571-11 is_transmit4_triggered_#res#1 := is_transmit4_triggered_~__retres1~4#1; 12994822#is_transmit4_triggered_returnLabel#12 activate_threads_#t~ret20#1 := is_transmit4_triggered_#res#1;havoc is_transmit4_triggered_~__retres1~4#1;assume { :end_inline_is_transmit4_triggered } true;activate_threads_~tmp___3~0#1 := activate_threads_#t~ret20#1;havoc activate_threads_#t~ret20#1; 12994821#L1277-33 assume !(0 != activate_threads_~tmp___3~0#1); 12994815#L1277-35 assume { :begin_inline_is_transmit5_triggered } true;havoc is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;havoc is_transmit5_triggered_~__retres1~5#1; 12994812#L579-33 assume !(1 == ~t5_pc~0); 12994810#L579-35 is_transmit5_triggered_~__retres1~5#1 := 0; 12994808#L590-11 is_transmit5_triggered_#res#1 := is_transmit5_triggered_~__retres1~5#1; 12994806#is_transmit5_triggered_returnLabel#12 activate_threads_#t~ret21#1 := is_transmit5_triggered_#res#1;havoc is_transmit5_triggered_~__retres1~5#1;assume { :end_inline_is_transmit5_triggered } true;activate_threads_~tmp___4~0#1 := activate_threads_#t~ret21#1;havoc activate_threads_#t~ret21#1; 12994804#L1285-33 assume !(0 != activate_threads_~tmp___4~0#1); 12994802#L1285-35 assume { :begin_inline_is_transmit6_triggered } true;havoc is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;havoc is_transmit6_triggered_~__retres1~6#1; 12994794#L598-33 assume !(1 == ~t6_pc~0); 12994788#L598-35 is_transmit6_triggered_~__retres1~6#1 := 0; 12994782#L609-11 is_transmit6_triggered_#res#1 := is_transmit6_triggered_~__retres1~6#1; 12994548#is_transmit6_triggered_returnLabel#12 activate_threads_#t~ret22#1 := is_transmit6_triggered_#res#1;havoc is_transmit6_triggered_~__retres1~6#1;assume { :end_inline_is_transmit6_triggered } true;activate_threads_~tmp___5~0#1 := activate_threads_#t~ret22#1;havoc activate_threads_#t~ret22#1; 12994544#L1293-33 assume !(0 != activate_threads_~tmp___5~0#1); 12994542#L1293-35 assume { :begin_inline_is_transmit7_triggered } true;havoc is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;havoc is_transmit7_triggered_~__retres1~7#1; 12994540#L617-33 assume 1 == ~t7_pc~0; 12994538#L618-11 assume 1 == ~E_7~0;is_transmit7_triggered_~__retres1~7#1 := 1; 12994539#L628-11 is_transmit7_triggered_#res#1 := is_transmit7_triggered_~__retres1~7#1; 12994557#is_transmit7_triggered_returnLabel#12 activate_threads_#t~ret23#1 := is_transmit7_triggered_#res#1;havoc is_transmit7_triggered_~__retres1~7#1;assume { :end_inline_is_transmit7_triggered } true;activate_threads_~tmp___6~0#1 := activate_threads_#t~ret23#1;havoc activate_threads_#t~ret23#1; 12994528#L1301-33 assume 0 != activate_threads_~tmp___6~0#1;~t7_st~0 := 0; 12994526#L1301-35 assume { :begin_inline_is_transmit8_triggered } true;havoc is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;havoc is_transmit8_triggered_~__retres1~8#1; 12994524#L636-33 assume !(1 == ~t8_pc~0); 12994522#L636-35 is_transmit8_triggered_~__retres1~8#1 := 0; 12994520#L647-11 is_transmit8_triggered_#res#1 := is_transmit8_triggered_~__retres1~8#1; 12994518#is_transmit8_triggered_returnLabel#12 activate_threads_#t~ret24#1 := is_transmit8_triggered_#res#1;havoc is_transmit8_triggered_~__retres1~8#1;assume { :end_inline_is_transmit8_triggered } true;activate_threads_~tmp___7~0#1 := activate_threads_#t~ret24#1;havoc activate_threads_#t~ret24#1; 12994515#L1309-33 assume !(0 != activate_threads_~tmp___7~0#1); 12994513#L1309-35 assume { :begin_inline_is_transmit9_triggered } true;havoc is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;havoc is_transmit9_triggered_~__retres1~9#1; 12994512#L655-33 assume 1 == ~t9_pc~0; 12994510#L656-11 assume 1 == ~E_9~0;is_transmit9_triggered_~__retres1~9#1 := 1; 12994511#L666-11 is_transmit9_triggered_#res#1 := is_transmit9_triggered_~__retres1~9#1; 12994509#is_transmit9_triggered_returnLabel#12 activate_threads_#t~ret25#1 := is_transmit9_triggered_#res#1;havoc is_transmit9_triggered_~__retres1~9#1;assume { :end_inline_is_transmit9_triggered } true;activate_threads_~tmp___8~0#1 := activate_threads_#t~ret25#1;havoc activate_threads_#t~ret25#1; 12994507#L1317-33 assume 0 != activate_threads_~tmp___8~0#1;~t9_st~0 := 0; 12994504#L1317-35 assume { :begin_inline_is_transmit10_triggered } true;havoc is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;havoc is_transmit10_triggered_~__retres1~10#1; 12994502#L674-33 assume !(1 == ~t10_pc~0); 12994500#L674-35 is_transmit10_triggered_~__retres1~10#1 := 0; 12994498#L685-11 is_transmit10_triggered_#res#1 := is_transmit10_triggered_~__retres1~10#1; 12994496#is_transmit10_triggered_returnLabel#12 activate_threads_#t~ret26#1 := is_transmit10_triggered_#res#1;havoc is_transmit10_triggered_~__retres1~10#1;assume { :end_inline_is_transmit10_triggered } true;activate_threads_~tmp___9~0#1 := activate_threads_#t~ret26#1;havoc activate_threads_#t~ret26#1; 12994494#L1325-33 assume !(0 != activate_threads_~tmp___9~0#1); 12994492#L1325-35 havoc activate_threads_#t~ret16#1, activate_threads_#t~ret17#1, activate_threads_#t~ret18#1, activate_threads_#t~ret19#1, activate_threads_#t~ret20#1, activate_threads_#t~ret21#1, activate_threads_#t~ret22#1, activate_threads_#t~ret23#1, activate_threads_#t~ret24#1, activate_threads_#t~ret25#1, activate_threads_#t~ret26#1, activate_threads_~tmp~1#1, activate_threads_~tmp___0~0#1, activate_threads_~tmp___1~0#1, activate_threads_~tmp___2~0#1, activate_threads_~tmp___3~0#1, activate_threads_~tmp___4~0#1, activate_threads_~tmp___5~0#1, activate_threads_~tmp___6~0#1, activate_threads_~tmp___7~0#1, activate_threads_~tmp___8~0#1, activate_threads_~tmp___9~0#1;assume { :end_inline_activate_threads } true;assume { :begin_inline_reset_delta_events } true; 12994490#L1119-3 assume 1 == ~M_E~0;~M_E~0 := 2; 12994488#L1119-5 assume 1 == ~T1_E~0;~T1_E~0 := 2; 12994486#L1124-3 assume !(1 == ~T2_E~0); 12994484#L1129-3 assume !(1 == ~T3_E~0); 12994482#L1134-3 assume 1 == ~T4_E~0;~T4_E~0 := 2; 12994480#L1139-3 assume 1 == ~T5_E~0;~T5_E~0 := 2; 12994478#L1144-3 assume !(1 == ~T6_E~0); 12994476#L1149-3 assume 1 == ~T7_E~0;~T7_E~0 := 2; 12994474#L1154-3 assume 1 == ~T8_E~0;~T8_E~0 := 2; 12994472#L1159-3 assume 1 == ~T9_E~0;~T9_E~0 := 2; 12994470#L1164-3 assume 1 == ~T10_E~0;~T10_E~0 := 2; 12994468#L1169-3 assume !(1 == ~E_1~0); 12994448#L1174-3 assume 1 == ~E_2~0;~E_2~0 := 2; 12994440#L1179-3 assume 1 == ~E_3~0;~E_3~0 := 2; 12994434#L1184-3 assume !(1 == ~E_4~0); 12994427#L1189-3 assume 1 == ~E_5~0;~E_5~0 := 2; 12994419#L1194-3 assume 1 == ~E_6~0;~E_6~0 := 2; 12994415#L1199-3 assume 1 == ~E_7~0;~E_7~0 := 2; 12994409#L1204-3 assume 1 == ~E_8~0;~E_8~0 := 2; 12994402#L1209-3 assume 1 == ~E_9~0;~E_9~0 := 2; 12994395#L1214-3 assume !(1 == ~E_10~0); 12993391#L1219-3 assume { :end_inline_reset_delta_events } true;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12993389#L764-1 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12993387#L821-1 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 12993384#exists_runnable_thread_returnLabel#2 start_simulation_#t~ret28#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;start_simulation_~tmp~3#1 := start_simulation_#t~ret28#1;havoc start_simulation_#t~ret28#1; 12993204#L1539 assume !(0 == start_simulation_~tmp~3#1); 12993195#L1539-2 assume { :begin_inline_stop_simulation } true;havoc stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;havoc stop_simulation_~tmp~2#1;havoc stop_simulation_~__retres2~0#1;assume { :begin_inline_exists_runnable_thread } true;havoc exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;havoc exists_runnable_thread_~__retres1~11#1; 12993187#L764-2 assume 0 == ~m_st~0;exists_runnable_thread_~__retres1~11#1 := 1; 12993178#L821-2 exists_runnable_thread_#res#1 := exists_runnable_thread_~__retres1~11#1; 12993169#exists_runnable_thread_returnLabel#3 stop_simulation_#t~ret27#1 := exists_runnable_thread_#res#1;havoc exists_runnable_thread_~__retres1~11#1;assume { :end_inline_exists_runnable_thread } true;stop_simulation_~tmp~2#1 := stop_simulation_#t~ret27#1;havoc stop_simulation_#t~ret27#1; 12993158#L1494 assume 0 != stop_simulation_~tmp~2#1;stop_simulation_~__retres2~0#1 := 0; 12993149#L1501 stop_simulation_#res#1 := stop_simulation_~__retres2~0#1; 12993146#stop_simulation_returnLabel#1 start_simulation_#t~ret29#1 := stop_simulation_#res#1;havoc stop_simulation_#t~ret27#1, stop_simulation_~tmp~2#1, stop_simulation_~__retres2~0#1;assume { :end_inline_stop_simulation } true;start_simulation_~tmp___0~1#1 := start_simulation_#t~ret29#1;havoc start_simulation_#t~ret29#1; 12993144#L1552 assume !(0 != start_simulation_~tmp___0~1#1); 12993142#L1520-2 assume !false; 12755367#L1521 [2023-11-29 02:57:14,590 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:57:14,590 INFO L85 PathProgramCache]: Analyzing trace with hash -503834872, now seen corresponding path program 1 times [2023-11-29 02:57:14,591 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:57:14,591 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1842944339] [2023-11-29 02:57:14,591 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:57:14,591 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:57:14,603 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:57:14,603 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:57:14,611 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:57:14,651 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:57:14,652 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:57:14,652 INFO L85 PathProgramCache]: Analyzing trace with hash -2135114797, now seen corresponding path program 1 times [2023-11-29 02:57:14,652 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:57:14,652 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [1817000347] [2023-11-29 02:57:14,652 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:57:14,652 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:57:14,668 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:57:14,668 INFO L356 TraceCheck]: Trace is feasible, we will do another trace check, this time with branch encoders. [2023-11-29 02:57:14,679 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is sat [2023-11-29 02:57:14,718 INFO L130 FreeRefinementEngine]: Strategy CAMEL found a feasible trace [2023-11-29 02:57:14,718 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:57:14,718 INFO L85 PathProgramCache]: Analyzing trace with hash -1798380134, now seen corresponding path program 1 times [2023-11-29 02:57:14,718 INFO L118 FreeRefinementEngine]: Executing refinement strategy CAMEL [2023-11-29 02:57:14,719 INFO L334 FreeRefinementEngine]: Using trace check IpTcStrategyModuleSmtInterpolCraig [462042720] [2023-11-29 02:57:14,719 INFO L95 rtionOrderModulation]: Keeping assertion order NOT_INCREMENTALLY [2023-11-29 02:57:14,719 INFO L127 SolverBuilder]: Constructing new instance of SMTInterpol with explicit timeout -1 ms and remaining time -1 ms [2023-11-29 02:57:14,738 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:57:14,796 INFO L134 CoverageAnalysis]: Checked inductivity of 7 backedges. 7 proven. 0 refuted. 0 times theorem prover too weak. 0 trivial. 0 not checked. [2023-11-29 02:57:14,796 INFO L136 FreeRefinementEngine]: Strategy CAMEL found an infeasible trace [2023-11-29 02:57:14,796 INFO L334 FreeRefinementEngine]: Using interpolant generator IpTcStrategyModuleSmtInterpolCraig [462042720] [2023-11-29 02:57:14,797 INFO L158 FreeRefinementEngine]: IpTcStrategyModuleSmtInterpolCraig [462042720] provided 1 perfect and 0 imperfect interpolant sequences [2023-11-29 02:57:14,797 INFO L185 FreeRefinementEngine]: Found 1 perfect and 0 imperfect interpolant sequences. [2023-11-29 02:57:14,797 INFO L198 FreeRefinementEngine]: Number of different interpolants: perfect sequences [2] imperfect sequences [] total 2 [2023-11-29 02:57:14,797 INFO L121 tionRefinementEngine]: Using interpolant automaton builder IpAbStrategyModuleStraightlineAll [865783196] [2023-11-29 02:57:14,797 INFO L85 oduleStraightlineAll]: Using 1 perfect interpolants to construct interpolant automaton [2023-11-29 02:57:17,521 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 02:57:17,521 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 02:57:17,521 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 02:57:17,521 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 02:57:17,521 INFO L129 ssoRankerPreferences]: Use exernal solver: true [2023-11-29 02:57:17,521 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:17,521 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 02:57:17,521 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 02:57:17,521 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.10.cil.c_Iteration39_Loop [2023-11-29 02:57:17,521 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 02:57:17,521 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 02:57:17,524 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,527 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,528 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,530 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,533 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,535 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,536 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,538 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,539 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,540 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,544 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,545 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,547 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,548 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,551 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,554 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,556 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,559 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,560 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,562 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,563 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,565 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,566 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,568 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,569 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,570 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,571 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,572 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,575 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,577 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,578 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,580 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,583 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,585 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,586 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,588 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,589 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,591 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,592 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,593 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,595 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,596 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,599 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,600 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,604 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,605 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,608 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,610 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,611 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,613 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,614 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,615 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,617 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,618 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,620 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,621 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,624 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,627 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,630 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,632 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,633 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,636 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,639 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,643 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,645 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,648 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,651 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,655 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,658 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,661 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,663 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,666 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,667 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,669 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,672 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,675 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,676 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,681 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,686 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,689 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,691 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,692 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,694 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,697 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,698 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,702 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,703 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,704 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,706 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,708 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,709 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,710 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,711 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,713 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,714 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,716 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,717 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,718 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,720 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,721 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,722 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,724 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,725 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,729 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,730 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,734 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,736 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,738 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,740 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,743 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,745 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,746 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,747 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,749 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,750 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,752 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:17,755 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,366 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 02:57:18,366 INFO L404 LassoAnalysis]: Checking for nontermination... [2023-11-29 02:57:18,366 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:18,367 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:18,367 INFO L229 MonitoredProcess]: Starting monitored process 38 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:18,369 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Waiting until timeout for monitored process [2023-11-29 02:57:18,370 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:57:18,370 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:57:18,387 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:57:18,388 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {~t4_st~0=-1} Honda state: {~t4_st~0=-1} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:57:18,390 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (38)] Ended with exit code 0 [2023-11-29 02:57:18,391 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:18,391 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:18,392 INFO L229 MonitoredProcess]: Starting monitored process 39 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:18,392 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Waiting until timeout for monitored process [2023-11-29 02:57:18,394 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:57:18,394 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:57:18,405 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:57:18,405 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_activate_threads_#t~ret20#1=0} Honda state: {ULTIMATE.start_activate_threads_#t~ret20#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:57:18,408 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (39)] Ended with exit code 0 [2023-11-29 02:57:18,408 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:18,408 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:18,409 INFO L229 MonitoredProcess]: Starting monitored process 40 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:18,409 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Waiting until timeout for monitored process [2023-11-29 02:57:18,411 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:57:18,411 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:57:18,422 INFO L437 LassoAnalysis]: Proved nontermination for one component. [2023-11-29 02:57:18,422 INFO L440 LassoAnalysis]: Non-Termination argument consisting of: Initial state: {ULTIMATE.start_is_transmit10_triggered_~__retres1~10#1=0} Honda state: {ULTIMATE.start_is_transmit10_triggered_~__retres1~10#1=0} Generalized eigenvectors: [] Lambdas: [] Nus: [] [2023-11-29 02:57:18,424 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (40)] Ended with exit code 0 [2023-11-29 02:57:18,424 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:18,424 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:18,425 INFO L229 MonitoredProcess]: Starting monitored process 41 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:18,426 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Waiting until timeout for monitored process [2023-11-29 02:57:18,427 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 0 Nilpotent components: true [2023-11-29 02:57:18,427 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:57:18,440 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (41)] Ended with exit code 0 [2023-11-29 02:57:18,440 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:18,441 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:18,441 INFO L229 MonitoredProcess]: Starting monitored process 42 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:18,442 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Waiting until timeout for monitored process [2023-11-29 02:57:18,443 INFO L148 nArgumentSynthesizer]: Nontermination analysis: NONLINEAR Allow bounded executions: true Number of generalized eigenvectors: 3 Nilpotent components: true [2023-11-29 02:57:18,443 INFO L160 nArgumentSynthesizer]: Using integer mode. [2023-11-29 02:57:18,470 INFO L444 LassoAnalysis]: Proving nontermination failed: No geometric nontermination argument exists. [2023-11-29 02:57:18,473 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (42)] Forceful destruction successful, exit code 0 [2023-11-29 02:57:18,473 INFO L210 LassoAnalysis]: Preferences: [2023-11-29 02:57:18,473 INFO L126 ssoRankerPreferences]: Compute integeral hull: false [2023-11-29 02:57:18,473 INFO L127 ssoRankerPreferences]: Enable LassoPartitioneer: true [2023-11-29 02:57:18,473 INFO L128 ssoRankerPreferences]: Term annotations enabled: false [2023-11-29 02:57:18,473 INFO L129 ssoRankerPreferences]: Use exernal solver: false [2023-11-29 02:57:18,473 INFO L130 ssoRankerPreferences]: SMT solver command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:18,473 INFO L131 ssoRankerPreferences]: Dump SMT script to file: false [2023-11-29 02:57:18,473 INFO L132 ssoRankerPreferences]: Path of dumped script: [2023-11-29 02:57:18,473 INFO L133 ssoRankerPreferences]: Filename of dumped script: transmitter.10.cil.c_Iteration39_Loop [2023-11-29 02:57:18,473 INFO L134 ssoRankerPreferences]: MapElimAlgo: Frank [2023-11-29 02:57:18,473 INFO L276 LassoAnalysis]: Starting lasso preprocessing... [2023-11-29 02:57:18,477 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,479 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,480 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,482 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,485 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,486 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,487 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,489 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,492 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,493 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,494 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,495 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,496 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,498 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,499 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,500 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,502 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,503 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,504 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,506 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,509 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,510 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,512 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,514 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,515 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,517 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,518 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,519 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,520 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,521 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,523 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,525 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,529 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,530 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,532 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,536 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,538 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,539 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,541 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,542 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,544 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,545 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,546 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,548 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,549 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,551 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,552 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,555 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,558 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,560 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,561 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,563 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,564 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,565 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,566 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,568 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,569 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,570 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,573 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,576 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,579 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,580 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,583 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,584 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,587 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,588 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,591 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,592 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,595 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,598 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,601 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,604 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,607 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,608 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,611 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,612 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,614 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,615 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,617 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,618 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,619 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,622 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,624 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,625 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,626 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,628 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,629 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,631 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,634 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,636 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,638 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,640 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,641 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,643 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,644 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,645 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,646 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,648 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,649 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,650 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,651 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,653 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,654 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,655 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,657 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,660 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,662 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,665 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,667 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,668 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,670 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,671 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,673 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,674 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,677 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,679 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,680 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,681 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,683 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,684 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,685 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:18,687 INFO L118 MapEliminator]: Using MapEliminator with SimplificationTechnique=SIMPLIFY_DDA XnfConversionTechnique=BOTTOM_UP_WITH_LOCAL_SIMPLIFICATION AddInequalities=false OnlyTrivialImplicationsArrayWrite=true OnlyTrivialImplicationsForModifiedArguments=true OnlyArgumentsInFormula=true [2023-11-29 02:57:19,267 INFO L294 LassoAnalysis]: Preprocessing complete. [2023-11-29 02:57:19,267 INFO L490 LassoAnalysis]: Using template 'affine'. [2023-11-29 02:57:19,267 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:19,267 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:19,268 INFO L229 MonitoredProcess]: Starting monitored process 43 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:19,269 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Waiting until timeout for monitored process [2023-11-29 02:57:19,270 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:57:19,280 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:57:19,280 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:57:19,280 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:57:19,281 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:57:19,281 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:57:19,281 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:57:19,281 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:57:19,282 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:57:19,285 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (43)] Ended with exit code 0 [2023-11-29 02:57:19,285 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:19,285 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:19,286 INFO L229 MonitoredProcess]: Starting monitored process 44 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:19,286 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Waiting until timeout for monitored process [2023-11-29 02:57:19,288 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:57:19,298 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:57:19,298 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:57:19,298 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:57:19,298 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 02:57:19,298 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:57:19,299 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 02:57:19,299 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:57:19,300 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:57:19,303 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (44)] Ended with exit code 0 [2023-11-29 02:57:19,303 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:19,303 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:19,304 INFO L229 MonitoredProcess]: Starting monitored process 45 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:19,304 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Waiting until timeout for monitored process [2023-11-29 02:57:19,306 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:57:19,316 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:57:19,316 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:57:19,316 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:57:19,316 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:57:19,316 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:57:19,316 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:57:19,316 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:57:19,318 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:57:19,320 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (45)] Ended with exit code 0 [2023-11-29 02:57:19,321 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:19,321 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:19,322 INFO L229 MonitoredProcess]: Starting monitored process 46 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:19,322 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Waiting until timeout for monitored process [2023-11-29 02:57:19,324 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:57:19,334 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:57:19,334 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:57:19,334 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:57:19,334 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 02:57:19,334 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:57:19,335 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 02:57:19,335 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:57:19,338 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:57:19,341 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (46)] Ended with exit code 0 [2023-11-29 02:57:19,341 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:19,341 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:19,342 INFO L229 MonitoredProcess]: Starting monitored process 47 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:19,343 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Waiting until timeout for monitored process [2023-11-29 02:57:19,344 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:57:19,355 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:57:19,355 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:57:19,355 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:57:19,355 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:57:19,355 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:57:19,356 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:57:19,356 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:57:19,357 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:57:19,359 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (47)] Ended with exit code 0 [2023-11-29 02:57:19,360 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:19,360 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:19,360 INFO L229 MonitoredProcess]: Starting monitored process 48 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:19,361 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Waiting until timeout for monitored process [2023-11-29 02:57:19,363 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:57:19,373 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:57:19,373 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:57:19,373 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:57:19,373 INFO L204 nArgumentSynthesizer]: 2 loop disjuncts [2023-11-29 02:57:19,373 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:57:19,374 INFO L401 nArgumentSynthesizer]: We have 4 Motzkin's Theorem applications. [2023-11-29 02:57:19,374 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:57:19,376 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:57:19,378 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (48)] Ended with exit code 0 [2023-11-29 02:57:19,379 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:19,379 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:19,379 INFO L229 MonitoredProcess]: Starting monitored process 49 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:19,380 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Waiting until timeout for monitored process [2023-11-29 02:57:19,382 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:57:19,392 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:57:19,392 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:57:19,392 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:57:19,392 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:57:19,392 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:57:19,392 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:57:19,392 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:57:19,394 INFO L527 LassoAnalysis]: Proving termination failed for this template and these settings. [2023-11-29 02:57:19,396 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (49)] Forceful destruction successful, exit code 0 [2023-11-29 02:57:19,396 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:19,396 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:19,397 INFO L229 MonitoredProcess]: Starting monitored process 50 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:19,398 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Waiting until timeout for monitored process [2023-11-29 02:57:19,399 INFO L120 nArgumentSynthesizer]: Termination Analysis Settings: Termination analysis: LINEAR_WITH_GUESSESNumber of strict supporting invariants: 0Number of non-strict supporting invariants: 1Consider only non-deceasing supporting invariants: trueSimplify termination arguments: trueSimplify supporting invariants: trueOverapproximate stem: false [2023-11-29 02:57:19,409 INFO L338 nArgumentSynthesizer]: Template has degree 0. [2023-11-29 02:57:19,409 INFO L351 nArgumentSynthesizer]: There is no stem transition; disabling supporting invariant generation. [2023-11-29 02:57:19,409 INFO L203 nArgumentSynthesizer]: 1 stem disjuncts [2023-11-29 02:57:19,409 INFO L204 nArgumentSynthesizer]: 1 loop disjuncts [2023-11-29 02:57:19,409 INFO L205 nArgumentSynthesizer]: 2 template conjuncts. [2023-11-29 02:57:19,410 INFO L401 nArgumentSynthesizer]: We have 2 Motzkin's Theorem applications. [2023-11-29 02:57:19,410 INFO L402 nArgumentSynthesizer]: A total of 0 supporting invariants were added. [2023-11-29 02:57:19,412 INFO L420 nArgumentSynthesizer]: Found a termination argument, trying to simplify. [2023-11-29 02:57:19,414 INFO L443 ModelExtractionUtils]: Simplification made 3 calls to the SMT solver. [2023-11-29 02:57:19,414 INFO L444 ModelExtractionUtils]: 0 out of 3 variables were initially zero. Simplification set additionally 0 variables to zero. [2023-11-29 02:57:19,414 INFO L173 SolverBuilder]: Constructing external solver with command: z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 [2023-11-29 02:57:19,414 INFO L189 MonitoredProcess]: No working directory specified, using /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 [2023-11-29 02:57:19,415 INFO L229 MonitoredProcess]: Starting monitored process 51 with /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (exit command is (exit), workingDir is null) [2023-11-29 02:57:19,416 INFO L327 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Waiting until timeout for monitored process [2023-11-29 02:57:19,417 INFO L435 nArgumentSynthesizer]: Simplifying supporting invariants... [2023-11-29 02:57:19,417 INFO L438 nArgumentSynthesizer]: Removed 0 redundant supporting invariants from a total of 0. [2023-11-29 02:57:19,417 INFO L513 LassoAnalysis]: Proved termination. [2023-11-29 02:57:19,417 INFO L515 LassoAnalysis]: Termination argument consisting of: Ranking function f(~T7_E~0) = -1*~T7_E~0 + 1 Supporting invariants [] [2023-11-29 02:57:19,420 INFO L552 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (50)] Ended with exit code 0 [2023-11-29 02:57:19,420 INFO L156 tatePredicateManager]: 0 out of 0 supporting invariants were superfluous and have been removed [2023-11-29 02:57:19,429 INFO L160 PredicateUnifier]: Initialized classic predicate unifier [2023-11-29 02:57:19,481 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:57:19,483 INFO L262 TraceCheckSpWp]: Trace formula consists of 354 conjuncts, 2 conjunts are in the unsatisfiable core [2023-11-29 02:57:19,484 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 02:57:19,650 INFO L136 AnnotateAndAsserter]: Conjunction of SSA is unsat [2023-11-29 02:57:19,652 INFO L262 TraceCheckSpWp]: Trace formula consists of 341 conjuncts, 4 conjunts are in the unsatisfiable core [2023-11-29 02:57:19,654 INFO L285 TraceCheckSpWp]: Computing forward predicates... [2023-11-29 02:57:19,890 INFO L134 CoverageAnalysis]: Checked inductivity of 6 backedges. 0 proven. 0 refuted. 0 times theorem prover too weak. 6 trivial. 0 not checked. [2023-11-29 02:57:19,891 INFO L141 lantAutomatonBouncer]: Defining deterministic Buchi interpolant automaton with honda bouncer for stem and without honda bouncer for loop.1 stem predicates 3 loop predicates [2023-11-29 02:57:19,892 INFO L71 iDifferenceNCSBLazy3]: Start buchiDifferenceNCSBLazy3. First operand 678187 states and 875212 transitions. cyclomatic complexity: 197217 Second operand has 5 states, 5 states have (on average 57.8) internal successors, (289), 5 states have internal predecessors, (289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:57:20,431 INFO L540 MonitoredProcess]: [MP /tmp/vcloud_worker_vcloud-master_on_vcloud-master/run_dir_3a8b8d79-209d-43a8-bbd8-be25ac0e0445/bin/uautomizer-verify-BQ2R08f2Ya/z3 SMTLIB2_COMPLIANT=true -memory:1024 -smt2 -in -t:12000 (51)] Forceful destruction successful, exit code 0 [2023-11-29 02:57:24,160 INFO L75 iDifferenceNCSBLazy3]: Finished buchiDifferenceNCSBLazy3. First operand 678187 states and 875212 transitions. cyclomatic complexity: 197217. Second operand has 5 states, 5 states have (on average 57.8) internal successors, (289), 5 states have internal predecessors, (289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) Result 1359790 states and 1759025 transitions. Complement of second has 4 states. [2023-11-29 02:57:24,160 INFO L141 InterpolantAutomaton]: Switched to read-only mode: Buchi interpolant automaton has 3 states 1 stem states 1 non-accepting loop states 1 accepting loop states [2023-11-29 02:57:24,161 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 5 states, 5 states have (on average 57.8) internal successors, (289), 5 states have internal predecessors, (289), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:57:24,163 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 3 states to 3 states and 1842 transitions. [2023-11-29 02:57:24,163 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1842 transitions. Stem has 127 letters. Loop has 166 letters. [2023-11-29 02:57:24,165 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 02:57:24,165 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1842 transitions. Stem has 293 letters. Loop has 166 letters. [2023-11-29 02:57:24,167 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 02:57:24,167 INFO L84 BuchiAccepts]: Start buchiAccepts Operand 3 states and 1842 transitions. Stem has 127 letters. Loop has 332 letters. [2023-11-29 02:57:24,171 INFO L116 BuchiAccepts]: Finished buchiAccepts. [2023-11-29 02:57:24,171 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1359790 states and 1759025 transitions. [2023-11-29 02:57:29,661 INFO L131 ngComponentsAnalysis]: Automaton has 128 accepting balls. 457600 [2023-11-29 02:57:33,223 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1359790 states to 1359790 states and 1759025 transitions. [2023-11-29 02:57:33,223 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 460460 [2023-11-29 02:57:33,387 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 461741 [2023-11-29 02:57:33,387 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1359790 states and 1759025 transitions. [2023-11-29 02:57:33,390 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 02:57:33,390 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1359790 states and 1759025 transitions. [2023-11-29 02:57:34,037 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1359790 states and 1759025 transitions. [2023-11-29 02:57:43,330 INFO L88 GeneralOperation]: Finished minimizeSevpa. Reduced states from 1359790 to 1358509. [2023-11-29 02:57:44,465 INFO L82 GeneralOperation]: Start removeUnreachable. Operand has 1358509 states, 1358509 states have (on average 1.292935122255355) internal successors, (1756464), 1358508 states have internal predecessors, (1756464), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:57:48,426 INFO L88 GeneralOperation]: Finished removeUnreachable. Reduced from 1358509 states to 1358509 states and 1756464 transitions. [2023-11-29 02:57:48,426 INFO L240 hiAutomatonCegarLoop]: Abstraction has 1358509 states and 1756464 transitions. [2023-11-29 02:57:48,426 INFO L100 FreeRefinementEngine]: Using predicate unifier PredicateUnifier provided by strategy CAMEL [2023-11-29 02:57:48,427 INFO L143 InterpolantAutomaton]: Constructing interpolant automaton starting with 3 interpolants. [2023-11-29 02:57:48,427 INFO L145 InterpolantAutomaton]: CoverageRelationStatistics Valid=3, Invalid=3, Unknown=0, NotChecked=0, Total=6 [2023-11-29 02:57:48,427 INFO L87 Difference]: Start difference. First operand 1358509 states and 1756464 transitions. Second operand has 3 states, 3 states have (on average 97.66666666666667) internal successors, (293), 2 states have internal predecessors, (293), 0 states have call successors, (0), 0 states have call predecessors, (0), 0 states have return successors, (0), 0 states have call predecessors, (0), 0 states have call successors, (0) [2023-11-29 02:57:54,564 INFO L144 Difference]: Subtrahend was deterministic. Have not used determinization. [2023-11-29 02:57:54,565 INFO L93 Difference]: Finished difference Result 1889385 states and 2411913 transitions. [2023-11-29 02:57:54,565 INFO L82 GeneralOperation]: Start removeNonLiveStates. Operand 1889385 states and 2411913 transitions. [2023-11-29 02:58:01,471 INFO L131 ngComponentsAnalysis]: Automaton has 320 accepting balls. 637056 [2023-11-29 02:58:06,005 INFO L88 GeneralOperation]: Finished removeNonLiveStates. Reduced from 1889385 states to 1889385 states and 2411913 transitions. [2023-11-29 02:58:06,005 INFO L87 BuchiClosureNwa]: Accepting states before buchiClosure: 641320 [2023-11-29 02:58:06,267 INFO L106 BuchiClosureNwa]: Accepting states after buchiClosure: 641320 [2023-11-29 02:58:06,267 INFO L73 IsDeterministic]: Start isDeterministic. Operand 1889385 states and 2411913 transitions. [2023-11-29 02:58:06,270 INFO L80 IsDeterministic]: Finished isDeterministic. Operand is not deterministic. [2023-11-29 02:58:06,270 INFO L218 hiAutomatonCegarLoop]: Abstraction has 1889385 states and 2411913 transitions. [2023-11-29 02:58:07,656 INFO L82 GeneralOperation]: Start minimizeSevpa. Operand 1889385 states and 2411913 transitions.